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Iglesias" To: Peter Maydell Subject: Re: [PATCH v1 1/1] target/arm: Drop access_el3_aa32ns() Message-ID: <20200504141812.GA2945@toto> References: <20200428160350.10030-1-edgar.iglesias@gmail.com> <20200428160350.10030-2-edgar.iglesias@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.80.198; CTRY:IE; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:xir-pvapexch01.xlnx.xilinx.com; PTR:unknown-80-198.xilinx.com; CAT:NONE; SFTY:; SFS:(7916004)(39860400002)(396003)(346002)(376002)(136003)(46966005)(70206006)(26005)(356005)(70586007)(316002)(9786002)(36906005)(8936002)(54906003)(8676002)(33656002)(1076003)(478600001)(7636003)(426003)(6916009)(336012)(33716001)(5660300002)(4326008)(82310400002)(186003)(47076004)(2906002)(82740400003)(9686003); DIR:OUT; SFP:1101; X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: d2dadae4-ff56-4ae4-2092-08d7f035fc3a X-MS-TrafficTypeDiagnostic: SN6PR02MB5038: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:10000; X-Forefront-PRVS: 03932714EB X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: PiMCGdEayvnLYHklwXuyiu/H82DtRETawlfbEkBotELyaZweLX7X0o2xV03GMesHrqBxdMhou6TFmy+v8HGeekBPR3wNMUJkWoj6g9auCX9SPZmFAflRt6awam/ACb7IBxY4BNQky5BnGDNezI6rJ1vzQcWtDoN6JARjv30W5mxJID6Iy80pIiHfq/5XIDTI65HFXqZBNRTRmkK4SrsMEPTPj8jCPX8vzqvc5fUf/OmRXWWx/97k4Ur5xC7xk8AwhU7ImpipghsmKo5Y+L6c+5cPskEnOFvsPxs0eZLbaiBZZUN4ZxsIL/G5m29kfyV3h42fROjzBEZbqXOpHSIlG2oSm45BxT4B3tbhnu42f5lmhZ7MqSRNWvfQh3kINSjN7dMy19oTGsEf71JRgow34kwdOKZg3du7ycnkdrwWZUsXo/CcHpS11gvz0O8iRx/Wsq7cwMMOZ/KZEB2XNrnQtBh0gBUBZHqlxmx4BTf+moXjxS7wPoBfj9N8iOjfKXXn66IKVn9QDh+W9n2tJ/mmFA== X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 May 2020 14:18:14.9106 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d2dadae4-ff56-4ae4-2092-08d7f035fc3a X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.80.198]; Helo=[xir-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR02MB5038 Received-SPF: pass client-ip=40.107.244.43; envelope-from=edgar@xilinx.com; helo=NAM12-MW2-obe.outbound.protection.outlook.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/05/04 10:18:17 X-ACL-Warn: Detected OS = Windows NT kernel [generic] [fuzzy] X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Desnogues , "Edgar E. Iglesias" , qemu-arm , Richard Henderson , QEMU Developers Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Mon, May 04, 2020 at 12:01:07PM +0100, Peter Maydell wrote: > On Tue, 28 Apr 2020 at 17:03, Edgar E. Iglesias > wrote: > > > > From: "Edgar E. Iglesias" > > > > Calling access_el3_aa32ns() works for AArch32 only cores > > but it does not handle 32-bit EL2 on top of 64-bit EL3 > > for mixed 32/64-bit cores. > > > > Fold access_el3_aa32ns() into access_el3_aa32ns_aa64any() > > and replace all direct uses of the aa32 only version with > > access_el3_aa32ns_aa64any(). > > > > Fixes: 68e9c2fe65 ("target-arm: Add VTCR_EL2") > > Reported-by: Laurent Desnogues > > Signed-off-by: Edgar E. Iglesias > > So, this is definitely a bug, but I think we could be > clearer about what we're fixing. > > For all these registers, the way the Arm ARM pseudocode phrases > this access check is: > * for the AArch64 view of the register, no check > * for the AArch32 view of the register: > ... > elsif PSTATE.EL == EL2 then > return VTTBR; > elsif PSTATE.EL == EL3 then > if SCR.NS == '0' then > UNDEFINED; > else > return VTTBR; > (similarly for the write path). We don't implement the HSTR.T2 > traps, so for us these registers are all .access = PL2_RW and > we just UNDEF for all EL0/EL1 accesses. > > So what we're really trying to check for is "current EL is EL3 > and we are AArch32 and SCR.NS == '0'". Because it's not possible > to be in AArch32 Hyp with SCR.NS == 0, the check we make in > your function is an equivalent test, but we could improve > the comments: > > --- > > target/arm/helper.c | 34 ++++++++++------------------------ > > 1 file changed, 10 insertions(+), 24 deletions(-) > > > > diff --git a/target/arm/helper.c b/target/arm/helper.c > > index 7e9ea5d20f..888f5f2314 100644 > > --- a/target/arm/helper.c > > +++ b/target/arm/helper.c > > @@ -504,29 +504,15 @@ void init_cpreg_list(ARMCPU *cpu) > > /* > > * Some registers are not accessible if EL3.NS=0 and EL3 is using AArch32 but > > * they are accessible when EL3 is using AArch64 regardless of EL3.NS. > > This could be rewritten as: > Some registers are not accessible from AArch32 EL3 if SCR.NS == 0. Done in v2. > > > - * > > - * access_el3_aa32ns: Used to check AArch32 register views. > > - * access_el3_aa32ns_aa64any: Used to check both AArch32/64 register views. > > */ > > -static CPAccessResult access_el3_aa32ns(CPUARMState *env, > > - const ARMCPRegInfo *ri, > > - bool isread) > > -{ > > - bool secure = arm_is_secure_below_el3(env); > > - > > - assert(!arm_el_is_aa64(env, 3)); > > - if (secure) { > > - return CP_ACCESS_TRAP_UNCATEGORIZED; > > - } > > - return CP_ACCESS_OK; > > -} > > - > > static CPAccessResult access_el3_aa32ns_aa64any(CPUARMState *env, > > const ARMCPRegInfo *ri, > > bool isread) > > { > > - if (!arm_el_is_aa64(env, 3)) { > > - return access_el3_aa32ns(env, ri, isread); > > + bool secure = arm_is_secure_below_el3(env); > > + > > + if (!arm_el_is_aa64(env, 3) && secure) { > > We could either rephrase this as > if (!is_a64(env) && arm_current_el(env) == 3 && > arm_is_secure_below_el3(env)) { Went for this logic in v2. > > or just have a comment > /* > * This access function is only used with .access = PL2_RW > * registers, so we are in AArch32 EL3 with SCR.NS == 0 > * if and only if EL3 is AArch32 and SCR.NS == 0, because > * if SCR.NS == 0 we cannot be in EL2. > */ > > depending on how much you proritize a more efficient test > over a more clearly correct test :-) > > > + return CP_ACCESS_TRAP_UNCATEGORIZED; > > } > > return CP_ACCESS_OK; > > } > > Also, once we don't have a distinction between two different > flavours of this access function we should use the simpler > "access_el2_aa32ns", rather than ending up using the longer > name for the one version of the function we're keeping. Done in v2. Thanks, Edgar