From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.7 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D9D9EC47254 for ; Tue, 5 May 2020 11:16:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B9B56206B9 for ; Tue, 5 May 2020 11:16:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728953AbgEELQc (ORCPT ); Tue, 5 May 2020 07:16:32 -0400 Received: from foss.arm.com ([217.140.110.172]:37558 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728497AbgEELQa (ORCPT ); Tue, 5 May 2020 07:16:30 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3BD6530E; Tue, 5 May 2020 04:16:30 -0700 (PDT) Received: from C02TD0UTHF1T.local (unknown [10.57.25.241]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 11C4A3F305; Tue, 5 May 2020 04:16:27 -0700 (PDT) Date: Tue, 5 May 2020 12:16:07 +0100 From: Mark Rutland To: Will Deacon Cc: Anshuman Khandual , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Marc Zyngier , James Morse , Suzuki K Poulose , kvmarm@lists.cs.columbia.edu, linux-kernel@vger.kernel.org Subject: Re: [PATCH V3 04/16] arm64/cpufeature: Introduce ID_PFR2 CPU register Message-ID: <20200505111607.GA82823@C02TD0UTHF1T.local> References: <1588426445-24344-1-git-send-email-anshuman.khandual@arm.com> <1588426445-24344-5-git-send-email-anshuman.khandual@arm.com> <20200505111241.GF19710@willie-the-truck> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200505111241.GF19710@willie-the-truck> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, May 05, 2020 at 12:12:41PM +0100, Will Deacon wrote: > On Sat, May 02, 2020 at 07:03:53PM +0530, Anshuman Khandual wrote: > > This adds basic building blocks required for ID_PFR2 CPU register which > > provides information about the AArch32 programmers model which must be > > interpreted along with ID_PFR0 and ID_PFR1 CPU registers. This is added > > per ARM DDI 0487F.a specification. > > > > Cc: Catalin Marinas > > Cc: Will Deacon > > Cc: Marc Zyngier > > Cc: Mark Rutland > > Cc: James Morse > > Cc: Suzuki K Poulose > > Cc: kvmarm@lists.cs.columbia.edu > > Cc: linux-arm-kernel@lists.infradead.org > > Cc: linux-kernel@vger.kernel.org > > > > Suggested-by: Mark Rutland > > Reviewed-by: Suzuki K Poulose > > Signed-off-by: Anshuman Khandual > > --- > > arch/arm64/include/asm/cpu.h | 1 + > > arch/arm64/include/asm/sysreg.h | 4 ++++ > > arch/arm64/kernel/cpufeature.c | 11 +++++++++++ > > arch/arm64/kernel/cpuinfo.c | 1 + > > arch/arm64/kvm/sys_regs.c | 2 +- > > 5 files changed, 18 insertions(+), 1 deletion(-) > > > > diff --git a/arch/arm64/include/asm/cpu.h b/arch/arm64/include/asm/cpu.h > > index b4a40535a3d8..464e828a994d 100644 > > --- a/arch/arm64/include/asm/cpu.h > > +++ b/arch/arm64/include/asm/cpu.h > > @@ -46,6 +46,7 @@ struct cpuinfo_arm64 { > > u32 reg_id_mmfr3; > > u32 reg_id_pfr0; > > u32 reg_id_pfr1; > > + u32 reg_id_pfr2; > > > > u32 reg_mvfr0; > > u32 reg_mvfr1; > > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > > index e5317a6367b6..c977449e02db 100644 > > --- a/arch/arm64/include/asm/sysreg.h > > +++ b/arch/arm64/include/asm/sysreg.h > > @@ -153,6 +153,7 @@ > > #define SYS_MVFR0_EL1 sys_reg(3, 0, 0, 3, 0) > > #define SYS_MVFR1_EL1 sys_reg(3, 0, 0, 3, 1) > > #define SYS_MVFR2_EL1 sys_reg(3, 0, 0, 3, 2) > > +#define SYS_ID_PFR2_EL1 sys_reg(3, 0, 0, 3, 4) > > nit: but please group these defines by name rather than encoding. So far we've *always* grouped these by encoding in this file, so can we keep things that way for now? Otherwise we're inconsistent with both schemes. Mark. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.7 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 332B3C47258 for ; Tue, 5 May 2020 11:16:35 +0000 (UTC) Received: from mm01.cs.columbia.edu (mm01.cs.columbia.edu [128.59.11.253]) by mail.kernel.org (Postfix) with ESMTP id C15752078C for ; Tue, 5 May 2020 11:16:34 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C15752078C Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=kvmarm-bounces@lists.cs.columbia.edu Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 3C4DC4B319; Tue, 5 May 2020 07:16:34 -0400 (EDT) X-Virus-Scanned: at lists.cs.columbia.edu Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 56uRz1nHkdrR; Tue, 5 May 2020 07:16:33 -0400 (EDT) Received: from mm01.cs.columbia.edu (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 0428D4B31A; Tue, 5 May 2020 07:16:33 -0400 (EDT) Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 189944B318 for ; Tue, 5 May 2020 07:16:32 -0400 (EDT) X-Virus-Scanned: at lists.cs.columbia.edu Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id DyCfMao-WN3E for ; Tue, 5 May 2020 07:16:30 -0400 (EDT) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mm01.cs.columbia.edu (Postfix) with ESMTP id C72F64B315 for ; Tue, 5 May 2020 07:16:30 -0400 (EDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3BD6530E; Tue, 5 May 2020 04:16:30 -0700 (PDT) Received: from C02TD0UTHF1T.local (unknown [10.57.25.241]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 11C4A3F305; Tue, 5 May 2020 04:16:27 -0700 (PDT) Date: Tue, 5 May 2020 12:16:07 +0100 From: Mark Rutland To: Will Deacon Subject: Re: [PATCH V3 04/16] arm64/cpufeature: Introduce ID_PFR2 CPU register Message-ID: <20200505111607.GA82823@C02TD0UTHF1T.local> References: <1588426445-24344-1-git-send-email-anshuman.khandual@arm.com> <1588426445-24344-5-git-send-email-anshuman.khandual@arm.com> <20200505111241.GF19710@willie-the-truck> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200505111241.GF19710@willie-the-truck> Cc: Catalin Marinas , Anshuman Khandual , linux-kernel@vger.kernel.org, Marc Zyngier , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu On Tue, May 05, 2020 at 12:12:41PM +0100, Will Deacon wrote: > On Sat, May 02, 2020 at 07:03:53PM +0530, Anshuman Khandual wrote: > > This adds basic building blocks required for ID_PFR2 CPU register which > > provides information about the AArch32 programmers model which must be > > interpreted along with ID_PFR0 and ID_PFR1 CPU registers. This is added > > per ARM DDI 0487F.a specification. > > > > Cc: Catalin Marinas > > Cc: Will Deacon > > Cc: Marc Zyngier > > Cc: Mark Rutland > > Cc: James Morse > > Cc: Suzuki K Poulose > > Cc: kvmarm@lists.cs.columbia.edu > > Cc: linux-arm-kernel@lists.infradead.org > > Cc: linux-kernel@vger.kernel.org > > > > Suggested-by: Mark Rutland > > Reviewed-by: Suzuki K Poulose > > Signed-off-by: Anshuman Khandual > > --- > > arch/arm64/include/asm/cpu.h | 1 + > > arch/arm64/include/asm/sysreg.h | 4 ++++ > > arch/arm64/kernel/cpufeature.c | 11 +++++++++++ > > arch/arm64/kernel/cpuinfo.c | 1 + > > arch/arm64/kvm/sys_regs.c | 2 +- > > 5 files changed, 18 insertions(+), 1 deletion(-) > > > > diff --git a/arch/arm64/include/asm/cpu.h b/arch/arm64/include/asm/cpu.h > > index b4a40535a3d8..464e828a994d 100644 > > --- a/arch/arm64/include/asm/cpu.h > > +++ b/arch/arm64/include/asm/cpu.h > > @@ -46,6 +46,7 @@ struct cpuinfo_arm64 { > > u32 reg_id_mmfr3; > > u32 reg_id_pfr0; > > u32 reg_id_pfr1; > > + u32 reg_id_pfr2; > > > > u32 reg_mvfr0; > > u32 reg_mvfr1; > > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > > index e5317a6367b6..c977449e02db 100644 > > --- a/arch/arm64/include/asm/sysreg.h > > +++ b/arch/arm64/include/asm/sysreg.h > > @@ -153,6 +153,7 @@ > > #define SYS_MVFR0_EL1 sys_reg(3, 0, 0, 3, 0) > > #define SYS_MVFR1_EL1 sys_reg(3, 0, 0, 3, 1) > > #define SYS_MVFR2_EL1 sys_reg(3, 0, 0, 3, 2) > > +#define SYS_ID_PFR2_EL1 sys_reg(3, 0, 0, 3, 4) > > nit: but please group these defines by name rather than encoding. So far we've *always* grouped these by encoding in this file, so can we keep things that way for now? Otherwise we're inconsistent with both schemes. Mark. _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6D3B8C47259 for ; Tue, 5 May 2020 11:16:34 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2706F206B9 for ; Tue, 5 May 2020 11:16:34 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="Km1vMRML" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 2706F206B9 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=r6BC7Q/L4/YexmqceWVXrtXK+4Nft6NQhHvTZNAYJVU=; b=Km1vMRMLqIKlWR mS0cFhSNx+ECykZ9aOQ9Fps62eLnvyCFNR3xVyzGT4PX/swVGx2mY0LuL87TUW3t8MpuTwSkqHdNp C02Ob4zjNWgirXzcJ6ZZ6/Ae28ytenphuTkeQSpQcNzR18VoQSzTGyLRuWlu9VpIUlxcGvkGwMx6k 9uj8zzmdTM+zVrK6lwaHrEdJDm1UCjTZg3HVuRzMmJpbrfXVN/Nk4Tn8fqQuEGkHiL/BTf12nnJle y2z+tvJEOJtwk7DHumASmcCzQeJ8N1F8ezKp0ZeBH8dWMPvRZPP05aTYVOlaiAoltOswdJiFAO5Z4 rgyg1NfkPy9wv8SH1SMQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jVvYv-0000Cs-JN; Tue, 05 May 2020 11:16:33 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jVvYs-0000C2-To for linux-arm-kernel@lists.infradead.org; Tue, 05 May 2020 11:16:32 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3BD6530E; Tue, 5 May 2020 04:16:30 -0700 (PDT) Received: from C02TD0UTHF1T.local (unknown [10.57.25.241]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 11C4A3F305; Tue, 5 May 2020 04:16:27 -0700 (PDT) Date: Tue, 5 May 2020 12:16:07 +0100 From: Mark Rutland To: Will Deacon Subject: Re: [PATCH V3 04/16] arm64/cpufeature: Introduce ID_PFR2 CPU register Message-ID: <20200505111607.GA82823@C02TD0UTHF1T.local> References: <1588426445-24344-1-git-send-email-anshuman.khandual@arm.com> <1588426445-24344-5-git-send-email-anshuman.khandual@arm.com> <20200505111241.GF19710@willie-the-truck> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200505111241.GF19710@willie-the-truck> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200505_041631_011143_BA9C07DA X-CRM114-Status: GOOD ( 15.96 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Suzuki K Poulose , Catalin Marinas , Anshuman Khandual , linux-kernel@vger.kernel.org, James Morse , Marc Zyngier , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, May 05, 2020 at 12:12:41PM +0100, Will Deacon wrote: > On Sat, May 02, 2020 at 07:03:53PM +0530, Anshuman Khandual wrote: > > This adds basic building blocks required for ID_PFR2 CPU register which > > provides information about the AArch32 programmers model which must be > > interpreted along with ID_PFR0 and ID_PFR1 CPU registers. This is added > > per ARM DDI 0487F.a specification. > > > > Cc: Catalin Marinas > > Cc: Will Deacon > > Cc: Marc Zyngier > > Cc: Mark Rutland > > Cc: James Morse > > Cc: Suzuki K Poulose > > Cc: kvmarm@lists.cs.columbia.edu > > Cc: linux-arm-kernel@lists.infradead.org > > Cc: linux-kernel@vger.kernel.org > > > > Suggested-by: Mark Rutland > > Reviewed-by: Suzuki K Poulose > > Signed-off-by: Anshuman Khandual > > --- > > arch/arm64/include/asm/cpu.h | 1 + > > arch/arm64/include/asm/sysreg.h | 4 ++++ > > arch/arm64/kernel/cpufeature.c | 11 +++++++++++ > > arch/arm64/kernel/cpuinfo.c | 1 + > > arch/arm64/kvm/sys_regs.c | 2 +- > > 5 files changed, 18 insertions(+), 1 deletion(-) > > > > diff --git a/arch/arm64/include/asm/cpu.h b/arch/arm64/include/asm/cpu.h > > index b4a40535a3d8..464e828a994d 100644 > > --- a/arch/arm64/include/asm/cpu.h > > +++ b/arch/arm64/include/asm/cpu.h > > @@ -46,6 +46,7 @@ struct cpuinfo_arm64 { > > u32 reg_id_mmfr3; > > u32 reg_id_pfr0; > > u32 reg_id_pfr1; > > + u32 reg_id_pfr2; > > > > u32 reg_mvfr0; > > u32 reg_mvfr1; > > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > > index e5317a6367b6..c977449e02db 100644 > > --- a/arch/arm64/include/asm/sysreg.h > > +++ b/arch/arm64/include/asm/sysreg.h > > @@ -153,6 +153,7 @@ > > #define SYS_MVFR0_EL1 sys_reg(3, 0, 0, 3, 0) > > #define SYS_MVFR1_EL1 sys_reg(3, 0, 0, 3, 1) > > #define SYS_MVFR2_EL1 sys_reg(3, 0, 0, 3, 2) > > +#define SYS_ID_PFR2_EL1 sys_reg(3, 0, 0, 3, 4) > > nit: but please group these defines by name rather than encoding. So far we've *always* grouped these by encoding in this file, so can we keep things that way for now? Otherwise we're inconsistent with both schemes. Mark. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel