From mboxrd@z Thu Jan 1 00:00:00 1970 From: Tom Rini Date: Thu, 7 May 2020 14:52:54 -0400 Subject: [PATCH v4 05/12] phy: atheros: Clarify the intention of ar8021_config In-Reply-To: <20200506221159.1298-6-michael@walle.cc> References: <20200506221159.1298-1-michael@walle.cc> <20200506221159.1298-6-michael@walle.cc> Message-ID: <20200507185254.GS12564@bill-the-cat> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Thu, May 07, 2020 at 12:11:52AM +0200, Michael Walle wrote: > From: Vladimir Oltean > > Debug register 5 contains TX_CLK DELAY at bit 8 and reserved values at > the other bit positions, just like the other PHYs in the family do. > Therefore, it is not necessary to hardcode the reserved values, but > instead simply follow the read-modify-write procedure from the common > function. > > Signed-off-by: Vladimir Oltean > Acked-by: Joe Hershberger Applied to u-boot/master, thanks! -- Tom -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 659 bytes Desc: not available URL: