From mboxrd@z Thu Jan 1 00:00:00 1970 From: Tom Rini Date: Thu, 7 May 2020 14:53:30 -0400 Subject: [PATCH v4 10/12] phy: atheros: add device tree bindings and config In-Reply-To: <20200506221159.1298-11-michael@walle.cc> References: <20200506221159.1298-1-michael@walle.cc> <20200506221159.1298-11-michael@walle.cc> Message-ID: <20200507185330.GX12564@bill-the-cat> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Thu, May 07, 2020 at 12:11:57AM +0200, Michael Walle wrote: > Add support for configuring the CLK_25M pin as well as the RGMII I/O > voltage by the device tree. > > By default the AT803x PHYs outputs the 25MHz clock of the XTAL input. > But this output can also be changed by software to other frequencies. > This commit introduces a generic way to configure this output. > > Also the PHY supports different RGMII I/O voltages: 1.5V, 1.8V and 2.5V. > An internal LDO is able to provide 1.5V (default) and 1.8V. The 2.5V > option needs an external supply voltage. This commit adds support to > switch the internal LDO to 1.8V. > > Signed-off-by: Michael Walle > Acked-by: Joe Hershberger Applied to u-boot/master, thanks! -- Tom -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 659 bytes Desc: not available URL: