From mboxrd@z Thu Jan 1 00:00:00 1970 From: Tom Rini Date: Thu, 7 May 2020 14:53:43 -0400 Subject: [PATCH v4 11/12] phy: atheros: ar8035: remove static clock config In-Reply-To: <20200506221159.1298-12-michael@walle.cc> References: <20200506221159.1298-1-michael@walle.cc> <20200506221159.1298-12-michael@walle.cc> Message-ID: <20200507185343.GY12564@bill-the-cat> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Thu, May 07, 2020 at 12:11:58AM +0200, Michael Walle wrote: > We can configure the clock output in the device tree. Disable the > hardcoded one in here. This is highly board-specific and should have > never been enabled in the PHY driver. > > If bisecting shows that this commit breaks your board it probably > depends on the clock output of your Atheros AR8035 PHY. Please have a > look at doc/device-tree-bindings/net/phy/atheros.txt. You need to set > "clk-out-frequency = <125000000>" because that value was the hardcoded > value until this commit. > > Signed-off-by: Michael Walle > Acked-by: Joe Hershberger Applied to u-boot/master, thanks! -- Tom -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 659 bytes Desc: not available URL: