* [PATCH v8 00/21] RISC-V SiFive FU540 support SPL
@ 2020-05-09 14:30 Pragnesh Patel
2020-05-09 14:30 ` [PATCH v8 01/21] misc: add driver for the SiFive otp controller Pragnesh Patel
` (20 more replies)
0 siblings, 21 replies; 31+ messages in thread
From: Pragnesh Patel @ 2020-05-09 14:30 UTC (permalink / raw)
To: u-boot
This series add support for SPL to FU540. U-Boot SPL can boot from
L2 LIM (0x0800_0000) and jump to OpenSBI(FW_DYNAMIC firmware) and
U-Boot proper from MMC devices.
This series depends on:
[1] https://patchwork.ozlabs.org/patch/1281853
[2] https://patchwork.ozlabs.org/patch/1281852
All these together is available for testing here [3]
[3] https://github.com/pragnesh26992/u-boot/tree/spl
How to test this patch:
1) Go to OpenSBI-dir : make PLATFORM=generic FW_DYNAMIC=y
2) export OPENSBI=<path/to/opensbi/build/platform/generic/firmware/fw_dynamic.bin>
3) Change to u-boot-dir
4) make sifive_fu540_defconfig
5) make all
6) Format the SD card (make sure the disk has GPT, otherwise use gdisk to switch)
# sudo sgdisk --clear \
> --set-alignment=2 \
> --new=1:34:2081 --change-name=1:loader1 --typecode=1:5B193300-FC78-40CD-8002-E86C45580B47 \
> --new=2:2082:10273 --change-name=2:loader2 --typecode=2:2E54B353-1271-4842-806F-E436D6AF6985 \
> --new=3:10274: --change-name=3:rootfs --typecode=3:0FC63DAF-8483-4772-8E79-3D69D8477DE4 \
> /dev/sda
7) sudo dd if=spl/u-boot-spl.bin of=/dev/sda seek=34
8) sudo dd if=u-boot.itb of=/dev/sda seek=2082
Changes in v8:
- Remove SPL_CRC7_SUPPORT Kconfig option and compile
crc7.o when CONFIG_MMC_SPI selected
- Add "TODO" in drivers/ram/sifive/sdram_fu540.c
- Remove unnecessary TODO from drivers/clk/sifive/fu540-prci.c
- Make fu540-hifive-unleashed-a00-sdram-ddr4.dtsi file dual-licensed
- Add 2 new patches
sifive: fu540: Add sample SD gpt partition layout
(https://patchwork.ozlabs.org/patch/1092)
sifive: fu540: Add U-Boot proper sector start
(https://patchwork.ozlabs.org/patch/1093)
- Remove patch
riscv: Enable cpu clock if it is present
(https://patchwork.ozlabs.org/patch/1281573)
- Update doc/board/sifive/fu540.rst for PLATFORM=generic
Changes in v7:
- Standardize SD gpt partition layout
- Add delay for SiFive OTP driver
- Use DM way for corepll and ddrpll
- Add new cpu fu540 (arch/riscv/cpu/fu540)
- Update document for FU540 (doc/board/sifive/fu540.rst)
Changes in v6:
- Typo Correction
- Make fu540-c000-u-boot.dtsi and hifive-unleashed-a00-u-boot.dtsi
Dual Licensed
- Sync Hifive unleashed dts from Linux
- Add arch/riscv/fu540 for FU540 specific code
Changes in v5:
- Return read/write bytes for sifive_otp_read and sifive_otp_write
- Correct Palmer's email address
Changes in v4:
- Split misc DM driver patch into multiple patches
- Added new SPL_CRC7_SUPPORT Kconfig option
- Added DM driver for DDR
- Added clk_enable and clk_disable ops in SiFive PRCI driver
- Added early clock initialization for SPL in SiFive PRCI driver
- Added SPL config options in sifive_fu540_defconfig instead of
creatiing a new config file for SPL
- Update fu540.rst on how to build and flash U-boot SPL
Changes in v3:
- Remove arch-fu540 and arch-sifive from arch/riscv/include/asm/
- Split SPL patches into DDR and SPL and spl defconfig
- Update fu540/MAINTAINERS file
- Update fu540.rst on how to build and flash U-boot SPL
Changes in v2:
- Add DM driver Sifive OTP
- Split SPL patches into multiple patches
- Add a seprate patch for _image_binary_end and crc7.c
- Add a seprate patch to add board -u-boot.dtsi files
- Update FU540 RISC-V documentation
Jagan Teki (2):
sifive: fu540: Add sample SD gpt partition layout
sifive: fu540: Add U-Boot proper sector start
Pragnesh Patel (19):
misc: add driver for the SiFive otp controller
riscv: sifive: fu540: Use OTP DM driver for serial environment
variable
riscv: Add _image_binary_end for SPL
lib: Makefile: build crc7.c when CONFIG_MMC_SPI
riscv: sifive: dts: fu540: Add board -u-boot.dtsi files
sifive: fu540: add ddr driver
sifive: dts: fu540: Add DDR controller and phy register settings
riscv: sifive: dts: fu540: add U-Boot dmc node
clk: sifive: fu540-prci: Add clock enable and disable ops
clk: sifive: fu540-prci: Add ddr clock initialization in SPL
clk: sifive: fu540-prci: Add ehternet clock initialization in SPL
riscv: dts: sifive: Sync hifive-unleashed-a00 dts from linux
riscv: cpu: fu540: Add support for cpu fu540
riscv: Add place-holder for driver compilation
riscv: sifive: fu540: add SPL configuration
configs: fu540: Add config options for U-Boot SPL
sifive: dts: fu540: Enable L2 Cache in U-Boot
riscv: sifive: fu540: enable all cache ways from U-Boot proper
doc: sifive: fu540: Add description for OpenSBI generic platform
arch/riscv/Kconfig | 1 +
arch/riscv/cpu/fu540/Kconfig | 15 +
arch/riscv/cpu/fu540/Makefile | 12 +
arch/riscv/cpu/fu540/cache.c | 53 +
arch/riscv/cpu/fu540/cpu.c | 22 +
arch/riscv/cpu/fu540/dram.c | 38 +
arch/riscv/cpu/fu540/spl.c | 23 +
arch/riscv/cpu/u-boot-spl.lds | 1 +
arch/riscv/dts/fu540-c000-u-boot.dtsi | 88 +
arch/riscv/dts/fu540-c000.dtsi | 37 +-
...fu540-hifive-unleashed-a00-sdram-ddr4.dtsi | 1489 +++++++++++++++++
.../dts/hifive-unleashed-a00-u-boot.dtsi | 22 +
arch/riscv/dts/hifive-unleashed-a00.dts | 9 +
arch/riscv/include/asm/arch-fu540/cache.h | 14 +
arch/riscv/include/asm/arch-fu540/clk.h | 14 +
arch/riscv/include/asm/arch-fu540/gpio.h | 38 +
arch/riscv/include/asm/arch-fu540/spl.h | 14 +
board/sifive/fu540/Kconfig | 18 +-
board/sifive/fu540/Makefile | 4 +
board/sifive/fu540/fu540.c | 145 +-
board/sifive/fu540/spl.c | 72 +
common/spl/Kconfig | 3 +-
configs/sifive_fu540_defconfig | 8 +
doc/board/sifive/fu540.rst | 145 +-
drivers/clk/sifive/fu540-prci.c | 196 ++-
drivers/misc/Kconfig | 7 +
drivers/misc/Makefile | 1 +
drivers/misc/sifive-otp.c | 273 +++
drivers/ram/Kconfig | 1 +
drivers/ram/Makefile | 2 +
drivers/ram/sifive/Kconfig | 13 +
drivers/ram/sifive/Makefile | 6 +
drivers/ram/sifive/sdram_fu540.c | 416 +++++
include/configs/sifive-fu540.h | 31 +
lib/Makefile | 2 +-
35 files changed, 3127 insertions(+), 106 deletions(-)
create mode 100644 arch/riscv/cpu/fu540/Kconfig
create mode 100644 arch/riscv/cpu/fu540/Makefile
create mode 100644 arch/riscv/cpu/fu540/cache.c
create mode 100644 arch/riscv/cpu/fu540/cpu.c
create mode 100644 arch/riscv/cpu/fu540/dram.c
create mode 100644 arch/riscv/cpu/fu540/spl.c
create mode 100644 arch/riscv/dts/fu540-c000-u-boot.dtsi
create mode 100644 arch/riscv/dts/fu540-hifive-unleashed-a00-sdram-ddr4.dtsi
create mode 100644 arch/riscv/include/asm/arch-fu540/cache.h
create mode 100644 arch/riscv/include/asm/arch-fu540/clk.h
create mode 100644 arch/riscv/include/asm/arch-fu540/gpio.h
create mode 100644 arch/riscv/include/asm/arch-fu540/spl.h
create mode 100644 board/sifive/fu540/spl.c
create mode 100644 drivers/misc/sifive-otp.c
create mode 100644 drivers/ram/sifive/Kconfig
create mode 100644 drivers/ram/sifive/Makefile
create mode 100644 drivers/ram/sifive/sdram_fu540.c
--
2.17.1
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH v8 01/21] misc: add driver for the SiFive otp controller
2020-05-09 14:30 [PATCH v8 00/21] RISC-V SiFive FU540 support SPL Pragnesh Patel
@ 2020-05-09 14:30 ` Pragnesh Patel
2020-05-09 14:30 ` [PATCH v8 02/21] riscv: sifive: fu540: Use OTP DM driver for serial environment variable Pragnesh Patel
` (19 subsequent siblings)
20 siblings, 0 replies; 31+ messages in thread
From: Pragnesh Patel @ 2020-05-09 14:30 UTC (permalink / raw)
To: u-boot
Added a misc driver to handle OTP memory in SiFive SoCs.
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
---
drivers/misc/Kconfig | 7 +
drivers/misc/Makefile | 1 +
drivers/misc/sifive-otp.c | 273 ++++++++++++++++++++++++++++++++++++++
3 files changed, 281 insertions(+)
create mode 100644 drivers/misc/sifive-otp.c
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 766402745d..59f758661e 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -68,6 +68,13 @@ config ROCKCHIP_OTP
addressing and a length or through child-nodes that are generated
based on the e-fuse map retrieved from the DTS.
+config SIFIVE_OTP
+ bool "SiFive eMemory OTP driver"
+ depends on MISC
+ help
+ Enable support for reading and writing the eMemory OTP on the
+ SiFive SoCs.
+
config VEXPRESS_CONFIG
bool "Enable support for Arm Versatile Express config bus"
depends on MISC
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 68e0e7ad17..ed6bfc1356 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -58,6 +58,7 @@ obj-$(CONFIG_$(SPL_)PWRSEQ) += pwrseq-uclass.o
obj-$(CONFIG_QFW) += qfw.o
obj-$(CONFIG_ROCKCHIP_EFUSE) += rockchip-efuse.o
obj-$(CONFIG_ROCKCHIP_OTP) += rockchip-otp.o
+obj-$(CONFIG_SIFIVE_OTP) += sifive-otp.o
obj-$(CONFIG_SANDBOX) += syscon_sandbox.o misc_sandbox.o
obj-$(CONFIG_SMSC_LPC47M) += smsc_lpc47m.o
obj-$(CONFIG_SMSC_SIO1007) += smsc_sio1007.o
diff --git a/drivers/misc/sifive-otp.c b/drivers/misc/sifive-otp.c
new file mode 100644
index 0000000000..6a788f540d
--- /dev/null
+++ b/drivers/misc/sifive-otp.c
@@ -0,0 +1,273 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * This is a driver for the eMemory EG004K32TQ028XW01 NeoFuse
+ * One-Time-Programmable (OTP) memory used within the SiFive FU540.
+ * It is documented in the FU540 manual here:
+ * https://www.sifive.com/documentation/chips/freedom-u540-c000-manual/
+ *
+ * Copyright (C) 2018 Philipp Hug <philipp@hug.cx>
+ * Copyright (C) 2018 Joey Hewitt <joey@joeyhewitt.com>
+ *
+ * Copyright (C) 2020 SiFive, Inc
+ */
+
+/*
+ * The FU540 stores 4096x32 bit (16KiB) values.
+ * Index 0x00-0xff are reserved for SiFive internal use. (first 1KiB)
+ * Right now first 1KiB is used to store only serial number.
+ */
+
+#include <common.h>
+#include <dm/device.h>
+#include <dm/read.h>
+#include <linux/io.h>
+#include <misc.h>
+
+#define BYTES_PER_FUSE 4
+
+#define PA_RESET_VAL 0x00
+#define PAS_RESET_VAL 0x00
+#define PAIO_RESET_VAL 0x00
+#define PDIN_RESET_VAL 0x00
+#define PTM_RESET_VAL 0x00
+
+#define PCLK_ENABLE_VAL BIT(0)
+#define PCLK_DISABLE_VAL 0x00
+
+#define PWE_WRITE_ENABLE BIT(0)
+#define PWE_WRITE_DISABLE 0x00
+
+#define PTM_FUSE_PROGRAM_VAL BIT(1)
+
+#define PCE_ENABLE_INPUT BIT(0)
+#define PCE_DISABLE_INPUT 0x00
+
+#define PPROG_ENABLE_INPUT BIT(0)
+#define PPROG_DISABLE_INPUT 0x00
+
+#define PTRIM_ENABLE_INPUT BIT(0)
+#define PTRIM_DISABLE_INPUT 0x00
+
+#define PDSTB_DEEP_STANDBY_ENABLE BIT(0)
+#define PDSTB_DEEP_STANDBY_DISABLE 0x00
+
+/* Tpw - Program Pulse width delay */
+#define TPW_DELAY 20
+
+/* Tpwi - Program Pulse interval delay */
+#define TPWI_DELAY 5
+
+/* Tasp - Program address setup delay */
+#define TASP_DELAY 1
+
+/* Tcd - read data access delay */
+#define TCD_DELAY 40
+
+/* Tkl - clok pulse low delay */
+#define TKL_DELAY 10
+
+/* Tms - PTM mode setup delay */
+#define TMS_DELAY 1
+
+struct sifive_otp_regs {
+ u32 pa; /* Address input */
+ u32 paio; /* Program address input */
+ u32 pas; /* Program redundancy cell selection input */
+ u32 pce; /* OTP Macro enable input */
+ u32 pclk; /* Clock input */
+ u32 pdin; /* Write data input */
+ u32 pdout; /* Read data output */
+ u32 pdstb; /* Deep standby mode enable input (active low) */
+ u32 pprog; /* Program mode enable input */
+ u32 ptc; /* Test column enable input */
+ u32 ptm; /* Test mode enable input */
+ u32 ptm_rep;/* Repair function test mode enable input */
+ u32 ptr; /* Test row enable input */
+ u32 ptrim; /* Repair function enable input */
+ u32 pwe; /* Write enable input (defines program cycle) */
+};
+
+struct sifive_otp_platdata {
+ struct sifive_otp_regs __iomem *regs;
+ u32 total_fuses;
+};
+
+/*
+ * offset and size are assumed aligned to the size of the fuses (32-bit).
+ */
+static int sifive_otp_read(struct udevice *dev, int offset,
+ void *buf, int size)
+{
+ struct sifive_otp_platdata *plat = dev_get_platdata(dev);
+ struct sifive_otp_regs *regs = (struct sifive_otp_regs *)plat->regs;
+
+ /* Check if offset and size are multiple of BYTES_PER_FUSE */
+ if ((size % BYTES_PER_FUSE) || (offset % BYTES_PER_FUSE)) {
+ printf("%s: size and offset must be multiple of 4.\n",
+ __func__);
+ return -EINVAL;
+ }
+
+ int fuseidx = offset / BYTES_PER_FUSE;
+ int fusecount = size / BYTES_PER_FUSE;
+
+ /* check bounds */
+ if (offset < 0 || size < 0)
+ return -EINVAL;
+ if (fuseidx >= plat->total_fuses)
+ return -EINVAL;
+ if ((fuseidx + fusecount) > plat->total_fuses)
+ return -EINVAL;
+
+ u32 fusebuf[fusecount];
+
+ /* init OTP */
+ writel(PDSTB_DEEP_STANDBY_ENABLE, ®s->pdstb);
+ writel(PTRIM_ENABLE_INPUT, ®s->ptrim);
+ writel(PCE_ENABLE_INPUT, ®s->pce);
+
+ /* read all requested fuses */
+ for (unsigned int i = 0; i < fusecount; i++, fuseidx++) {
+ writel(fuseidx, ®s->pa);
+
+ /* cycle clock to read */
+ writel(PCLK_ENABLE_VAL, ®s->pclk);
+ ndelay(TCD_DELAY * 1000);
+ writel(PCLK_DISABLE_VAL, ®s->pclk);
+ ndelay(TKL_DELAY * 1000);
+
+ /* read the value */
+ fusebuf[i] = readl(®s->pdout);
+ }
+
+ /* shut down */
+ writel(PCE_DISABLE_INPUT, ®s->pce);
+ writel(PTRIM_DISABLE_INPUT, ®s->ptrim);
+ writel(PDSTB_DEEP_STANDBY_DISABLE, ®s->pdstb);
+
+ /* copy out */
+ memcpy(buf, fusebuf, size);
+
+ return size;
+}
+
+/*
+ * Caution:
+ * OTP can be written only once, so use carefully.
+ *
+ * offset and size are assumed aligned to the size of the fuses (32-bit).
+ */
+static int sifive_otp_write(struct udevice *dev, int offset,
+ const void *buf, int size)
+{
+ struct sifive_otp_platdata *plat = dev_get_platdata(dev);
+ struct sifive_otp_regs *regs = (struct sifive_otp_regs *)plat->regs;
+
+ /* Check if offset and size are multiple of BYTES_PER_FUSE */
+ if ((size % BYTES_PER_FUSE) || (offset % BYTES_PER_FUSE)) {
+ printf("%s: size and offset must be multiple of 4.\n",
+ __func__);
+ return -EINVAL;
+ }
+
+ int fuseidx = offset / BYTES_PER_FUSE;
+ int fusecount = size / BYTES_PER_FUSE;
+ u32 *write_buf = (u32 *)buf;
+ u32 write_data;
+ int i, pas, bit;
+
+ /* check bounds */
+ if (offset < 0 || size < 0)
+ return -EINVAL;
+ if (fuseidx >= plat->total_fuses)
+ return -EINVAL;
+ if ((fuseidx + fusecount) > plat->total_fuses)
+ return -EINVAL;
+
+ /* init OTP */
+ writel(PDSTB_DEEP_STANDBY_ENABLE, ®s->pdstb);
+ writel(PTRIM_ENABLE_INPUT, ®s->ptrim);
+
+ /* reset registers */
+ writel(PCLK_DISABLE_VAL, ®s->pclk);
+ writel(PA_RESET_VAL, ®s->pa);
+ writel(PAS_RESET_VAL, ®s->pas);
+ writel(PAIO_RESET_VAL, ®s->paio);
+ writel(PDIN_RESET_VAL, ®s->pdin);
+ writel(PWE_WRITE_DISABLE, ®s->pwe);
+ writel(PTM_FUSE_PROGRAM_VAL, ®s->ptm);
+ ndelay(TMS_DELAY * 1000);
+
+ writel(PCE_ENABLE_INPUT, ®s->pce);
+ writel(PPROG_ENABLE_INPUT, ®s->pprog);
+
+ /* write all requested fuses */
+ for (i = 0; i < fusecount; i++, fuseidx++) {
+ writel(fuseidx, ®s->pa);
+ write_data = *(write_buf++);
+
+ for (pas = 0; pas < 2; pas++) {
+ writel(pas, ®s->pas);
+
+ for (bit = 0; bit < 32; bit++) {
+ writel(bit, ®s->paio);
+ writel(((write_data >> bit) & 1),
+ ®s->pdin);
+ ndelay(TASP_DELAY * 1000);
+
+ writel(PWE_WRITE_ENABLE, ®s->pwe);
+ udelay(TPW_DELAY);
+ writel(PWE_WRITE_DISABLE, ®s->pwe);
+ udelay(TPWI_DELAY);
+ }
+ }
+
+ writel(PAS_RESET_VAL, ®s->pas);
+ }
+
+ /* shut down */
+ writel(PWE_WRITE_DISABLE, ®s->pwe);
+ writel(PPROG_DISABLE_INPUT, ®s->pprog);
+ writel(PCE_DISABLE_INPUT, ®s->pce);
+ writel(PTM_RESET_VAL, ®s->ptm);
+
+ writel(PTRIM_DISABLE_INPUT, ®s->ptrim);
+ writel(PDSTB_DEEP_STANDBY_DISABLE, ®s->pdstb);
+
+ return size;
+}
+
+static int sifive_otp_ofdata_to_platdata(struct udevice *dev)
+{
+ struct sifive_otp_platdata *plat = dev_get_platdata(dev);
+ int ret;
+
+ plat->regs = dev_read_addr_ptr(dev);
+
+ ret = dev_read_u32(dev, "fuse-count", &plat->total_fuses);
+ if (ret < 0) {
+ pr_err("\"fuse-count\" not found\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static const struct misc_ops sifive_otp_ops = {
+ .read = sifive_otp_read,
+ .write = sifive_otp_write,
+};
+
+static const struct udevice_id sifive_otp_ids[] = {
+ { .compatible = "sifive,fu540-c000-otp" },
+ {}
+};
+
+U_BOOT_DRIVER(sifive_otp) = {
+ .name = "sifive_otp",
+ .id = UCLASS_MISC,
+ .of_match = sifive_otp_ids,
+ .ofdata_to_platdata = sifive_otp_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct sifive_otp_platdata),
+ .ops = &sifive_otp_ops,
+};
--
2.17.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v8 02/21] riscv: sifive: fu540: Use OTP DM driver for serial environment variable
2020-05-09 14:30 [PATCH v8 00/21] RISC-V SiFive FU540 support SPL Pragnesh Patel
2020-05-09 14:30 ` [PATCH v8 01/21] misc: add driver for the SiFive otp controller Pragnesh Patel
@ 2020-05-09 14:30 ` Pragnesh Patel
2020-05-09 14:30 ` [PATCH v8 03/21] riscv: Add _image_binary_end for SPL Pragnesh Patel
` (18 subsequent siblings)
20 siblings, 0 replies; 31+ messages in thread
From: Pragnesh Patel @ 2020-05-09 14:30 UTC (permalink / raw)
To: u-boot
Use the OTP DM driver to set the serial environment variable.
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
---
arch/riscv/dts/fu540-c000-u-boot.dtsi | 14 +++
.../dts/hifive-unleashed-a00-u-boot.dtsi | 2 +
board/sifive/fu540/Kconfig | 2 +
board/sifive/fu540/fu540.c | 111 ++++++------------
4 files changed, 57 insertions(+), 72 deletions(-)
create mode 100644 arch/riscv/dts/fu540-c000-u-boot.dtsi
diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi b/arch/riscv/dts/fu540-c000-u-boot.dtsi
new file mode 100644
index 0000000000..db55773bd2
--- /dev/null
+++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * (C) Copyright 2019 SiFive, Inc
+ */
+
+/ {
+ soc {
+ otp: otp at 10070000 {
+ compatible = "sifive,fu540-c000-otp";
+ reg = <0x0 0x10070000 0x0 0x0FFF>;
+ fuse-count = <0x1000>;
+ };
+ };
+};
diff --git a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
index 2aebfab646..9af089ffe7 100644
--- a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
+++ b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
@@ -3,6 +3,8 @@
* Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com>
*/
+#include "fu540-c000-u-boot.dtsi"
+
/ {
aliases {
spi0 = &qspi0;
diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig
index 75661f35f8..4330ac4491 100644
--- a/board/sifive/fu540/Kconfig
+++ b/board/sifive/fu540/Kconfig
@@ -51,5 +51,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
imply SIFIVE_GPIO
imply CMD_GPIO
imply SMP
+ imply MISC
+ imply SIFIVE_OTP
endif
diff --git a/board/sifive/fu540/fu540.c b/board/sifive/fu540/fu540.c
index 47a2090251..540638c919 100644
--- a/board/sifive/fu540/fu540.c
+++ b/board/sifive/fu540/fu540.c
@@ -10,94 +10,61 @@
#include <dm.h>
#include <linux/delay.h>
#include <linux/io.h>
+#include <misc.h>
+
+/*
+ * This define is a value used for error/unknown serial.
+ * If we really care about distinguishing errors and 0 is
+ * valid, we'll need a different one.
+ */
+#define ERROR_READING_SERIAL_NUMBER 0
#ifdef CONFIG_MISC_INIT_R
-#define FU540_OTP_BASE_ADDR 0x10070000
-
-struct fu540_otp_regs {
- u32 pa; /* Address input */
- u32 paio; /* Program address input */
- u32 pas; /* Program redundancy cell selection input */
- u32 pce; /* OTP Macro enable input */
- u32 pclk; /* Clock input */
- u32 pdin; /* Write data input */
- u32 pdout; /* Read data output */
- u32 pdstb; /* Deep standby mode enable input (active low) */
- u32 pprog; /* Program mode enable input */
- u32 ptc; /* Test column enable input */
- u32 ptm; /* Test mode enable input */
- u32 ptm_rep;/* Repair function test mode enable input */
- u32 ptr; /* Test row enable input */
- u32 ptrim; /* Repair function enable input */
- u32 pwe; /* Write enable input (defines program cycle) */
-} __packed;
-
-#define BYTES_PER_FUSE 4
-#define NUM_FUSES 0x1000
-
-static int fu540_otp_read(int offset, void *buf, int size)
+#if CONFIG_IS_ENABLED(SIFIVE_OTP)
+static u32 otp_read_serialnum(struct udevice *dev)
{
- struct fu540_otp_regs *regs = (void __iomem *)FU540_OTP_BASE_ADDR;
- unsigned int i;
- int fuseidx = offset / BYTES_PER_FUSE;
- int fusecount = size / BYTES_PER_FUSE;
- u32 fusebuf[fusecount];
-
- /* check bounds */
- if (offset < 0 || size < 0)
- return -EINVAL;
- if (fuseidx >= NUM_FUSES)
- return -EINVAL;
- if ((fuseidx + fusecount) > NUM_FUSES)
- return -EINVAL;
+ int ret;
+ u32 serial[2] = {0};
- /* init OTP */
- writel(0x01, ®s->pdstb); /* wake up from stand-by */
- writel(0x01, ®s->ptrim); /* enable repair function */
- writel(0x01, ®s->pce); /* enable input */
-
- /* read all requested fuses */
- for (i = 0; i < fusecount; i++, fuseidx++) {
- writel(fuseidx, ®s->pa);
-
- /* cycle clock to read */
- writel(0x01, ®s->pclk);
- mdelay(1);
- writel(0x00, ®s->pclk);
- mdelay(1);
-
- /* read the value */
- fusebuf[i] = readl(®s->pdout);
- }
+ for (int i = 0xfe * 4; i > 0; i -= 8) {
+ ret = misc_read(dev, i, serial, sizeof(serial));
- /* shut down */
- writel(0, ®s->pce);
- writel(0, ®s->ptrim);
- writel(0, ®s->pdstb);
+ if (ret != sizeof(serial)) {
+ printf("%s: error reading serial from OTP\n", __func__);
+ break;
+ }
- /* copy out */
- memcpy(buf, fusebuf, size);
+ if (serial[0] == ~serial[1])
+ return serial[0];
+ }
- return 0;
+ return ERROR_READING_SERIAL_NUMBER;
}
+#endif
static u32 fu540_read_serialnum(void)
{
+ u32 serial = ERROR_READING_SERIAL_NUMBER;
+
+#if CONFIG_IS_ENABLED(SIFIVE_OTP)
+ struct udevice *dev;
int ret;
- u32 serial[2] = {0};
- for (int i = 0xfe * 4; i > 0; i -= 8) {
- ret = fu540_otp_read(i, serial, sizeof(serial));
- if (ret) {
- printf("%s: error reading from OTP\n", __func__);
- break;
- }
- if (serial[0] == ~serial[1])
- return serial[0];
+ /* init OTP */
+ ret = uclass_get_device_by_driver(UCLASS_MISC,
+ DM_GET_DRIVER(sifive_otp), &dev);
+
+ if (ret) {
+ debug("%s: could not find otp device\n", __func__);
+ return serial;
}
- return 0;
+ /* read serial from OTP and set env var */
+ serial = otp_read_serialnum(dev);
+#endif
+
+ return serial;
}
static void fu540_setup_macaddr(u32 serialnum)
--
2.17.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v8 03/21] riscv: Add _image_binary_end for SPL
2020-05-09 14:30 [PATCH v8 00/21] RISC-V SiFive FU540 support SPL Pragnesh Patel
2020-05-09 14:30 ` [PATCH v8 01/21] misc: add driver for the SiFive otp controller Pragnesh Patel
2020-05-09 14:30 ` [PATCH v8 02/21] riscv: sifive: fu540: Use OTP DM driver for serial environment variable Pragnesh Patel
@ 2020-05-09 14:30 ` Pragnesh Patel
2020-05-09 14:30 ` [PATCH v8 04/21] lib: Makefile: build crc7.c when CONFIG_MMC_SPI Pragnesh Patel
` (17 subsequent siblings)
20 siblings, 0 replies; 31+ messages in thread
From: Pragnesh Patel @ 2020-05-09 14:30 UTC (permalink / raw)
To: u-boot
For SPL_SEPARATE_BSS, Device tree will be put at _image_binary_end
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
---
arch/riscv/cpu/u-boot-spl.lds | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/cpu/u-boot-spl.lds b/arch/riscv/cpu/u-boot-spl.lds
index 955dd3106d..d0495ce248 100644
--- a/arch/riscv/cpu/u-boot-spl.lds
+++ b/arch/riscv/cpu/u-boot-spl.lds
@@ -72,6 +72,7 @@ SECTIONS
. = ALIGN(4);
_end = .;
+ _image_binary_end = .;
.bss : {
__bss_start = .;
--
2.17.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v8 04/21] lib: Makefile: build crc7.c when CONFIG_MMC_SPI
2020-05-09 14:30 [PATCH v8 00/21] RISC-V SiFive FU540 support SPL Pragnesh Patel
` (2 preceding siblings ...)
2020-05-09 14:30 ` [PATCH v8 03/21] riscv: Add _image_binary_end for SPL Pragnesh Patel
@ 2020-05-09 14:30 ` Pragnesh Patel
2020-05-09 14:30 ` [PATCH v8 05/21] riscv: sifive: dts: fu540: Add board -u-boot.dtsi files Pragnesh Patel
` (16 subsequent siblings)
20 siblings, 0 replies; 31+ messages in thread
From: Pragnesh Patel @ 2020-05-09 14:30 UTC (permalink / raw)
To: u-boot
When build U-Boot SPL, meet an issue of undefined reference to
'crc7' for drivers/mmc/mmc_spi.c, so let's compile crc7.c when
CONFIG_MMC_SPI selected.
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
---
lib/Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/lib/Makefile b/lib/Makefile
index c6f862b0c2..a6812ea4a3 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -30,7 +30,6 @@ obj-y += charset.o
endif
endif
obj-$(CONFIG_USB_TTY) += circbuf.o
-obj-y += crc7.o
obj-y += crc8.o
obj-y += crc16.o
obj-$(CONFIG_ERRNO_STR) += errno_str.o
@@ -90,6 +89,7 @@ obj-y += errno.o
obj-y += display_options.o
CFLAGS_display_options.o := $(if $(BUILD_TAG),-DBUILD_TAG='"$(BUILD_TAG)"')
obj-$(CONFIG_BCH) += bch.o
+obj-$(CONFIG_MMC_SPI) += crc7.o
obj-y += crc32.o
obj-$(CONFIG_CRC32C) += crc32c.o
obj-y += ctype.o
--
2.17.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v8 05/21] riscv: sifive: dts: fu540: Add board -u-boot.dtsi files
2020-05-09 14:30 [PATCH v8 00/21] RISC-V SiFive FU540 support SPL Pragnesh Patel
` (3 preceding siblings ...)
2020-05-09 14:30 ` [PATCH v8 04/21] lib: Makefile: build crc7.c when CONFIG_MMC_SPI Pragnesh Patel
@ 2020-05-09 14:30 ` Pragnesh Patel
2020-05-09 14:30 ` [PATCH v8 06/21] sifive: fu540: add ddr driver Pragnesh Patel
` (15 subsequent siblings)
20 siblings, 0 replies; 31+ messages in thread
From: Pragnesh Patel @ 2020-05-09 14:30 UTC (permalink / raw)
To: u-boot
Devicetree files in FU540 platform is synced from Linux, like other
platforms does. Apart from these U-Boot in FU540 would also require
some U-Boot specific node like clint.
So, create board specific -u-boot.dtsi files. This would help of
maintain U-Boot specific changes separately without touching Linux
dts(i) files which indeed easy for syncing from Linux between
releases.
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
---
arch/riscv/dts/fu540-c000-u-boot.dtsi | 61 +++++++++++++++++++
.../dts/hifive-unleashed-a00-u-boot.dtsi | 15 +++++
2 files changed, 76 insertions(+)
diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi b/arch/riscv/dts/fu540-c000-u-boot.dtsi
index db55773bd2..fbfe296a03 100644
--- a/arch/riscv/dts/fu540-c000-u-boot.dtsi
+++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi
@@ -4,11 +4,72 @@
*/
/ {
+ cpus {
+ assigned-clocks = <&prci PRCI_CLK_COREPLL>;
+ assigned-clock-rates = <1000000000>;
+ u-boot,dm-spl;
+ cpu0: cpu at 0 {
+ clocks = <&prci PRCI_CLK_COREPLL>;
+ u-boot,dm-spl;
+ status = "okay";
+ cpu0_intc: interrupt-controller {
+ u-boot,dm-spl;
+ };
+ };
+ cpu1: cpu at 1 {
+ clocks = <&prci PRCI_CLK_COREPLL>;
+ u-boot,dm-spl;
+ cpu1_intc: interrupt-controller {
+ u-boot,dm-spl;
+ };
+ };
+ cpu2: cpu at 2 {
+ clocks = <&prci PRCI_CLK_COREPLL>;
+ u-boot,dm-spl;
+ cpu2_intc: interrupt-controller {
+ u-boot,dm-spl;
+ };
+ };
+ cpu3: cpu at 3 {
+ clocks = <&prci PRCI_CLK_COREPLL>;
+ u-boot,dm-spl;
+ cpu3_intc: interrupt-controller {
+ u-boot,dm-spl;
+ };
+ };
+ cpu4: cpu at 4 {
+ clocks = <&prci PRCI_CLK_COREPLL>;
+ u-boot,dm-spl;
+ cpu4_intc: interrupt-controller {
+ u-boot,dm-spl;
+ };
+ };
+ };
+
soc {
+ u-boot,dm-spl;
otp: otp at 10070000 {
compatible = "sifive,fu540-c000-otp";
reg = <0x0 0x10070000 0x0 0x0FFF>;
fuse-count = <0x1000>;
};
+ clint at 2000000 {
+ compatible = "riscv,clint0";
+ interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 &cpu1_intc 3 &cpu1_intc 7 &cpu2_intc 3 &cpu2_intc 7 &cpu3_intc 3 &cpu3_intc 7 &cpu4_intc 3 &cpu4_intc 7>;
+ reg = <0x0 0x2000000 0x0 0xc0000>;
+ u-boot,dm-spl;
+ };
};
};
+
+&prci {
+ u-boot,dm-spl;
+};
+
+&uart0 {
+ u-boot,dm-spl;
+};
+
+&qspi2 {
+ u-boot,dm-spl;
+};
diff --git a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
index 9af089ffe7..9787332bf1 100644
--- a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
+++ b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
@@ -10,4 +10,19 @@
spi0 = &qspi0;
spi2 = &qspi2;
};
+
+ hfclk {
+ u-boot,dm-spl;
+ };
+
+ rtcclk {
+ u-boot,dm-spl;
+ };
+
+};
+
+&qspi2 {
+ mmc at 0 {
+ u-boot,dm-spl;
+ };
};
--
2.17.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v8 06/21] sifive: fu540: add ddr driver
2020-05-09 14:30 [PATCH v8 00/21] RISC-V SiFive FU540 support SPL Pragnesh Patel
` (4 preceding siblings ...)
2020-05-09 14:30 ` [PATCH v8 05/21] riscv: sifive: dts: fu540: Add board -u-boot.dtsi files Pragnesh Patel
@ 2020-05-09 14:30 ` Pragnesh Patel
2020-05-09 19:47 ` Giulio Benetti
2020-05-09 14:30 ` [PATCH v8 07/21] sifive: dts: fu540: Add DDR controller and phy register settings Pragnesh Patel
` (14 subsequent siblings)
20 siblings, 1 reply; 31+ messages in thread
From: Pragnesh Patel @ 2020-05-09 14:30 UTC (permalink / raw)
To: u-boot
Add driver for fu540 to support ddr initialization in SPL.
This driver is based on FSBL
(https://github.com/sifive/freedom-u540-c000-bootloader.git)
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
---
board/sifive/fu540/Kconfig | 2 +
drivers/ram/Kconfig | 1 +
drivers/ram/Makefile | 2 +
drivers/ram/sifive/Kconfig | 13 +
drivers/ram/sifive/Makefile | 6 +
drivers/ram/sifive/sdram_fu540.c | 416 +++++++++++++++++++++++++++++++
6 files changed, 440 insertions(+)
create mode 100644 drivers/ram/sifive/Kconfig
create mode 100644 drivers/ram/sifive/Makefile
create mode 100644 drivers/ram/sifive/sdram_fu540.c
diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig
index 4330ac4491..d41c305227 100644
--- a/board/sifive/fu540/Kconfig
+++ b/board/sifive/fu540/Kconfig
@@ -19,6 +19,8 @@ config SYS_TEXT_BASE
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select GENERIC_RISCV
+ select RAM
+ select SPL_RAM if SPL
imply CMD_DHCP
imply CMD_EXT2
imply CMD_EXT4
diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig
index 56fea7c94c..66074d1feb 100644
--- a/drivers/ram/Kconfig
+++ b/drivers/ram/Kconfig
@@ -75,3 +75,4 @@ config IMXRT_SDRAM
source "drivers/ram/rockchip/Kconfig"
source "drivers/ram/stm32mp1/Kconfig"
+source "drivers/ram/sifive/Kconfig"
diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile
index 5c897410c6..769c9d6218 100644
--- a/drivers/ram/Makefile
+++ b/drivers/ram/Makefile
@@ -17,3 +17,5 @@ obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
obj-$(CONFIG_K3_J721E_DDRSS) += k3-j721e/
obj-$(CONFIG_IMXRT_SDRAM) += imxrt_sdram.o
+
+obj-$(CONFIG_RAM_SIFIVE) += sifive/
diff --git a/drivers/ram/sifive/Kconfig b/drivers/ram/sifive/Kconfig
new file mode 100644
index 0000000000..6aca22ab2a
--- /dev/null
+++ b/drivers/ram/sifive/Kconfig
@@ -0,0 +1,13 @@
+config RAM_SIFIVE
+ bool "Ram drivers support for SiFive SoCs"
+ depends on RAM && RISCV
+ default y
+ help
+ This enables support for ram drivers of SiFive SoCs.
+
+config SIFIVE_FU540_DDR
+ bool "SiFive FU540 DDR driver"
+ depends on RAM_SIFIVE
+ default y if TARGET_SIFIVE_FU540
+ help
+ This enables DDR support for the platforms based on SiFive FU540 SoC.
diff --git a/drivers/ram/sifive/Makefile b/drivers/ram/sifive/Makefile
new file mode 100644
index 0000000000..0187805199
--- /dev/null
+++ b/drivers/ram/sifive/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2020 SiFive, Inc
+#
+
+obj-$(CONFIG_SIFIVE_FU540_DDR) += sdram_fu540.o
diff --git a/drivers/ram/sifive/sdram_fu540.c b/drivers/ram/sifive/sdram_fu540.c
new file mode 100644
index 0000000000..419359ff3b
--- /dev/null
+++ b/drivers/ram/sifive/sdram_fu540.c
@@ -0,0 +1,416 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * (C) Copyright 2020 SiFive, Inc.
+ *
+ * Authors:
+ * Pragnesh Patel <pragnesh.patel@sifive.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <init.h>
+#include <ram.h>
+#include <regmap.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <clk.h>
+#include <wait_bit.h>
+
+#define DENALI_CTL_0 0
+#define DENALI_CTL_21 21
+#define DENALI_CTL_120 120
+#define DENALI_CTL_132 132
+#define DENALI_CTL_136 136
+#define DENALI_CTL_170 170
+#define DENALI_CTL_181 181
+#define DENALI_CTL_182 182
+#define DENALI_CTL_184 184
+#define DENALI_CTL_208 208
+#define DENALI_CTL_209 209
+#define DENALI_CTL_210 210
+#define DENALI_CTL_212 212
+#define DENALI_CTL_214 214
+#define DENALI_CTL_216 216
+#define DENALI_CTL_224 224
+#define DENALI_CTL_225 225
+#define DENALI_CTL_260 260
+
+#define DENALI_PHY_1152 1152
+#define DENALI_PHY_1214 1214
+
+#define PAYLOAD_DEST 0x80000000
+#define DDR_MEM_SIZE (8UL * 1024UL * 1024UL * 1024UL)
+
+#define DRAM_CLASS_OFFSET 8
+#define DRAM_CLASS_DDR4 0xA
+#define OPTIMAL_RMODW_EN_OFFSET 0
+#define DISABLE_RD_INTERLEAVE_OFFSET 16
+#define OUT_OF_RANGE_OFFSET 1
+#define MULTIPLE_OUT_OF_RANGE_OFFSET 2
+#define PORT_COMMAND_CHANNEL_ERROR_OFFSET 7
+#define MC_INIT_COMPLETE_OFFSET 8
+#define LEVELING_OPERATION_COMPLETED_OFFSET 22
+#define DFI_PHY_WRLELV_MODE_OFFSET 24
+#define DFI_PHY_RDLVL_MODE_OFFSET 24
+#define DFI_PHY_RDLVL_GATE_MODE_OFFSET 0
+#define VREF_EN_OFFSET 24
+#define PORT_ADDR_PROTECTION_EN_OFFSET 0
+#define AXI0_ADDRESS_RANGE_ENABLE 8
+#define AXI0_RANGE_PROT_BITS_0_OFFSET 24
+#define RDLVL_EN_OFFSET 16
+#define RDLVL_GATE_EN_OFFSET 24
+#define WRLVL_EN_OFFSET 0
+
+#define PHY_RX_CAL_DQ0_0_OFFSET 0
+#define PHY_RX_CAL_DQ1_0_OFFSET 16
+
+struct fu540_ddrctl {
+ volatile u32 denali_ctl[265];
+};
+
+struct fu540_ddrphy {
+ volatile u32 denali_phy[1215];
+};
+
+/**
+ * struct ddr_info
+ *
+ * @dev : pointer for the device
+ * @info : UCLASS RAM information
+ * @ctl : DDR controller base address
+ * @phy : DDR PHY base address
+ * @ctrl : DDR control base address
+ * @physical_filter_ctrl : DDR physical filter control base address
+ */
+struct ddr_info {
+ struct udevice *dev;
+ struct ram_info info;
+ struct fu540_ddrctl *ctl;
+ struct fu540_ddrphy *phy;
+ struct clk ddr_clk;
+ u32 *physical_filter_ctrl;
+};
+
+#if defined(CONFIG_TPL_BUILD) || \
+ (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
+
+struct fu540_sdram_params {
+ struct fu540_ddrctl pctl_regs;
+ struct fu540_ddrphy phy_regs;
+};
+
+struct sifive_dmc_plat {
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+ struct dtd_sifive_fu540_dmc dtplat;
+#else
+ struct fu540_sdram_params sdram_params;
+#endif
+};
+
+/*
+ * TODO : It can be possible to use common sdram_copy_to_reg() API
+ * n: Unit bytes
+ */
+static void sdram_copy_to_reg(volatile u32 *dest,
+ volatile u32 *src, u32 n)
+{
+ int i;
+
+ for (i = 0; i < n / sizeof(u32); i++) {
+ writel(*src, dest);
+ src++;
+ dest++;
+ }
+}
+
+static void ddr_setuprangeprotection(volatile u32 *ctl, u64 end_addr)
+{
+ u32 end_addr_16kblocks = ((end_addr >> 14) & 0x7FFFFF) - 1;
+
+ writel(0x0, DENALI_CTL_209 + ctl);
+ writel(end_addr_16kblocks, DENALI_CTL_210 + ctl);
+ writel(0x0, DENALI_CTL_212 + ctl);
+ writel(0x0, DENALI_CTL_214 + ctl);
+ writel(0x0, DENALI_CTL_216 + ctl);
+ setbits_le32(DENALI_CTL_224 + ctl,
+ 0x3 << AXI0_RANGE_PROT_BITS_0_OFFSET);
+ writel(0xFFFFFFFF, DENALI_CTL_225 + ctl);
+ setbits_le32(DENALI_CTL_208 + ctl, 0x1 << AXI0_ADDRESS_RANGE_ENABLE);
+ setbits_le32(DENALI_CTL_208 + ctl,
+ 0x1 << PORT_ADDR_PROTECTION_EN_OFFSET);
+}
+
+static void ddr_start(volatile u32 *ctl, u32 *physical_filter_ctrl, u64 ddr_end)
+{
+ volatile u64 *filterreg = (volatile u64 *)physical_filter_ctrl;
+
+ setbits_le32(DENALI_CTL_0 + ctl, 0x1);
+
+ wait_for_bit_le32((void *)ctl + DENALI_CTL_132,
+ BIT(MC_INIT_COMPLETE_OFFSET), false, 100, false);
+
+ /* Disable the BusBlocker in front of the controller AXI slave ports */
+ filterreg[0] = 0x0f00000000000000UL | (ddr_end >> 2);
+}
+
+static void check_errata(u32 regbase, u32 updownreg)
+{
+ u64 fails = 0;
+ u32 dq = 0;
+ u32 down, up;
+ u8 failc0, failc1;
+ u32 phy_rx_cal_dqn_0_offset;
+
+ for (u32 bit = 0; bit < 2; bit++) {
+ if (bit == 0) {
+ phy_rx_cal_dqn_0_offset =
+ PHY_RX_CAL_DQ0_0_OFFSET;
+ } else {
+ phy_rx_cal_dqn_0_offset =
+ PHY_RX_CAL_DQ1_0_OFFSET;
+ }
+
+ down = (updownreg >>
+ phy_rx_cal_dqn_0_offset) & 0x3F;
+ up = (updownreg >>
+ (phy_rx_cal_dqn_0_offset + 6)) &
+ 0x3F;
+
+ failc0 = ((down == 0) && (up == 0x3F));
+ failc1 = ((up == 0) && (down == 0x3F));
+
+ /* print error message on failure */
+ if (failc0 || failc1) {
+ if (fails == 0)
+ printf("DDR error in fixing up\n");
+
+ fails |= (1 << dq);
+
+ char slicelsc = '0';
+ char slicemsc = '0';
+
+ slicelsc += (dq % 10);
+ slicemsc += (dq / 10);
+ printf("S ");
+ printf("%c", slicemsc);
+ printf("%c", slicelsc);
+
+ if (failc0)
+ printf("U");
+ else
+ printf("D");
+
+ printf("\n");
+ }
+ dq++;
+ }
+}
+
+static u64 ddr_phy_fixup(volatile u32 *ddrphyreg)
+{
+ u32 slicebase = 0;
+
+ /* check errata condition */
+ for (u32 slice = 0; slice < 8; slice++) {
+ u32 regbase = slicebase + 34;
+
+ for (u32 reg = 0; reg < 4; reg++) {
+ u32 updownreg = readl(regbase + reg + ddrphyreg);
+
+ check_errata(regbase, updownreg);
+ }
+ slicebase += 128;
+ }
+
+ return(0);
+}
+
+static u32 ddr_getdramclass(volatile u32 *ctl)
+{
+ u32 reg = readl(DENALI_CTL_0 + ctl);
+
+ return ((reg >> DRAM_CLASS_OFFSET) & 0xF);
+}
+
+static int fu540_ddr_setup(struct udevice *dev)
+{
+ struct ddr_info *priv = dev_get_priv(dev);
+ struct sifive_dmc_plat *plat = dev_get_platdata(dev);
+ struct fu540_sdram_params *params = &plat->sdram_params;
+ int ret, i;
+ u32 physet;
+ const u64 ddr_size = DDR_MEM_SIZE;
+ const u64 ddr_end = PAYLOAD_DEST + ddr_size;
+ volatile u32 *denali_ctl = &priv->ctl->denali_ctl[0];
+ volatile u32 *denali_phy = &priv->phy->denali_phy[0];
+
+ ret = dev_read_u32_array(dev, "sifive,sdram-params",
+ (u32 *)&plat->sdram_params,
+ sizeof(plat->sdram_params) / sizeof(u32));
+ if (ret) {
+ printf("%s: Cannot read sifive,sdram-params %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ sdram_copy_to_reg(&priv->ctl->denali_ctl[0],
+ ¶ms->pctl_regs.denali_ctl[0],
+ sizeof(struct fu540_ddrctl));
+
+ /* phy reset */
+ for (i = DENALI_PHY_1152; i <= DENALI_PHY_1214; i++) {
+ physet = params->phy_regs.denali_phy[i];
+ priv->phy->denali_phy[i] = physet;
+ }
+
+ for (i = 0; i < DENALI_PHY_1152; i++) {
+ physet = params->phy_regs.denali_phy[i];
+ priv->phy->denali_phy[i] = physet;
+ }
+
+ /* Disable read interleave DENALI_CTL_120 */
+ setbits_le32(DENALI_CTL_120 + denali_ctl,
+ 1 << DISABLE_RD_INTERLEAVE_OFFSET);
+
+ /* Disable optimal read/modify/write logic DENALI_CTL_21 */
+ clrbits_le32(DENALI_CTL_21 + denali_ctl, 1 << OPTIMAL_RMODW_EN_OFFSET);
+
+ /* Enable write Leveling DENALI_CTL_170 */
+ setbits_le32(DENALI_CTL_170 + denali_ctl, (1 << WRLVL_EN_OFFSET)
+ | (1 << DFI_PHY_WRLELV_MODE_OFFSET));
+
+ /* Enable read leveling DENALI_CTL_181 and DENALI_CTL_260 */
+ setbits_le32(DENALI_CTL_181 + denali_ctl,
+ 1 << DFI_PHY_RDLVL_MODE_OFFSET);
+ setbits_le32(DENALI_CTL_260 + denali_ctl, 1 << RDLVL_EN_OFFSET);
+
+ /* Enable read leveling gate DENALI_CTL_260 and DENALI_CTL_182 */
+ setbits_le32(DENALI_CTL_260 + denali_ctl, 1 << RDLVL_GATE_EN_OFFSET);
+ setbits_le32(DENALI_CTL_182 + denali_ctl,
+ 1 << DFI_PHY_RDLVL_GATE_MODE_OFFSET);
+
+ if (ddr_getdramclass(denali_ctl) == DRAM_CLASS_DDR4) {
+ /* Enable vref training DENALI_CTL_184 */
+ setbits_le32(DENALI_CTL_184 + denali_ctl, 1 << VREF_EN_OFFSET);
+ }
+
+ /* Mask off leveling completion interrupt DENALI_CTL_136 */
+ setbits_le32(DENALI_CTL_136 + denali_ctl,
+ 1 << LEVELING_OPERATION_COMPLETED_OFFSET);
+
+ /* Mask off MC init complete interrupt DENALI_CTL_136 */
+ setbits_le32(DENALI_CTL_136 + denali_ctl, 1 << MC_INIT_COMPLETE_OFFSET);
+
+ /* Mask off out of range interrupts DENALI_CTL_136 */
+ setbits_le32(DENALI_CTL_136 + denali_ctl, (1 << OUT_OF_RANGE_OFFSET)
+ | (1 << MULTIPLE_OUT_OF_RANGE_OFFSET));
+
+ /* set up range protection */
+ ddr_setuprangeprotection(denali_ctl, DDR_MEM_SIZE);
+
+ /* Mask off port command error interrupt DENALI_CTL_136 */
+ setbits_le32(DENALI_CTL_136 + denali_ctl,
+ 1 << PORT_COMMAND_CHANNEL_ERROR_OFFSET);
+
+ ddr_start(denali_ctl, priv->physical_filter_ctrl, ddr_end);
+
+ ddr_phy_fixup(denali_phy);
+
+ /* check size */
+ priv->info.size = get_ram_size((long *)priv->info.base,
+ DDR_MEM_SIZE);
+
+ debug("%s : %lx\n", __func__, priv->info.size);
+
+ /* check memory access for all memory */
+ if (priv->info.size != DDR_MEM_SIZE) {
+ printf("DDR invalid size : 0x%lx, expected 0x%lx\n",
+ priv->info.size, DDR_MEM_SIZE);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+#endif
+
+static int fu540_ddr_probe(struct udevice *dev)
+{
+ struct ddr_info *priv = dev_get_priv(dev);
+
+#if defined(CONFIG_TPL_BUILD) || \
+ (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
+ struct regmap *map;
+ int ret;
+ u32 clock = 0;
+
+ debug("FU540 DDR probe\n");
+ priv->dev = dev;
+
+ ret = regmap_init_mem(dev_ofnode(dev), &map);
+ if (ret)
+ return ret;
+
+ ret = clk_get_by_index(dev, 0, &priv->ddr_clk);
+ if (ret) {
+ debug("clk get failed %d\n", ret);
+ return ret;
+ }
+
+ ret = dev_read_u32(dev, "clock-frequency", &clock);
+ if (ret) {
+ debug("clock-frequency not found in dt %d\n", ret);
+ return ret;
+ } else {
+ ret = clk_set_rate(&priv->ddr_clk, clock);
+ if (ret < 0) {
+ debug("Could not set DDR clock\n");
+ return ret;
+ }
+ }
+
+ ret = clk_enable(&priv->ddr_clk);
+ priv->ctl = regmap_get_range(map, 0);
+ priv->phy = regmap_get_range(map, 1);
+ priv->physical_filter_ctrl = regmap_get_range(map, 2);
+
+ priv->info.base = CONFIG_SYS_SDRAM_BASE;
+
+ priv->info.size = 0;
+ return fu540_ddr_setup(dev);
+#else
+ priv->info.base = CONFIG_SYS_SDRAM_BASE;
+ priv->info.size = DDR_MEM_SIZE;
+#endif
+ return 0;
+}
+
+static int fu540_ddr_get_info(struct udevice *dev, struct ram_info *info)
+{
+ struct ddr_info *priv = dev_get_priv(dev);
+
+ *info = priv->info;
+
+ return 0;
+}
+
+static struct ram_ops fu540_ddr_ops = {
+ .get_info = fu540_ddr_get_info,
+};
+
+static const struct udevice_id fu540_ddr_ids[] = {
+ { .compatible = "sifive,fu540-c000-ddr" },
+ { }
+};
+
+U_BOOT_DRIVER(fu540_ddr) = {
+ .name = "fu540_ddr",
+ .id = UCLASS_RAM,
+ .of_match = fu540_ddr_ids,
+ .ops = &fu540_ddr_ops,
+ .probe = fu540_ddr_probe,
+ .priv_auto_alloc_size = sizeof(struct ddr_info),
+#if defined(CONFIG_TPL_BUILD) || \
+ (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
+ .platdata_auto_alloc_size = sizeof(struct sifive_dmc_plat),
+#endif
+};
--
2.17.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v8 07/21] sifive: dts: fu540: Add DDR controller and phy register settings
2020-05-09 14:30 [PATCH v8 00/21] RISC-V SiFive FU540 support SPL Pragnesh Patel
` (5 preceding siblings ...)
2020-05-09 14:30 ` [PATCH v8 06/21] sifive: fu540: add ddr driver Pragnesh Patel
@ 2020-05-09 14:30 ` Pragnesh Patel
2020-05-09 14:30 ` [PATCH v8 08/21] riscv: sifive: dts: fu540: add U-Boot dmc node Pragnesh Patel
` (13 subsequent siblings)
20 siblings, 0 replies; 31+ messages in thread
From: Pragnesh Patel @ 2020-05-09 14:30 UTC (permalink / raw)
To: u-boot
Add DDR controller and phy register settings, taken from fsbl
(https://github.com/sifive/freedom-u540-c000-bootloader.git)
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
---
...fu540-hifive-unleashed-a00-sdram-ddr4.dtsi | 1489 +++++++++++++++++
1 file changed, 1489 insertions(+)
create mode 100644 arch/riscv/dts/fu540-hifive-unleashed-a00-sdram-ddr4.dtsi
diff --git a/arch/riscv/dts/fu540-hifive-unleashed-a00-sdram-ddr4.dtsi b/arch/riscv/dts/fu540-hifive-unleashed-a00-sdram-ddr4.dtsi
new file mode 100644
index 0000000000..02a2880f72
--- /dev/null
+++ b/arch/riscv/dts/fu540-hifive-unleashed-a00-sdram-ddr4.dtsi
@@ -0,0 +1,1489 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * (C) Copyright 2020 SiFive, Inc
+ */
+
+&dmc {
+ sifive,sdram-params = <
+ 0x00000a00 /* DENALI_CTL_00_DATA */
+ 0x00000000 /* DENALI_CTL_01_DATA */
+ 0x00000000 /* DENALI_CTL_02_DATA */
+ 0x00000000 /* DENALI_CTL_03_DATA */
+ 0x00000000 /* DENALI_CTL_04_DATA */
+ 0x00000000 /* DENALI_CTL_05_DATA */
+ 0x0000000a /* DENALI_CTL_06_DATA */
+ 0x0002d362 /* DENALI_CTL_07_DATA */
+ 0x00071073 /* DENALI_CTL_08_DATA */
+ 0x0a1c0255 /* DENALI_CTL_09_DATA */
+ 0x1c1c0400 /* DENALI_CTL_10_DATA */
+ 0x0404990b /* DENALI_CTL_11_DATA */
+ 0x2b050405 /* DENALI_CTL_12_DATA */
+ 0x0e0c081e /* DENALI_CTL_13_DATA */
+ 0x08090914 /* DENALI_CTL_14_DATA */
+ 0x00fde718 /* DENALI_CTL_15_DATA */
+ 0x00180a05 /* DENALI_CTL_16_DATA */
+ 0x008b130e /* DENALI_CTL_17_DATA */
+ 0x01000118 /* DENALI_CTL_18_DATA */
+ 0x0e032101 /* DENALI_CTL_19_DATA */
+ 0x00000000 /* DENALI_CTL_20_DATA */
+ 0x00000101 /* DENALI_CTL_21_DATA */
+ 0x00000000 /* DENALI_CTL_22_DATA */
+ 0x0a000000 /* DENALI_CTL_23_DATA */
+ 0x00000000 /* DENALI_CTL_24_DATA */
+ 0x01450100 /* DENALI_CTL_25_DATA */
+ 0x00001c36 /* DENALI_CTL_26_DATA */
+ 0x00000005 /* DENALI_CTL_27_DATA */
+ 0x00170006 /* DENALI_CTL_28_DATA */
+ 0x014e0300 /* DENALI_CTL_29_DATA */
+ 0x03010000 /* DENALI_CTL_30_DATA */
+ 0x000a0e00 /* DENALI_CTL_31_DATA */
+ 0x04030200 /* DENALI_CTL_32_DATA */
+ 0x0000031f /* DENALI_CTL_33_DATA */
+ 0x00070004 /* DENALI_CTL_34_DATA */
+ 0x00000000 /* DENALI_CTL_35_DATA */
+ 0x00000000 /* DENALI_CTL_36_DATA */
+ 0x00000000 /* DENALI_CTL_37_DATA */
+ 0x00000000 /* DENALI_CTL_38_DATA */
+ 0x00000000 /* DENALI_CTL_39_DATA */
+ 0x00000000 /* DENALI_CTL_40_DATA */
+ 0x00000000 /* DENALI_CTL_41_DATA */
+ 0x00000000 /* DENALI_CTL_42_DATA */
+ 0x00000000 /* DENALI_CTL_43_DATA */
+ 0x00000000 /* DENALI_CTL_44_DATA */
+ 0x00000000 /* DENALI_CTL_45_DATA */
+ 0x00000000 /* DENALI_CTL_46_DATA */
+ 0x00000000 /* DENALI_CTL_47_DATA */
+ 0x00000000 /* DENALI_CTL_48_DATA */
+ 0x00000000 /* DENALI_CTL_49_DATA */
+ 0x00000000 /* DENALI_CTL_50_DATA */
+ 0x00000000 /* DENALI_CTL_51_DATA */
+ 0x00000000 /* DENALI_CTL_52_DATA */
+ 0x00000000 /* DENALI_CTL_53_DATA */
+ 0x00000000 /* DENALI_CTL_54_DATA */
+ 0x00000000 /* DENALI_CTL_55_DATA */
+ 0x00000000 /* DENALI_CTL_56_DATA */
+ 0x00000000 /* DENALI_CTL_57_DATA */
+ 0x00000000 /* DENALI_CTL_58_DATA */
+ 0x00000000 /* DENALI_CTL_59_DATA */
+ 0x00000424 /* DENALI_CTL_60_DATA */
+ 0x00000201 /* DENALI_CTL_61_DATA */
+ 0x00001008 /* DENALI_CTL_62_DATA */
+ 0x00000000 /* DENALI_CTL_63_DATA */
+ 0x00000200 /* DENALI_CTL_64_DATA */
+ 0x00000000 /* DENALI_CTL_65_DATA */
+ 0x00000481 /* DENALI_CTL_66_DATA */
+ 0x00000400 /* DENALI_CTL_67_DATA */
+ 0x00000424 /* DENALI_CTL_68_DATA */
+ 0x00000201 /* DENALI_CTL_69_DATA */
+ 0x00001008 /* DENALI_CTL_70_DATA */
+ 0x00000000 /* DENALI_CTL_71_DATA */
+ 0x00000200 /* DENALI_CTL_72_DATA */
+ 0x00000000 /* DENALI_CTL_73_DATA */
+ 0x00000481 /* DENALI_CTL_74_DATA */
+ 0x00000400 /* DENALI_CTL_75_DATA */
+ 0x01010000 /* DENALI_CTL_76_DATA */
+ 0x00000000 /* DENALI_CTL_77_DATA */
+ 0x00000000 /* DENALI_CTL_78_DATA */
+ 0x00000000 /* DENALI_CTL_79_DATA */
+ 0x00000000 /* DENALI_CTL_80_DATA */
+ 0x00000000 /* DENALI_CTL_81_DATA */
+ 0x00000000 /* DENALI_CTL_82_DATA */
+ 0x00000000 /* DENALI_CTL_83_DATA */
+ 0x00000000 /* DENALI_CTL_84_DATA */
+ 0x00000000 /* DENALI_CTL_85_DATA */
+ 0x00000000 /* DENALI_CTL_86_DATA */
+ 0x00000000 /* DENALI_CTL_87_DATA */
+ 0x00000000 /* DENALI_CTL_88_DATA */
+ 0x00000000 /* DENALI_CTL_89_DATA */
+ 0x00000000 /* DENALI_CTL_90_DATA */
+ 0x00000000 /* DENALI_CTL_91_DATA */
+ 0x00000000 /* DENALI_CTL_92_DATA */
+ 0x00000000 /* DENALI_CTL_93_DATA */
+ 0x00000000 /* DENALI_CTL_94_DATA */
+ 0x00000000 /* DENALI_CTL_95_DATA */
+ 0x00000000 /* DENALI_CTL_96_DATA */
+ 0x00000000 /* DENALI_CTL_97_DATA */
+ 0x00000000 /* DENALI_CTL_98_DATA */
+ 0x00000000 /* DENALI_CTL_99_DATA */
+ 0x00000000 /* DENALI_CTL_100_DATA */
+ 0x00000000 /* DENALI_CTL_101_DATA */
+ 0x00000000 /* DENALI_CTL_102_DATA */
+ 0x00000000 /* DENALI_CTL_103_DATA */
+ 0x00000000 /* DENALI_CTL_104_DATA */
+ 0x00000003 /* DENALI_CTL_105_DATA */
+ 0x00000000 /* DENALI_CTL_106_DATA */
+ 0x00000000 /* DENALI_CTL_107_DATA */
+ 0x00000000 /* DENALI_CTL_108_DATA */
+ 0x00000000 /* DENALI_CTL_109_DATA */
+ 0x01000000 /* DENALI_CTL_110_DATA */
+ 0x00040000 /* DENALI_CTL_111_DATA */
+ 0x00800200 /* DENALI_CTL_112_DATA */
+ 0x00000200 /* DENALI_CTL_113_DATA */
+ 0x00000040 /* DENALI_CTL_114_DATA */
+ 0x01000100 /* DENALI_CTL_115_DATA */
+ 0x0a000002 /* DENALI_CTL_116_DATA */
+ 0x0101ffff /* DENALI_CTL_117_DATA */
+ 0x01010101 /* DENALI_CTL_118_DATA */
+ 0x01010101 /* DENALI_CTL_119_DATA */
+ 0x0000010b /* DENALI_CTL_120_DATA */
+ 0x00000c01 /* DENALI_CTL_121_DATA */
+ 0x00000000 /* DENALI_CTL_122_DATA */
+ 0x00000000 /* DENALI_CTL_123_DATA */
+ 0x00000000 /* DENALI_CTL_124_DATA */
+ 0x00000000 /* DENALI_CTL_125_DATA */
+ 0x00030300 /* DENALI_CTL_126_DATA */
+ 0x00000000 /* DENALI_CTL_127_DATA */
+ 0x00010001 /* DENALI_CTL_128_DATA */
+ 0x00000000 /* DENALI_CTL_129_DATA */
+ 0x00000000 /* DENALI_CTL_130_DATA */
+ 0x00000000 /* DENALI_CTL_131_DATA */
+ 0x00000000 /* DENALI_CTL_132_DATA */
+ 0x00000000 /* DENALI_CTL_133_DATA */
+ 0x00000000 /* DENALI_CTL_134_DATA */
+ 0x00000000 /* DENALI_CTL_135_DATA */
+ 0x00000000 /* DENALI_CTL_136_DATA */
+ 0x00000000 /* DENALI_CTL_137_DATA */
+ 0x00000000 /* DENALI_CTL_138_DATA */
+ 0x00000000 /* DENALI_CTL_139_DATA */
+ 0x00000000 /* DENALI_CTL_140_DATA */
+ 0x00000000 /* DENALI_CTL_141_DATA */
+ 0x00000000 /* DENALI_CTL_142_DATA */
+ 0x00000000 /* DENALI_CTL_143_DATA */
+ 0x00000000 /* DENALI_CTL_144_DATA */
+ 0x00000000 /* DENALI_CTL_145_DATA */
+ 0x00000000 /* DENALI_CTL_146_DATA */
+ 0x00000000 /* DENALI_CTL_147_DATA */
+ 0x00000000 /* DENALI_CTL_148_DATA */
+ 0x00000000 /* DENALI_CTL_149_DATA */
+ 0x00000000 /* DENALI_CTL_150_DATA */
+ 0x00000000 /* DENALI_CTL_151_DATA */
+ 0x00000000 /* DENALI_CTL_152_DATA */
+ 0x00000000 /* DENALI_CTL_153_DATA */
+ 0x00000000 /* DENALI_CTL_154_DATA */
+ 0x00000000 /* DENALI_CTL_155_DATA */
+ 0x00000000 /* DENALI_CTL_156_DATA */
+ 0x00000000 /* DENALI_CTL_157_DATA */
+ 0x00000000 /* DENALI_CTL_158_DATA */
+ 0x00000000 /* DENALI_CTL_159_DATA */
+ 0x00000000 /* DENALI_CTL_160_DATA */
+ 0x02010102 /* DENALI_CTL_161_DATA */
+ 0x0107070d /* DENALI_CTL_162_DATA */
+ 0x04040400 /* DENALI_CTL_163_DATA */
+ 0x03000503 /* DENALI_CTL_164_DATA */
+ 0x00000000 /* DENALI_CTL_165_DATA */
+ 0x00000000 /* DENALI_CTL_166_DATA */
+ 0x00000000 /* DENALI_CTL_167_DATA */
+ 0x00000000 /* DENALI_CTL_168_DATA */
+ 0x280d0000 /* DENALI_CTL_169_DATA */
+ 0x01000000 /* DENALI_CTL_170_DATA */
+ 0x00000000 /* DENALI_CTL_171_DATA */
+ 0x00010001 /* DENALI_CTL_172_DATA */
+ 0x00000000 /* DENALI_CTL_173_DATA */
+ 0x00000000 /* DENALI_CTL_174_DATA */
+ 0x00000000 /* DENALI_CTL_175_DATA */
+ 0x00000000 /* DENALI_CTL_176_DATA */
+ 0x00000000 /* DENALI_CTL_177_DATA */
+ 0x00000000 /* DENALI_CTL_178_DATA */
+ 0x00000000 /* DENALI_CTL_179_DATA */
+ 0x00000000 /* DENALI_CTL_180_DATA */
+ 0x01000000 /* DENALI_CTL_181_DATA */
+ 0x00000001 /* DENALI_CTL_182_DATA */
+ 0x00000100 /* DENALI_CTL_183_DATA */
+ 0x00000101 /* DENALI_CTL_184_DATA */
+ 0x67676701 /* DENALI_CTL_185_DATA */
+ 0x67676767 /* DENALI_CTL_186_DATA */
+ 0x67676767 /* DENALI_CTL_187_DATA */
+ 0x67676767 /* DENALI_CTL_188_DATA */
+ 0x67676767 /* DENALI_CTL_189_DATA */
+ 0x67676767 /* DENALI_CTL_190_DATA */
+ 0x67676767 /* DENALI_CTL_191_DATA */
+ 0x67676767 /* DENALI_CTL_192_DATA */
+ 0x67676767 /* DENALI_CTL_193_DATA */
+ 0x01000067 /* DENALI_CTL_194_DATA */
+ 0x00000001 /* DENALI_CTL_195_DATA */
+ 0x00000101 /* DENALI_CTL_196_DATA */
+ 0x00000000 /* DENALI_CTL_197_DATA */
+ 0x00000000 /* DENALI_CTL_198_DATA */
+ 0x00000000 /* DENALI_CTL_199_DATA */
+ 0x00000000 /* DENALI_CTL_200_DATA */
+ 0x00000000 /* DENALI_CTL_201_DATA */
+ 0x00000000 /* DENALI_CTL_202_DATA */
+ 0x00000000 /* DENALI_CTL_203_DATA */
+ 0x00000000 /* DENALI_CTL_204_DATA */
+ 0x00000000 /* DENALI_CTL_205_DATA */
+ 0x00000000 /* DENALI_CTL_206_DATA */
+ 0x00000000 /* DENALI_CTL_207_DATA */
+ 0x00000001 /* DENALI_CTL_208_DATA */
+ 0x00000000 /* DENALI_CTL_209_DATA */
+ 0x007fffff /* DENALI_CTL_210_DATA */
+ 0x00000000 /* DENALI_CTL_211_DATA */
+ 0x007fffff /* DENALI_CTL_212_DATA */
+ 0x00000000 /* DENALI_CTL_213_DATA */
+ 0x007fffff /* DENALI_CTL_214_DATA */
+ 0x00000000 /* DENALI_CTL_215_DATA */
+ 0x007fffff /* DENALI_CTL_216_DATA */
+ 0x00000000 /* DENALI_CTL_217_DATA */
+ 0x007fffff /* DENALI_CTL_218_DATA */
+ 0x00000000 /* DENALI_CTL_219_DATA */
+ 0x007fffff /* DENALI_CTL_220_DATA */
+ 0x00000000 /* DENALI_CTL_221_DATA */
+ 0x007fffff /* DENALI_CTL_222_DATA */
+ 0x00000000 /* DENALI_CTL_223_DATA */
+ 0x037fffff /* DENALI_CTL_224_DATA */
+ 0xffffffff /* DENALI_CTL_225_DATA */
+ 0x000f000f /* DENALI_CTL_226_DATA */
+ 0x00ffff03 /* DENALI_CTL_227_DATA */
+ 0x000fffff /* DENALI_CTL_228_DATA */
+ 0x0003000f /* DENALI_CTL_229_DATA */
+ 0xffffffff /* DENALI_CTL_230_DATA */
+ 0x000f000f /* DENALI_CTL_231_DATA */
+ 0x00ffff03 /* DENALI_CTL_232_DATA */
+ 0x000fffff /* DENALI_CTL_233_DATA */
+ 0x0003000f /* DENALI_CTL_234_DATA */
+ 0xffffffff /* DENALI_CTL_235_DATA */
+ 0x000f000f /* DENALI_CTL_236_DATA */
+ 0x00ffff03 /* DENALI_CTL_237_DATA */
+ 0x000fffff /* DENALI_CTL_238_DATA */
+ 0x0003000f /* DENALI_CTL_239_DATA */
+ 0xffffffff /* DENALI_CTL_240_DATA */
+ 0x000f000f /* DENALI_CTL_241_DATA */
+ 0x00ffff03 /* DENALI_CTL_242_DATA */
+ 0x000fffff /* DENALI_CTL_243_DATA */
+ 0x6407000f /* DENALI_CTL_244_DATA */
+ 0x01640001 /* DENALI_CTL_245_DATA */
+ 0x00000000 /* DENALI_CTL_246_DATA */
+ 0x00000000 /* DENALI_CTL_247_DATA */
+ 0x00001700 /* DENALI_CTL_248_DATA */
+ 0x00386c05 /* DENALI_CTL_249_DATA */
+ 0x02000200 /* DENALI_CTL_250_DATA */
+ 0x02000200 /* DENALI_CTL_251_DATA */
+ 0x0000386c /* DENALI_CTL_252_DATA */
+ 0x00023438 /* DENALI_CTL_253_DATA */
+ 0x02020d10 /* DENALI_CTL_254_DATA */
+ 0x00140303 /* DENALI_CTL_255_DATA */
+ 0x00000000 /* DENALI_CTL_256_DATA */
+ 0x00000000 /* DENALI_CTL_257_DATA */
+ 0x00001403 /* DENALI_CTL_258_DATA */
+ 0x00000000 /* DENALI_CTL_259_DATA */
+ 0x00000000 /* DENALI_CTL_260_DATA */
+ 0x00000000 /* DENALI_CTL_261_DATA */
+ 0x00000000 /* DENALI_CTL_262_DATA */
+ 0x0d010000 /* DENALI_CTL_263_DATA */
+ 0x00000008 /* DENALI_CTL_264_DATA */
+ 0x31706542 /* DENALI_PHY_00_DATA */
+ 0x0004c008 /* DENALI_PHY_01_DATA */
+ 0x000000da /* DENALI_PHY_02_DATA */
+ 0x00000000 /* DENALI_PHY_03_DATA */
+ 0x00000000 /* DENALI_PHY_04_DATA */
+ 0x00010000 /* DENALI_PHY_05_DATA */
+ 0x01DDDD90 /* DENALI_PHY_06_DATA */
+ 0x01DDDD90 /* DENALI_PHY_07_DATA */
+ 0x01030000 /* DENALI_PHY_08_DATA */
+ 0x01000000 /* DENALI_PHY_09_DATA */
+ 0x00c00000 /* DENALI_PHY_10_DATA */
+ 0x00000007 /* DENALI_PHY_11_DATA */
+ 0x00000000 /* DENALI_PHY_12_DATA */
+ 0x00000000 /* DENALI_PHY_13_DATA */
+ 0x04000408 /* DENALI_PHY_14_DATA */
+ 0x00000408 /* DENALI_PHY_15_DATA */
+ 0x00e4e400 /* DENALI_PHY_16_DATA */
+ 0x00000000 /* DENALI_PHY_17_DATA */
+ 0x00000000 /* DENALI_PHY_18_DATA */
+ 0x00000000 /* DENALI_PHY_19_DATA */
+ 0x00000000 /* DENALI_PHY_20_DATA */
+ 0x00000000 /* DENALI_PHY_21_DATA */
+ 0x00000000 /* DENALI_PHY_22_DATA */
+ 0x00000000 /* DENALI_PHY_23_DATA */
+ 0x00000000 /* DENALI_PHY_24_DATA */
+ 0x00000000 /* DENALI_PHY_25_DATA */
+ 0x00000000 /* DENALI_PHY_26_DATA */
+ 0x00000000 /* DENALI_PHY_27_DATA */
+ 0x00000000 /* DENALI_PHY_28_DATA */
+ 0x00000000 /* DENALI_PHY_29_DATA */
+ 0x00000000 /* DENALI_PHY_30_DATA */
+ 0x00000000 /* DENALI_PHY_31_DATA */
+ 0x00000000 /* DENALI_PHY_32_DATA */
+ 0x00200000 /* DENALI_PHY_33_DATA */
+ 0x00000000 /* DENALI_PHY_34_DATA */
+ 0x00000000 /* DENALI_PHY_35_DATA */
+ 0x00000000 /* DENALI_PHY_36_DATA */
+ 0x00000000 /* DENALI_PHY_37_DATA */
+ 0x00000000 /* DENALI_PHY_38_DATA */
+ 0x00000000 /* DENALI_PHY_39_DATA */
+ 0x02800280 /* DENALI_PHY_40_DATA */
+ 0x02800280 /* DENALI_PHY_41_DATA */
+ 0x02800280 /* DENALI_PHY_42_DATA */
+ 0x02800280 /* DENALI_PHY_43_DATA */
+ 0x00000280 /* DENALI_PHY_44_DATA */
+ 0x00000000 /* DENALI_PHY_45_DATA */
+ 0x00000000 /* DENALI_PHY_46_DATA */
+ 0x00000000 /* DENALI_PHY_47_DATA */
+ 0x00000000 /* DENALI_PHY_48_DATA */
+ 0x00000000 /* DENALI_PHY_49_DATA */
+ 0x00800080 /* DENALI_PHY_50_DATA */
+ 0x00800080 /* DENALI_PHY_51_DATA */
+ 0x00800080 /* DENALI_PHY_52_DATA */
+ 0x00800080 /* DENALI_PHY_53_DATA */
+ 0x00800080 /* DENALI_PHY_54_DATA */
+ 0x00800080 /* DENALI_PHY_55_DATA */
+ 0x00800080 /* DENALI_PHY_56_DATA */
+ 0x00800080 /* DENALI_PHY_57_DATA */
+ 0x00800080 /* DENALI_PHY_58_DATA */
+ 0x000100da /* DENALI_PHY_59_DATA */
+ 0x01000200 /* DENALI_PHY_60_DATA */
+ 0x00000000 /* DENALI_PHY_61_DATA */
+ 0x00000000 /* DENALI_PHY_62_DATA */
+ 0x00000002 /* DENALI_PHY_63_DATA */
+ 0x51313152 /* DENALI_PHY_64_DATA */
+ 0x80013130 /* DENALI_PHY_65_DATA */
+ 0x02000080 /* DENALI_PHY_66_DATA */
+ 0x00100001 /* DENALI_PHY_67_DATA */
+ 0x0c064208 /* DENALI_PHY_68_DATA */
+ 0x000f0c0f /* DENALI_PHY_69_DATA */
+ 0x01000140 /* DENALI_PHY_70_DATA */
+ 0x0000000c /* DENALI_PHY_71_DATA */
+ 0x00000000 /* DENALI_PHY_72_DATA */
+ 0x00000000 /* DENALI_PHY_73_DATA */
+ 0x00000000 /* DENALI_PHY_74_DATA */
+ 0x00000000 /* DENALI_PHY_75_DATA */
+ 0x00000000 /* DENALI_PHY_76_DATA */
+ 0x00000000 /* DENALI_PHY_77_DATA */
+ 0x00000000 /* DENALI_PHY_78_DATA */
+ 0x00000000 /* DENALI_PHY_79_DATA */
+ 0x00000000 /* DENALI_PHY_80_DATA */
+ 0x00000000 /* DENALI_PHY_81_DATA */
+ 0x00000000 /* DENALI_PHY_82_DATA */
+ 0x00000000 /* DENALI_PHY_83_DATA */
+ 0x00000000 /* DENALI_PHY_84_DATA */
+ 0x00000000 /* DENALI_PHY_85_DATA */
+ 0x00000000 /* DENALI_PHY_86_DATA */
+ 0x00000000 /* DENALI_PHY_87_DATA */
+ 0x00000000 /* DENALI_PHY_88_DATA */
+ 0x00000000 /* DENALI_PHY_89_DATA */
+ 0x00000000 /* DENALI_PHY_90_DATA */
+ 0x00000000 /* DENALI_PHY_91_DATA */
+ 0x00000000 /* DENALI_PHY_92_DATA */
+ 0x00000000 /* DENALI_PHY_93_DATA */
+ 0x00000000 /* DENALI_PHY_94_DATA */
+ 0x00000000 /* DENALI_PHY_95_DATA */
+ 0x00000000 /* DENALI_PHY_96_DATA */
+ 0x00000000 /* DENALI_PHY_97_DATA */
+ 0x00000000 /* DENALI_PHY_98_DATA */
+ 0x00000000 /* DENALI_PHY_99_DATA */
+ 0x00000000 /* DENALI_PHY_100_DATA */
+ 0x00000000 /* DENALI_PHY_101_DATA */
+ 0x00000000 /* DENALI_PHY_102_DATA */
+ 0x00000000 /* DENALI_PHY_103_DATA */
+ 0x00000000 /* DENALI_PHY_104_DATA */
+ 0x00000000 /* DENALI_PHY_105_DATA */
+ 0x00000000 /* DENALI_PHY_106_DATA */
+ 0x00000000 /* DENALI_PHY_107_DATA */
+ 0x00000000 /* DENALI_PHY_108_DATA */
+ 0x00000000 /* DENALI_PHY_109_DATA */
+ 0x00000000 /* DENALI_PHY_110_DATA */
+ 0x00000000 /* DENALI_PHY_111_DATA */
+ 0x00000000 /* DENALI_PHY_112_DATA */
+ 0x00000000 /* DENALI_PHY_113_DATA */
+ 0x00000000 /* DENALI_PHY_114_DATA */
+ 0x00000000 /* DENALI_PHY_115_DATA */
+ 0x00000000 /* DENALI_PHY_116_DATA */
+ 0x00000000 /* DENALI_PHY_117_DATA */
+ 0x00000000 /* DENALI_PHY_118_DATA */
+ 0x00000000 /* DENALI_PHY_119_DATA */
+ 0x00000000 /* DENALI_PHY_120_DATA */
+ 0x00000000 /* DENALI_PHY_121_DATA */
+ 0x00000000 /* DENALI_PHY_122_DATA */
+ 0x00000000 /* DENALI_PHY_123_DATA */
+ 0x00000000 /* DENALI_PHY_124_DATA */
+ 0x00000000 /* DENALI_PHY_125_DATA */
+ 0x00000000 /* DENALI_PHY_126_DATA */
+ 0x00000000 /* DENALI_PHY_127_DATA */
+ 0x40263571 /* DENALI_PHY_128_DATA */
+ 0x0004c008 /* DENALI_PHY_129_DATA */
+ 0x000000da /* DENALI_PHY_130_DATA */
+ 0x00000000 /* DENALI_PHY_131_DATA */
+ 0x00000000 /* DENALI_PHY_132_DATA */
+ 0x00010000 /* DENALI_PHY_133_DATA */
+ 0x01DDDD90 /* DENALI_PHY_134_DATA */
+ 0x01DDDD90 /* DENALI_PHY_135_DATA */
+ 0x01030000 /* DENALI_PHY_136_DATA */
+ 0x01000000 /* DENALI_PHY_137_DATA */
+ 0x00c00000 /* DENALI_PHY_138_DATA */
+ 0x00000007 /* DENALI_PHY_139_DATA */
+ 0x00000000 /* DENALI_PHY_140_DATA */
+ 0x00000000 /* DENALI_PHY_141_DATA */
+ 0x04000408 /* DENALI_PHY_142_DATA */
+ 0x00000408 /* DENALI_PHY_143_DATA */
+ 0x00e4e400 /* DENALI_PHY_144_DATA */
+ 0x00000000 /* DENALI_PHY_145_DATA */
+ 0x00000000 /* DENALI_PHY_146_DATA */
+ 0x00000000 /* DENALI_PHY_147_DATA */
+ 0x00000000 /* DENALI_PHY_148_DATA */
+ 0x00000000 /* DENALI_PHY_149_DATA */
+ 0x00000000 /* DENALI_PHY_150_DATA */
+ 0x00000000 /* DENALI_PHY_151_DATA */
+ 0x00000000 /* DENALI_PHY_152_DATA */
+ 0x00000000 /* DENALI_PHY_153_DATA */
+ 0x00000000 /* DENALI_PHY_154_DATA */
+ 0x00000000 /* DENALI_PHY_155_DATA */
+ 0x00000000 /* DENALI_PHY_156_DATA */
+ 0x00000000 /* DENALI_PHY_157_DATA */
+ 0x00000000 /* DENALI_PHY_158_DATA */
+ 0x00000000 /* DENALI_PHY_159_DATA */
+ 0x00000000 /* DENALI_PHY_160_DATA */
+ 0x00200000 /* DENALI_PHY_161_DATA */
+ 0x00000000 /* DENALI_PHY_162_DATA */
+ 0x00000000 /* DENALI_PHY_163_DATA */
+ 0x00000000 /* DENALI_PHY_164_DATA */
+ 0x00000000 /* DENALI_PHY_165_DATA */
+ 0x00000000 /* DENALI_PHY_166_DATA */
+ 0x00000000 /* DENALI_PHY_167_DATA */
+ 0x02800280 /* DENALI_PHY_168_DATA */
+ 0x02800280 /* DENALI_PHY_169_DATA */
+ 0x02800280 /* DENALI_PHY_170_DATA */
+ 0x02800280 /* DENALI_PHY_171_DATA */
+ 0x00000280 /* DENALI_PHY_172_DATA */
+ 0x00000000 /* DENALI_PHY_173_DATA */
+ 0x00000000 /* DENALI_PHY_174_DATA */
+ 0x00000000 /* DENALI_PHY_175_DATA */
+ 0x00000000 /* DENALI_PHY_176_DATA */
+ 0x00000000 /* DENALI_PHY_177_DATA */
+ 0x00800080 /* DENALI_PHY_178_DATA */
+ 0x00800080 /* DENALI_PHY_179_DATA */
+ 0x00800080 /* DENALI_PHY_180_DATA */
+ 0x00800080 /* DENALI_PHY_181_DATA */
+ 0x00800080 /* DENALI_PHY_182_DATA */
+ 0x00800080 /* DENALI_PHY_183_DATA */
+ 0x00800080 /* DENALI_PHY_184_DATA */
+ 0x00800080 /* DENALI_PHY_185_DATA */
+ 0x00800080 /* DENALI_PHY_186_DATA */
+ 0x000100da /* DENALI_PHY_187_DATA */
+ 0x01000200 /* DENALI_PHY_188_DATA */
+ 0x00000000 /* DENALI_PHY_189_DATA */
+ 0x00000000 /* DENALI_PHY_190_DATA */
+ 0x00000002 /* DENALI_PHY_191_DATA */
+ 0x51313152 /* DENALI_PHY_192_DATA */
+ 0x80013130 /* DENALI_PHY_193_DATA */
+ 0x02000080 /* DENALI_PHY_194_DATA */
+ 0x00100001 /* DENALI_PHY_195_DATA */
+ 0x0c064208 /* DENALI_PHY_196_DATA */
+ 0x000f0c0f /* DENALI_PHY_197_DATA */
+ 0x01000140 /* DENALI_PHY_198_DATA */
+ 0x0000000c /* DENALI_PHY_199_DATA */
+ 0x00000000 /* DENALI_PHY_200_DATA */
+ 0x00000000 /* DENALI_PHY_201_DATA */
+ 0x00000000 /* DENALI_PHY_202_DATA */
+ 0x00000000 /* DENALI_PHY_203_DATA */
+ 0x00000000 /* DENALI_PHY_204_DATA */
+ 0x00000000 /* DENALI_PHY_205_DATA */
+ 0x00000000 /* DENALI_PHY_206_DATA */
+ 0x00000000 /* DENALI_PHY_207_DATA */
+ 0x00000000 /* DENALI_PHY_208_DATA */
+ 0x00000000 /* DENALI_PHY_209_DATA */
+ 0x00000000 /* DENALI_PHY_210_DATA */
+ 0x00000000 /* DENALI_PHY_211_DATA */
+ 0x00000000 /* DENALI_PHY_212_DATA */
+ 0x00000000 /* DENALI_PHY_213_DATA */
+ 0x00000000 /* DENALI_PHY_214_DATA */
+ 0x00000000 /* DENALI_PHY_215_DATA */
+ 0x00000000 /* DENALI_PHY_216_DATA */
+ 0x00000000 /* DENALI_PHY_217_DATA */
+ 0x00000000 /* DENALI_PHY_218_DATA */
+ 0x00000000 /* DENALI_PHY_219_DATA */
+ 0x00000000 /* DENALI_PHY_220_DATA */
+ 0x00000000 /* DENALI_PHY_221_DATA */
+ 0x00000000 /* DENALI_PHY_222_DATA */
+ 0x00000000 /* DENALI_PHY_223_DATA */
+ 0x00000000 /* DENALI_PHY_224_DATA */
+ 0x00000000 /* DENALI_PHY_225_DATA */
+ 0x00000000 /* DENALI_PHY_226_DATA */
+ 0x00000000 /* DENALI_PHY_227_DATA */
+ 0x00000000 /* DENALI_PHY_228_DATA */
+ 0x00000000 /* DENALI_PHY_229_DATA */
+ 0x00000000 /* DENALI_PHY_230_DATA */
+ 0x00000000 /* DENALI_PHY_231_DATA */
+ 0x00000000 /* DENALI_PHY_232_DATA */
+ 0x00000000 /* DENALI_PHY_233_DATA */
+ 0x00000000 /* DENALI_PHY_234_DATA */
+ 0x00000000 /* DENALI_PHY_235_DATA */
+ 0x00000000 /* DENALI_PHY_236_DATA */
+ 0x00000000 /* DENALI_PHY_237_DATA */
+ 0x00000000 /* DENALI_PHY_238_DATA */
+ 0x00000000 /* DENALI_PHY_239_DATA */
+ 0x00000000 /* DENALI_PHY_240_DATA */
+ 0x00000000 /* DENALI_PHY_241_DATA */
+ 0x00000000 /* DENALI_PHY_242_DATA */
+ 0x00000000 /* DENALI_PHY_243_DATA */
+ 0x00000000 /* DENALI_PHY_244_DATA */
+ 0x00000000 /* DENALI_PHY_245_DATA */
+ 0x00000000 /* DENALI_PHY_246_DATA */
+ 0x00000000 /* DENALI_PHY_247_DATA */
+ 0x00000000 /* DENALI_PHY_248_DATA */
+ 0x00000000 /* DENALI_PHY_249_DATA */
+ 0x00000000 /* DENALI_PHY_250_DATA */
+ 0x00000000 /* DENALI_PHY_251_DATA */
+ 0x00000000 /* DENALI_PHY_252_DATA */
+ 0x00000000 /* DENALI_PHY_253_DATA */
+ 0x00000000 /* DENALI_PHY_254_DATA */
+ 0x00000000 /* DENALI_PHY_255_DATA */
+ 0x46052371 /* DENALI_PHY_256_DATA */
+ 0x0004c008 /* DENALI_PHY_257_DATA */
+ 0x000000da /* DENALI_PHY_258_DATA */
+ 0x00000000 /* DENALI_PHY_259_DATA */
+ 0x00000000 /* DENALI_PHY_260_DATA */
+ 0x00010000 /* DENALI_PHY_261_DATA */
+ 0x01DDDD90 /* DENALI_PHY_262_DATA */
+ 0x01DDDD90 /* DENALI_PHY_263_DATA */
+ 0x01030000 /* DENALI_PHY_264_DATA */
+ 0x01000000 /* DENALI_PHY_265_DATA */
+ 0x00c00000 /* DENALI_PHY_266_DATA */
+ 0x00000007 /* DENALI_PHY_267_DATA */
+ 0x00000000 /* DENALI_PHY_268_DATA */
+ 0x00000000 /* DENALI_PHY_269_DATA */
+ 0x04000408 /* DENALI_PHY_270_DATA */
+ 0x00000408 /* DENALI_PHY_271_DATA */
+ 0x00e4e400 /* DENALI_PHY_272_DATA */
+ 0x00000000 /* DENALI_PHY_273_DATA */
+ 0x00000000 /* DENALI_PHY_274_DATA */
+ 0x00000000 /* DENALI_PHY_275_DATA */
+ 0x00000000 /* DENALI_PHY_276_DATA */
+ 0x00000000 /* DENALI_PHY_277_DATA */
+ 0x00000000 /* DENALI_PHY_278_DATA */
+ 0x00000000 /* DENALI_PHY_279_DATA */
+ 0x00000000 /* DENALI_PHY_280_DATA */
+ 0x00000000 /* DENALI_PHY_281_DATA */
+ 0x00000000 /* DENALI_PHY_282_DATA */
+ 0x00000000 /* DENALI_PHY_283_DATA */
+ 0x00000000 /* DENALI_PHY_284_DATA */
+ 0x00000000 /* DENALI_PHY_285_DATA */
+ 0x00000000 /* DENALI_PHY_286_DATA */
+ 0x00000000 /* DENALI_PHY_287_DATA */
+ 0x00000000 /* DENALI_PHY_288_DATA */
+ 0x00200000 /* DENALI_PHY_289_DATA */
+ 0x00000000 /* DENALI_PHY_290_DATA */
+ 0x00000000 /* DENALI_PHY_291_DATA */
+ 0x00000000 /* DENALI_PHY_292_DATA */
+ 0x00000000 /* DENALI_PHY_293_DATA */
+ 0x00000000 /* DENALI_PHY_294_DATA */
+ 0x00000000 /* DENALI_PHY_295_DATA */
+ 0x02800280 /* DENALI_PHY_296_DATA */
+ 0x02800280 /* DENALI_PHY_297_DATA */
+ 0x02800280 /* DENALI_PHY_298_DATA */
+ 0x02800280 /* DENALI_PHY_299_DATA */
+ 0x00000280 /* DENALI_PHY_300_DATA */
+ 0x00000000 /* DENALI_PHY_301_DATA */
+ 0x00000000 /* DENALI_PHY_302_DATA */
+ 0x00000000 /* DENALI_PHY_303_DATA */
+ 0x00000000 /* DENALI_PHY_304_DATA */
+ 0x00000000 /* DENALI_PHY_305_DATA */
+ 0x00800080 /* DENALI_PHY_306_DATA */
+ 0x00800080 /* DENALI_PHY_307_DATA */
+ 0x00800080 /* DENALI_PHY_308_DATA */
+ 0x00800080 /* DENALI_PHY_309_DATA */
+ 0x00800080 /* DENALI_PHY_310_DATA */
+ 0x00800080 /* DENALI_PHY_311_DATA */
+ 0x00800080 /* DENALI_PHY_312_DATA */
+ 0x00800080 /* DENALI_PHY_313_DATA */
+ 0x00800080 /* DENALI_PHY_314_DATA */
+ 0x000100da /* DENALI_PHY_315_DATA */
+ 0x00000200 /* DENALI_PHY_316_DATA */
+ 0x00000000 /* DENALI_PHY_317_DATA */
+ 0x00000000 /* DENALI_PHY_318_DATA */
+ 0x00000002 /* DENALI_PHY_319_DATA */
+ 0x51313152 /* DENALI_PHY_320_DATA */
+ 0x80013130 /* DENALI_PHY_321_DATA */
+ 0x02000080 /* DENALI_PHY_322_DATA */
+ 0x00100001 /* DENALI_PHY_323_DATA */
+ 0x0c064208 /* DENALI_PHY_324_DATA */
+ 0x000f0c0f /* DENALI_PHY_325_DATA */
+ 0x01000140 /* DENALI_PHY_326_DATA */
+ 0x0000000c /* DENALI_PHY_327_DATA */
+ 0x00000000 /* DENALI_PHY_328_DATA */
+ 0x00000000 /* DENALI_PHY_329_DATA */
+ 0x00000000 /* DENALI_PHY_330_DATA */
+ 0x00000000 /* DENALI_PHY_331_DATA */
+ 0x00000000 /* DENALI_PHY_332_DATA */
+ 0x00000000 /* DENALI_PHY_333_DATA */
+ 0x00000000 /* DENALI_PHY_334_DATA */
+ 0x00000000 /* DENALI_PHY_335_DATA */
+ 0x00000000 /* DENALI_PHY_336_DATA */
+ 0x00000000 /* DENALI_PHY_337_DATA */
+ 0x00000000 /* DENALI_PHY_338_DATA */
+ 0x00000000 /* DENALI_PHY_339_DATA */
+ 0x00000000 /* DENALI_PHY_340_DATA */
+ 0x00000000 /* DENALI_PHY_341_DATA */
+ 0x00000000 /* DENALI_PHY_342_DATA */
+ 0x00000000 /* DENALI_PHY_343_DATA */
+ 0x00000000 /* DENALI_PHY_344_DATA */
+ 0x00000000 /* DENALI_PHY_345_DATA */
+ 0x00000000 /* DENALI_PHY_346_DATA */
+ 0x00000000 /* DENALI_PHY_347_DATA */
+ 0x00000000 /* DENALI_PHY_348_DATA */
+ 0x00000000 /* DENALI_PHY_349_DATA */
+ 0x00000000 /* DENALI_PHY_350_DATA */
+ 0x00000000 /* DENALI_PHY_351_DATA */
+ 0x00000000 /* DENALI_PHY_352_DATA */
+ 0x00000000 /* DENALI_PHY_353_DATA */
+ 0x00000000 /* DENALI_PHY_354_DATA */
+ 0x00000000 /* DENALI_PHY_355_DATA */
+ 0x00000000 /* DENALI_PHY_356_DATA */
+ 0x00000000 /* DENALI_PHY_357_DATA */
+ 0x00000000 /* DENALI_PHY_358_DATA */
+ 0x00000000 /* DENALI_PHY_359_DATA */
+ 0x00000000 /* DENALI_PHY_360_DATA */
+ 0x00000000 /* DENALI_PHY_361_DATA */
+ 0x00000000 /* DENALI_PHY_362_DATA */
+ 0x00000000 /* DENALI_PHY_363_DATA */
+ 0x00000000 /* DENALI_PHY_364_DATA */
+ 0x00000000 /* DENALI_PHY_365_DATA */
+ 0x00000000 /* DENALI_PHY_366_DATA */
+ 0x00000000 /* DENALI_PHY_367_DATA */
+ 0x00000000 /* DENALI_PHY_368_DATA */
+ 0x00000000 /* DENALI_PHY_369_DATA */
+ 0x00000000 /* DENALI_PHY_370_DATA */
+ 0x00000000 /* DENALI_PHY_371_DATA */
+ 0x00000000 /* DENALI_PHY_372_DATA */
+ 0x00000000 /* DENALI_PHY_373_DATA */
+ 0x00000000 /* DENALI_PHY_374_DATA */
+ 0x00000000 /* DENALI_PHY_375_DATA */
+ 0x00000000 /* DENALI_PHY_376_DATA */
+ 0x00000000 /* DENALI_PHY_377_DATA */
+ 0x00000000 /* DENALI_PHY_378_DATA */
+ 0x00000000 /* DENALI_PHY_379_DATA */
+ 0x00000000 /* DENALI_PHY_380_DATA */
+ 0x00000000 /* DENALI_PHY_381_DATA */
+ 0x00000000 /* DENALI_PHY_382_DATA */
+ 0x00000000 /* DENALI_PHY_383_DATA */
+ 0x37654120 /* DENALI_PHY_384_DATA */
+ 0x0004c008 /* DENALI_PHY_385_DATA */
+ 0x000000da /* DENALI_PHY_386_DATA */
+ 0x00000000 /* DENALI_PHY_387_DATA */
+ 0x00000000 /* DENALI_PHY_388_DATA */
+ 0x00010000 /* DENALI_PHY_389_DATA */
+ 0x01DDDD90 /* DENALI_PHY_390_DATA */
+ 0x01DDDD90 /* DENALI_PHY_391_DATA */
+ 0x01030000 /* DENALI_PHY_392_DATA */
+ 0x01000000 /* DENALI_PHY_393_DATA */
+ 0x00c00000 /* DENALI_PHY_394_DATA */
+ 0x00000007 /* DENALI_PHY_395_DATA */
+ 0x00000000 /* DENALI_PHY_396_DATA */
+ 0x00000000 /* DENALI_PHY_397_DATA */
+ 0x04000408 /* DENALI_PHY_398_DATA */
+ 0x00000408 /* DENALI_PHY_399_DATA */
+ 0x00e4e400 /* DENALI_PHY_400_DATA */
+ 0x00000000 /* DENALI_PHY_401_DATA */
+ 0x00000000 /* DENALI_PHY_402_DATA */
+ 0x00000000 /* DENALI_PHY_403_DATA */
+ 0x00000000 /* DENALI_PHY_404_DATA */
+ 0x00000000 /* DENALI_PHY_405_DATA */
+ 0x00000000 /* DENALI_PHY_406_DATA */
+ 0x00000000 /* DENALI_PHY_407_DATA */
+ 0x00000000 /* DENALI_PHY_408_DATA */
+ 0x00000000 /* DENALI_PHY_409_DATA */
+ 0x00000000 /* DENALI_PHY_410_DATA */
+ 0x00000000 /* DENALI_PHY_411_DATA */
+ 0x00000000 /* DENALI_PHY_412_DATA */
+ 0x00000000 /* DENALI_PHY_413_DATA */
+ 0x00000000 /* DENALI_PHY_414_DATA */
+ 0x00000000 /* DENALI_PHY_415_DATA */
+ 0x00000000 /* DENALI_PHY_416_DATA */
+ 0x00200000 /* DENALI_PHY_417_DATA */
+ 0x00000000 /* DENALI_PHY_418_DATA */
+ 0x00000000 /* DENALI_PHY_419_DATA */
+ 0x00000000 /* DENALI_PHY_420_DATA */
+ 0x00000000 /* DENALI_PHY_421_DATA */
+ 0x00000000 /* DENALI_PHY_422_DATA */
+ 0x00000000 /* DENALI_PHY_423_DATA */
+ 0x02800280 /* DENALI_PHY_424_DATA */
+ 0x02800280 /* DENALI_PHY_425_DATA */
+ 0x02800280 /* DENALI_PHY_426_DATA */
+ 0x02800280 /* DENALI_PHY_427_DATA */
+ 0x00000280 /* DENALI_PHY_428_DATA */
+ 0x00000000 /* DENALI_PHY_429_DATA */
+ 0x00000000 /* DENALI_PHY_430_DATA */
+ 0x00000000 /* DENALI_PHY_431_DATA */
+ 0x00000000 /* DENALI_PHY_432_DATA */
+ 0x00000000 /* DENALI_PHY_433_DATA */
+ 0x00800080 /* DENALI_PHY_434_DATA */
+ 0x00800080 /* DENALI_PHY_435_DATA */
+ 0x00800080 /* DENALI_PHY_436_DATA */
+ 0x00800080 /* DENALI_PHY_437_DATA */
+ 0x00800080 /* DENALI_PHY_438_DATA */
+ 0x00800080 /* DENALI_PHY_439_DATA */
+ 0x00800080 /* DENALI_PHY_440_DATA */
+ 0x00800080 /* DENALI_PHY_441_DATA */
+ 0x00800080 /* DENALI_PHY_442_DATA */
+ 0x000100da /* DENALI_PHY_443_DATA */
+ 0x00000200 /* DENALI_PHY_444_DATA */
+ 0x00000000 /* DENALI_PHY_445_DATA */
+ 0x00000000 /* DENALI_PHY_446_DATA */
+ 0x00000002 /* DENALI_PHY_447_DATA */
+ 0x51313152 /* DENALI_PHY_448_DATA */
+ 0x80013130 /* DENALI_PHY_449_DATA */
+ 0x02000080 /* DENALI_PHY_450_DATA */
+ 0x00100001 /* DENALI_PHY_451_DATA */
+ 0x0c064208 /* DENALI_PHY_452_DATA */
+ 0x000f0c0f /* DENALI_PHY_453_DATA */
+ 0x01000140 /* DENALI_PHY_454_DATA */
+ 0x0000000c /* DENALI_PHY_455_DATA */
+ 0x00000000 /* DENALI_PHY_456_DATA */
+ 0x00000000 /* DENALI_PHY_457_DATA */
+ 0x00000000 /* DENALI_PHY_458_DATA */
+ 0x00000000 /* DENALI_PHY_459_DATA */
+ 0x00000000 /* DENALI_PHY_460_DATA */
+ 0x00000000 /* DENALI_PHY_461_DATA */
+ 0x00000000 /* DENALI_PHY_462_DATA */
+ 0x00000000 /* DENALI_PHY_463_DATA */
+ 0x00000000 /* DENALI_PHY_464_DATA */
+ 0x00000000 /* DENALI_PHY_465_DATA */
+ 0x00000000 /* DENALI_PHY_466_DATA */
+ 0x00000000 /* DENALI_PHY_467_DATA */
+ 0x00000000 /* DENALI_PHY_468_DATA */
+ 0x00000000 /* DENALI_PHY_469_DATA */
+ 0x00000000 /* DENALI_PHY_470_DATA */
+ 0x00000000 /* DENALI_PHY_471_DATA */
+ 0x00000000 /* DENALI_PHY_472_DATA */
+ 0x00000000 /* DENALI_PHY_473_DATA */
+ 0x00000000 /* DENALI_PHY_474_DATA */
+ 0x00000000 /* DENALI_PHY_475_DATA */
+ 0x00000000 /* DENALI_PHY_476_DATA */
+ 0x00000000 /* DENALI_PHY_477_DATA */
+ 0x00000000 /* DENALI_PHY_478_DATA */
+ 0x00000000 /* DENALI_PHY_479_DATA */
+ 0x00000000 /* DENALI_PHY_480_DATA */
+ 0x00000000 /* DENALI_PHY_481_DATA */
+ 0x00000000 /* DENALI_PHY_482_DATA */
+ 0x00000000 /* DENALI_PHY_483_DATA */
+ 0x00000000 /* DENALI_PHY_484_DATA */
+ 0x00000000 /* DENALI_PHY_485_DATA */
+ 0x00000000 /* DENALI_PHY_486_DATA */
+ 0x00000000 /* DENALI_PHY_487_DATA */
+ 0x00000000 /* DENALI_PHY_488_DATA */
+ 0x00000000 /* DENALI_PHY_489_DATA */
+ 0x00000000 /* DENALI_PHY_490_DATA */
+ 0x00000000 /* DENALI_PHY_491_DATA */
+ 0x00000000 /* DENALI_PHY_492_DATA */
+ 0x00000000 /* DENALI_PHY_493_DATA */
+ 0x00000000 /* DENALI_PHY_494_DATA */
+ 0x00000000 /* DENALI_PHY_495_DATA */
+ 0x00000000 /* DENALI_PHY_496_DATA */
+ 0x00000000 /* DENALI_PHY_497_DATA */
+ 0x00000000 /* DENALI_PHY_498_DATA */
+ 0x00000000 /* DENALI_PHY_499_DATA */
+ 0x00000000 /* DENALI_PHY_500_DATA */
+ 0x00000000 /* DENALI_PHY_501_DATA */
+ 0x00000000 /* DENALI_PHY_502_DATA */
+ 0x00000000 /* DENALI_PHY_503_DATA */
+ 0x00000000 /* DENALI_PHY_504_DATA */
+ 0x00000000 /* DENALI_PHY_505_DATA */
+ 0x00000000 /* DENALI_PHY_506_DATA */
+ 0x00000000 /* DENALI_PHY_507_DATA */
+ 0x00000000 /* DENALI_PHY_508_DATA */
+ 0x00000000 /* DENALI_PHY_509_DATA */
+ 0x00000000 /* DENALI_PHY_510_DATA */
+ 0x00000000 /* DENALI_PHY_511_DATA */
+ 0x24316750 /* DENALI_PHY_512_DATA */
+ 0x0004c008 /* DENALI_PHY_513_DATA */
+ 0x000000da /* DENALI_PHY_514_DATA */
+ 0x00000000 /* DENALI_PHY_515_DATA */
+ 0x00000000 /* DENALI_PHY_516_DATA */
+ 0x00010000 /* DENALI_PHY_517_DATA */
+ 0x01DDDD90 /* DENALI_PHY_518_DATA */
+ 0x01DDDD90 /* DENALI_PHY_519_DATA */
+ 0x01030000 /* DENALI_PHY_520_DATA */
+ 0x01000000 /* DENALI_PHY_521_DATA */
+ 0x00c00000 /* DENALI_PHY_522_DATA */
+ 0x00000007 /* DENALI_PHY_523_DATA */
+ 0x00000000 /* DENALI_PHY_524_DATA */
+ 0x00000000 /* DENALI_PHY_525_DATA */
+ 0x04000408 /* DENALI_PHY_526_DATA */
+ 0x00000408 /* DENALI_PHY_527_DATA */
+ 0x00e4e400 /* DENALI_PHY_528_DATA */
+ 0x00000000 /* DENALI_PHY_529_DATA */
+ 0x00000000 /* DENALI_PHY_530_DATA */
+ 0x00000000 /* DENALI_PHY_531_DATA */
+ 0x00000000 /* DENALI_PHY_532_DATA */
+ 0x00000000 /* DENALI_PHY_533_DATA */
+ 0x00000000 /* DENALI_PHY_534_DATA */
+ 0x00000000 /* DENALI_PHY_535_DATA */
+ 0x00000000 /* DENALI_PHY_536_DATA */
+ 0x00000000 /* DENALI_PHY_537_DATA */
+ 0x00000000 /* DENALI_PHY_538_DATA */
+ 0x00000000 /* DENALI_PHY_539_DATA */
+ 0x00000000 /* DENALI_PHY_540_DATA */
+ 0x00000000 /* DENALI_PHY_541_DATA */
+ 0x00000000 /* DENALI_PHY_542_DATA */
+ 0x00000000 /* DENALI_PHY_543_DATA */
+ 0x00000000 /* DENALI_PHY_544_DATA */
+ 0x00200000 /* DENALI_PHY_545_DATA */
+ 0x00000000 /* DENALI_PHY_546_DATA */
+ 0x00000000 /* DENALI_PHY_547_DATA */
+ 0x00000000 /* DENALI_PHY_548_DATA */
+ 0x00000000 /* DENALI_PHY_549_DATA */
+ 0x00000000 /* DENALI_PHY_550_DATA */
+ 0x00000000 /* DENALI_PHY_551_DATA */
+ 0x02800280 /* DENALI_PHY_552_DATA */
+ 0x02800280 /* DENALI_PHY_553_DATA */
+ 0x02800280 /* DENALI_PHY_554_DATA */
+ 0x02800280 /* DENALI_PHY_555_DATA */
+ 0x00000280 /* DENALI_PHY_556_DATA */
+ 0x00000000 /* DENALI_PHY_557_DATA */
+ 0x00000000 /* DENALI_PHY_558_DATA */
+ 0x00000000 /* DENALI_PHY_559_DATA */
+ 0x00000000 /* DENALI_PHY_560_DATA */
+ 0x00000000 /* DENALI_PHY_561_DATA */
+ 0x00800080 /* DENALI_PHY_562_DATA */
+ 0x00800080 /* DENALI_PHY_563_DATA */
+ 0x00800080 /* DENALI_PHY_564_DATA */
+ 0x00800080 /* DENALI_PHY_565_DATA */
+ 0x00800080 /* DENALI_PHY_566_DATA */
+ 0x00800080 /* DENALI_PHY_567_DATA */
+ 0x00800080 /* DENALI_PHY_568_DATA */
+ 0x00800080 /* DENALI_PHY_569_DATA */
+ 0x00800080 /* DENALI_PHY_570_DATA */
+ 0x000100da /* DENALI_PHY_571_DATA */
+ 0x00000200 /* DENALI_PHY_572_DATA */
+ 0x00000000 /* DENALI_PHY_573_DATA */
+ 0x00000000 /* DENALI_PHY_574_DATA */
+ 0x00000002 /* DENALI_PHY_575_DATA */
+ 0x51313152 /* DENALI_PHY_576_DATA */
+ 0x80013130 /* DENALI_PHY_577_DATA */
+ 0x02000080 /* DENALI_PHY_578_DATA */
+ 0x00100001 /* DENALI_PHY_579_DATA */
+ 0x0c064208 /* DENALI_PHY_580_DATA */
+ 0x000f0c0f /* DENALI_PHY_581_DATA */
+ 0x01000140 /* DENALI_PHY_582_DATA */
+ 0x0000000c /* DENALI_PHY_583_DATA */
+ 0x00000000 /* DENALI_PHY_584_DATA */
+ 0x00000000 /* DENALI_PHY_585_DATA */
+ 0x00000000 /* DENALI_PHY_586_DATA */
+ 0x00000000 /* DENALI_PHY_587_DATA */
+ 0x00000000 /* DENALI_PHY_588_DATA */
+ 0x00000000 /* DENALI_PHY_589_DATA */
+ 0x00000000 /* DENALI_PHY_590_DATA */
+ 0x00000000 /* DENALI_PHY_591_DATA */
+ 0x00000000 /* DENALI_PHY_592_DATA */
+ 0x00000000 /* DENALI_PHY_593_DATA */
+ 0x00000000 /* DENALI_PHY_594_DATA */
+ 0x00000000 /* DENALI_PHY_595_DATA */
+ 0x00000000 /* DENALI_PHY_596_DATA */
+ 0x00000000 /* DENALI_PHY_597_DATA */
+ 0x00000000 /* DENALI_PHY_598_DATA */
+ 0x00000000 /* DENALI_PHY_599_DATA */
+ 0x00000000 /* DENALI_PHY_600_DATA */
+ 0x00000000 /* DENALI_PHY_601_DATA */
+ 0x00000000 /* DENALI_PHY_602_DATA */
+ 0x00000000 /* DENALI_PHY_603_DATA */
+ 0x00000000 /* DENALI_PHY_604_DATA */
+ 0x00000000 /* DENALI_PHY_605_DATA */
+ 0x00000000 /* DENALI_PHY_606_DATA */
+ 0x00000000 /* DENALI_PHY_607_DATA */
+ 0x00000000 /* DENALI_PHY_608_DATA */
+ 0x00000000 /* DENALI_PHY_609_DATA */
+ 0x00000000 /* DENALI_PHY_610_DATA */
+ 0x00000000 /* DENALI_PHY_611_DATA */
+ 0x00000000 /* DENALI_PHY_612_DATA */
+ 0x00000000 /* DENALI_PHY_613_DATA */
+ 0x00000000 /* DENALI_PHY_614_DATA */
+ 0x00000000 /* DENALI_PHY_615_DATA */
+ 0x00000000 /* DENALI_PHY_616_DATA */
+ 0x00000000 /* DENALI_PHY_617_DATA */
+ 0x00000000 /* DENALI_PHY_618_DATA */
+ 0x00000000 /* DENALI_PHY_619_DATA */
+ 0x00000000 /* DENALI_PHY_620_DATA */
+ 0x00000000 /* DENALI_PHY_621_DATA */
+ 0x00000000 /* DENALI_PHY_622_DATA */
+ 0x00000000 /* DENALI_PHY_623_DATA */
+ 0x00000000 /* DENALI_PHY_624_DATA */
+ 0x00000000 /* DENALI_PHY_625_DATA */
+ 0x00000000 /* DENALI_PHY_626_DATA */
+ 0x00000000 /* DENALI_PHY_627_DATA */
+ 0x00000000 /* DENALI_PHY_628_DATA */
+ 0x00000000 /* DENALI_PHY_629_DATA */
+ 0x00000000 /* DENALI_PHY_630_DATA */
+ 0x00000000 /* DENALI_PHY_631_DATA */
+ 0x00000000 /* DENALI_PHY_632_DATA */
+ 0x00000000 /* DENALI_PHY_633_DATA */
+ 0x00000000 /* DENALI_PHY_634_DATA */
+ 0x00000000 /* DENALI_PHY_635_DATA */
+ 0x00000000 /* DENALI_PHY_636_DATA */
+ 0x00000000 /* DENALI_PHY_637_DATA */
+ 0x00000000 /* DENALI_PHY_638_DATA */
+ 0x00000000 /* DENALI_PHY_639_DATA */
+ 0x35174620 /* DENALI_PHY_640_DATA */
+ 0x0004c008 /* DENALI_PHY_641_DATA */
+ 0x000000da /* DENALI_PHY_642_DATA */
+ 0x00000000 /* DENALI_PHY_643_DATA */
+ 0x00000000 /* DENALI_PHY_644_DATA */
+ 0x00010000 /* DENALI_PHY_645_DATA */
+ 0x01DDDD90 /* DENALI_PHY_646_DATA */
+ 0x01DDDD90 /* DENALI_PHY_647_DATA */
+ 0x01030000 /* DENALI_PHY_648_DATA */
+ 0x01000000 /* DENALI_PHY_649_DATA */
+ 0x00c00000 /* DENALI_PHY_650_DATA */
+ 0x00000007 /* DENALI_PHY_651_DATA */
+ 0x00000000 /* DENALI_PHY_652_DATA */
+ 0x00000000 /* DENALI_PHY_653_DATA */
+ 0x04000408 /* DENALI_PHY_654_DATA */
+ 0x00000408 /* DENALI_PHY_655_DATA */
+ 0x00e4e400 /* DENALI_PHY_656_DATA */
+ 0x00000000 /* DENALI_PHY_657_DATA */
+ 0x00000000 /* DENALI_PHY_658_DATA */
+ 0x00000000 /* DENALI_PHY_659_DATA */
+ 0x00000000 /* DENALI_PHY_660_DATA */
+ 0x00000000 /* DENALI_PHY_661_DATA */
+ 0x00000000 /* DENALI_PHY_662_DATA */
+ 0x00000000 /* DENALI_PHY_663_DATA */
+ 0x00000000 /* DENALI_PHY_664_DATA */
+ 0x00000000 /* DENALI_PHY_665_DATA */
+ 0x00000000 /* DENALI_PHY_666_DATA */
+ 0x00000000 /* DENALI_PHY_667_DATA */
+ 0x00000000 /* DENALI_PHY_668_DATA */
+ 0x00000000 /* DENALI_PHY_669_DATA */
+ 0x00000000 /* DENALI_PHY_670_DATA */
+ 0x00000000 /* DENALI_PHY_671_DATA */
+ 0x00000000 /* DENALI_PHY_672_DATA */
+ 0x00200000 /* DENALI_PHY_673_DATA */
+ 0x00000000 /* DENALI_PHY_674_DATA */
+ 0x00000000 /* DENALI_PHY_675_DATA */
+ 0x00000000 /* DENALI_PHY_676_DATA */
+ 0x00000000 /* DENALI_PHY_677_DATA */
+ 0x00000000 /* DENALI_PHY_678_DATA */
+ 0x00000000 /* DENALI_PHY_679_DATA */
+ 0x02800280 /* DENALI_PHY_680_DATA */
+ 0x02800280 /* DENALI_PHY_681_DATA */
+ 0x02800280 /* DENALI_PHY_682_DATA */
+ 0x02800280 /* DENALI_PHY_683_DATA */
+ 0x00000280 /* DENALI_PHY_684_DATA */
+ 0x00000000 /* DENALI_PHY_685_DATA */
+ 0x00000000 /* DENALI_PHY_686_DATA */
+ 0x00000000 /* DENALI_PHY_687_DATA */
+ 0x00000000 /* DENALI_PHY_688_DATA */
+ 0x00000000 /* DENALI_PHY_689_DATA */
+ 0x00800080 /* DENALI_PHY_690_DATA */
+ 0x00800080 /* DENALI_PHY_691_DATA */
+ 0x00800080 /* DENALI_PHY_692_DATA */
+ 0x00800080 /* DENALI_PHY_693_DATA */
+ 0x00800080 /* DENALI_PHY_694_DATA */
+ 0x00800080 /* DENALI_PHY_695_DATA */
+ 0x00800080 /* DENALI_PHY_696_DATA */
+ 0x00800080 /* DENALI_PHY_697_DATA */
+ 0x00800080 /* DENALI_PHY_698_DATA */
+ 0x000100da /* DENALI_PHY_699_DATA */
+ 0x00000200 /* DENALI_PHY_700_DATA */
+ 0x00000000 /* DENALI_PHY_701_DATA */
+ 0x00000000 /* DENALI_PHY_702_DATA */
+ 0x00000002 /* DENALI_PHY_703_DATA */
+ 0x51313152 /* DENALI_PHY_704_DATA */
+ 0x80013130 /* DENALI_PHY_705_DATA */
+ 0x02000080 /* DENALI_PHY_706_DATA */
+ 0x00100001 /* DENALI_PHY_707_DATA */
+ 0x0c064208 /* DENALI_PHY_708_DATA */
+ 0x000f0c0f /* DENALI_PHY_709_DATA */
+ 0x01000140 /* DENALI_PHY_710_DATA */
+ 0x0000000c /* DENALI_PHY_711_DATA */
+ 0x00000000 /* DENALI_PHY_712_DATA */
+ 0x00000000 /* DENALI_PHY_713_DATA */
+ 0x00000000 /* DENALI_PHY_714_DATA */
+ 0x00000000 /* DENALI_PHY_715_DATA */
+ 0x00000000 /* DENALI_PHY_716_DATA */
+ 0x00000000 /* DENALI_PHY_717_DATA */
+ 0x00000000 /* DENALI_PHY_718_DATA */
+ 0x00000000 /* DENALI_PHY_719_DATA */
+ 0x00000000 /* DENALI_PHY_720_DATA */
+ 0x00000000 /* DENALI_PHY_721_DATA */
+ 0x00000000 /* DENALI_PHY_722_DATA */
+ 0x00000000 /* DENALI_PHY_723_DATA */
+ 0x00000000 /* DENALI_PHY_724_DATA */
+ 0x00000000 /* DENALI_PHY_725_DATA */
+ 0x00000000 /* DENALI_PHY_726_DATA */
+ 0x00000000 /* DENALI_PHY_727_DATA */
+ 0x00000000 /* DENALI_PHY_728_DATA */
+ 0x00000000 /* DENALI_PHY_729_DATA */
+ 0x00000000 /* DENALI_PHY_730_DATA */
+ 0x00000000 /* DENALI_PHY_731_DATA */
+ 0x00000000 /* DENALI_PHY_732_DATA */
+ 0x00000000 /* DENALI_PHY_733_DATA */
+ 0x00000000 /* DENALI_PHY_734_DATA */
+ 0x00000000 /* DENALI_PHY_735_DATA */
+ 0x00000000 /* DENALI_PHY_736_DATA */
+ 0x00000000 /* DENALI_PHY_737_DATA */
+ 0x00000000 /* DENALI_PHY_738_DATA */
+ 0x00000000 /* DENALI_PHY_739_DATA */
+ 0x00000000 /* DENALI_PHY_740_DATA */
+ 0x00000000 /* DENALI_PHY_741_DATA */
+ 0x00000000 /* DENALI_PHY_742_DATA */
+ 0x00000000 /* DENALI_PHY_743_DATA */
+ 0x00000000 /* DENALI_PHY_744_DATA */
+ 0x00000000 /* DENALI_PHY_745_DATA */
+ 0x00000000 /* DENALI_PHY_746_DATA */
+ 0x00000000 /* DENALI_PHY_747_DATA */
+ 0x00000000 /* DENALI_PHY_748_DATA */
+ 0x00000000 /* DENALI_PHY_749_DATA */
+ 0x00000000 /* DENALI_PHY_750_DATA */
+ 0x00000000 /* DENALI_PHY_751_DATA */
+ 0x00000000 /* DENALI_PHY_752_DATA */
+ 0x00000000 /* DENALI_PHY_753_DATA */
+ 0x00000000 /* DENALI_PHY_754_DATA */
+ 0x00000000 /* DENALI_PHY_755_DATA */
+ 0x00000000 /* DENALI_PHY_756_DATA */
+ 0x00000000 /* DENALI_PHY_757_DATA */
+ 0x00000000 /* DENALI_PHY_758_DATA */
+ 0x00000000 /* DENALI_PHY_759_DATA */
+ 0x00000000 /* DENALI_PHY_760_DATA */
+ 0x00000000 /* DENALI_PHY_761_DATA */
+ 0x00000000 /* DENALI_PHY_762_DATA */
+ 0x00000000 /* DENALI_PHY_763_DATA */
+ 0x00000000 /* DENALI_PHY_764_DATA */
+ 0x00000000 /* DENALI_PHY_765_DATA */
+ 0x00000000 /* DENALI_PHY_766_DATA */
+ 0x00000000 /* DENALI_PHY_767_DATA */
+ 0x15203476 /* DENALI_PHY_768_DATA */
+ 0x0004c008 /* DENALI_PHY_769_DATA */
+ 0x000000da /* DENALI_PHY_770_DATA */
+ 0x00000000 /* DENALI_PHY_771_DATA */
+ 0x00000000 /* DENALI_PHY_772_DATA */
+ 0x00010000 /* DENALI_PHY_773_DATA */
+ 0x01DDDD90 /* DENALI_PHY_774_DATA */
+ 0x01DDDD90 /* DENALI_PHY_775_DATA */
+ 0x01030000 /* DENALI_PHY_776_DATA */
+ 0x01000000 /* DENALI_PHY_777_DATA */
+ 0x00c00000 /* DENALI_PHY_778_DATA */
+ 0x00000007 /* DENALI_PHY_779_DATA */
+ 0x00000000 /* DENALI_PHY_780_DATA */
+ 0x00000000 /* DENALI_PHY_781_DATA */
+ 0x04000408 /* DENALI_PHY_782_DATA */
+ 0x00000408 /* DENALI_PHY_783_DATA */
+ 0x00e4e400 /* DENALI_PHY_784_DATA */
+ 0x00000000 /* DENALI_PHY_785_DATA */
+ 0x00000000 /* DENALI_PHY_786_DATA */
+ 0x00000000 /* DENALI_PHY_787_DATA */
+ 0x00000000 /* DENALI_PHY_788_DATA */
+ 0x00000000 /* DENALI_PHY_789_DATA */
+ 0x00000000 /* DENALI_PHY_790_DATA */
+ 0x00000000 /* DENALI_PHY_791_DATA */
+ 0x00000000 /* DENALI_PHY_792_DATA */
+ 0x00000000 /* DENALI_PHY_793_DATA */
+ 0x00000000 /* DENALI_PHY_794_DATA */
+ 0x00000000 /* DENALI_PHY_795_DATA */
+ 0x00000000 /* DENALI_PHY_796_DATA */
+ 0x00000000 /* DENALI_PHY_797_DATA */
+ 0x00000000 /* DENALI_PHY_798_DATA */
+ 0x00000000 /* DENALI_PHY_799_DATA */
+ 0x00000000 /* DENALI_PHY_800_DATA */
+ 0x00200000 /* DENALI_PHY_801_DATA */
+ 0x00000000 /* DENALI_PHY_802_DATA */
+ 0x00000000 /* DENALI_PHY_803_DATA */
+ 0x00000000 /* DENALI_PHY_804_DATA */
+ 0x00000000 /* DENALI_PHY_805_DATA */
+ 0x00000000 /* DENALI_PHY_806_DATA */
+ 0x00000000 /* DENALI_PHY_807_DATA */
+ 0x02800280 /* DENALI_PHY_808_DATA */
+ 0x02800280 /* DENALI_PHY_809_DATA */
+ 0x02800280 /* DENALI_PHY_810_DATA */
+ 0x02800280 /* DENALI_PHY_811_DATA */
+ 0x00000280 /* DENALI_PHY_812_DATA */
+ 0x00000000 /* DENALI_PHY_813_DATA */
+ 0x00000000 /* DENALI_PHY_814_DATA */
+ 0x00000000 /* DENALI_PHY_815_DATA */
+ 0x00000000 /* DENALI_PHY_816_DATA */
+ 0x00000000 /* DENALI_PHY_817_DATA */
+ 0x00800080 /* DENALI_PHY_818_DATA */
+ 0x00800080 /* DENALI_PHY_819_DATA */
+ 0x00800080 /* DENALI_PHY_820_DATA */
+ 0x00800080 /* DENALI_PHY_821_DATA */
+ 0x00800080 /* DENALI_PHY_822_DATA */
+ 0x00800080 /* DENALI_PHY_823_DATA */
+ 0x00800080 /* DENALI_PHY_824_DATA */
+ 0x00800080 /* DENALI_PHY_825_DATA */
+ 0x00800080 /* DENALI_PHY_826_DATA */
+ 0x000100da /* DENALI_PHY_827_DATA */
+ 0x00000200 /* DENALI_PHY_828_DATA */
+ 0x00000000 /* DENALI_PHY_829_DATA */
+ 0x00000000 /* DENALI_PHY_830_DATA */
+ 0x00000002 /* DENALI_PHY_831_DATA */
+ 0x51313152 /* DENALI_PHY_832_DATA */
+ 0x80013130 /* DENALI_PHY_833_DATA */
+ 0x02000080 /* DENALI_PHY_834_DATA */
+ 0x00100001 /* DENALI_PHY_835_DATA */
+ 0x0c064208 /* DENALI_PHY_836_DATA */
+ 0x000f0c0f /* DENALI_PHY_837_DATA */
+ 0x01000140 /* DENALI_PHY_838_DATA */
+ 0x0000000c /* DENALI_PHY_839_DATA */
+ 0x00000000 /* DENALI_PHY_840_DATA */
+ 0x00000000 /* DENALI_PHY_841_DATA */
+ 0x00000000 /* DENALI_PHY_842_DATA */
+ 0x00000000 /* DENALI_PHY_843_DATA */
+ 0x00000000 /* DENALI_PHY_844_DATA */
+ 0x00000000 /* DENALI_PHY_845_DATA */
+ 0x00000000 /* DENALI_PHY_846_DATA */
+ 0x00000000 /* DENALI_PHY_847_DATA */
+ 0x00000000 /* DENALI_PHY_848_DATA */
+ 0x00000000 /* DENALI_PHY_849_DATA */
+ 0x00000000 /* DENALI_PHY_850_DATA */
+ 0x00000000 /* DENALI_PHY_851_DATA */
+ 0x00000000 /* DENALI_PHY_852_DATA */
+ 0x00000000 /* DENALI_PHY_853_DATA */
+ 0x00000000 /* DENALI_PHY_854_DATA */
+ 0x00000000 /* DENALI_PHY_855_DATA */
+ 0x00000000 /* DENALI_PHY_856_DATA */
+ 0x00000000 /* DENALI_PHY_857_DATA */
+ 0x00000000 /* DENALI_PHY_858_DATA */
+ 0x00000000 /* DENALI_PHY_859_DATA */
+ 0x00000000 /* DENALI_PHY_860_DATA */
+ 0x00000000 /* DENALI_PHY_861_DATA */
+ 0x00000000 /* DENALI_PHY_862_DATA */
+ 0x00000000 /* DENALI_PHY_863_DATA */
+ 0x00000000 /* DENALI_PHY_864_DATA */
+ 0x00000000 /* DENALI_PHY_865_DATA */
+ 0x00000000 /* DENALI_PHY_866_DATA */
+ 0x00000000 /* DENALI_PHY_867_DATA */
+ 0x00000000 /* DENALI_PHY_868_DATA */
+ 0x00000000 /* DENALI_PHY_869_DATA */
+ 0x00000000 /* DENALI_PHY_870_DATA */
+ 0x00000000 /* DENALI_PHY_871_DATA */
+ 0x00000000 /* DENALI_PHY_872_DATA */
+ 0x00000000 /* DENALI_PHY_873_DATA */
+ 0x00000000 /* DENALI_PHY_874_DATA */
+ 0x00000000 /* DENALI_PHY_875_DATA */
+ 0x00000000 /* DENALI_PHY_876_DATA */
+ 0x00000000 /* DENALI_PHY_877_DATA */
+ 0x00000000 /* DENALI_PHY_878_DATA */
+ 0x00000000 /* DENALI_PHY_879_DATA */
+ 0x00000000 /* DENALI_PHY_880_DATA */
+ 0x00000000 /* DENALI_PHY_881_DATA */
+ 0x00000000 /* DENALI_PHY_882_DATA */
+ 0x00000000 /* DENALI_PHY_883_DATA */
+ 0x00000000 /* DENALI_PHY_884_DATA */
+ 0x00000000 /* DENALI_PHY_885_DATA */
+ 0x00000000 /* DENALI_PHY_886_DATA */
+ 0x00000000 /* DENALI_PHY_887_DATA */
+ 0x00000000 /* DENALI_PHY_888_DATA */
+ 0x00000000 /* DENALI_PHY_889_DATA */
+ 0x00000000 /* DENALI_PHY_890_DATA */
+ 0x00000000 /* DENALI_PHY_891_DATA */
+ 0x00000000 /* DENALI_PHY_892_DATA */
+ 0x00000000 /* DENALI_PHY_893_DATA */
+ 0x00000000 /* DENALI_PHY_894_DATA */
+ 0x00000000 /* DENALI_PHY_895_DATA */
+ 0x41753206 /* DENALI_PHY_896_DATA */
+ 0x0004c008 /* DENALI_PHY_897_DATA */
+ 0x000000da /* DENALI_PHY_898_DATA */
+ 0x00000000 /* DENALI_PHY_899_DATA */
+ 0x00000000 /* DENALI_PHY_900_DATA */
+ 0x00010000 /* DENALI_PHY_901_DATA */
+ 0x01DDDD90 /* DENALI_PHY_902_DATA */
+ 0x01DDDD90 /* DENALI_PHY_903_DATA */
+ 0x01030000 /* DENALI_PHY_904_DATA */
+ 0x01000000 /* DENALI_PHY_905_DATA */
+ 0x00c00000 /* DENALI_PHY_906_DATA */
+ 0x00000007 /* DENALI_PHY_907_DATA */
+ 0x00000000 /* DENALI_PHY_908_DATA */
+ 0x00000000 /* DENALI_PHY_909_DATA */
+ 0x04000408 /* DENALI_PHY_910_DATA */
+ 0x00000408 /* DENALI_PHY_911_DATA */
+ 0x00e4e400 /* DENALI_PHY_912_DATA */
+ 0x00000000 /* DENALI_PHY_913_DATA */
+ 0x00000000 /* DENALI_PHY_914_DATA */
+ 0x00000000 /* DENALI_PHY_915_DATA */
+ 0x00000000 /* DENALI_PHY_916_DATA */
+ 0x00000000 /* DENALI_PHY_917_DATA */
+ 0x00000000 /* DENALI_PHY_918_DATA */
+ 0x00000000 /* DENALI_PHY_919_DATA */
+ 0x00000000 /* DENALI_PHY_920_DATA */
+ 0x00000000 /* DENALI_PHY_921_DATA */
+ 0x00000000 /* DENALI_PHY_922_DATA */
+ 0x00000000 /* DENALI_PHY_923_DATA */
+ 0x00000000 /* DENALI_PHY_924_DATA */
+ 0x00000000 /* DENALI_PHY_925_DATA */
+ 0x00000000 /* DENALI_PHY_926_DATA */
+ 0x00000000 /* DENALI_PHY_927_DATA */
+ 0x00000000 /* DENALI_PHY_928_DATA */
+ 0x00200000 /* DENALI_PHY_929_DATA */
+ 0x00000000 /* DENALI_PHY_930_DATA */
+ 0x00000000 /* DENALI_PHY_931_DATA */
+ 0x00000000 /* DENALI_PHY_932_DATA */
+ 0x00000000 /* DENALI_PHY_933_DATA */
+ 0x00000000 /* DENALI_PHY_934_DATA */
+ 0x00000000 /* DENALI_PHY_935_DATA */
+ 0x02800280 /* DENALI_PHY_936_DATA */
+ 0x02800280 /* DENALI_PHY_937_DATA */
+ 0x02800280 /* DENALI_PHY_938_DATA */
+ 0x02800280 /* DENALI_PHY_939_DATA */
+ 0x00000280 /* DENALI_PHY_940_DATA */
+ 0x00000000 /* DENALI_PHY_941_DATA */
+ 0x00000000 /* DENALI_PHY_942_DATA */
+ 0x00000000 /* DENALI_PHY_943_DATA */
+ 0x00000000 /* DENALI_PHY_944_DATA */
+ 0x00000000 /* DENALI_PHY_945_DATA */
+ 0x00800080 /* DENALI_PHY_946_DATA */
+ 0x00800080 /* DENALI_PHY_947_DATA */
+ 0x00800080 /* DENALI_PHY_948_DATA */
+ 0x00800080 /* DENALI_PHY_949_DATA */
+ 0x00800080 /* DENALI_PHY_950_DATA */
+ 0x00800080 /* DENALI_PHY_951_DATA */
+ 0x00800080 /* DENALI_PHY_952_DATA */
+ 0x00800080 /* DENALI_PHY_953_DATA */
+ 0x00800080 /* DENALI_PHY_954_DATA */
+ 0x000100da /* DENALI_PHY_955_DATA */
+ 0x00000200 /* DENALI_PHY_956_DATA */
+ 0x00000000 /* DENALI_PHY_957_DATA */
+ 0x00000000 /* DENALI_PHY_958_DATA */
+ 0x00000002 /* DENALI_PHY_959_DATA */
+ 0x51313152 /* DENALI_PHY_960_DATA */
+ 0x80013130 /* DENALI_PHY_961_DATA */
+ 0x02000080 /* DENALI_PHY_962_DATA */
+ 0x00100001 /* DENALI_PHY_963_DATA */
+ 0x0c064208 /* DENALI_PHY_964_DATA */
+ 0x000f0c0f /* DENALI_PHY_965_DATA */
+ 0x01000140 /* DENALI_PHY_966_DATA */
+ 0x0000000c /* DENALI_PHY_967_DATA */
+ 0x00000000 /* DENALI_PHY_968_DATA */
+ 0x00000000 /* DENALI_PHY_969_DATA */
+ 0x00000000 /* DENALI_PHY_970_DATA */
+ 0x00000000 /* DENALI_PHY_971_DATA */
+ 0x00000000 /* DENALI_PHY_972_DATA */
+ 0x00000000 /* DENALI_PHY_973_DATA */
+ 0x00000000 /* DENALI_PHY_974_DATA */
+ 0x00000000 /* DENALI_PHY_975_DATA */
+ 0x00000000 /* DENALI_PHY_976_DATA */
+ 0x00000000 /* DENALI_PHY_977_DATA */
+ 0x00000000 /* DENALI_PHY_978_DATA */
+ 0x00000000 /* DENALI_PHY_979_DATA */
+ 0x00000000 /* DENALI_PHY_980_DATA */
+ 0x00000000 /* DENALI_PHY_981_DATA */
+ 0x00000000 /* DENALI_PHY_982_DATA */
+ 0x00000000 /* DENALI_PHY_983_DATA */
+ 0x00000000 /* DENALI_PHY_984_DATA */
+ 0x00000000 /* DENALI_PHY_985_DATA */
+ 0x00000000 /* DENALI_PHY_986_DATA */
+ 0x00000000 /* DENALI_PHY_987_DATA */
+ 0x00000000 /* DENALI_PHY_988_DATA */
+ 0x00000000 /* DENALI_PHY_989_DATA */
+ 0x00000000 /* DENALI_PHY_990_DATA */
+ 0x00000000 /* DENALI_PHY_991_DATA */
+ 0x00000000 /* DENALI_PHY_992_DATA */
+ 0x00000000 /* DENALI_PHY_993_DATA */
+ 0x00000000 /* DENALI_PHY_994_DATA */
+ 0x00000000 /* DENALI_PHY_995_DATA */
+ 0x00000000 /* DENALI_PHY_996_DATA */
+ 0x00000000 /* DENALI_PHY_997_DATA */
+ 0x00000000 /* DENALI_PHY_998_DATA */
+ 0x00000000 /* DENALI_PHY_999_DATA */
+ 0x00000000 /* DENALI_PHY_1000_DATA */
+ 0x00000000 /* DENALI_PHY_1001_DATA */
+ 0x00000000 /* DENALI_PHY_1002_DATA */
+ 0x00000000 /* DENALI_PHY_1003_DATA */
+ 0x00000000 /* DENALI_PHY_1004_DATA */
+ 0x00000000 /* DENALI_PHY_1005_DATA */
+ 0x00000000 /* DENALI_PHY_1006_DATA */
+ 0x00000000 /* DENALI_PHY_1007_DATA */
+ 0x00000000 /* DENALI_PHY_1008_DATA */
+ 0x00000000 /* DENALI_PHY_1009_DATA */
+ 0x00000000 /* DENALI_PHY_1010_DATA */
+ 0x00000000 /* DENALI_PHY_1011_DATA */
+ 0x00000000 /* DENALI_PHY_1012_DATA */
+ 0x00000000 /* DENALI_PHY_1013_DATA */
+ 0x00000000 /* DENALI_PHY_1014_DATA */
+ 0x00000000 /* DENALI_PHY_1015_DATA */
+ 0x00000000 /* DENALI_PHY_1016_DATA */
+ 0x00000000 /* DENALI_PHY_1017_DATA */
+ 0x00000000 /* DENALI_PHY_1018_DATA */
+ 0x00000000 /* DENALI_PHY_1019_DATA */
+ 0x00000000 /* DENALI_PHY_1020_DATA */
+ 0x00000000 /* DENALI_PHY_1021_DATA */
+ 0x00000000 /* DENALI_PHY_1022_DATA */
+ 0x00000000 /* DENALI_PHY_1023_DATA */
+ 0x36025174 /* DENALI_PHY_1024_DATA */
+ 0x0004c008 /* DENALI_PHY_1025_DATA */
+ 0x000000da /* DENALI_PHY_1026_DATA */
+ 0x00000000 /* DENALI_PHY_1027_DATA */
+ 0x00000000 /* DENALI_PHY_1028_DATA */
+ 0x00010000 /* DENALI_PHY_1029_DATA */
+ 0x01DDDD90 /* DENALI_PHY_1030_DATA */
+ 0x01DDDD90 /* DENALI_PHY_1031_DATA */
+ 0x01030000 /* DENALI_PHY_1032_DATA */
+ 0x01000000 /* DENALI_PHY_1033_DATA */
+ 0x00c00000 /* DENALI_PHY_1034_DATA */
+ 0x00000007 /* DENALI_PHY_1035_DATA */
+ 0x00000000 /* DENALI_PHY_1036_DATA */
+ 0x00000000 /* DENALI_PHY_1037_DATA */
+ 0x04000408 /* DENALI_PHY_1038_DATA */
+ 0x00000408 /* DENALI_PHY_1039_DATA */
+ 0x00e4e400 /* DENALI_PHY_1040_DATA */
+ 0x00000000 /* DENALI_PHY_1041_DATA */
+ 0x00000000 /* DENALI_PHY_1042_DATA */
+ 0x00000000 /* DENALI_PHY_1043_DATA */
+ 0x00000000 /* DENALI_PHY_1044_DATA */
+ 0x00000000 /* DENALI_PHY_1045_DATA */
+ 0x00000000 /* DENALI_PHY_1046_DATA */
+ 0x00000000 /* DENALI_PHY_1047_DATA */
+ 0x00000000 /* DENALI_PHY_1048_DATA */
+ 0x00000000 /* DENALI_PHY_1049_DATA */
+ 0x00000000 /* DENALI_PHY_1050_DATA */
+ 0x00000000 /* DENALI_PHY_1051_DATA */
+ 0x00000000 /* DENALI_PHY_1052_DATA */
+ 0x00000000 /* DENALI_PHY_1053_DATA */
+ 0x00000000 /* DENALI_PHY_1054_DATA */
+ 0x00000000 /* DENALI_PHY_1055_DATA */
+ 0x00000000 /* DENALI_PHY_1056_DATA */
+ 0x00200000 /* DENALI_PHY_1057_DATA */
+ 0x00000000 /* DENALI_PHY_1058_DATA */
+ 0x00000000 /* DENALI_PHY_1059_DATA */
+ 0x00000000 /* DENALI_PHY_1060_DATA */
+ 0x00000000 /* DENALI_PHY_1061_DATA */
+ 0x00000000 /* DENALI_PHY_1062_DATA */
+ 0x00000000 /* DENALI_PHY_1063_DATA */
+ 0x02800280 /* DENALI_PHY_1064_DATA */
+ 0x02800280 /* DENALI_PHY_1065_DATA */
+ 0x02800280 /* DENALI_PHY_1066_DATA */
+ 0x02800280 /* DENALI_PHY_1067_DATA */
+ 0x00000280 /* DENALI_PHY_1068_DATA */
+ 0x00000000 /* DENALI_PHY_1069_DATA */
+ 0x00000000 /* DENALI_PHY_1070_DATA */
+ 0x00000000 /* DENALI_PHY_1071_DATA */
+ 0x00000000 /* DENALI_PHY_1072_DATA */
+ 0x00000000 /* DENALI_PHY_1073_DATA */
+ 0x00800080 /* DENALI_PHY_1074_DATA */
+ 0x00800080 /* DENALI_PHY_1075_DATA */
+ 0x00800080 /* DENALI_PHY_1076_DATA */
+ 0x00800080 /* DENALI_PHY_1077_DATA */
+ 0x00800080 /* DENALI_PHY_1078_DATA */
+ 0x00800080 /* DENALI_PHY_1079_DATA */
+ 0x00800080 /* DENALI_PHY_1080_DATA */
+ 0x00800080 /* DENALI_PHY_1081_DATA */
+ 0x00800080 /* DENALI_PHY_1082_DATA */
+ 0x000100da /* DENALI_PHY_1083_DATA */
+ 0x00000200 /* DENALI_PHY_1084_DATA */
+ 0x00000000 /* DENALI_PHY_1085_DATA */
+ 0x00000000 /* DENALI_PHY_1086_DATA */
+ 0x00000002 /* DENALI_PHY_1087_DATA */
+ 0x51313152 /* DENALI_PHY_1088_DATA */
+ 0x80013130 /* DENALI_PHY_1089_DATA */
+ 0x02000080 /* DENALI_PHY_1090_DATA */
+ 0x00100001 /* DENALI_PHY_1091_DATA */
+ 0x0c064208 /* DENALI_PHY_1092_DATA */
+ 0x000f0c0f /* DENALI_PHY_1093_DATA */
+ 0x01000140 /* DENALI_PHY_1094_DATA */
+ 0x0000000c /* DENALI_PHY_1095_DATA */
+ 0x00000000 /* DENALI_PHY_1096_DATA */
+ 0x00000000 /* DENALI_PHY_1097_DATA */
+ 0x00000000 /* DENALI_PHY_1098_DATA */
+ 0x00000000 /* DENALI_PHY_1099_DATA */
+ 0x00000000 /* DENALI_PHY_1100_DATA */
+ 0x00000000 /* DENALI_PHY_1101_DATA */
+ 0x00000000 /* DENALI_PHY_1102_DATA */
+ 0x00000000 /* DENALI_PHY_1103_DATA */
+ 0x00000000 /* DENALI_PHY_1104_DATA */
+ 0x00000000 /* DENALI_PHY_1105_DATA */
+ 0x00000000 /* DENALI_PHY_1106_DATA */
+ 0x00000000 /* DENALI_PHY_1107_DATA */
+ 0x00000000 /* DENALI_PHY_1108_DATA */
+ 0x00000000 /* DENALI_PHY_1109_DATA */
+ 0x00000000 /* DENALI_PHY_1110_DATA */
+ 0x00000000 /* DENALI_PHY_1111_DATA */
+ 0x00000000 /* DENALI_PHY_1112_DATA */
+ 0x00000000 /* DENALI_PHY_1113_DATA */
+ 0x00000000 /* DENALI_PHY_1114_DATA */
+ 0x00000000 /* DENALI_PHY_1115_DATA */
+ 0x00000000 /* DENALI_PHY_1116_DATA */
+ 0x00000000 /* DENALI_PHY_1117_DATA */
+ 0x00000000 /* DENALI_PHY_1118_DATA */
+ 0x00000000 /* DENALI_PHY_1119_DATA */
+ 0x00000000 /* DENALI_PHY_1120_DATA */
+ 0x00000000 /* DENALI_PHY_1121_DATA */
+ 0x00000000 /* DENALI_PHY_1122_DATA */
+ 0x00000000 /* DENALI_PHY_1123_DATA */
+ 0x00000000 /* DENALI_PHY_1124_DATA */
+ 0x00000000 /* DENALI_PHY_1125_DATA */
+ 0x00000000 /* DENALI_PHY_1126_DATA */
+ 0x00000000 /* DENALI_PHY_1127_DATA */
+ 0x00000000 /* DENALI_PHY_1128_DATA */
+ 0x00000000 /* DENALI_PHY_1129_DATA */
+ 0x00000000 /* DENALI_PHY_1130_DATA */
+ 0x00000000 /* DENALI_PHY_1131_DATA */
+ 0x00000000 /* DENALI_PHY_1132_DATA */
+ 0x00000000 /* DENALI_PHY_1133_DATA */
+ 0x00000000 /* DENALI_PHY_1134_DATA */
+ 0x00000000 /* DENALI_PHY_1135_DATA */
+ 0x00000000 /* DENALI_PHY_1136_DATA */
+ 0x00000000 /* DENALI_PHY_1137_DATA */
+ 0x00000000 /* DENALI_PHY_1138_DATA */
+ 0x00000000 /* DENALI_PHY_1139_DATA */
+ 0x00000000 /* DENALI_PHY_1140_DATA */
+ 0x00000000 /* DENALI_PHY_1141_DATA */
+ 0x00000000 /* DENALI_PHY_1142_DATA */
+ 0x00000000 /* DENALI_PHY_1143_DATA */
+ 0x00000000 /* DENALI_PHY_1144_DATA */
+ 0x00000000 /* DENALI_PHY_1145_DATA */
+ 0x00000000 /* DENALI_PHY_1146_DATA */
+ 0x00000000 /* DENALI_PHY_1147_DATA */
+ 0x00000000 /* DENALI_PHY_1148_DATA */
+ 0x00000000 /* DENALI_PHY_1149_DATA */
+ 0x00000000 /* DENALI_PHY_1150_DATA */
+ 0x00000000 /* DENALI_PHY_1151_DATA */
+ 0x00000000 /* DENALI_PHY_1152_DATA */
+ 0x00000000 /* DENALI_PHY_1153_DATA */
+ 0x00050000 /* DENALI_PHY_1154_DATA */
+ 0x00000000 /* DENALI_PHY_1155_DATA */
+ 0x00000000 /* DENALI_PHY_1156_DATA */
+ 0x00000000 /* DENALI_PHY_1157_DATA */
+ 0x00000100 /* DENALI_PHY_1158_DATA */
+ 0x00000000 /* DENALI_PHY_1159_DATA */
+ 0x00000000 /* DENALI_PHY_1160_DATA */
+ 0x00506401 /* DENALI_PHY_1161_DATA */
+ 0x01221102 /* DENALI_PHY_1162_DATA */
+ 0x00000122 /* DENALI_PHY_1163_DATA */
+ 0x00000000 /* DENALI_PHY_1164_DATA */
+ 0x000B1F00 /* DENALI_PHY_1165_DATA */
+ 0x0B1F0B1F /* DENALI_PHY_1166_DATA */
+ 0x0B1F0B1B /* DENALI_PHY_1167_DATA */
+ 0x0B1F0B1F /* DENALI_PHY_1168_DATA */
+ 0x0B1F0B1F /* DENALI_PHY_1169_DATA */
+ 0x00000B00 /* DENALI_PHY_1170_DATA */
+ 0x42080010 /* DENALI_PHY_1171_DATA */
+ 0x01000100 /* DENALI_PHY_1172_DATA */
+ 0x01000100 /* DENALI_PHY_1173_DATA */
+ 0x01000100 /* DENALI_PHY_1174_DATA */
+ 0x01000100 /* DENALI_PHY_1175_DATA */
+ 0x00000000 /* DENALI_PHY_1176_DATA */
+ 0x00000000 /* DENALI_PHY_1177_DATA */
+ 0x00000000 /* DENALI_PHY_1178_DATA */
+ 0x00000000 /* DENALI_PHY_1179_DATA */
+ 0x00000000 /* DENALI_PHY_1180_DATA */
+ 0x00000803 /* DENALI_PHY_1181_DATA */
+ 0x223FFF00 /* DENALI_PHY_1182_DATA */
+ 0x000008FF /* DENALI_PHY_1183_DATA */
+ 0x0000057F /* DENALI_PHY_1184_DATA */
+ 0x0000057F /* DENALI_PHY_1185_DATA */
+ 0x00037FFF /* DENALI_PHY_1186_DATA */
+ 0x00037FFF /* DENALI_PHY_1187_DATA */
+ 0x00004410 /* DENALI_PHY_1188_DATA */
+ 0x00004410 /* DENALI_PHY_1189_DATA */
+ 0x00004410 /* DENALI_PHY_1190_DATA */
+ 0x00004410 /* DENALI_PHY_1191_DATA */
+ 0x00004410 /* DENALI_PHY_1192_DATA */
+ 0x00037FFF /* DENALI_PHY_1193_DATA */
+ 0x00037FFF /* DENALI_PHY_1194_DATA */
+ 0x00000000 /* DENALI_PHY_1195_DATA */
+ 0x00000000 /* DENALI_PHY_1196_DATA */
+ 0x00000000 /* DENALI_PHY_1197_DATA */
+ 0x04000000 /* DENALI_PHY_1198_DATA */
+ 0x00000000 /* DENALI_PHY_1199_DATA */
+ 0x00000000 /* DENALI_PHY_1200_DATA */
+ 0x00000108 /* DENALI_PHY_1201_DATA */
+ 0x00000000 /* DENALI_PHY_1202_DATA */
+ 0x00000000 /* DENALI_PHY_1203_DATA */
+ 0x00000000 /* DENALI_PHY_1204_DATA */
+ 0x00000001 /* DENALI_PHY_1205_DATA */
+ 0x00000000 /* DENALI_PHY_1206_DATA */
+ 0x00000000 /* DENALI_PHY_1207_DATA */
+ 0x00000000 /* DENALI_PHY_1208_DATA */
+ 0x00000000 /* DENALI_PHY_1209_DATA */
+ 0x00000000 /* DENALI_PHY_1210_DATA */
+ 0x00000000 /* DENALI_PHY_1211_DATA */
+ 0x00020100 /* DENALI_PHY_1212_DATA */
+ 0x00000000 /* DENALI_PHY_1213_DATA */
+ 0x00000000 /* DENALI_PHY_1214_DATA */
+ >;
+};
--
2.17.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v8 08/21] riscv: sifive: dts: fu540: add U-Boot dmc node
2020-05-09 14:30 [PATCH v8 00/21] RISC-V SiFive FU540 support SPL Pragnesh Patel
` (6 preceding siblings ...)
2020-05-09 14:30 ` [PATCH v8 07/21] sifive: dts: fu540: Add DDR controller and phy register settings Pragnesh Patel
@ 2020-05-09 14:30 ` Pragnesh Patel
2020-05-09 14:30 ` [PATCH v8 09/21] clk: sifive: fu540-prci: Add clock enable and disable ops Pragnesh Patel
` (12 subsequent siblings)
20 siblings, 0 replies; 31+ messages in thread
From: Pragnesh Patel @ 2020-05-09 14:30 UTC (permalink / raw)
To: u-boot
Add dmc node to enable sdram driver. dmc is used to
initialize the memory controller.
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
---
arch/riscv/dts/fu540-c000-u-boot.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi b/arch/riscv/dts/fu540-c000-u-boot.dtsi
index fbfe296a03..fc91a7c987 100644
--- a/arch/riscv/dts/fu540-c000-u-boot.dtsi
+++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi
@@ -59,6 +59,15 @@
reg = <0x0 0x2000000 0x0 0xc0000>;
u-boot,dm-spl;
};
+ dmc: dmc at 100b0000 {
+ compatible = "sifive,fu540-c000-ddr";
+ reg = <0x0 0x100b0000 0x0 0x0800
+ 0x0 0x100b2000 0x0 0x2000
+ 0x0 0x100b8000 0x0 0x0fff>;
+ clocks = <&prci PRCI_CLK_DDRPLL>;
+ clock-frequency = <933333324>;
+ u-boot,dm-spl;
+ };
};
};
--
2.17.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v8 09/21] clk: sifive: fu540-prci: Add clock enable and disable ops
2020-05-09 14:30 [PATCH v8 00/21] RISC-V SiFive FU540 support SPL Pragnesh Patel
` (7 preceding siblings ...)
2020-05-09 14:30 ` [PATCH v8 08/21] riscv: sifive: dts: fu540: add U-Boot dmc node Pragnesh Patel
@ 2020-05-09 14:30 ` Pragnesh Patel
2020-05-09 14:30 ` [PATCH v8 10/21] clk: sifive: fu540-prci: Add ddr clock initialization in SPL Pragnesh Patel
` (11 subsequent siblings)
20 siblings, 0 replies; 31+ messages in thread
From: Pragnesh Patel @ 2020-05-09 14:30 UTC (permalink / raw)
To: u-boot
Added clock enable and disable functions in prci ops
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
---
drivers/clk/sifive/fu540-prci.c | 108 ++++++++++++++++++++++++++++----
1 file changed, 96 insertions(+), 12 deletions(-)
diff --git a/drivers/clk/sifive/fu540-prci.c b/drivers/clk/sifive/fu540-prci.c
index 8847178001..bf06c3a3bb 100644
--- a/drivers/clk/sifive/fu540-prci.c
+++ b/drivers/clk/sifive/fu540-prci.c
@@ -68,6 +68,11 @@
#define PRCI_COREPLLCFG0_LOCK_SHIFT 31
#define PRCI_COREPLLCFG0_LOCK_MASK (0x1 << PRCI_COREPLLCFG0_LOCK_SHIFT)
+/* COREPLLCFG1 */
+#define PRCI_COREPLLCFG1_OFFSET 0x8
+#define PRCI_COREPLLCFG1_CKE_SHIFT 31
+#define PRCI_COREPLLCFG1_CKE_MASK (0x1 << PRCI_COREPLLCFG1_CKE_SHIFT)
+
/* DDRPLLCFG0 */
#define PRCI_DDRPLLCFG0_OFFSET 0xc
#define PRCI_DDRPLLCFG0_DIVR_SHIFT 0
@@ -87,7 +92,7 @@
/* DDRPLLCFG1 */
#define PRCI_DDRPLLCFG1_OFFSET 0x10
-#define PRCI_DDRPLLCFG1_CKE_SHIFT 24
+#define PRCI_DDRPLLCFG1_CKE_SHIFT 31
#define PRCI_DDRPLLCFG1_CKE_MASK (0x1 << PRCI_DDRPLLCFG1_CKE_SHIFT)
/* GEMGXLPLLCFG0 */
@@ -114,7 +119,7 @@
/* GEMGXLPLLCFG1 */
#define PRCI_GEMGXLPLLCFG1_OFFSET 0x20
-#define PRCI_GEMGXLPLLCFG1_CKE_SHIFT 24
+#define PRCI_GEMGXLPLLCFG1_CKE_SHIFT 31
#define PRCI_GEMGXLPLLCFG1_CKE_MASK (0x1 << PRCI_GEMGXLPLLCFG1_CKE_SHIFT)
/* CORECLKSEL */
@@ -142,7 +147,7 @@
(0x1 << PRCI_DEVICESRESETREG_GEMGXL_RST_N_SHIFT)
/* CLKMUXSTATUSREG */
-#define PRCI_CLKMUXSTATUSREG_OFFSET 0x2c
+#define PRCI_CLKMUXSTATUSREG_OFFSET 0x2c
#define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT 1
#define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_MASK \
(0x1 << PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT)
@@ -170,6 +175,7 @@ struct __prci_data {
* @enable_bypass: fn ptr to code to bypass the WRPLL (if applicable; else NULL)
* @disable_bypass: fn ptr to code to not bypass the WRPLL (or NULL)
* @cfg0_offs: WRPLL CFG0 register offset (in bytes) from the PRCI base address
+ * @cfg1_offs: WRPLL CFG1 register offset (in bytes) from the PRCI base address
*
* @enable_bypass and @disable_bypass are used for WRPLL instances
* that contain a separate external glitchless clock mux downstream
@@ -180,6 +186,7 @@ struct __prci_wrpll_data {
void (*enable_bypass)(struct __prci_data *pd);
void (*disable_bypass)(struct __prci_data *pd);
u8 cfg0_offs;
+ u8 cfg1_offs;
};
struct __prci_clock;
@@ -194,6 +201,7 @@ struct __prci_clock_ops {
unsigned long *parent_rate);
unsigned long (*recalc_rate)(struct __prci_clock *pc,
unsigned long parent_rate);
+ int (*enable_clk)(struct __prci_clock *pc, bool enable);
};
/**
@@ -316,7 +324,7 @@ static u32 __prci_wrpll_pack(const struct wrpll_cfg *c)
}
/**
- * __prci_wrpll_read_cfg() - read the WRPLL configuration from the PRCI
+ * __prci_wrpll_read_cfg0() - read the WRPLL configuration from the PRCI
* @pd: PRCI context
* @pwd: PRCI WRPLL metadata
*
@@ -327,14 +335,14 @@ static u32 __prci_wrpll_pack(const struct wrpll_cfg *c)
* Context: Any context. Caller must prevent the records pointed to by
* @pd and @pwd from changing during execution.
*/
-static void __prci_wrpll_read_cfg(struct __prci_data *pd,
- struct __prci_wrpll_data *pwd)
+static void __prci_wrpll_read_cfg0(struct __prci_data *pd,
+ struct __prci_wrpll_data *pwd)
{
__prci_wrpll_unpack(&pwd->c, __prci_readl(pd, pwd->cfg0_offs));
}
/**
- * __prci_wrpll_write_cfg() - write WRPLL configuration into the PRCI
+ * __prci_wrpll_write_cfg0() - write WRPLL configuration into the PRCI
* @pd: PRCI context
* @pwd: PRCI WRPLL metadata
* @c: WRPLL configuration record to write
@@ -347,15 +355,29 @@ static void __prci_wrpll_read_cfg(struct __prci_data *pd,
* Context: Any context. Caller must prevent the records pointed to by
* @pd and @pwd from changing during execution.
*/
-static void __prci_wrpll_write_cfg(struct __prci_data *pd,
- struct __prci_wrpll_data *pwd,
- struct wrpll_cfg *c)
+static void __prci_wrpll_write_cfg0(struct __prci_data *pd,
+ struct __prci_wrpll_data *pwd,
+ struct wrpll_cfg *c)
{
__prci_writel(__prci_wrpll_pack(c), pwd->cfg0_offs, pd);
memcpy(&pwd->c, c, sizeof(*c));
}
+/**
+ * __prci_wrpll_write_cfg1() - write Clock enable/disable configuration
+ * into the PRCI
+ * @pd: PRCI context
+ * @pwd: PRCI WRPLL metadata
+ * @enable: Clock enable or disable value
+ */
+static void __prci_wrpll_write_cfg1(struct __prci_data *pd,
+ struct __prci_wrpll_data *pwd,
+ u32 enable)
+{
+ __prci_writel(enable, pwd->cfg1_offs, pd);
+}
+
/* Core clock mux control */
/**
@@ -437,7 +459,7 @@ static int sifive_fu540_prci_wrpll_set_rate(struct __prci_clock *pc,
if (pwd->enable_bypass)
pwd->enable_bypass(pd);
- __prci_wrpll_write_cfg(pd, pwd, &pwd->c);
+ __prci_wrpll_write_cfg0(pd, pwd, &pwd->c);
udelay(wrpll_calc_max_lock_us(&pwd->c));
@@ -447,14 +469,35 @@ static int sifive_fu540_prci_wrpll_set_rate(struct __prci_clock *pc,
return 0;
}
+static int sifive_fu540_prci_clock_enable(struct __prci_clock *pc, bool enable)
+{
+ struct __prci_wrpll_data *pwd = pc->pwd;
+ struct __prci_data *pd = pc->pd;
+
+ if (enable) {
+ __prci_wrpll_write_cfg1(pd, pwd, PRCI_COREPLLCFG1_CKE_MASK);
+ } else {
+ u32 r;
+
+ r = __prci_readl(pd, pwd->cfg1_offs);
+ r &= ~PRCI_COREPLLCFG1_CKE_MASK;
+
+ __prci_wrpll_write_cfg1(pd, pwd, r);
+ }
+
+ return 0;
+}
+
static const struct __prci_clock_ops sifive_fu540_prci_wrpll_clk_ops = {
.set_rate = sifive_fu540_prci_wrpll_set_rate,
.round_rate = sifive_fu540_prci_wrpll_round_rate,
.recalc_rate = sifive_fu540_prci_wrpll_recalc_rate,
+ .enable_clk = sifive_fu540_prci_clock_enable,
};
static const struct __prci_clock_ops sifive_fu540_prci_wrpll_ro_clk_ops = {
.recalc_rate = sifive_fu540_prci_wrpll_recalc_rate,
+ .enable_clk = sifive_fu540_prci_clock_enable,
};
/* TLCLKSEL clock integration */
@@ -484,16 +527,19 @@ static const struct __prci_clock_ops sifive_fu540_prci_tlclksel_clk_ops = {
static struct __prci_wrpll_data __prci_corepll_data = {
.cfg0_offs = PRCI_COREPLLCFG0_OFFSET,
+ .cfg1_offs = PRCI_COREPLLCFG1_OFFSET,
.enable_bypass = __prci_coreclksel_use_hfclk,
.disable_bypass = __prci_coreclksel_use_corepll,
};
static struct __prci_wrpll_data __prci_ddrpll_data = {
.cfg0_offs = PRCI_DDRPLLCFG0_OFFSET,
+ .cfg1_offs = PRCI_DDRPLLCFG1_OFFSET,
};
static struct __prci_wrpll_data __prci_gemgxlpll_data = {
.cfg0_offs = PRCI_GEMGXLPLLCFG0_OFFSET,
+ .cfg1_offs = PRCI_GEMGXLPLLCFG1_OFFSET,
};
/*
@@ -580,6 +626,42 @@ static ulong sifive_fu540_prci_set_rate(struct clk *clk, ulong rate)
return rate;
}
+static int sifive_fu540_prci_enable(struct clk *clk)
+{
+ struct __prci_clock *pc;
+ int ret = 0;
+
+ if (ARRAY_SIZE(__prci_init_clocks) <= clk->id)
+ return -ENXIO;
+
+ pc = &__prci_init_clocks[clk->id];
+ if (!pc->pd)
+ return -ENXIO;
+
+ if (pc->ops->enable_clk)
+ ret = pc->ops->enable_clk(pc, 1);
+
+ return ret;
+}
+
+static int sifive_fu540_prci_disable(struct clk *clk)
+{
+ struct __prci_clock *pc;
+ int ret = 0;
+
+ if (ARRAY_SIZE(__prci_init_clocks) <= clk->id)
+ return -ENXIO;
+
+ pc = &__prci_init_clocks[clk->id];
+ if (!pc->pd)
+ return -ENXIO;
+
+ if (pc->ops->enable_clk)
+ ret = pc->ops->enable_clk(pc, 0);
+
+ return ret;
+}
+
static int sifive_fu540_prci_probe(struct udevice *dev)
{
int i, err;
@@ -602,7 +684,7 @@ static int sifive_fu540_prci_probe(struct udevice *dev)
pc = &__prci_init_clocks[i];
pc->pd = pd;
if (pc->pwd)
- __prci_wrpll_read_cfg(pd, pc->pwd);
+ __prci_wrpll_read_cfg0(pd, pc->pwd);
}
return 0;
@@ -611,6 +693,8 @@ static int sifive_fu540_prci_probe(struct udevice *dev)
static struct clk_ops sifive_fu540_prci_ops = {
.set_rate = sifive_fu540_prci_set_rate,
.get_rate = sifive_fu540_prci_get_rate,
+ .enable = sifive_fu540_prci_enable,
+ .disable = sifive_fu540_prci_disable,
};
static const struct udevice_id sifive_fu540_prci_ids[] = {
--
2.17.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v8 10/21] clk: sifive: fu540-prci: Add ddr clock initialization in SPL
2020-05-09 14:30 [PATCH v8 00/21] RISC-V SiFive FU540 support SPL Pragnesh Patel
` (8 preceding siblings ...)
2020-05-09 14:30 ` [PATCH v8 09/21] clk: sifive: fu540-prci: Add clock enable and disable ops Pragnesh Patel
@ 2020-05-09 14:30 ` Pragnesh Patel
2020-05-09 14:30 ` [PATCH v8 11/21] clk: sifive: fu540-prci: Add ehternet " Pragnesh Patel
` (10 subsequent siblings)
20 siblings, 0 replies; 31+ messages in thread
From: Pragnesh Patel @ 2020-05-09 14:30 UTC (permalink / raw)
To: u-boot
Add ddr clock release reset for SPL
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
---
drivers/clk/sifive/fu540-prci.c | 59 +++++++++++++++++++++++++++++----
1 file changed, 53 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/sifive/fu540-prci.c b/drivers/clk/sifive/fu540-prci.c
index bf06c3a3bb..033562274e 100644
--- a/drivers/clk/sifive/fu540-prci.c
+++ b/drivers/clk/sifive/fu540-prci.c
@@ -152,6 +152,12 @@
#define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_MASK \
(0x1 << PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT)
+/* PROCMONCFG */
+#define PRCI_PROCMONCFG_OFFSET 0xF0
+#define PRCI_PROCMONCFG_CORE_CLOCK_SHIFT 24
+#define PRCI_PROCMONCFG_CORE_CLOCK_MASK \
+ (0x1 << PRCI_PROCMONCFG_CORE_CLOCK_SHIFT)
+
/*
* Private structures
*/
@@ -176,6 +182,7 @@ struct __prci_data {
* @disable_bypass: fn ptr to code to not bypass the WRPLL (or NULL)
* @cfg0_offs: WRPLL CFG0 register offset (in bytes) from the PRCI base address
* @cfg1_offs: WRPLL CFG1 register offset (in bytes) from the PRCI base address
+ * @release_reset: fn ptr to code to release clock reset
*
* @enable_bypass and @disable_bypass are used for WRPLL instances
* that contain a separate external glitchless clock mux downstream
@@ -187,6 +194,9 @@ struct __prci_wrpll_data {
void (*disable_bypass)(struct __prci_data *pd);
u8 cfg0_offs;
u8 cfg1_offs;
+#ifdef CONFIG_SPL_BUILD
+ void (*release_reset)(struct __prci_data *pd);
+#endif
};
struct __prci_clock;
@@ -476,6 +486,11 @@ static int sifive_fu540_prci_clock_enable(struct __prci_clock *pc, bool enable)
if (enable) {
__prci_wrpll_write_cfg1(pd, pwd, PRCI_COREPLLCFG1_CKE_MASK);
+
+#ifdef CONFIG_SPL_BUILD
+ if (pwd->release_reset)
+ pwd->release_reset(pd);
+#endif
} else {
u32 r;
@@ -495,11 +510,6 @@ static const struct __prci_clock_ops sifive_fu540_prci_wrpll_clk_ops = {
.enable_clk = sifive_fu540_prci_clock_enable,
};
-static const struct __prci_clock_ops sifive_fu540_prci_wrpll_ro_clk_ops = {
- .recalc_rate = sifive_fu540_prci_wrpll_recalc_rate,
- .enable_clk = sifive_fu540_prci_clock_enable,
-};
-
/* TLCLKSEL clock integration */
static unsigned long sifive_fu540_prci_tlclksel_recalc_rate(
@@ -521,6 +531,40 @@ static const struct __prci_clock_ops sifive_fu540_prci_tlclksel_clk_ops = {
.recalc_rate = sifive_fu540_prci_tlclksel_recalc_rate,
};
+#ifdef CONFIG_SPL_BUILD
+/**
+ * __prci_ddr_release_reset() - Release DDR reset
+ * @pd: struct __prci_data * for the PRCI containing the DDRCLK mux reg
+ *
+ */
+static void __prci_ddr_release_reset(struct __prci_data *pd)
+{
+ u32 v;
+
+ v = __prci_readl(pd, PRCI_DEVICESRESETREG_OFFSET);
+ v |= PRCI_DEVICESRESETREG_DDR_CTRL_RST_N_MASK;
+ __prci_writel(v, PRCI_DEVICESRESETREG_OFFSET, pd);
+
+ /* HACK to get the '1 full controller clock cycle'. */
+ asm volatile ("fence");
+ v = __prci_readl(pd, PRCI_DEVICESRESETREG_OFFSET);
+ v |= (PRCI_DEVICESRESETREG_DDR_AXI_RST_N_MASK |
+ PRCI_DEVICESRESETREG_DDR_AHB_RST_N_MASK |
+ PRCI_DEVICESRESETREG_DDR_PHY_RST_N_MASK);
+ __prci_writel(v, PRCI_DEVICESRESETREG_OFFSET, pd);
+
+ /* HACK to get the '1 full controller clock cycle'. */
+ asm volatile ("fence");
+
+ /*
+ * These take like 16 cycles to actually propagate. We can't go sending
+ * stuff before they come out of reset. So wait.
+ */
+ for (int i = 0; i < 256; i++)
+ asm volatile ("nop");
+}
+#endif
+
/*
* PRCI integration data for each WRPLL instance
*/
@@ -535,6 +579,9 @@ static struct __prci_wrpll_data __prci_corepll_data = {
static struct __prci_wrpll_data __prci_ddrpll_data = {
.cfg0_offs = PRCI_DDRPLLCFG0_OFFSET,
.cfg1_offs = PRCI_DDRPLLCFG1_OFFSET,
+#ifdef CONFIG_SPL_BUILD
+ .release_reset = __prci_ddr_release_reset,
+#endif
};
static struct __prci_wrpll_data __prci_gemgxlpll_data = {
@@ -556,7 +603,7 @@ static struct __prci_clock __prci_init_clocks[] = {
[PRCI_CLK_DDRPLL] = {
.name = "ddrpll",
.parent_name = "hfclk",
- .ops = &sifive_fu540_prci_wrpll_ro_clk_ops,
+ .ops = &sifive_fu540_prci_wrpll_clk_ops,
.pwd = &__prci_ddrpll_data,
},
[PRCI_CLK_GEMGXLPLL] = {
--
2.17.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v8 11/21] clk: sifive: fu540-prci: Add ehternet clock initialization in SPL
2020-05-09 14:30 [PATCH v8 00/21] RISC-V SiFive FU540 support SPL Pragnesh Patel
` (9 preceding siblings ...)
2020-05-09 14:30 ` [PATCH v8 10/21] clk: sifive: fu540-prci: Add ddr clock initialization in SPL Pragnesh Patel
@ 2020-05-09 14:30 ` Pragnesh Patel
2020-05-09 14:30 ` [PATCH v8 12/21] riscv: dts: sifive: Sync hifive-unleashed-a00 dts from linux Pragnesh Patel
` (9 subsequent siblings)
20 siblings, 0 replies; 31+ messages in thread
From: Pragnesh Patel @ 2020-05-09 14:30 UTC (permalink / raw)
To: u-boot
Add ehternet clock initialization for SPL
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
---
drivers/clk/sifive/fu540-prci.c | 29 +++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/drivers/clk/sifive/fu540-prci.c b/drivers/clk/sifive/fu540-prci.c
index 033562274e..e7ceda0dcf 100644
--- a/drivers/clk/sifive/fu540-prci.c
+++ b/drivers/clk/sifive/fu540-prci.c
@@ -41,6 +41,8 @@
#include <linux/clk/analogbits-wrpll-cln28hpc.h>
#include <dt-bindings/clock/sifive-fu540-prci.h>
+#define MHz 1000000
+
/*
* EXPECTED_CLK_PARENT_COUNT: how many parent clocks this driver expects:
* hfclk and rtcclk
@@ -709,6 +711,29 @@ static int sifive_fu540_prci_disable(struct clk *clk)
return ret;
}
+#ifdef CONFIG_SPL_BUILD
+static void ethernet_init(struct udevice *dev)
+{
+ u32 v;
+ struct clk clock;
+ struct __prci_data *pd = dev_get_priv(dev);
+
+ /* GEMGXL init */
+ clock.id = PRCI_CLK_GEMGXLPLL;
+ sifive_fu540_prci_set_rate(&clock, 125UL * MHz);
+ sifive_fu540_prci_clock_enable(&__prci_init_clocks[clock.id], 1);
+
+ /* Release GEMGXL reset */
+ v = __prci_readl(pd, PRCI_DEVICESRESETREG_OFFSET);
+ v |= PRCI_DEVICESRESETREG_GEMGXL_RST_N_MASK;
+ __prci_writel(v, PRCI_DEVICESRESETREG_OFFSET, pd);
+
+ /* Procmon => core clock */
+ __prci_writel(PRCI_PROCMONCFG_CORE_CLOCK_MASK, PRCI_PROCMONCFG_OFFSET,
+ pd);
+}
+#endif
+
static int sifive_fu540_prci_probe(struct udevice *dev)
{
int i, err;
@@ -734,6 +759,10 @@ static int sifive_fu540_prci_probe(struct udevice *dev)
__prci_wrpll_read_cfg0(pd, pc->pwd);
}
+#ifdef CONFIG_SPL_BUILD
+ ethernet_init(dev);
+#endif
+
return 0;
}
--
2.17.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v8 12/21] riscv: dts: sifive: Sync hifive-unleashed-a00 dts from linux
2020-05-09 14:30 [PATCH v8 00/21] RISC-V SiFive FU540 support SPL Pragnesh Patel
` (10 preceding siblings ...)
2020-05-09 14:30 ` [PATCH v8 11/21] clk: sifive: fu540-prci: Add ehternet " Pragnesh Patel
@ 2020-05-09 14:30 ` Pragnesh Patel
2020-05-09 14:30 ` [PATCH v8 13/21] riscv: cpu: fu540: Add support for cpu fu540 Pragnesh Patel
` (8 subsequent siblings)
20 siblings, 0 replies; 31+ messages in thread
From: Pragnesh Patel @ 2020-05-09 14:30 UTC (permalink / raw)
To: u-boot
This sync has changes required to use GPIO in U-Boot and
U-Boot SPL.
Sync dts from linux v5.7-rc2 commit:
"riscv: dts: Add GPIO reboot method to HiFive Unleashed DTS file"
(sha1: 0a91330b2af9f71ceeeed483f92774182b58f6d9)
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
arch/riscv/dts/fu540-c000.dtsi | 37 ++++++++++++++++++++++++-
arch/riscv/dts/hifive-unleashed-a00.dts | 9 ++++++
2 files changed, 45 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/dts/fu540-c000.dtsi b/arch/riscv/dts/fu540-c000.dtsi
index afa43c7ea3..7db8610534 100644
--- a/arch/riscv/dts/fu540-c000.dtsi
+++ b/arch/riscv/dts/fu540-c000.dtsi
@@ -54,6 +54,7 @@
reg = <1>;
riscv,isa = "rv64imafdc";
tlb-split;
+ next-level-cache = <&l2cache>;
cpu1_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
@@ -77,6 +78,7 @@
reg = <2>;
riscv,isa = "rv64imafdc";
tlb-split;
+ next-level-cache = <&l2cache>;
cpu2_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
@@ -100,6 +102,7 @@
reg = <3>;
riscv,isa = "rv64imafdc";
tlb-split;
+ next-level-cache = <&l2cache>;
cpu3_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
@@ -123,6 +126,7 @@
reg = <4>;
riscv,isa = "rv64imafdc";
tlb-split;
+ next-level-cache = <&l2cache>;
cpu4_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
@@ -162,6 +166,13 @@
clocks = <&prci PRCI_CLK_TLCLK>;
status = "disabled";
};
+ dma: dma at 3000000 {
+ compatible = "sifive,fu540-c000-pdma";
+ reg = <0x0 0x3000000 0x0 0x8000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <23 24 25 26 27 28 29 30>;
+ #dma-cells = <1>;
+ };
uart1: serial at 10011000 {
compatible = "sifive,fu540-c000-uart", "sifive,uart0";
reg = <0x0 0x10011000 0x0 0x1000>;
@@ -246,6 +257,30 @@
#pwm-cells = <3>;
status = "disabled";
};
-
+ l2cache: cache-controller at 2010000 {
+ compatible = "sifive,fu540-c000-ccache", "cache";
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-sets = <1024>;
+ cache-size = <2097152>;
+ cache-unified;
+ interrupt-parent = <&plic0>;
+ interrupts = <1 2 3>;
+ reg = <0x0 0x2010000 0x0 0x1000>;
+ };
+ gpio: gpio at 10060000 {
+ compatible = "sifive,fu540-c000-gpio", "sifive,gpio0";
+ interrupt-parent = <&plic0>;
+ interrupts = <7>, <8>, <9>, <10>, <11>, <12>, <13>,
+ <14>, <15>, <16>, <17>, <18>, <19>, <20>,
+ <21>, <22>;
+ reg = <0x0 0x10060000 0x0 0x1000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&prci PRCI_CLK_TLCLK>;
+ status = "disabled";
+ };
};
};
diff --git a/arch/riscv/dts/hifive-unleashed-a00.dts b/arch/riscv/dts/hifive-unleashed-a00.dts
index 88cfcb96bf..4a2729f5ca 100644
--- a/arch/riscv/dts/hifive-unleashed-a00.dts
+++ b/arch/riscv/dts/hifive-unleashed-a00.dts
@@ -2,6 +2,7 @@
/* Copyright (c) 2018-2019 SiFive, Inc */
#include "fu540-c000.dtsi"
+#include <dt-bindings/gpio/gpio.h>
/* Clock frequency (in Hz) of the PCB crystal for rtcclk */
#define RTCCLK_FREQ 1000000
@@ -41,6 +42,10 @@
clock-frequency = <RTCCLK_FREQ>;
clock-output-names = "rtcclk";
};
+ gpio-restart {
+ compatible = "gpio-restart";
+ gpios = <&gpio 10 GPIO_ACTIVE_LOW>;
+ };
};
&uart0 {
@@ -94,3 +99,7 @@
&pwm1 {
status = "okay";
};
+
+&gpio {
+ status = "okay";
+};
--
2.17.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v8 13/21] riscv: cpu: fu540: Add support for cpu fu540
2020-05-09 14:30 [PATCH v8 00/21] RISC-V SiFive FU540 support SPL Pragnesh Patel
` (11 preceding siblings ...)
2020-05-09 14:30 ` [PATCH v8 12/21] riscv: dts: sifive: Sync hifive-unleashed-a00 dts from linux Pragnesh Patel
@ 2020-05-09 14:30 ` Pragnesh Patel
2020-05-09 14:30 ` [PATCH v8 14/21] riscv: Add place-holder for driver compilation Pragnesh Patel
` (7 subsequent siblings)
20 siblings, 0 replies; 31+ messages in thread
From: Pragnesh Patel @ 2020-05-09 14:30 UTC (permalink / raw)
To: u-boot
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
arch/riscv/Kconfig | 1 +
arch/riscv/cpu/fu540/Kconfig | 15 ++++++++++++++
arch/riscv/cpu/fu540/Makefile | 7 +++++++
arch/riscv/cpu/fu540/cpu.c | 22 ++++++++++++++++++++
arch/riscv/cpu/fu540/dram.c | 38 +++++++++++++++++++++++++++++++++++
5 files changed, 83 insertions(+)
create mode 100644 arch/riscv/cpu/fu540/Kconfig
create mode 100644 arch/riscv/cpu/fu540/Makefile
create mode 100644 arch/riscv/cpu/fu540/cpu.c
create mode 100644 arch/riscv/cpu/fu540/dram.c
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index fb5fe5afff..3044609971 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -57,6 +57,7 @@ source "board/sifive/fu540/Kconfig"
# platform-specific options below
source "arch/riscv/cpu/ax25/Kconfig"
source "arch/riscv/cpu/generic/Kconfig"
+source "arch/riscv/cpu/fu540/Kconfig"
# architecture-specific options below
diff --git a/arch/riscv/cpu/fu540/Kconfig b/arch/riscv/cpu/fu540/Kconfig
new file mode 100644
index 0000000000..e9302e87c0
--- /dev/null
+++ b/arch/riscv/cpu/fu540/Kconfig
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+
+config SIFIVE_FU540
+ bool
+ select ARCH_EARLY_INIT_R
+ imply CPU
+ imply CPU_RISCV
+ imply RISCV_TIMER
+ imply SIFIVE_CLINT if (RISCV_MMODE || SPL_RISCV_MMODE)
+ imply CMD_CPU
+ imply SPL_CPU_SUPPORT
+ imply SPL_OPENSBI
+ imply SPL_LOAD_FIT
diff --git a/arch/riscv/cpu/fu540/Makefile b/arch/riscv/cpu/fu540/Makefile
new file mode 100644
index 0000000000..44700d998c
--- /dev/null
+++ b/arch/riscv/cpu/fu540/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2020 SiFive, Inc
+# Pragnesh Patel <pragnesh.patel@sifive.com>
+
+obj-y += dram.o
+obj-y += cpu.o
diff --git a/arch/riscv/cpu/fu540/cpu.c b/arch/riscv/cpu/fu540/cpu.c
new file mode 100644
index 0000000000..13a69ef0cc
--- /dev/null
+++ b/arch/riscv/cpu/fu540/cpu.c
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <common.h>
+#include <irq_func.h>
+
+/*
+ * cleanup_before_linux() is called just before we call linux
+ * it prepares the processor for linux
+ *
+ * we disable interrupt and caches.
+ */
+int cleanup_before_linux(void)
+{
+ disable_interrupts();
+
+ cache_flush();
+
+ return 0;
+}
diff --git a/arch/riscv/cpu/fu540/dram.c b/arch/riscv/cpu/fu540/dram.c
new file mode 100644
index 0000000000..1dc77efeca
--- /dev/null
+++ b/arch/riscv/cpu/fu540/dram.c
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <init.h>
+#include <linux/sizes.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+ return fdtdec_setup_memory_banksize();
+}
+
+ulong board_get_usable_ram_top(ulong total_size)
+{
+#ifdef CONFIG_64BIT
+ /*
+ * Ensure that we run from first 4GB so that all
+ * addresses used by U-Boot are 32bit addresses.
+ *
+ * This in-turn ensures that 32bit DMA capable
+ * devices work fine because DMA mapping APIs will
+ * provide 32bit DMA addresses only.
+ */
+ if (gd->ram_top > SZ_4G)
+ return SZ_4G;
+#endif
+ return gd->ram_top;
+}
--
2.17.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v8 14/21] riscv: Add place-holder for driver compilation
2020-05-09 14:30 [PATCH v8 00/21] RISC-V SiFive FU540 support SPL Pragnesh Patel
` (12 preceding siblings ...)
2020-05-09 14:30 ` [PATCH v8 13/21] riscv: cpu: fu540: Add support for cpu fu540 Pragnesh Patel
@ 2020-05-09 14:30 ` Pragnesh Patel
2020-05-09 14:30 ` [PATCH v8 15/21] riscv: sifive: fu540: add SPL configuration Pragnesh Patel
` (6 subsequent siblings)
20 siblings, 0 replies; 31+ messages in thread
From: Pragnesh Patel @ 2020-05-09 14:30 UTC (permalink / raw)
To: u-boot
Add place-holder for RISC-V fu540 CPU
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
---
arch/riscv/include/asm/arch-fu540/clk.h | 14 +++++++++
arch/riscv/include/asm/arch-fu540/gpio.h | 38 ++++++++++++++++++++++++
2 files changed, 52 insertions(+)
create mode 100644 arch/riscv/include/asm/arch-fu540/clk.h
create mode 100644 arch/riscv/include/asm/arch-fu540/gpio.h
diff --git a/arch/riscv/include/asm/arch-fu540/clk.h b/arch/riscv/include/asm/arch-fu540/clk.h
new file mode 100644
index 0000000000..d71ed4357c
--- /dev/null
+++ b/arch/riscv/include/asm/arch-fu540/clk.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2020 SiFive Inc
+ *
+ * Authors:
+ * Pragnesh Patel <pragnesh.patel@sifive.com>
+ */
+
+#ifndef __CLK_SIFIVE_H
+#define __CLK_SIFIVE_H
+
+/* Note: This is a placeholder header for driver compilation. */
+
+#endif
diff --git a/arch/riscv/include/asm/arch-fu540/gpio.h b/arch/riscv/include/asm/arch-fu540/gpio.h
new file mode 100644
index 0000000000..0d16c59ca6
--- /dev/null
+++ b/arch/riscv/include/asm/arch-fu540/gpio.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019 SiFive, Inc.
+ */
+
+#ifndef _GPIO_SIFIVE_H
+#define _GPIO_SIFIVE_H
+
+#define GPIO_INPUT_VAL 0x00
+#define GPIO_INPUT_EN 0x04
+#define GPIO_OUTPUT_EN 0x08
+#define GPIO_OUTPUT_VAL 0x0C
+#define GPIO_RISE_IE 0x18
+#define GPIO_RISE_IP 0x1C
+#define GPIO_FALL_IE 0x20
+#define GPIO_FALL_IP 0x24
+#define GPIO_HIGH_IE 0x28
+#define GPIO_HIGH_IP 0x2C
+#define GPIO_LOW_IE 0x30
+#define GPIO_LOW_IP 0x34
+#define GPIO_OUTPUT_XOR 0x40
+
+#define NR_GPIOS 16
+
+enum gpio_state {
+ LOW,
+ HIGH
+};
+
+/* Details about a GPIO bank */
+struct sifive_gpio_platdata {
+ void *base; /* address of registers in physical memory */
+};
+
+#define SIFIVE_GENERIC_GPIO_NR(port, index) \
+ (((port) * NR_GPIOS) + ((index) & (NR_GPIOS - 1)))
+
+#endif /* _GPIO_SIFIVE_H */
--
2.17.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v8 15/21] riscv: sifive: fu540: add SPL configuration
2020-05-09 14:30 [PATCH v8 00/21] RISC-V SiFive FU540 support SPL Pragnesh Patel
` (13 preceding siblings ...)
2020-05-09 14:30 ` [PATCH v8 14/21] riscv: Add place-holder for driver compilation Pragnesh Patel
@ 2020-05-09 14:30 ` Pragnesh Patel
2020-05-11 9:00 ` Jagan Teki
2020-05-09 14:30 ` [PATCH v8 16/21] sifive: fu540: Add sample SD gpt partition layout Pragnesh Patel
` (5 subsequent siblings)
20 siblings, 1 reply; 31+ messages in thread
From: Pragnesh Patel @ 2020-05-09 14:30 UTC (permalink / raw)
To: u-boot
Add a support for SPL which will boot from L2 LIM (0x0800_0000) and
then SPL will boot U-Boot FIT image (OpenSBI FW_DYNAMIC + u-boot.bin)
from MMC boot devices.
SPL related code is leveraged from FSBL
(https://github.com/sifive/freedom-u540-c000-bootloader.git)
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
---
arch/riscv/cpu/fu540/Makefile | 4 ++
arch/riscv/cpu/fu540/spl.c | 23 ++++++
.../dts/hifive-unleashed-a00-u-boot.dtsi | 5 ++
arch/riscv/include/asm/arch-fu540/spl.h | 14 ++++
board/sifive/fu540/Kconfig | 12 +++-
board/sifive/fu540/Makefile | 4 ++
board/sifive/fu540/fu540.c | 24 +++++++
board/sifive/fu540/spl.c | 72 +++++++++++++++++++
include/configs/sifive-fu540.h | 18 +++++
9 files changed, 174 insertions(+), 2 deletions(-)
create mode 100644 arch/riscv/cpu/fu540/spl.c
create mode 100644 arch/riscv/include/asm/arch-fu540/spl.h
create mode 100644 board/sifive/fu540/spl.c
diff --git a/arch/riscv/cpu/fu540/Makefile b/arch/riscv/cpu/fu540/Makefile
index 44700d998c..043fb961a5 100644
--- a/arch/riscv/cpu/fu540/Makefile
+++ b/arch/riscv/cpu/fu540/Makefile
@@ -3,5 +3,9 @@
# Copyright (C) 2020 SiFive, Inc
# Pragnesh Patel <pragnesh.patel@sifive.com>
+ifeq ($(CONFIG_SPL_BUILD),y)
+obj-y += spl.o
+else
obj-y += dram.o
obj-y += cpu.o
+endif
diff --git a/arch/riscv/cpu/fu540/spl.c b/arch/riscv/cpu/fu540/spl.c
new file mode 100644
index 0000000000..2e05d8a6e2
--- /dev/null
+++ b/arch/riscv/cpu/fu540/spl.c
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 SiFive, Inc
+ * Pragnesh Patel <pragnesh.patel@sifive.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+
+int soc_spl_init(void)
+{
+ int ret;
+ struct udevice *dev;
+
+ /* DDR init */
+ ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+ if (ret) {
+ debug("DRAM init failed: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
diff --git a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
index 9787332bf1..37de015de6 100644
--- a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
+++ b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
@@ -4,6 +4,7 @@
*/
#include "fu540-c000-u-boot.dtsi"
+#include "fu540-hifive-unleashed-a00-sdram-ddr4.dtsi"
/ {
aliases {
@@ -26,3 +27,7 @@
u-boot,dm-spl;
};
};
+
+&gpio {
+ u-boot,dm-spl;
+};
diff --git a/arch/riscv/include/asm/arch-fu540/spl.h b/arch/riscv/include/asm/arch-fu540/spl.h
new file mode 100644
index 0000000000..0c188be747
--- /dev/null
+++ b/arch/riscv/include/asm/arch-fu540/spl.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2020 SiFive, Inc.
+ *
+ * Authors:
+ * Pragnesh Patel <pragnesh.patel@sifve.com>
+ */
+
+#ifndef _SPL_SIFIVE_H
+#define _SPL_SIFIVE_H
+
+int soc_spl_init(void);
+
+#endif /* _SPL_SIFIVE_H */
diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig
index d41c305227..4a77a2a37b 100644
--- a/board/sifive/fu540/Kconfig
+++ b/board/sifive/fu540/Kconfig
@@ -7,18 +7,26 @@ config SYS_VENDOR
default "sifive"
config SYS_CPU
- default "generic"
+ default "fu540"
config SYS_CONFIG_NAME
default "sifive-fu540"
config SYS_TEXT_BASE
+ default 0x80200000 if SPL
default 0x80000000 if !RISCV_SMODE
default 0x80200000 if RISCV_SMODE
+config SPL_TEXT_BASE
+ default 0x08000000
+
+config SPL_OPENSBI_LOAD_ADDR
+ default 0x80000000
+
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
- select GENERIC_RISCV
+ select SIFIVE_FU540
+ select SUPPORT_SPL
select RAM
select SPL_RAM if SPL
imply CMD_DHCP
diff --git a/board/sifive/fu540/Makefile b/board/sifive/fu540/Makefile
index 6e1862c475..b05e2f5807 100644
--- a/board/sifive/fu540/Makefile
+++ b/board/sifive/fu540/Makefile
@@ -3,3 +3,7 @@
# Copyright (c) 2019 Western Digital Corporation or its affiliates.
obj-y += fu540.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+endif
diff --git a/board/sifive/fu540/fu540.c b/board/sifive/fu540/fu540.c
index 540638c919..d05529a86b 100644
--- a/board/sifive/fu540/fu540.c
+++ b/board/sifive/fu540/fu540.c
@@ -11,6 +11,7 @@
#include <linux/delay.h>
#include <linux/io.h>
#include <misc.h>
+#include <spl.h>
/*
* This define is a value used for error/unknown serial.
@@ -114,3 +115,26 @@ int board_init(void)
return 0;
}
+
+#ifdef CONFIG_SPL
+void board_boot_order(u32 *spl_boot_list)
+{
+ u8 i;
+ u32 boot_devices[] = {
+#ifdef CONFIG_SPL_MMC_SUPPORT
+ BOOT_DEVICE_MMC1,
+#endif
+ };
+
+ for (i = 0; i < ARRAY_SIZE(boot_devices); i++)
+ spl_boot_list[i] = boot_devices[i];
+}
+#endif
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+ /* boot using first FIT config */
+ return 0;
+}
+#endif
diff --git a/board/sifive/fu540/spl.c b/board/sifive/fu540/spl.c
new file mode 100644
index 0000000000..b3ff6850e3
--- /dev/null
+++ b/board/sifive/fu540/spl.c
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019 SiFive, Inc
+ *
+ * Authors:
+ * Pragnesh Patel <pragnesh.patel@sifive.com>
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <misc.h>
+#include <asm/gpio.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/spl.h>
+
+#define GEM_PHY_RESET SIFIVE_GENERIC_GPIO_NR(0, 12)
+
+int init_clk_and_ddr(void)
+{
+ int ret;
+
+ ret = soc_spl_init();
+ if (ret) {
+ debug("FU540 SPL init failed: %d\n", ret);
+ return ret;
+ }
+
+ /*
+ * GEMGXL init VSC8541 PHY reset sequence;
+ * leave pull-down active for 2ms
+ */
+ udelay(2000);
+ ret = gpio_request(GEM_PHY_RESET, "gem_phy_reset");
+ if (ret) {
+ debug("gem_phy_reset gpio request failed: %d\n", ret);
+ return ret;
+ }
+
+ /* Set GPIO 12 (PHY NRESET) */
+ ret = gpio_direction_output(GEM_PHY_RESET, 1);
+ if (ret) {
+ debug("gem_phy_reset gpio direction set failed: %d\n", ret);
+ return ret;
+ }
+
+ udelay(1);
+
+ /* Reset PHY again to enter unmanaged mode */
+ gpio_set_value(GEM_PHY_RESET, 0);
+ udelay(1);
+ gpio_set_value(GEM_PHY_RESET, 1);
+ mdelay(15);
+
+ return 0;
+}
+
+void board_init_f(ulong dummy)
+{
+ int ret;
+
+ ret = spl_early_init();
+ if (ret)
+ panic("spl_early_init() failed: %d\n", ret);
+
+ arch_cpu_init_dm();
+
+ preloader_console_init();
+
+ ret = init_clk_and_ddr();
+ if (ret)
+ panic("init_clk_and_ddr() failed: %d\n", ret);
+}
diff --git a/include/configs/sifive-fu540.h b/include/configs/sifive-fu540.h
index 2756ed5a77..ef3ae9b650 100644
--- a/include/configs/sifive-fu540.h
+++ b/include/configs/sifive-fu540.h
@@ -11,6 +11,22 @@
#include <linux/sizes.h>
+#ifdef CONFIG_SPL
+
+#define CONFIG_SPL_MAX_SIZE 0x00100000
+#define CONFIG_SPL_BSS_START_ADDR 0x85000000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
+#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
+ CONFIG_SPL_BSS_MAX_SIZE)
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000
+
+#define CONFIG_SPL_LOAD_FIT_ADDRESS 0x84000000
+
+#define CONFIG_SPL_STACK (0x08000000 + 0x001D0000 - \
+ GENERATED_GBL_DATA_SIZE)
+
+#endif
+
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M)
@@ -24,6 +40,7 @@
/* Environment options */
+#ifndef CONFIG_SPL_BUILD
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0) \
func(DHCP, dhcp, na)
@@ -43,5 +60,6 @@
#define CONFIG_PREBOOT \
"setenv fdt_addr ${fdtcontroladdr};" \
"fdt addr ${fdtcontroladdr};"
+#endif
#endif /* __CONFIG_H */
--
2.17.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v8 16/21] sifive: fu540: Add sample SD gpt partition layout
2020-05-09 14:30 [PATCH v8 00/21] RISC-V SiFive FU540 support SPL Pragnesh Patel
` (14 preceding siblings ...)
2020-05-09 14:30 ` [PATCH v8 15/21] riscv: sifive: fu540: add SPL configuration Pragnesh Patel
@ 2020-05-09 14:30 ` Pragnesh Patel
2020-05-09 14:30 ` [PATCH v8 17/21] sifive: fu540: Add U-Boot proper sector start Pragnesh Patel
` (4 subsequent siblings)
20 siblings, 0 replies; 31+ messages in thread
From: Pragnesh Patel @ 2020-05-09 14:30 UTC (permalink / raw)
To: u-boot
From: Jagan Teki <jagan@amarulasolutions.com>
This is a sample GPT partition layout for SD card,
right now three important partitions are added to
make the system bootable.
partition layout:
Part Start LBA End LBA Name
Attributes
Type GUID
Partition GUID
1 0x00000022 0x00000821 "loader1"
attrs: 0x0000000000000000
type: 5b193300-fc78-40cd-8002-e86c45580b47
guid: cbcbef44-e627-42bc-b134-93b6f3784b8c
2 0x00000822 0x00002821 "loader2"
attrs: 0x0000000000000000
type: 2e54b353-1271-4842-806f-e436d6af6985
guid: f54eba28-d8de-4852-978d-1a673777e2ae
3 0x00002822 0x00020821 "rootfs"
attrs: 0x0000000000000004
type: 0fc63daf-8483-4772-8e79-3d69d8477de4
type: linux
guid: 9561df46-8d55-4799-a83b-cfee9ef6ff93
Note:
- loader1 would be fsbl or spl
- loader2 would be U-Boot or U-Boot proper
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
---
board/sifive/fu540/Kconfig | 2 ++
include/configs/sifive-fu540.h | 13 +++++++++++++
2 files changed, 15 insertions(+)
diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig
index 4a77a2a37b..86193d7668 100644
--- a/board/sifive/fu540/Kconfig
+++ b/board/sifive/fu540/Kconfig
@@ -34,6 +34,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
imply CMD_EXT4
imply CMD_FAT
imply CMD_FS_GENERIC
+ imply CMD_GPT
+ imply PARTITION_TYPE_GUID
imply CMD_NET
imply CMD_PING
imply CMD_SF
diff --git a/include/configs/sifive-fu540.h b/include/configs/sifive-fu540.h
index ef3ae9b650..72c841eb9b 100644
--- a/include/configs/sifive-fu540.h
+++ b/include/configs/sifive-fu540.h
@@ -47,6 +47,15 @@
#include <config_distro_bootcmd.h>
+#define TYPE_GUID_LOADER1 "5B193300-FC78-40CD-8002-E86C45580B47"
+#define TYPE_GUID_LOADER2 "2E54B353-1271-4842-806F-E436D6AF6985"
+#define TYPE_GUID_SYSTEM "0FC63DAF-8483-4772-8E79-3D69D8477DE4"
+
+#define PARTS_DEFAULT \
+ "name=loader1,start=17K,size=1M,type=${type_guid_gpt_loader1};" \
+ "name=loader2,size=4MB,type=${type_guid_gpt_loader2};" \
+ "name=system,size=-,bootable,type=${type_guid_gpt_system};"
+
#define CONFIG_EXTRA_ENV_SETTINGS \
"fdt_high=0xffffffffffffffff\0" \
"initrd_high=0xffffffffffffffff\0" \
@@ -55,6 +64,10 @@
"scriptaddr=0x88100000\0" \
"pxefile_addr_r=0x88200000\0" \
"ramdisk_addr_r=0x88300000\0" \
+ "type_guid_gpt_loader1=" TYPE_GUID_LOADER1 "\0" \
+ "type_guid_gpt_loader2=" TYPE_GUID_LOADER2 "\0" \
+ "type_guid_gpt_system=" TYPE_GUID_SYSTEM "\0" \
+ "partitions=" PARTS_DEFAULT "\0" \
BOOTENV
#define CONFIG_PREBOOT \
--
2.17.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v8 17/21] sifive: fu540: Add U-Boot proper sector start
2020-05-09 14:30 [PATCH v8 00/21] RISC-V SiFive FU540 support SPL Pragnesh Patel
` (15 preceding siblings ...)
2020-05-09 14:30 ` [PATCH v8 16/21] sifive: fu540: Add sample SD gpt partition layout Pragnesh Patel
@ 2020-05-09 14:30 ` Pragnesh Patel
2020-05-09 14:30 ` [PATCH v8 18/21] configs: fu540: Add config options for U-Boot SPL Pragnesh Patel
` (3 subsequent siblings)
20 siblings, 0 replies; 31+ messages in thread
From: Pragnesh Patel @ 2020-05-09 14:30 UTC (permalink / raw)
To: u-boot
From: Jagan Teki <jagan@amarulasolutions.com>
Add U-Boot proper sector start offset for SiFive FU540.
This value is based on the partition layout supported
by SiFive FU540.
u-boot.itb need to write on this specific offset so-that
the SPL will retrieve it from here and load.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
---
common/spl/Kconfig | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index 9feadb5e43..9d6f51d672 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -308,7 +308,7 @@ config SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
ARCH_MX6 || ARCH_MX7 || \
ARCH_ROCKCHIP || ARCH_MVEBU || ARCH_SOCFPGA || \
ARCH_AT91 || ARCH_ZYNQ || ARCH_KEYSTONE || OMAP34XX || \
- OMAP44XX || OMAP54XX || AM33XX || AM43XX
+ OMAP44XX || OMAP54XX || AM33XX || AM43XX || TARGET_SIFIVE_FU540
help
Use sector number for specifying U-Boot location on MMC/SD in
raw mode.
@@ -325,6 +325,7 @@ config SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR
default 0x300 if ARCH_ZYNQ || ARCH_KEYSTONE || OMAP34XX || OMAP44XX || \
OMAP54XX || AM33XX || AM43XX || ARCH_K3
default 0x4000 if ARCH_ROCKCHIP
+ default 0x822 if TARGET_SIFIVE_FU540
help
Address on the MMC to load U-Boot from, when the MMC is being used
in raw mode. Units: MMC sectors (1 sector = 512 bytes).
--
2.17.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v8 18/21] configs: fu540: Add config options for U-Boot SPL
2020-05-09 14:30 [PATCH v8 00/21] RISC-V SiFive FU540 support SPL Pragnesh Patel
` (16 preceding siblings ...)
2020-05-09 14:30 ` [PATCH v8 17/21] sifive: fu540: Add U-Boot proper sector start Pragnesh Patel
@ 2020-05-09 14:30 ` Pragnesh Patel
2020-05-10 9:20 ` Jagan Teki
2020-05-09 14:30 ` [PATCH v8 19/21] sifive: dts: fu540: Enable L2 Cache in U-Boot Pragnesh Patel
` (2 subsequent siblings)
20 siblings, 1 reply; 31+ messages in thread
From: Pragnesh Patel @ 2020-05-09 14:30 UTC (permalink / raw)
To: u-boot
With sifive_fu540_defconfig:
User can use FSBL or u-boot-spl.bin anyone at a time.
For FSBL,
fsbl->fw_payload.bin (opensbi + U-Boot)
For u-boot-spl.bin,
u-boot-spl.bin->FIT image (opensbi + U-Boot + dtb)
U-Boot SPL will be loaded by ZSBL from SD card (replace fsbl.bin with
u-boot-spl.bin) and runs in L2 LIM in machine mode and then load FIT
image u-boot.itb from SD card into RAM.
U-Boot SPL expects u-boot.itb FIT image at the starting of SD card sector
number (0x822) of GUID type "2E54B353-1271-4842-806F-E436D6AF6985"
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
configs/sifive_fu540_defconfig | 8 ++
doc/board/sifive/fu540.rst | 134 +++++++++++++++++++++++++++++++++
2 files changed, 142 insertions(+)
diff --git a/configs/sifive_fu540_defconfig b/configs/sifive_fu540_defconfig
index f805aacc7a..8d412f8d6a 100644
--- a/configs/sifive_fu540_defconfig
+++ b/configs/sifive_fu540_defconfig
@@ -1,6 +1,11 @@
CONFIG_RISCV=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x3000
CONFIG_ENV_SIZE=0x20000
+CONFIG_SPL_MMC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL=y
+CONFIG_SPL_SPI_SUPPORT=y
CONFIG_TARGET_SIFIVE_FU540=y
CONFIG_ARCH_RV64I=y
CONFIG_RISCV_SMODE=y
@@ -9,7 +14,10 @@ CONFIG_FIT=y
CONFIG_MISC_INIT_R=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_OF_BOARD_FIXUP=y
CONFIG_DEFAULT_DEVICE_TREE="hifive-unleashed-a00"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_CLK=y
CONFIG_DM_MTD=y
diff --git a/doc/board/sifive/fu540.rst b/doc/board/sifive/fu540.rst
index 610ba87074..89e8d66c56 100644
--- a/doc/board/sifive/fu540.rst
+++ b/doc/board/sifive/fu540.rst
@@ -31,6 +31,9 @@ TODO:
stdout-path = "/soc/serial at 10010000:115200";
};
+Booting from MMC using FSBL
+---------------------------
+
Building
--------
@@ -421,3 +424,134 @@ as well.
Please press Enter to activate this console.
/ #
+
+Booting from MMC using U-Boot SPL
+---------------------------------
+
+Building
+--------
+
+Before building U-Boot SPL, OpenSBI must be built first. OpenSBI can be
+cloned and built for FU540 as below:
+
+.. code-block:: console
+
+ git clone https://github.com/riscv/opensbi.git
+ cd opensbi
+ make PLATFORM=generic FW_DYNAMIC=y
+
+Copy OpenSBI FW_DYNAMIC image
+(build/platform/generic/firmware/fw_dynamic.bin) into U-Boot
+root directory
+
+.. code-block:: console
+
+ cp build/platform/generic/firmware/fw_dynamic.bin <u-boot-dir>
+
+Now build the U-Boot SPL and U-Boot proper
+
+.. code-block:: console
+
+ cd <U-Boot-dir>
+ make sifive_fu540_defconfig
+ make
+
+This will generate spl/u-boot-spl.bin and FIT image (u-boot.itb)
+
+
+Flashing
+--------
+
+ZSBL loads the U-Boot SPL (u-boot-spl.bin) from a partition with GUID type
+5B193300-FC78-40CD-8002-E86C45580B47
+
+U-Boot SPL expects a U-Boot FIT image (u-boot.itb) from a partition with GUID
+type 2E54B353-1271-4842-806F-E436D6AF6985
+
+FIT image (u-boot.itb) is a combination of fw_dynamic.bin, u-boot-nodtb.bin and
+device tree blob (hifive-unleashed-a00.dtb)
+
+Format the SD card (make sure the disk has GPT, otherwise use gdisk to switch)
+
+.. code-block:: none
+
+ # sudo sgdisk --clear \
+ > --set-alignment=2 \
+ > --new=1:34:2081 --change-name=1:loader1 --typecode=1:5B193300-FC78-40CD-8002-E86C45580B47 \
+ > --new=2:2082:10273 --change-name=2:loader2 --typecode=2:2E54B353-1271-4842-806F-E436D6AF6985 \
+ > --new=3:10274: --change-name=3:rootfs --typecode=3:0FC63DAF-8483-4772-8E79-3D69D8477DE4 \
+ > /dev/sda
+
+Program the SD card
+
+.. code-block:: none
+
+ sudo dd if=spl/u-boot-spl.bin of=/dev/sda seek=34
+ sudo dd if=u-boot.itb of=/dev/sda seek=2082
+
+Booting
+-------
+Once you plugin the sdcard and power up, you should see the U-Boot prompt.
+
+Sample boot log from HiFive Unleashed board
+-------------------------------------------
+
+.. code-block:: none
+
+ U-Boot SPL 2020.04-rc2-00109-g63efc7e07e-dirty (Apr 30 2020 - 13:52:36 +0530)
+ Trying to boot from MMC1
+
+
+ U-Boot 2020.04-rc2-00109-g63efc7e07e-dirty (Apr 30 2020 - 13:52:36 +0530)
+
+ CPU: rv64imafdc
+ Model: SiFive HiFive Unleashed A00
+ DRAM: 8 GiB
+ MMC: spi at 10050000:mmc at 0: 0
+ In: serial at 10010000
+ Out: serial at 10010000
+ Err: serial at 10010000
+ Board serial number should not be 0 !!
+ Net:
+ Warning: ethernet at 10090000 (eth0) using random MAC address - 96:06:92:18:eb:04
+ eth0: ethernet at 10090000
+ Hit any key to stop autoboot: 0
+ => version
+ U-Boot 2020.04-rc2-00109-g63efc7e07e-dirty (Apr 30 2020 - 13:52:36 +0530)
+
+ riscv64-unknown-linux-gnu-gcc (crosstool-NG 1.24.0.37-3f461da) 9.2.0
+ GNU ld (crosstool-NG 1.24.0.37-3f461da) 2.32
+ => mmc info
+ Device: spi at 10050000:mmc at 0
+ Manufacturer ID: 3
+ OEM: 5344
+ Name: SC16G
+ Bus Speed: 20000000
+ Mode: SD Legacy
+ Rd Block Len: 512
+ SD version 2.0
+ High Capacity: Yes
+ Capacity: 14.8 GiB
+ Bus Width: 1-bit
+ Erase Group Size: 512 Bytes
+ => mmc part
+
+ Partition Map for MMC device 0 -- Partition Type: EFI
+
+ Part Start LBA End LBA Name
+ Attributes
+ Type GUID
+ Partition GUID
+ 1 0x00000022 0x00000821 "loader1"
+ attrs: 0x0000000000000000
+ type: 5b193300-fc78-40cd-8002-e86c45580b47
+ guid: 66e2b5d2-74db-4df8-ad6f-694b3617f87f
+ 2 0x00000822 0x00002821 "loader2"
+ attrs: 0x0000000000000000
+ type: 2e54b353-1271-4842-806f-e436d6af6985
+ guid: 8befaeaf-bca0-435d-b002-e201f37c0a2f
+ 3 0x00002822 0x01dacbde "rootfs"
+ attrs: 0x0000000000000000
+ type: 0fc63daf-8483-4772-8e79-3d69d8477de4
+ type: linux
+ guid: 9faa81b6-39b1-4418-af5e-89c48f29c20d
--
2.17.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v8 19/21] sifive: dts: fu540: Enable L2 Cache in U-Boot
2020-05-09 14:30 [PATCH v8 00/21] RISC-V SiFive FU540 support SPL Pragnesh Patel
` (17 preceding siblings ...)
2020-05-09 14:30 ` [PATCH v8 18/21] configs: fu540: Add config options for U-Boot SPL Pragnesh Patel
@ 2020-05-09 14:30 ` Pragnesh Patel
2020-05-10 15:14 ` Jagan Teki
2020-05-09 14:30 ` [PATCH v8 20/21] riscv: sifive: fu540: enable all cache ways from U-Boot proper Pragnesh Patel
2020-05-09 14:30 ` [PATCH v8 21/21] doc: sifive: fu540: Add description for OpenSBI generic platform Pragnesh Patel
20 siblings, 1 reply; 31+ messages in thread
From: Pragnesh Patel @ 2020-05-09 14:30 UTC (permalink / raw)
To: u-boot
Add L2 cache node to enable cache ways from U-Boot
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
arch/riscv/dts/fu540-c000-u-boot.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi b/arch/riscv/dts/fu540-c000-u-boot.dtsi
index fc91a7c987..42e43522ed 100644
--- a/arch/riscv/dts/fu540-c000-u-boot.dtsi
+++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi
@@ -82,3 +82,7 @@
&qspi2 {
u-boot,dm-spl;
};
+
+&l2cache {
+ status = "okay";
+};
--
2.17.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v8 20/21] riscv: sifive: fu540: enable all cache ways from U-Boot proper
2020-05-09 14:30 [PATCH v8 00/21] RISC-V SiFive FU540 support SPL Pragnesh Patel
` (18 preceding siblings ...)
2020-05-09 14:30 ` [PATCH v8 19/21] sifive: dts: fu540: Enable L2 Cache in U-Boot Pragnesh Patel
@ 2020-05-09 14:30 ` Pragnesh Patel
2020-05-09 14:30 ` [PATCH v8 21/21] doc: sifive: fu540: Add description for OpenSBI generic platform Pragnesh Patel
20 siblings, 0 replies; 31+ messages in thread
From: Pragnesh Patel @ 2020-05-09 14:30 UTC (permalink / raw)
To: u-boot
Enable all cache ways from U-Boot proper.
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
arch/riscv/cpu/fu540/Makefile | 1 +
arch/riscv/cpu/fu540/cache.c | 53 +++++++++++++++++++++++
arch/riscv/include/asm/arch-fu540/cache.h | 14 ++++++
board/sifive/fu540/fu540.c | 10 ++++-
4 files changed, 77 insertions(+), 1 deletion(-)
create mode 100644 arch/riscv/cpu/fu540/cache.c
create mode 100644 arch/riscv/include/asm/arch-fu540/cache.h
diff --git a/arch/riscv/cpu/fu540/Makefile b/arch/riscv/cpu/fu540/Makefile
index 043fb961a5..088205ef57 100644
--- a/arch/riscv/cpu/fu540/Makefile
+++ b/arch/riscv/cpu/fu540/Makefile
@@ -8,4 +8,5 @@ obj-y += spl.o
else
obj-y += dram.o
obj-y += cpu.o
+obj-y += cache.o
endif
diff --git a/arch/riscv/cpu/fu540/cache.c b/arch/riscv/cpu/fu540/cache.c
new file mode 100644
index 0000000000..d2dae7f17a
--- /dev/null
+++ b/arch/riscv/cpu/fu540/cache.c
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 SiFive, Inc
+ *
+ * Authors:
+ * Pragnesh Patel <pragnesh.patel@sifive.com>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <linux/bitops.h>
+
+/* Register offsets */
+#define CACHE_CONFIG 0x000
+#define CACHE_ENABLE 0x008
+
+#define MASK_NUM_WAYS GENMASK(15, 8)
+#define NUM_WAYS_SHIFT 8
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int cache_enable_ways(void)
+{
+ const void *blob = gd->fdt_blob;
+ int node = (-FDT_ERR_NOTFOUND);
+ fdt_addr_t base;
+ u32 config;
+ u32 ways;
+
+ volatile u32 *enable;
+
+ node = fdt_node_offset_by_compatible(blob, -1,
+ "sifive,fu540-c000-ccache");
+
+ if (node < 0)
+ return node;
+
+ base = fdtdec_get_addr(blob, node, "reg");
+ if (base == FDT_ADDR_T_NONE)
+ return FDT_ADDR_T_NONE;
+
+ config = readl((volatile u32 *)base + CACHE_CONFIG);
+ ways = (config & MASK_NUM_WAYS) >> NUM_WAYS_SHIFT;
+
+ enable = (volatile u32 *)(base + CACHE_ENABLE);
+
+ /* memory barrier */
+ mb();
+ (*enable) = ways - 1;
+ /* memory barrier */
+ mb();
+ return 0;
+}
diff --git a/arch/riscv/include/asm/arch-fu540/cache.h b/arch/riscv/include/asm/arch-fu540/cache.h
new file mode 100644
index 0000000000..135a17c679
--- /dev/null
+++ b/arch/riscv/include/asm/arch-fu540/cache.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2020 SiFive, Inc.
+ *
+ * Authors:
+ * Pragnesh Patel <pragnesh.patel@sifve.com>
+ */
+
+#ifndef _CACHE_SIFIVE_H
+#define _CACHE_SIFIVE_H
+
+int cache_enable_ways(void);
+
+#endif /* _CACHE_SIFIVE_H */
diff --git a/board/sifive/fu540/fu540.c b/board/sifive/fu540/fu540.c
index d05529a86b..6d5847abee 100644
--- a/board/sifive/fu540/fu540.c
+++ b/board/sifive/fu540/fu540.c
@@ -12,6 +12,7 @@
#include <linux/io.h>
#include <misc.h>
#include <spl.h>
+#include <asm/arch/cache.h>
/*
* This define is a value used for error/unknown serial.
@@ -111,7 +112,14 @@ int misc_init_r(void)
int board_init(void)
{
- /* For now nothing to do here. */
+ int ret;
+
+ /* enable all cache ways */
+ ret = cache_enable_ways();
+ if (ret) {
+ debug("%s: could not enable cache ways\n", __func__);
+ return ret;
+ }
return 0;
}
--
2.17.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v8 21/21] doc: sifive: fu540: Add description for OpenSBI generic platform
2020-05-09 14:30 [PATCH v8 00/21] RISC-V SiFive FU540 support SPL Pragnesh Patel
` (19 preceding siblings ...)
2020-05-09 14:30 ` [PATCH v8 20/21] riscv: sifive: fu540: enable all cache ways from U-Boot proper Pragnesh Patel
@ 2020-05-09 14:30 ` Pragnesh Patel
20 siblings, 0 replies; 31+ messages in thread
From: Pragnesh Patel @ 2020-05-09 14:30 UTC (permalink / raw)
To: u-boot
OpenSBI generic platform support provides platform specific
functionality based on the FDT passed by previous booting stage.
depends on OpenSBI commit:
platform: Add generic FDT based platform support
(sha1: f1aa9e54e00006ae70aeac638d5b75093520f65d)
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
---
doc/board/sifive/fu540.rst | 13 +------------
1 file changed, 1 insertion(+), 12 deletions(-)
diff --git a/doc/board/sifive/fu540.rst b/doc/board/sifive/fu540.rst
index 89e8d66c56..a51d086a6d 100644
--- a/doc/board/sifive/fu540.rst
+++ b/doc/board/sifive/fu540.rst
@@ -20,17 +20,6 @@ The support for following drivers are already enabled:
4. SiFive SPI Driver.
5. MMC SPI Driver for MMC/SD support.
-TODO:
-
-1. U-Boot expects the serial console device entry to be present under /chosen
- DT node. Without a serial console U-Boot will panic. Example:
-
-.. code-block:: none
-
- chosen {
- stdout-path = "/soc/serial at 10010000:115200";
- };
-
Booting from MMC using FSBL
---------------------------
@@ -61,7 +50,7 @@ firmware. We need to compile OpenSBI with below command:
.. code-block:: none
-make PLATFORM=sifive/fu540 FW_PAYLOAD_PATH=<path to u-boot-dtb.bin>
+ make PLATFORM=generic FW_PAYLOAD_PATH=<path to u-boot-dtb.bin>
More detailed description of steps required to build FW_PAYLOAD firmware
is beyond the scope of this document. Please refer OpenSBI documenation.
--
2.17.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v8 06/21] sifive: fu540: add ddr driver
2020-05-09 14:30 ` [PATCH v8 06/21] sifive: fu540: add ddr driver Pragnesh Patel
@ 2020-05-09 19:47 ` Giulio Benetti
2020-05-10 6:18 ` Pragnesh Patel
2020-05-10 6:35 ` Pragnesh Patel
0 siblings, 2 replies; 31+ messages in thread
From: Giulio Benetti @ 2020-05-09 19:47 UTC (permalink / raw)
To: u-boot
Hi Pragnesh,
On 5/9/20 4:30 PM, Pragnesh Patel wrote:
> Add driver for fu540 to support ddr initialization in SPL.
> This driver is based on FSBL
> (https://github.com/sifive/freedom-u540-c000-bootloader.git)
>
> Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> Tested-by: Bin Meng <bmeng.cn@gmail.com>
> ---
> board/sifive/fu540/Kconfig | 2 +
> drivers/ram/Kconfig | 1 +
> drivers/ram/Makefile | 2 +
> drivers/ram/sifive/Kconfig | 13 +
> drivers/ram/sifive/Makefile | 6 +
> drivers/ram/sifive/sdram_fu540.c | 416 +++++++++++++++++++++++++++++++
> 6 files changed, 440 insertions(+)
> create mode 100644 drivers/ram/sifive/Kconfig
> create mode 100644 drivers/ram/sifive/Makefile
> create mode 100644 drivers/ram/sifive/sdram_fu540.c
>
> diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig
> index 4330ac4491..d41c305227 100644
> --- a/board/sifive/fu540/Kconfig
> +++ b/board/sifive/fu540/Kconfig
> @@ -19,6 +19,8 @@ config SYS_TEXT_BASE
> config BOARD_SPECIFIC_OPTIONS # dummy
> def_bool y
> select GENERIC_RISCV
> + select RAM
> + select SPL_RAM if SPL
> imply CMD_DHCP
> imply CMD_EXT2
> imply CMD_EXT4
> diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig
> index 56fea7c94c..66074d1feb 100644
> --- a/drivers/ram/Kconfig
> +++ b/drivers/ram/Kconfig
> @@ -75,3 +75,4 @@ config IMXRT_SDRAM
>
> source "drivers/ram/rockchip/Kconfig"
> source "drivers/ram/stm32mp1/Kconfig"
> +source "drivers/ram/sifive/Kconfig"
> diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile
> index 5c897410c6..769c9d6218 100644
> --- a/drivers/ram/Makefile
> +++ b/drivers/ram/Makefile
> @@ -17,3 +17,5 @@ obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
> obj-$(CONFIG_K3_J721E_DDRSS) += k3-j721e/
>
> obj-$(CONFIG_IMXRT_SDRAM) += imxrt_sdram.o
> +
> +obj-$(CONFIG_RAM_SIFIVE) += sifive/
> diff --git a/drivers/ram/sifive/Kconfig b/drivers/ram/sifive/Kconfig
> new file mode 100644
> index 0000000000..6aca22ab2a
> --- /dev/null
> +++ b/drivers/ram/sifive/Kconfig
> @@ -0,0 +1,13 @@
> +config RAM_SIFIVE
> + bool "Ram drivers support for SiFive SoCs"
> + depends on RAM && RISCV
> + default y
> + help
> + This enables support for ram drivers of SiFive SoCs.
> +
> +config SIFIVE_FU540_DDR
> + bool "SiFive FU540 DDR driver"
> + depends on RAM_SIFIVE
> + default y if TARGET_SIFIVE_FU540
> + help
> + This enables DDR support for the platforms based on SiFive FU540 SoC.
> diff --git a/drivers/ram/sifive/Makefile b/drivers/ram/sifive/Makefile
> new file mode 100644
> index 0000000000..0187805199
> --- /dev/null
> +++ b/drivers/ram/sifive/Makefile
> @@ -0,0 +1,6 @@
> +# SPDX-License-Identifier: GPL-2.0+
> +#
> +# Copyright (c) 2020 SiFive, Inc
> +#
> +
> +obj-$(CONFIG_SIFIVE_FU540_DDR) += sdram_fu540.o
if this is a ddr-only driver I would change the name to:
fu540_ddr.o (keeping fu540 as prefix like the others).
> diff --git a/drivers/ram/sifive/sdram_fu540.c b/drivers/ram/sifive/sdram_fu540.c
> new file mode 100644
> index 0000000000..419359ff3b
> --- /dev/null
> +++ b/drivers/ram/sifive/sdram_fu540.c
> @@ -0,0 +1,416 @@
> +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
> +/*
> + * (C) Copyright 2020 SiFive, Inc.
> + *
> + * Authors:
> + * Pragnesh Patel <pragnesh.patel@sifive.com>
> + */
> +
> +#include <common.h>
> +#include <dm.h>
> +#include <init.h>
> +#include <ram.h>
> +#include <regmap.h>
> +#include <syscon.h>
> +#include <asm/io.h>
> +#include <clk.h>
> +#include <wait_bit.h>
> +
> +#define DENALI_CTL_0 0
> +#define DENALI_CTL_21 21
> +#define DENALI_CTL_120 120
> +#define DENALI_CTL_132 132
> +#define DENALI_CTL_136 136
> +#define DENALI_CTL_170 170
> +#define DENALI_CTL_181 181
> +#define DENALI_CTL_182 182
> +#define DENALI_CTL_184 184
> +#define DENALI_CTL_208 208
> +#define DENALI_CTL_209 209
> +#define DENALI_CTL_210 210
> +#define DENALI_CTL_212 212
> +#define DENALI_CTL_214 214
> +#define DENALI_CTL_216 216
> +#define DENALI_CTL_224 224
> +#define DENALI_CTL_225 225
> +#define DENALI_CTL_260 260
> +
> +#define DENALI_PHY_1152 1152
> +#define DENALI_PHY_1214 1214
> +
> +#define PAYLOAD_DEST 0x80000000
> +#define DDR_MEM_SIZE (8UL * 1024UL * 1024UL * 1024UL)
> +
> +#define DRAM_CLASS_OFFSET 8
> +#define DRAM_CLASS_DDR4 0xA
> +#define OPTIMAL_RMODW_EN_OFFSET 0
> +#define DISABLE_RD_INTERLEAVE_OFFSET 16
> +#define OUT_OF_RANGE_OFFSET 1
> +#define MULTIPLE_OUT_OF_RANGE_OFFSET 2
> +#define PORT_COMMAND_CHANNEL_ERROR_OFFSET 7
> +#define MC_INIT_COMPLETE_OFFSET 8
> +#define LEVELING_OPERATION_COMPLETED_OFFSET 22
> +#define DFI_PHY_WRLELV_MODE_OFFSET 24
> +#define DFI_PHY_RDLVL_MODE_OFFSET 24
> +#define DFI_PHY_RDLVL_GATE_MODE_OFFSET 0
> +#define VREF_EN_OFFSET 24
> +#define PORT_ADDR_PROTECTION_EN_OFFSET 0
> +#define AXI0_ADDRESS_RANGE_ENABLE 8
> +#define AXI0_RANGE_PROT_BITS_0_OFFSET 24
> +#define RDLVL_EN_OFFSET 16
> +#define RDLVL_GATE_EN_OFFSET 24
> +#define WRLVL_EN_OFFSET 0
> +
> +#define PHY_RX_CAL_DQ0_0_OFFSET 0
> +#define PHY_RX_CAL_DQ1_0_OFFSET 16
> +
> +struct fu540_ddrctl {
> + volatile u32 denali_ctl[265];
> +};
> +
> +struct fu540_ddrphy {
> + volatile u32 denali_phy[1215];
> +};
> +
> +/**
> + * struct ddr_info
> + *
> + * @dev : pointer for the device
> + * @info : UCLASS RAM information
> + * @ctl : DDR controller base address
> + * @phy : DDR PHY base address
> + * @ctrl : DDR control base address
> + * @physical_filter_ctrl : DDR physical filter control base address
> + */
> +struct ddr_info {
this should be 'struct fu540_ddr_info'
> + struct udevice *dev;
> + struct ram_info info;
> + struct fu540_ddrctl *ctl;
> + struct fu540_ddrphy *phy;
> + struct clk ddr_clk;
> + u32 *physical_filter_ctrl;
> +};
> +
> +#if defined(CONFIG_TPL_BUILD) || \
> + (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
> +
> +struct fu540_sdram_params {
this should be fu540_ddr_params
> + struct fu540_ddrctl pctl_regs;
> + struct fu540_ddrphy phy_regs;
> +};
> +
> +struct sifive_dmc_plat {
> +#if CONFIG_IS_ENABLED(OF_PLATDATA)
> + struct dtd_sifive_fu540_dmc dtplat;
> +#else
> + struct fu540_sdram_params sdram_params;
> +#endif
> +};
> +
> +/*
> + * TODO : It can be possible to use common sdram_copy_to_reg() API
> + * n: Unit bytes
> + */
> +static void sdram_copy_to_reg(volatile u32 *dest,
> + volatile u32 *src, u32 n)
if you mean to use local function then think about changing its name to:
fu540_ddr_sdram_copy_to_reg(...)
> +{
> + int i;
> +
> + for (i = 0; i < n / sizeof(u32); i++) {
> + writel(*src, dest);
> + src++;
> + dest++;
> + }
> +}
> +
> +static void ddr_setuprangeprotection(volatile u32 *ctl, u64 end_addr)
this should be 'fu540_ddr_setup_range_protection(...)'
> +{
> + u32 end_addr_16kblocks = ((end_addr >> 14) & 0x7FFFFF) - 1;
> +
> + writel(0x0, DENALI_CTL_209 + ctl);
> + writel(end_addr_16kblocks, DENALI_CTL_210 + ctl);
> + writel(0x0, DENALI_CTL_212 + ctl);
> + writel(0x0, DENALI_CTL_214 + ctl);
> + writel(0x0, DENALI_CTL_216 + ctl);
> + setbits_le32(DENALI_CTL_224 + ctl,
> + 0x3 << AXI0_RANGE_PROT_BITS_0_OFFSET);
> + writel(0xFFFFFFFF, DENALI_CTL_225 + ctl);
> + setbits_le32(DENALI_CTL_208 + ctl, 0x1 << AXI0_ADDRESS_RANGE_ENABLE);
> + setbits_le32(DENALI_CTL_208 + ctl,
> + 0x1 << PORT_ADDR_PROTECTION_EN_OFFSET);
> +}
> +
> +static void ddr_start(volatile u32 *ctl, u32 *physical_filter_ctrl, u64 ddr_end)
fu540_ddr_start(...)
> +{
> + volatile u64 *filterreg = (volatile u64 *)physical_filter_ctrl;
> +
> + setbits_le32(DENALI_CTL_0 + ctl, 0x1);
> +
> + wait_for_bit_le32((void *)ctl + DENALI_CTL_132,
> + BIT(MC_INIT_COMPLETE_OFFSET), false, 100, false);
> +
> + /* Disable the BusBlocker in front of the controller AXI slave ports */
> + filterreg[0] = 0x0f00000000000000UL | (ddr_end >> 2);
> +}
> +
> +static void check_errata(u32 regbase, u32 updownreg)
fu540_ddr_check_errata(...)
> +{
> + u64 fails = 0;
> + u32 dq = 0;
> + u32 down, up;
> + u8 failc0, failc1;
> + u32 phy_rx_cal_dqn_0_offset;
> +
> + for (u32 bit = 0; bit < 2; bit++) {
> + if (bit == 0) {
> + phy_rx_cal_dqn_0_offset =
> + PHY_RX_CAL_DQ0_0_OFFSET;
> + } else {
> + phy_rx_cal_dqn_0_offset =
> + PHY_RX_CAL_DQ1_0_OFFSET;
> + }
> +
> + down = (updownreg >>
> + phy_rx_cal_dqn_0_offset) & 0x3F;
> + up = (updownreg >>
> + (phy_rx_cal_dqn_0_offset + 6)) &
> + 0x3F;
> +
> + failc0 = ((down == 0) && (up == 0x3F));
> + failc1 = ((up == 0) && (down == 0x3F));
> +
> + /* print error message on failure */
> + if (failc0 || failc1) {
> + if (fails == 0)
> + printf("DDR error in fixing up\n");
> +
> + fails |= (1 << dq);
> +
> + char slicelsc = '0';
> + char slicemsc = '0';
> +
> + slicelsc += (dq % 10);
> + slicemsc += (dq / 10);
> + printf("S ");
> + printf("%c", slicemsc);
> + printf("%c", slicelsc);
> +
> + if (failc0)
> + printf("U");
> + else
> + printf("D");
> +
> + printf("\n");
> + }
> + dq++;
> + }
> +}
> +
> +static u64 ddr_phy_fixup(volatile u32 *ddrphyreg)
fu540_ddr_fixup(...)
> +{
> + u32 slicebase = 0;
> +
> + /* check errata condition */
> + for (u32 slice = 0; slice < 8; slice++) {
> + u32 regbase = slicebase + 34;
> +
> + for (u32 reg = 0; reg < 4; reg++) {
> + u32 updownreg = readl(regbase + reg + ddrphyreg);
> +
> + check_errata(regbase, updownreg);
> + }
> + slicebase += 128;
> + }
> +
> + return(0);
> +}
> +
> +static u32 ddr_getdramclass(volatile u32 *ctl)
fu540_ddr_get_dram_class(...)
> +{
> + u32 reg = readl(DENALI_CTL_0 + ctl);
> +
> + return ((reg >> DRAM_CLASS_OFFSET) & 0xF);
> +}
> +
> +static int fu540_ddr_setup(struct udevice *dev)
> +{
> + struct ddr_info *priv = dev_get_priv(dev);
> + struct sifive_dmc_plat *plat = dev_get_platdata(dev);
> + struct fu540_sdram_params *params = &plat->sdram_params;
> + int ret, i;
> + u32 physet;
> + const u64 ddr_size = DDR_MEM_SIZE;
> + const u64 ddr_end = PAYLOAD_DEST + ddr_size;
> + volatile u32 *denali_ctl = &priv->ctl->denali_ctl[0];
> + volatile u32 *denali_phy = &priv->phy->denali_phy[0];
would this 2 last be ok with:
volatile u32 *denali_ctl = priv->ctl->denali_ctl;
volatile u32 *denali_phy = priv->phy->denali_phy;
?
an maybe leaving shorter declarations as last ones i.e.:
struct ddr_info *priv = dev_get_priv(dev);
struct sifive_dmc_plat *plat = dev_get_platdata(dev);
struct fu540_sdram_params *params = &plat->sdram_params;
volatile u32 *denali_ctl = &priv->ctl->denali_ctl[0];
volatile u32 *denali_phy = &priv->phy->denali_phy[0];
const u64 ddr_size = DDR_MEM_SIZE;
const u64 ddr_end = PAYLOAD_DEST + ddr_size;
int ret, i;
u32 physet;
> +
> + ret = dev_read_u32_array(dev, "sifive,sdram-params",
> + (u32 *)&plat->sdram_params,
> + sizeof(plat->sdram_params) / sizeof(u32));
> + if (ret) {
> + printf("%s: Cannot read sifive,sdram-params %d\n",
> + __func__, ret);
> + return ret;
> + }
> +
> + sdram_copy_to_reg(&priv->ctl->denali_ctl[0],
> + ¶ms->pctl_regs.denali_ctl[0],
> + sizeof(struct fu540_ddrctl));
> +
> + /* phy reset */
> + for (i = DENALI_PHY_1152; i <= DENALI_PHY_1214; i++) {
> + physet = params->phy_regs.denali_phy[i];
> + priv->phy->denali_phy[i] = physet;
> + }
> +
> + for (i = 0; i < DENALI_PHY_1152; i++) {
> + physet = params->phy_regs.denali_phy[i];
> + priv->phy->denali_phy[i] = physet;
> + }
> +
> + /* Disable read interleave DENALI_CTL_120 */
> + setbits_le32(DENALI_CTL_120 + denali_ctl,
> + 1 << DISABLE_RD_INTERLEAVE_OFFSET);
> +
> + /* Disable optimal read/modify/write logic DENALI_CTL_21 */
> + clrbits_le32(DENALI_CTL_21 + denali_ctl, 1 << OPTIMAL_RMODW_EN_OFFSET);
> +
> + /* Enable write Leveling DENALI_CTL_170 */
> + setbits_le32(DENALI_CTL_170 + denali_ctl, (1 << WRLVL_EN_OFFSET)
> + | (1 << DFI_PHY_WRLELV_MODE_OFFSET));
> +
> + /* Enable read leveling DENALI_CTL_181 and DENALI_CTL_260 */
> + setbits_le32(DENALI_CTL_181 + denali_ctl,
> + 1 << DFI_PHY_RDLVL_MODE_OFFSET);
> + setbits_le32(DENALI_CTL_260 + denali_ctl, 1 << RDLVL_EN_OFFSET);
> +
> + /* Enable read leveling gate DENALI_CTL_260 and DENALI_CTL_182 */
> + setbits_le32(DENALI_CTL_260 + denali_ctl, 1 << RDLVL_GATE_EN_OFFSET);
> + setbits_le32(DENALI_CTL_182 + denali_ctl,
> + 1 << DFI_PHY_RDLVL_GATE_MODE_OFFSET);
> +
> + if (ddr_getdramclass(denali_ctl) == DRAM_CLASS_DDR4) {
> + /* Enable vref training DENALI_CTL_184 */
> + setbits_le32(DENALI_CTL_184 + denali_ctl, 1 << VREF_EN_OFFSET);
> + }
> +
> + /* Mask off leveling completion interrupt DENALI_CTL_136 */
> + setbits_le32(DENALI_CTL_136 + denali_ctl,
> + 1 << LEVELING_OPERATION_COMPLETED_OFFSET);
> +
> + /* Mask off MC init complete interrupt DENALI_CTL_136 */
> + setbits_le32(DENALI_CTL_136 + denali_ctl, 1 << MC_INIT_COMPLETE_OFFSET);
> +
> + /* Mask off out of range interrupts DENALI_CTL_136 */
> + setbits_le32(DENALI_CTL_136 + denali_ctl, (1 << OUT_OF_RANGE_OFFSET)
> + | (1 << MULTIPLE_OUT_OF_RANGE_OFFSET));
> +
> + /* set up range protection */
> + ddr_setuprangeprotection(denali_ctl, DDR_MEM_SIZE);
> +
> + /* Mask off port command error interrupt DENALI_CTL_136 */
> + setbits_le32(DENALI_CTL_136 + denali_ctl,
> + 1 << PORT_COMMAND_CHANNEL_ERROR_OFFSET);
> +
> + ddr_start(denali_ctl, priv->physical_filter_ctrl, ddr_end);
> +
> + ddr_phy_fixup(denali_phy);
> +
> + /* check size */
> + priv->info.size = get_ram_size((long *)priv->info.base,
> + DDR_MEM_SIZE);
> +
> + debug("%s : %lx\n", __func__, priv->info.size);
> +
> + /* check memory access for all memory */
> + if (priv->info.size != DDR_MEM_SIZE) {
> + printf("DDR invalid size : 0x%lx, expected 0x%lx\n",
> + priv->info.size, DDR_MEM_SIZE);
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +#endif
> +
> +static int fu540_ddr_probe(struct udevice *dev)
> +{
> + struct ddr_info *priv = dev_get_priv(dev);
> +
> +#if defined(CONFIG_TPL_BUILD) || \
> + (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
> + struct regmap *map;
> + int ret;
> + u32 clock = 0;
> +
> + debug("FU540 DDR probe\n");
> + priv->dev = dev;
> +
> + ret = regmap_init_mem(dev_ofnode(dev), &map);
> + if (ret)
> + return ret;
> +
> + ret = clk_get_by_index(dev, 0, &priv->ddr_clk);
> + if (ret) {
> + debug("clk get failed %d\n", ret);
> + return ret;
> + }
> +
> + ret = dev_read_u32(dev, "clock-frequency", &clock);
> + if (ret) {
> + debug("clock-frequency not found in dt %d\n", ret);
> + return ret;
> + } else {
> + ret = clk_set_rate(&priv->ddr_clk, clock);
> + if (ret < 0) {
> + debug("Could not set DDR clock\n");
> + return ret;
> + }
> + }
> +
> + ret = clk_enable(&priv->ddr_clk);
> + priv->ctl = regmap_get_range(map, 0);
> + priv->phy = regmap_get_range(map, 1);
> + priv->physical_filter_ctrl = regmap_get_range(map, 2);
> +
> + priv->info.base = CONFIG_SYS_SDRAM_BASE;
> +
> + priv->info.size = 0;
> + return fu540_ddr_setup(dev);
> +#else
> + priv->info.base = CONFIG_SYS_SDRAM_BASE;
> + priv->info.size = DDR_MEM_SIZE;
> +#endif
> + return 0;
> +}
> +
> +static int fu540_ddr_get_info(struct udevice *dev, struct ram_info *info)
> +{
> + struct ddr_info *priv = dev_get_priv(dev);
> +
> + *info = priv->info;
> +
> + return 0;
> +}
> +
> +static struct ram_ops fu540_ddr_ops = {
> + .get_info = fu540_ddr_get_info,
> +};
> +
> +static const struct udevice_id fu540_ddr_ids[] = {
> + { .compatible = "sifive,fu540-c000-ddr" },
> + { }
> +};
> +
> +U_BOOT_DRIVER(fu540_ddr) = {
> + .name = "fu540_ddr",
> + .id = UCLASS_RAM,
> + .of_match = fu540_ddr_ids,
> + .ops = &fu540_ddr_ops,
> + .probe = fu540_ddr_probe,
> + .priv_auto_alloc_size = sizeof(struct ddr_info),
> +#if defined(CONFIG_TPL_BUILD) || \
> + (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
> + .platdata_auto_alloc_size = sizeof(struct sifive_dmc_plat),
> +#endif
> +};
>
Best regards
--
Giulio Benetti
Benetti Engineering sas
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH v8 06/21] sifive: fu540: add ddr driver
2020-05-09 19:47 ` Giulio Benetti
@ 2020-05-10 6:18 ` Pragnesh Patel
2020-05-10 6:35 ` Pragnesh Patel
1 sibling, 0 replies; 31+ messages in thread
From: Pragnesh Patel @ 2020-05-10 6:18 UTC (permalink / raw)
To: u-boot
Hi Giulio,
>-----Original Message-----
>From: Giulio Benetti <giulio.benetti@benettiengineering.com>
>Sent: 10 May 2020 01:18
>To: Pragnesh Patel <pragnesh.patel@sifive.com>; u-boot at lists.denx.de
>Cc: atish.patra at wdc.com; palmerdabbelt at google.com;
>bmeng.cn at gmail.com; Paul Walmsley <paul.walmsley@sifive.com>;
>jagan at amarulasolutions.com; Troy Benjegerdes
><troy.benjegerdes@sifive.com>; anup.patel at wdc.com; Sagar Kadam
><sagar.kadam@sifive.com>; rick at andestech.com; Palmer Dabbelt
><palmer@sifive.com>; Kever Yang <kever.yang@rock-chips.com>; Lokesh
>Vutla <lokeshvutla@ti.com>; YouMin Chen <cym@rock-chips.com>; Kevin
>Scholz <k-scholz@ti.com>
>Subject: Re: [PATCH v8 06/21] sifive: fu540: add ddr driver
>
>[External Email] Do not click links or attachments unless you recognize the
>sender and know the content is safe
>
>Hi Pragnesh,
>
>On 5/9/20 4:30 PM, Pragnesh Patel wrote:
>> Add driver for fu540 to support ddr initialization in SPL.
>> This driver is based on FSBL
>> (https://github.com/sifive/freedom-u540-c000-bootloader.git)
>>
>> Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
>> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
>> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
>> Tested-by: Bin Meng <bmeng.cn@gmail.com>
>> ---
>> board/sifive/fu540/Kconfig | 2 +
>> drivers/ram/Kconfig | 1 +
>> drivers/ram/Makefile | 2 +
>> drivers/ram/sifive/Kconfig | 13 +
>> drivers/ram/sifive/Makefile | 6 +
>> drivers/ram/sifive/sdram_fu540.c | 416
>+++++++++++++++++++++++++++++++
>> 6 files changed, 440 insertions(+)
>> create mode 100644 drivers/ram/sifive/Kconfig
>> create mode 100644 drivers/ram/sifive/Makefile
>> create mode 100644 drivers/ram/sifive/sdram_fu540.c
>>
>> diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig
>> index 4330ac4491..d41c305227 100644
>> --- a/board/sifive/fu540/Kconfig
>> +++ b/board/sifive/fu540/Kconfig
>> @@ -19,6 +19,8 @@ config SYS_TEXT_BASE
>> config BOARD_SPECIFIC_OPTIONS # dummy
>> def_bool y
>> select GENERIC_RISCV
>> + select RAM
>> + select SPL_RAM if SPL
>> imply CMD_DHCP
>> imply CMD_EXT2
>> imply CMD_EXT4
>> diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig index
>> 56fea7c94c..66074d1feb 100644
>> --- a/drivers/ram/Kconfig
>> +++ b/drivers/ram/Kconfig
>> @@ -75,3 +75,4 @@ config IMXRT_SDRAM
>>
>> source "drivers/ram/rockchip/Kconfig"
>> source "drivers/ram/stm32mp1/Kconfig"
>> +source "drivers/ram/sifive/Kconfig"
>> diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile index
>> 5c897410c6..769c9d6218 100644
>> --- a/drivers/ram/Makefile
>> +++ b/drivers/ram/Makefile
>> @@ -17,3 +17,5 @@ obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
>> obj-$(CONFIG_K3_J721E_DDRSS) += k3-j721e/
>>
>> obj-$(CONFIG_IMXRT_SDRAM) += imxrt_sdram.o
>> +
>> +obj-$(CONFIG_RAM_SIFIVE) += sifive/
>> diff --git a/drivers/ram/sifive/Kconfig b/drivers/ram/sifive/Kconfig
>> new file mode 100644 index 0000000000..6aca22ab2a
>> --- /dev/null
>> +++ b/drivers/ram/sifive/Kconfig
>> @@ -0,0 +1,13 @@
>> +config RAM_SIFIVE
>> + bool "Ram drivers support for SiFive SoCs"
>> + depends on RAM && RISCV
>> + default y
>> + help
>> + This enables support for ram drivers of SiFive SoCs.
>> +
>> +config SIFIVE_FU540_DDR
>> + bool "SiFive FU540 DDR driver"
>> + depends on RAM_SIFIVE
>> + default y if TARGET_SIFIVE_FU540
>> + help
>> + This enables DDR support for the platforms based on SiFive FU540 SoC.
>> diff --git a/drivers/ram/sifive/Makefile b/drivers/ram/sifive/Makefile
>> new file mode 100644 index 0000000000..0187805199
>> --- /dev/null
>> +++ b/drivers/ram/sifive/Makefile
>> @@ -0,0 +1,6 @@
>> +# SPDX-License-Identifier: GPL-2.0+
>> +#
>> +# Copyright (c) 2020 SiFive, Inc
>> +#
>> +
>> +obj-$(CONFIG_SIFIVE_FU540_DDR) += sdram_fu540.o
>
>if this is a ddr-only driver I would change the name to:
>fu540_ddr.o (keeping fu540 as prefix like the others).
Will update in v9.
>
>> diff --git a/drivers/ram/sifive/sdram_fu540.c
>> b/drivers/ram/sifive/sdram_fu540.c
>> new file mode 100644
>> index 0000000000..419359ff3b
>> --- /dev/null
>> +++ b/drivers/ram/sifive/sdram_fu540.c
>> @@ -0,0 +1,416 @@
>> +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
>> +/*
>> + * (C) Copyright 2020 SiFive, Inc.
>> + *
>> + * Authors:
>> + * Pragnesh Patel <pragnesh.patel@sifive.com>
>> + */
>> +
>> +#include <common.h>
>> +#include <dm.h>
>> +#include <init.h>
>> +#include <ram.h>
>> +#include <regmap.h>
>> +#include <syscon.h>
>> +#include <asm/io.h>
>> +#include <clk.h>
>> +#include <wait_bit.h>
>> +
>> +#define DENALI_CTL_0 0
>> +#define DENALI_CTL_21 21
>> +#define DENALI_CTL_120 120
>> +#define DENALI_CTL_132 132
>> +#define DENALI_CTL_136 136
>> +#define DENALI_CTL_170 170
>> +#define DENALI_CTL_181 181
>> +#define DENALI_CTL_182 182
>> +#define DENALI_CTL_184 184
>> +#define DENALI_CTL_208 208
>> +#define DENALI_CTL_209 209
>> +#define DENALI_CTL_210 210
>> +#define DENALI_CTL_212 212
>> +#define DENALI_CTL_214 214
>> +#define DENALI_CTL_216 216
>> +#define DENALI_CTL_224 224
>> +#define DENALI_CTL_225 225
>> +#define DENALI_CTL_260 260
>> +
>> +#define DENALI_PHY_1152 1152
>> +#define DENALI_PHY_1214 1214
>> +
>> +#define PAYLOAD_DEST 0x80000000
>> +#define DDR_MEM_SIZE (8UL * 1024UL * 1024UL * 1024UL)
>> +
>> +#define DRAM_CLASS_OFFSET 8
>> +#define DRAM_CLASS_DDR4 0xA
>> +#define OPTIMAL_RMODW_EN_OFFSET 0
>> +#define DISABLE_RD_INTERLEAVE_OFFSET 16
>> +#define OUT_OF_RANGE_OFFSET 1
>> +#define MULTIPLE_OUT_OF_RANGE_OFFSET 2
>> +#define PORT_COMMAND_CHANNEL_ERROR_OFFSET 7
>> +#define MC_INIT_COMPLETE_OFFSET 8
>> +#define LEVELING_OPERATION_COMPLETED_OFFSET 22
>> +#define DFI_PHY_WRLELV_MODE_OFFSET 24
>> +#define DFI_PHY_RDLVL_MODE_OFFSET 24
>> +#define DFI_PHY_RDLVL_GATE_MODE_OFFSET 0
>> +#define VREF_EN_OFFSET 24
>> +#define PORT_ADDR_PROTECTION_EN_OFFSET 0
>> +#define AXI0_ADDRESS_RANGE_ENABLE 8
>> +#define AXI0_RANGE_PROT_BITS_0_OFFSET 24
>> +#define RDLVL_EN_OFFSET 16
>> +#define RDLVL_GATE_EN_OFFSET 24
>> +#define WRLVL_EN_OFFSET 0
>> +
>> +#define PHY_RX_CAL_DQ0_0_OFFSET 0
>> +#define PHY_RX_CAL_DQ1_0_OFFSET 16
>> +
>> +struct fu540_ddrctl {
>> + volatile u32 denali_ctl[265];
>> +};
>> +
>> +struct fu540_ddrphy {
>> + volatile u32 denali_phy[1215];
>> +};
>> +
>> +/**
>> + * struct ddr_info
>> + *
>> + * @dev : pointer for the device
>> + * @info : UCLASS RAM information
>> + * @ctl : DDR controller base address
>> + * @phy : DDR PHY base address
>> + * @ctrl : DDR control base address
>> + * @physical_filter_ctrl : DDR physical filter control base address
>> + */
>> +struct ddr_info {
>
>this should be 'struct fu540_ddr_info'
Will update in v9.
>
>> + struct udevice *dev;
>> + struct ram_info info;
>> + struct fu540_ddrctl *ctl;
>> + struct fu540_ddrphy *phy;
>> + struct clk ddr_clk;
>> + u32 *physical_filter_ctrl;
>> +};
>> +
>> +#if defined(CONFIG_TPL_BUILD) || \
>> + (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
>> +
>> +struct fu540_sdram_params {
>
>this should be fu540_ddr_params
Will update in v9.
>
>> + struct fu540_ddrctl pctl_regs;
>> + struct fu540_ddrphy phy_regs;
>> +};
>> +
>> +struct sifive_dmc_plat {
>> +#if CONFIG_IS_ENABLED(OF_PLATDATA)
>> + struct dtd_sifive_fu540_dmc dtplat; #else
>> + struct fu540_sdram_params sdram_params; #endif };
>> +
>> +/*
>> + * TODO : It can be possible to use common sdram_copy_to_reg() API
>> + * n: Unit bytes
>> + */
>> +static void sdram_copy_to_reg(volatile u32 *dest,
>> + volatile u32 *src, u32 n)
>
>if you mean to use local function then think about changing its name to:
>fu540_ddr_sdram_copy_to_reg(...)
There are other RAM drivers who also used the same function sdram_copy_to_reg(), so the plan
is to move sdram_copy_to_reg() to some common code area and all RAM drivers will use that.
It's better to use the same name sdram_copy_to_reg(), so that in future we can replace all at a time.
Any suggestions are welcome.
>
>> +{
>> + int i;
>> +
>> + for (i = 0; i < n / sizeof(u32); i++) {
>> + writel(*src, dest);
>> + src++;
>> + dest++;
>> + }
>> +}
>> +
>> +static void ddr_setuprangeprotection(volatile u32 *ctl, u64 end_addr)
>
>this should be 'fu540_ddr_setup_range_protection(...)'
Will update in v9.
>
>> +{
>> + u32 end_addr_16kblocks = ((end_addr >> 14) & 0x7FFFFF) - 1;
>> +
>> + writel(0x0, DENALI_CTL_209 + ctl);
>> + writel(end_addr_16kblocks, DENALI_CTL_210 + ctl);
>> + writel(0x0, DENALI_CTL_212 + ctl);
>> + writel(0x0, DENALI_CTL_214 + ctl);
>> + writel(0x0, DENALI_CTL_216 + ctl);
>> + setbits_le32(DENALI_CTL_224 + ctl,
>> + 0x3 << AXI0_RANGE_PROT_BITS_0_OFFSET);
>> + writel(0xFFFFFFFF, DENALI_CTL_225 + ctl);
>> + setbits_le32(DENALI_CTL_208 + ctl, 0x1 <<
>AXI0_ADDRESS_RANGE_ENABLE);
>> + setbits_le32(DENALI_CTL_208 + ctl,
>> + 0x1 << PORT_ADDR_PROTECTION_EN_OFFSET); }
>> +
>> +static void ddr_start(volatile u32 *ctl, u32 *physical_filter_ctrl,
>> +u64 ddr_end)
>
>fu540_ddr_start(...)
Will update in v9.
>
>> +{
>> + volatile u64 *filterreg = (volatile u64 *)physical_filter_ctrl;
>> +
>> + setbits_le32(DENALI_CTL_0 + ctl, 0x1);
>> +
>> + wait_for_bit_le32((void *)ctl + DENALI_CTL_132,
>> + BIT(MC_INIT_COMPLETE_OFFSET), false, 100,
>> + false);
>> +
>> + /* Disable the BusBlocker in front of the controller AXI slave ports */
>> + filterreg[0] = 0x0f00000000000000UL | (ddr_end >> 2); }
>> +
>> +static void check_errata(u32 regbase, u32 updownreg)
>
>fu540_ddr_check_errata(...)
Will update in v9.
>
>> +{
>> + u64 fails = 0;
>> + u32 dq = 0;
>> + u32 down, up;
>> + u8 failc0, failc1;
>> + u32 phy_rx_cal_dqn_0_offset;
>> +
>> + for (u32 bit = 0; bit < 2; bit++) {
>> + if (bit == 0) {
>> + phy_rx_cal_dqn_0_offset =
>> + PHY_RX_CAL_DQ0_0_OFFSET;
>> + } else {
>> + phy_rx_cal_dqn_0_offset =
>> + PHY_RX_CAL_DQ1_0_OFFSET;
>> + }
>> +
>> + down = (updownreg >>
>> + phy_rx_cal_dqn_0_offset) & 0x3F;
>> + up = (updownreg >>
>> + (phy_rx_cal_dqn_0_offset + 6)) &
>> + 0x3F;
>> +
>> + failc0 = ((down == 0) && (up == 0x3F));
>> + failc1 = ((up == 0) && (down == 0x3F));
>> +
>> + /* print error message on failure */
>> + if (failc0 || failc1) {
>> + if (fails == 0)
>> + printf("DDR error in fixing up\n");
>> +
>> + fails |= (1 << dq);
>> +
>> + char slicelsc = '0';
>> + char slicemsc = '0';
>> +
>> + slicelsc += (dq % 10);
>> + slicemsc += (dq / 10);
>> + printf("S ");
>> + printf("%c", slicemsc);
>> + printf("%c", slicelsc);
>> +
>> + if (failc0)
>> + printf("U");
>> + else
>> + printf("D");
>> +
>> + printf("\n");
>> + }
>> + dq++;
>> + }
>> +}
>> +
>> +static u64 ddr_phy_fixup(volatile u32 *ddrphyreg)
>
>fu540_ddr_fixup(...)
Will update in v9.
>
>> +{
>> + u32 slicebase = 0;
>> +
>> + /* check errata condition */
>> + for (u32 slice = 0; slice < 8; slice++) {
>> + u32 regbase = slicebase + 34;
>> +
>> + for (u32 reg = 0; reg < 4; reg++) {
>> + u32 updownreg = readl(regbase + reg +
>> + ddrphyreg);
>> +
>> + check_errata(regbase, updownreg);
>> + }
>> + slicebase += 128;
>> + }
>> +
>> + return(0);
>> +}
>> +
>> +static u32 ddr_getdramclass(volatile u32 *ctl)
>
>fu540_ddr_get_dram_class(...)
Will update in v9.
>
>> +{
>> + u32 reg = readl(DENALI_CTL_0 + ctl);
>> +
>> + return ((reg >> DRAM_CLASS_OFFSET) & 0xF); }
>> +
>> +static int fu540_ddr_setup(struct udevice *dev) {
>> + struct ddr_info *priv = dev_get_priv(dev);
>> + struct sifive_dmc_plat *plat = dev_get_platdata(dev);
>> + struct fu540_sdram_params *params = &plat->sdram_params;
>> + int ret, i;
>> + u32 physet;
>> + const u64 ddr_size = DDR_MEM_SIZE;
>> + const u64 ddr_end = PAYLOAD_DEST + ddr_size;
>> + volatile u32 *denali_ctl = &priv->ctl->denali_ctl[0];
>> + volatile u32 *denali_phy = &priv->phy->denali_phy[0];
>
>would this 2 last be ok with:
>volatile u32 *denali_ctl = priv->ctl->denali_ctl; volatile u32 *denali_phy =
>priv->phy->denali_phy; ?
>
>an maybe leaving shorter declarations as last ones i.e.:
> struct ddr_info *priv = dev_get_priv(dev);
> struct sifive_dmc_plat *plat = dev_get_platdata(dev);
> struct fu540_sdram_params *params = &plat->sdram_params;
> volatile u32 *denali_ctl = &priv->ctl->denali_ctl[0];
> volatile u32 *denali_phy = &priv->phy->denali_phy[0];
> const u64 ddr_size = DDR_MEM_SIZE;
> const u64 ddr_end = PAYLOAD_DEST + ddr_size;
> int ret, i;
> u32 physet;
>
>> +
>> + ret = dev_read_u32_array(dev, "sifive,sdram-params",
>> + (u32 *)&plat->sdram_params,
>> + sizeof(plat->sdram_params) / sizeof(u32));
>> + if (ret) {
>> + printf("%s: Cannot read sifive,sdram-params %d\n",
>> + __func__, ret);
>> + return ret;
>> + }
>> +
>> + sdram_copy_to_reg(&priv->ctl->denali_ctl[0],
>> + ¶ms->pctl_regs.denali_ctl[0],
>> + sizeof(struct fu540_ddrctl));
>> +
>> + /* phy reset */
>> + for (i = DENALI_PHY_1152; i <= DENALI_PHY_1214; i++) {
>> + physet = params->phy_regs.denali_phy[i];
>> + priv->phy->denali_phy[i] = physet;
>> + }
>> +
>> + for (i = 0; i < DENALI_PHY_1152; i++) {
>> + physet = params->phy_regs.denali_phy[i];
>> + priv->phy->denali_phy[i] = physet;
>> + }
>> +
>> + /* Disable read interleave DENALI_CTL_120 */
>> + setbits_le32(DENALI_CTL_120 + denali_ctl,
>> + 1 << DISABLE_RD_INTERLEAVE_OFFSET);
>> +
>> + /* Disable optimal read/modify/write logic DENALI_CTL_21 */
>> + clrbits_le32(DENALI_CTL_21 + denali_ctl, 1 <<
>> + OPTIMAL_RMODW_EN_OFFSET);
>> +
>> + /* Enable write Leveling DENALI_CTL_170 */
>> + setbits_le32(DENALI_CTL_170 + denali_ctl, (1 << WRLVL_EN_OFFSET)
>> + | (1 << DFI_PHY_WRLELV_MODE_OFFSET));
>> +
>> + /* Enable read leveling DENALI_CTL_181 and DENALI_CTL_260 */
>> + setbits_le32(DENALI_CTL_181 + denali_ctl,
>> + 1 << DFI_PHY_RDLVL_MODE_OFFSET);
>> + setbits_le32(DENALI_CTL_260 + denali_ctl, 1 << RDLVL_EN_OFFSET);
>> +
>> + /* Enable read leveling gate DENALI_CTL_260 and DENALI_CTL_182 */
>> + setbits_le32(DENALI_CTL_260 + denali_ctl, 1 <<
>RDLVL_GATE_EN_OFFSET);
>> + setbits_le32(DENALI_CTL_182 + denali_ctl,
>> + 1 << DFI_PHY_RDLVL_GATE_MODE_OFFSET);
>> +
>> + if (ddr_getdramclass(denali_ctl) == DRAM_CLASS_DDR4) {
>> + /* Enable vref training DENALI_CTL_184 */
>> + setbits_le32(DENALI_CTL_184 + denali_ctl, 1 << VREF_EN_OFFSET);
>> + }
>> +
>> + /* Mask off leveling completion interrupt DENALI_CTL_136 */
>> + setbits_le32(DENALI_CTL_136 + denali_ctl,
>> + 1 << LEVELING_OPERATION_COMPLETED_OFFSET);
>> +
>> + /* Mask off MC init complete interrupt DENALI_CTL_136 */
>> + setbits_le32(DENALI_CTL_136 + denali_ctl, 1 <<
>> + MC_INIT_COMPLETE_OFFSET);
>> +
>> + /* Mask off out of range interrupts DENALI_CTL_136 */
>> + setbits_le32(DENALI_CTL_136 + denali_ctl, (1 <<
>OUT_OF_RANGE_OFFSET)
>> + | (1 << MULTIPLE_OUT_OF_RANGE_OFFSET));
>> +
>> + /* set up range protection */
>> + ddr_setuprangeprotection(denali_ctl, DDR_MEM_SIZE);
>> +
>> + /* Mask off port command error interrupt DENALI_CTL_136 */
>> + setbits_le32(DENALI_CTL_136 + denali_ctl,
>> + 1 << PORT_COMMAND_CHANNEL_ERROR_OFFSET);
>> +
>> + ddr_start(denali_ctl, priv->physical_filter_ctrl, ddr_end);
>> +
>> + ddr_phy_fixup(denali_phy);
>> +
>> + /* check size */
>> + priv->info.size = get_ram_size((long *)priv->info.base,
>> + DDR_MEM_SIZE);
>> +
>> + debug("%s : %lx\n", __func__, priv->info.size);
>> +
>> + /* check memory access for all memory */
>> + if (priv->info.size != DDR_MEM_SIZE) {
>> + printf("DDR invalid size : 0x%lx, expected 0x%lx\n",
>> + priv->info.size, DDR_MEM_SIZE);
>> + return -EINVAL;
>> + }
>> +
>> + return 0;
>> +}
>> +#endif
>> +
>> +static int fu540_ddr_probe(struct udevice *dev) {
>> + struct ddr_info *priv = dev_get_priv(dev);
>> +
>> +#if defined(CONFIG_TPL_BUILD) || \
>> + (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
>> + struct regmap *map;
>> + int ret;
>> + u32 clock = 0;
>> +
>> + debug("FU540 DDR probe\n");
>> + priv->dev = dev;
>> +
>> + ret = regmap_init_mem(dev_ofnode(dev), &map);
>> + if (ret)
>> + return ret;
>> +
>> + ret = clk_get_by_index(dev, 0, &priv->ddr_clk);
>> + if (ret) {
>> + debug("clk get failed %d\n", ret);
>> + return ret;
>> + }
>> +
>> + ret = dev_read_u32(dev, "clock-frequency", &clock);
>> + if (ret) {
>> + debug("clock-frequency not found in dt %d\n", ret);
>> + return ret;
>> + } else {
>> + ret = clk_set_rate(&priv->ddr_clk, clock);
>> + if (ret < 0) {
>> + debug("Could not set DDR clock\n");
>> + return ret;
>> + }
>> + }
>> +
>> + ret = clk_enable(&priv->ddr_clk);
>> + priv->ctl = regmap_get_range(map, 0);
>> + priv->phy = regmap_get_range(map, 1);
>> + priv->physical_filter_ctrl = regmap_get_range(map, 2);
>> +
>> + priv->info.base = CONFIG_SYS_SDRAM_BASE;
>> +
>> + priv->info.size = 0;
>> + return fu540_ddr_setup(dev);
>> +#else
>> + priv->info.base = CONFIG_SYS_SDRAM_BASE;
>> + priv->info.size = DDR_MEM_SIZE;
>> +#endif
>> + return 0;
>> +}
>> +
>> +static int fu540_ddr_get_info(struct udevice *dev, struct ram_info
>> +*info) {
>> + struct ddr_info *priv = dev_get_priv(dev);
>> +
>> + *info = priv->info;
>> +
>> + return 0;
>> +}
>> +
>> +static struct ram_ops fu540_ddr_ops = {
>> + .get_info = fu540_ddr_get_info,
>> +};
>> +
>> +static const struct udevice_id fu540_ddr_ids[] = {
>> + { .compatible = "sifive,fu540-c000-ddr" },
>> + { }
>> +};
>> +
>> +U_BOOT_DRIVER(fu540_ddr) = {
>> + .name = "fu540_ddr",
>> + .id = UCLASS_RAM,
>> + .of_match = fu540_ddr_ids,
>> + .ops = &fu540_ddr_ops,
>> + .probe = fu540_ddr_probe,
>> + .priv_auto_alloc_size = sizeof(struct ddr_info), #if
>> +defined(CONFIG_TPL_BUILD) || \
>> + (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
>> + .platdata_auto_alloc_size = sizeof(struct sifive_dmc_plat),
>> +#endif };
>>
>
>Best regards
>--
>Giulio Benetti
>Benetti Engineering sas
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH v8 06/21] sifive: fu540: add ddr driver
2020-05-09 19:47 ` Giulio Benetti
2020-05-10 6:18 ` Pragnesh Patel
@ 2020-05-10 6:35 ` Pragnesh Patel
1 sibling, 0 replies; 31+ messages in thread
From: Pragnesh Patel @ 2020-05-10 6:35 UTC (permalink / raw)
To: u-boot
Hi Giulio,
>-----Original Message-----
>From: Giulio Benetti <giulio.benetti@benettiengineering.com>
>Sent: 10 May 2020 01:18
>To: Pragnesh Patel <pragnesh.patel@sifive.com>; u-boot at lists.denx.de
>Cc: atish.patra at wdc.com; palmerdabbelt at google.com;
>bmeng.cn at gmail.com; Paul Walmsley <paul.walmsley@sifive.com>;
>jagan at amarulasolutions.com; Troy Benjegerdes
><troy.benjegerdes@sifive.com>; anup.patel at wdc.com; Sagar Kadam
><sagar.kadam@sifive.com>; rick at andestech.com; Palmer Dabbelt
><palmer@sifive.com>; Kever Yang <kever.yang@rock-chips.com>; Lokesh
>Vutla <lokeshvutla@ti.com>; YouMin Chen <cym@rock-chips.com>; Kevin
>Scholz <k-scholz@ti.com>
>Subject: Re: [PATCH v8 06/21] sifive: fu540: add ddr driver
>
>[External Email] Do not click links or attachments unless you recognize the
>sender and know the content is safe
>
>Hi Pragnesh,
>
>On 5/9/20 4:30 PM, Pragnesh Patel wrote:
>> Add driver for fu540 to support ddr initialization in SPL.
>> This driver is based on FSBL
>> (https://github.com/sifive/freedom-u540-c000-bootloader.git)
>>
>> Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
>> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
>> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
>> Tested-by: Bin Meng <bmeng.cn@gmail.com>
>> ---
>> board/sifive/fu540/Kconfig | 2 +
>> drivers/ram/Kconfig | 1 +
>> drivers/ram/Makefile | 2 +
>> drivers/ram/sifive/Kconfig | 13 +
>> drivers/ram/sifive/Makefile | 6 +
>> drivers/ram/sifive/sdram_fu540.c | 416
>+++++++++++++++++++++++++++++++
>> 6 files changed, 440 insertions(+)
>> create mode 100644 drivers/ram/sifive/Kconfig
>> create mode 100644 drivers/ram/sifive/Makefile
>> create mode 100644 drivers/ram/sifive/sdram_fu540.c
>>
>> diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig
>> index 4330ac4491..d41c305227 100644
>> --- a/board/sifive/fu540/Kconfig
>> +++ b/board/sifive/fu540/Kconfig
>> @@ -19,6 +19,8 @@ config SYS_TEXT_BASE
>> config BOARD_SPECIFIC_OPTIONS # dummy
>> def_bool y
>> select GENERIC_RISCV
>> + select RAM
>> + select SPL_RAM if SPL
>> imply CMD_DHCP
>> imply CMD_EXT2
>> imply CMD_EXT4
>> diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig index
>> 56fea7c94c..66074d1feb 100644
>> --- a/drivers/ram/Kconfig
>> +++ b/drivers/ram/Kconfig
>> @@ -75,3 +75,4 @@ config IMXRT_SDRAM
>>
>> source "drivers/ram/rockchip/Kconfig"
>> source "drivers/ram/stm32mp1/Kconfig"
>> +source "drivers/ram/sifive/Kconfig"
>> diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile index
>> 5c897410c6..769c9d6218 100644
>> --- a/drivers/ram/Makefile
>> +++ b/drivers/ram/Makefile
>> @@ -17,3 +17,5 @@ obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
>> obj-$(CONFIG_K3_J721E_DDRSS) += k3-j721e/
>>
>> obj-$(CONFIG_IMXRT_SDRAM) += imxrt_sdram.o
>> +
>> +obj-$(CONFIG_RAM_SIFIVE) += sifive/
>> diff --git a/drivers/ram/sifive/Kconfig b/drivers/ram/sifive/Kconfig
>> new file mode 100644 index 0000000000..6aca22ab2a
>> --- /dev/null
>> +++ b/drivers/ram/sifive/Kconfig
>> @@ -0,0 +1,13 @@
>> +config RAM_SIFIVE
>> + bool "Ram drivers support for SiFive SoCs"
>> + depends on RAM && RISCV
>> + default y
>> + help
>> + This enables support for ram drivers of SiFive SoCs.
>> +
>> +config SIFIVE_FU540_DDR
>> + bool "SiFive FU540 DDR driver"
>> + depends on RAM_SIFIVE
>> + default y if TARGET_SIFIVE_FU540
>> + help
>> + This enables DDR support for the platforms based on SiFive FU540 SoC.
>> diff --git a/drivers/ram/sifive/Makefile b/drivers/ram/sifive/Makefile
>> new file mode 100644 index 0000000000..0187805199
>> --- /dev/null
>> +++ b/drivers/ram/sifive/Makefile
>> @@ -0,0 +1,6 @@
>> +# SPDX-License-Identifier: GPL-2.0+
>> +#
>> +# Copyright (c) 2020 SiFive, Inc
>> +#
>> +
>> +obj-$(CONFIG_SIFIVE_FU540_DDR) += sdram_fu540.o
>
>if this is a ddr-only driver I would change the name to:
>fu540_ddr.o (keeping fu540 as prefix like the others).
>
>> diff --git a/drivers/ram/sifive/sdram_fu540.c
>> b/drivers/ram/sifive/sdram_fu540.c
>> new file mode 100644
>> index 0000000000..419359ff3b
>> --- /dev/null
>> +++ b/drivers/ram/sifive/sdram_fu540.c
>> @@ -0,0 +1,416 @@
>> +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
>> +/*
>> + * (C) Copyright 2020 SiFive, Inc.
>> + *
>> + * Authors:
>> + * Pragnesh Patel <pragnesh.patel@sifive.com>
>> + */
>> +
>> +#include <common.h>
>> +#include <dm.h>
>> +#include <init.h>
>> +#include <ram.h>
>> +#include <regmap.h>
>> +#include <syscon.h>
>> +#include <asm/io.h>
>> +#include <clk.h>
>> +#include <wait_bit.h>
>> +
>> +#define DENALI_CTL_0 0
>> +#define DENALI_CTL_21 21
>> +#define DENALI_CTL_120 120
>> +#define DENALI_CTL_132 132
>> +#define DENALI_CTL_136 136
>> +#define DENALI_CTL_170 170
>> +#define DENALI_CTL_181 181
>> +#define DENALI_CTL_182 182
>> +#define DENALI_CTL_184 184
>> +#define DENALI_CTL_208 208
>> +#define DENALI_CTL_209 209
>> +#define DENALI_CTL_210 210
>> +#define DENALI_CTL_212 212
>> +#define DENALI_CTL_214 214
>> +#define DENALI_CTL_216 216
>> +#define DENALI_CTL_224 224
>> +#define DENALI_CTL_225 225
>> +#define DENALI_CTL_260 260
>> +
>> +#define DENALI_PHY_1152 1152
>> +#define DENALI_PHY_1214 1214
>> +
>> +#define PAYLOAD_DEST 0x80000000
>> +#define DDR_MEM_SIZE (8UL * 1024UL * 1024UL * 1024UL)
>> +
>> +#define DRAM_CLASS_OFFSET 8
>> +#define DRAM_CLASS_DDR4 0xA
>> +#define OPTIMAL_RMODW_EN_OFFSET 0
>> +#define DISABLE_RD_INTERLEAVE_OFFSET 16
>> +#define OUT_OF_RANGE_OFFSET 1
>> +#define MULTIPLE_OUT_OF_RANGE_OFFSET 2
>> +#define PORT_COMMAND_CHANNEL_ERROR_OFFSET 7
>> +#define MC_INIT_COMPLETE_OFFSET 8
>> +#define LEVELING_OPERATION_COMPLETED_OFFSET 22
>> +#define DFI_PHY_WRLELV_MODE_OFFSET 24
>> +#define DFI_PHY_RDLVL_MODE_OFFSET 24
>> +#define DFI_PHY_RDLVL_GATE_MODE_OFFSET 0
>> +#define VREF_EN_OFFSET 24
>> +#define PORT_ADDR_PROTECTION_EN_OFFSET 0
>> +#define AXI0_ADDRESS_RANGE_ENABLE 8
>> +#define AXI0_RANGE_PROT_BITS_0_OFFSET 24
>> +#define RDLVL_EN_OFFSET 16
>> +#define RDLVL_GATE_EN_OFFSET 24
>> +#define WRLVL_EN_OFFSET 0
>> +
>> +#define PHY_RX_CAL_DQ0_0_OFFSET 0
>> +#define PHY_RX_CAL_DQ1_0_OFFSET 16
>> +
>> +struct fu540_ddrctl {
>> + volatile u32 denali_ctl[265];
>> +};
>> +
>> +struct fu540_ddrphy {
>> + volatile u32 denali_phy[1215];
>> +};
>> +
>> +/**
>> + * struct ddr_info
>> + *
>> + * @dev : pointer for the device
>> + * @info : UCLASS RAM information
>> + * @ctl : DDR controller base address
>> + * @phy : DDR PHY base address
>> + * @ctrl : DDR control base address
>> + * @physical_filter_ctrl : DDR physical filter control base address
>> + */
>> +struct ddr_info {
>
>this should be 'struct fu540_ddr_info'
>
>> + struct udevice *dev;
>> + struct ram_info info;
>> + struct fu540_ddrctl *ctl;
>> + struct fu540_ddrphy *phy;
>> + struct clk ddr_clk;
>> + u32 *physical_filter_ctrl;
>> +};
>> +
>> +#if defined(CONFIG_TPL_BUILD) || \
>> + (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
>> +
>> +struct fu540_sdram_params {
>
>this should be fu540_ddr_params
>
>> + struct fu540_ddrctl pctl_regs;
>> + struct fu540_ddrphy phy_regs;
>> +};
>> +
>> +struct sifive_dmc_plat {
>> +#if CONFIG_IS_ENABLED(OF_PLATDATA)
>> + struct dtd_sifive_fu540_dmc dtplat; #else
>> + struct fu540_sdram_params sdram_params; #endif };
>> +
>> +/*
>> + * TODO : It can be possible to use common sdram_copy_to_reg() API
>> + * n: Unit bytes
>> + */
>> +static void sdram_copy_to_reg(volatile u32 *dest,
>> + volatile u32 *src, u32 n)
>
>if you mean to use local function then think about changing its name to:
>fu540_ddr_sdram_copy_to_reg(...)
>
>> +{
>> + int i;
>> +
>> + for (i = 0; i < n / sizeof(u32); i++) {
>> + writel(*src, dest);
>> + src++;
>> + dest++;
>> + }
>> +}
>> +
>> +static void ddr_setuprangeprotection(volatile u32 *ctl, u64 end_addr)
>
>this should be 'fu540_ddr_setup_range_protection(...)'
>
>> +{
>> + u32 end_addr_16kblocks = ((end_addr >> 14) & 0x7FFFFF) - 1;
>> +
>> + writel(0x0, DENALI_CTL_209 + ctl);
>> + writel(end_addr_16kblocks, DENALI_CTL_210 + ctl);
>> + writel(0x0, DENALI_CTL_212 + ctl);
>> + writel(0x0, DENALI_CTL_214 + ctl);
>> + writel(0x0, DENALI_CTL_216 + ctl);
>> + setbits_le32(DENALI_CTL_224 + ctl,
>> + 0x3 << AXI0_RANGE_PROT_BITS_0_OFFSET);
>> + writel(0xFFFFFFFF, DENALI_CTL_225 + ctl);
>> + setbits_le32(DENALI_CTL_208 + ctl, 0x1 <<
>AXI0_ADDRESS_RANGE_ENABLE);
>> + setbits_le32(DENALI_CTL_208 + ctl,
>> + 0x1 << PORT_ADDR_PROTECTION_EN_OFFSET); }
>> +
>> +static void ddr_start(volatile u32 *ctl, u32 *physical_filter_ctrl,
>> +u64 ddr_end)
>
>fu540_ddr_start(...)
>
>> +{
>> + volatile u64 *filterreg = (volatile u64 *)physical_filter_ctrl;
>> +
>> + setbits_le32(DENALI_CTL_0 + ctl, 0x1);
>> +
>> + wait_for_bit_le32((void *)ctl + DENALI_CTL_132,
>> + BIT(MC_INIT_COMPLETE_OFFSET), false, 100,
>> + false);
>> +
>> + /* Disable the BusBlocker in front of the controller AXI slave ports */
>> + filterreg[0] = 0x0f00000000000000UL | (ddr_end >> 2); }
>> +
>> +static void check_errata(u32 regbase, u32 updownreg)
>
>fu540_ddr_check_errata(...)
>
>> +{
>> + u64 fails = 0;
>> + u32 dq = 0;
>> + u32 down, up;
>> + u8 failc0, failc1;
>> + u32 phy_rx_cal_dqn_0_offset;
>> +
>> + for (u32 bit = 0; bit < 2; bit++) {
>> + if (bit == 0) {
>> + phy_rx_cal_dqn_0_offset =
>> + PHY_RX_CAL_DQ0_0_OFFSET;
>> + } else {
>> + phy_rx_cal_dqn_0_offset =
>> + PHY_RX_CAL_DQ1_0_OFFSET;
>> + }
>> +
>> + down = (updownreg >>
>> + phy_rx_cal_dqn_0_offset) & 0x3F;
>> + up = (updownreg >>
>> + (phy_rx_cal_dqn_0_offset + 6)) &
>> + 0x3F;
>> +
>> + failc0 = ((down == 0) && (up == 0x3F));
>> + failc1 = ((up == 0) && (down == 0x3F));
>> +
>> + /* print error message on failure */
>> + if (failc0 || failc1) {
>> + if (fails == 0)
>> + printf("DDR error in fixing up\n");
>> +
>> + fails |= (1 << dq);
>> +
>> + char slicelsc = '0';
>> + char slicemsc = '0';
>> +
>> + slicelsc += (dq % 10);
>> + slicemsc += (dq / 10);
>> + printf("S ");
>> + printf("%c", slicemsc);
>> + printf("%c", slicelsc);
>> +
>> + if (failc0)
>> + printf("U");
>> + else
>> + printf("D");
>> +
>> + printf("\n");
>> + }
>> + dq++;
>> + }
>> +}
>> +
>> +static u64 ddr_phy_fixup(volatile u32 *ddrphyreg)
>
>fu540_ddr_fixup(...)
>
>> +{
>> + u32 slicebase = 0;
>> +
>> + /* check errata condition */
>> + for (u32 slice = 0; slice < 8; slice++) {
>> + u32 regbase = slicebase + 34;
>> +
>> + for (u32 reg = 0; reg < 4; reg++) {
>> + u32 updownreg = readl(regbase + reg +
>> + ddrphyreg);
>> +
>> + check_errata(regbase, updownreg);
>> + }
>> + slicebase += 128;
>> + }
>> +
>> + return(0);
>> +}
>> +
>> +static u32 ddr_getdramclass(volatile u32 *ctl)
>
>fu540_ddr_get_dram_class(...)
>
>> +{
>> + u32 reg = readl(DENALI_CTL_0 + ctl);
>> +
>> + return ((reg >> DRAM_CLASS_OFFSET) & 0xF); }
>> +
>> +static int fu540_ddr_setup(struct udevice *dev) {
>> + struct ddr_info *priv = dev_get_priv(dev);
>> + struct sifive_dmc_plat *plat = dev_get_platdata(dev);
>> + struct fu540_sdram_params *params = &plat->sdram_params;
>> + int ret, i;
>> + u32 physet;
>> + const u64 ddr_size = DDR_MEM_SIZE;
>> + const u64 ddr_end = PAYLOAD_DEST + ddr_size;
>> + volatile u32 *denali_ctl = &priv->ctl->denali_ctl[0];
>> + volatile u32 *denali_phy = &priv->phy->denali_phy[0];
>
>would this 2 last be ok with:
>volatile u32 *denali_ctl = priv->ctl->denali_ctl; volatile u32 *denali_phy =
>priv->phy->denali_phy; ?
>
>an maybe leaving shorter declarations as last ones i.e.:
> struct ddr_info *priv = dev_get_priv(dev);
> struct sifive_dmc_plat *plat = dev_get_platdata(dev);
> struct fu540_sdram_params *params = &plat->sdram_params;
> volatile u32 *denali_ctl = &priv->ctl->denali_ctl[0];
> volatile u32 *denali_phy = &priv->phy->denali_phy[0];
> const u64 ddr_size = DDR_MEM_SIZE;
> const u64 ddr_end = PAYLOAD_DEST + ddr_size;
> int ret, i;
> u32 physet;
Will update in v9.
>
>> +
>> + ret = dev_read_u32_array(dev, "sifive,sdram-params",
>> + (u32 *)&plat->sdram_params,
>> + sizeof(plat->sdram_params) / sizeof(u32));
>> + if (ret) {
>> + printf("%s: Cannot read sifive,sdram-params %d\n",
>> + __func__, ret);
>> + return ret;
>> + }
>> +
>> + sdram_copy_to_reg(&priv->ctl->denali_ctl[0],
>> + ¶ms->pctl_regs.denali_ctl[0],
>> + sizeof(struct fu540_ddrctl));
>> +
>> + /* phy reset */
>> + for (i = DENALI_PHY_1152; i <= DENALI_PHY_1214; i++) {
>> + physet = params->phy_regs.denali_phy[i];
>> + priv->phy->denali_phy[i] = physet;
>> + }
>> +
>> + for (i = 0; i < DENALI_PHY_1152; i++) {
>> + physet = params->phy_regs.denali_phy[i];
>> + priv->phy->denali_phy[i] = physet;
>> + }
>> +
>> + /* Disable read interleave DENALI_CTL_120 */
>> + setbits_le32(DENALI_CTL_120 + denali_ctl,
>> + 1 << DISABLE_RD_INTERLEAVE_OFFSET);
>> +
>> + /* Disable optimal read/modify/write logic DENALI_CTL_21 */
>> + clrbits_le32(DENALI_CTL_21 + denali_ctl, 1 <<
>> + OPTIMAL_RMODW_EN_OFFSET);
>> +
>> + /* Enable write Leveling DENALI_CTL_170 */
>> + setbits_le32(DENALI_CTL_170 + denali_ctl, (1 << WRLVL_EN_OFFSET)
>> + | (1 << DFI_PHY_WRLELV_MODE_OFFSET));
>> +
>> + /* Enable read leveling DENALI_CTL_181 and DENALI_CTL_260 */
>> + setbits_le32(DENALI_CTL_181 + denali_ctl,
>> + 1 << DFI_PHY_RDLVL_MODE_OFFSET);
>> + setbits_le32(DENALI_CTL_260 + denali_ctl, 1 << RDLVL_EN_OFFSET);
>> +
>> + /* Enable read leveling gate DENALI_CTL_260 and DENALI_CTL_182 */
>> + setbits_le32(DENALI_CTL_260 + denali_ctl, 1 <<
>RDLVL_GATE_EN_OFFSET);
>> + setbits_le32(DENALI_CTL_182 + denali_ctl,
>> + 1 << DFI_PHY_RDLVL_GATE_MODE_OFFSET);
>> +
>> + if (ddr_getdramclass(denali_ctl) == DRAM_CLASS_DDR4) {
>> + /* Enable vref training DENALI_CTL_184 */
>> + setbits_le32(DENALI_CTL_184 + denali_ctl, 1 << VREF_EN_OFFSET);
>> + }
>> +
>> + /* Mask off leveling completion interrupt DENALI_CTL_136 */
>> + setbits_le32(DENALI_CTL_136 + denali_ctl,
>> + 1 << LEVELING_OPERATION_COMPLETED_OFFSET);
>> +
>> + /* Mask off MC init complete interrupt DENALI_CTL_136 */
>> + setbits_le32(DENALI_CTL_136 + denali_ctl, 1 <<
>> + MC_INIT_COMPLETE_OFFSET);
>> +
>> + /* Mask off out of range interrupts DENALI_CTL_136 */
>> + setbits_le32(DENALI_CTL_136 + denali_ctl, (1 <<
>OUT_OF_RANGE_OFFSET)
>> + | (1 << MULTIPLE_OUT_OF_RANGE_OFFSET));
>> +
>> + /* set up range protection */
>> + ddr_setuprangeprotection(denali_ctl, DDR_MEM_SIZE);
>> +
>> + /* Mask off port command error interrupt DENALI_CTL_136 */
>> + setbits_le32(DENALI_CTL_136 + denali_ctl,
>> + 1 << PORT_COMMAND_CHANNEL_ERROR_OFFSET);
>> +
>> + ddr_start(denali_ctl, priv->physical_filter_ctrl, ddr_end);
>> +
>> + ddr_phy_fixup(denali_phy);
>> +
>> + /* check size */
>> + priv->info.size = get_ram_size((long *)priv->info.base,
>> + DDR_MEM_SIZE);
>> +
>> + debug("%s : %lx\n", __func__, priv->info.size);
>> +
>> + /* check memory access for all memory */
>> + if (priv->info.size != DDR_MEM_SIZE) {
>> + printf("DDR invalid size : 0x%lx, expected 0x%lx\n",
>> + priv->info.size, DDR_MEM_SIZE);
>> + return -EINVAL;
>> + }
>> +
>> + return 0;
>> +}
>> +#endif
>> +
>> +static int fu540_ddr_probe(struct udevice *dev) {
>> + struct ddr_info *priv = dev_get_priv(dev);
>> +
>> +#if defined(CONFIG_TPL_BUILD) || \
>> + (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
>> + struct regmap *map;
>> + int ret;
>> + u32 clock = 0;
>> +
>> + debug("FU540 DDR probe\n");
>> + priv->dev = dev;
>> +
>> + ret = regmap_init_mem(dev_ofnode(dev), &map);
>> + if (ret)
>> + return ret;
>> +
>> + ret = clk_get_by_index(dev, 0, &priv->ddr_clk);
>> + if (ret) {
>> + debug("clk get failed %d\n", ret);
>> + return ret;
>> + }
>> +
>> + ret = dev_read_u32(dev, "clock-frequency", &clock);
>> + if (ret) {
>> + debug("clock-frequency not found in dt %d\n", ret);
>> + return ret;
>> + } else {
>> + ret = clk_set_rate(&priv->ddr_clk, clock);
>> + if (ret < 0) {
>> + debug("Could not set DDR clock\n");
>> + return ret;
>> + }
>> + }
>> +
>> + ret = clk_enable(&priv->ddr_clk);
>> + priv->ctl = regmap_get_range(map, 0);
>> + priv->phy = regmap_get_range(map, 1);
>> + priv->physical_filter_ctrl = regmap_get_range(map, 2);
>> +
>> + priv->info.base = CONFIG_SYS_SDRAM_BASE;
>> +
>> + priv->info.size = 0;
>> + return fu540_ddr_setup(dev);
>> +#else
>> + priv->info.base = CONFIG_SYS_SDRAM_BASE;
>> + priv->info.size = DDR_MEM_SIZE;
>> +#endif
>> + return 0;
>> +}
>> +
>> +static int fu540_ddr_get_info(struct udevice *dev, struct ram_info
>> +*info) {
>> + struct ddr_info *priv = dev_get_priv(dev);
>> +
>> + *info = priv->info;
>> +
>> + return 0;
>> +}
>> +
>> +static struct ram_ops fu540_ddr_ops = {
>> + .get_info = fu540_ddr_get_info,
>> +};
>> +
>> +static const struct udevice_id fu540_ddr_ids[] = {
>> + { .compatible = "sifive,fu540-c000-ddr" },
>> + { }
>> +};
>> +
>> +U_BOOT_DRIVER(fu540_ddr) = {
>> + .name = "fu540_ddr",
>> + .id = UCLASS_RAM,
>> + .of_match = fu540_ddr_ids,
>> + .ops = &fu540_ddr_ops,
>> + .probe = fu540_ddr_probe,
>> + .priv_auto_alloc_size = sizeof(struct ddr_info), #if
>> +defined(CONFIG_TPL_BUILD) || \
>> + (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
>> + .platdata_auto_alloc_size = sizeof(struct sifive_dmc_plat),
>> +#endif };
>>
>
>Best regards
>--
>Giulio Benetti
>Benetti Engineering sas
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH v8 18/21] configs: fu540: Add config options for U-Boot SPL
2020-05-09 14:30 ` [PATCH v8 18/21] configs: fu540: Add config options for U-Boot SPL Pragnesh Patel
@ 2020-05-10 9:20 ` Jagan Teki
2020-05-11 5:59 ` Pragnesh Patel
0 siblings, 1 reply; 31+ messages in thread
From: Jagan Teki @ 2020-05-10 9:20 UTC (permalink / raw)
To: u-boot
On Sat, May 9, 2020 at 8:02 PM Pragnesh Patel <pragnesh.patel@sifive.com> wrote:
>
> With sifive_fu540_defconfig:
>
> User can use FSBL or u-boot-spl.bin anyone at a time.
>
> For FSBL,
> fsbl->fw_payload.bin (opensbi + U-Boot)
>
> For u-boot-spl.bin,
> u-boot-spl.bin->FIT image (opensbi + U-Boot + dtb)
s/U-Boot/U-Boot proper
>
> U-Boot SPL will be loaded by ZSBL from SD card (replace fsbl.bin with
> u-boot-spl.bin) and runs in L2 LIM in machine mode and then load FIT
> image u-boot.itb from SD card into RAM.
>
> U-Boot SPL expects u-boot.itb FIT image at the starting of SD card sector
> number (0x822) of GUID type "2E54B353-1271-4842-806F-E436D6AF6985"
>
> Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> ---
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH v8 19/21] sifive: dts: fu540: Enable L2 Cache in U-Boot
2020-05-09 14:30 ` [PATCH v8 19/21] sifive: dts: fu540: Enable L2 Cache in U-Boot Pragnesh Patel
@ 2020-05-10 15:14 ` Jagan Teki
2020-05-11 6:06 ` Pragnesh Patel
0 siblings, 1 reply; 31+ messages in thread
From: Jagan Teki @ 2020-05-10 15:14 UTC (permalink / raw)
To: u-boot
On Sat, May 9, 2020 at 8:02 PM Pragnesh Patel <pragnesh.patel@sifive.com> wrote:
>
> Add L2 cache node to enable cache ways from U-Boot
>
> Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
> arch/riscv/dts/fu540-c000-u-boot.dtsi | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi b/arch/riscv/dts/fu540-c000-u-boot.dtsi
> index fc91a7c987..42e43522ed 100644
> --- a/arch/riscv/dts/fu540-c000-u-boot.dtsi
> +++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi
> @@ -82,3 +82,7 @@
> &qspi2 {
> u-boot,dm-spl;
> };
> +
> +&l2cache {
> + status = "okay";
> +};
Squash with next commit.
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH v8 18/21] configs: fu540: Add config options for U-Boot SPL
2020-05-10 9:20 ` Jagan Teki
@ 2020-05-11 5:59 ` Pragnesh Patel
0 siblings, 0 replies; 31+ messages in thread
From: Pragnesh Patel @ 2020-05-11 5:59 UTC (permalink / raw)
To: u-boot
>-----Original Message-----
>From: Jagan Teki <jagan@amarulasolutions.com>
>Sent: 10 May 2020 14:50
>To: Pragnesh Patel <pragnesh.patel@sifive.com>
>Cc: U-Boot-Denx <u-boot@lists.denx.de>; Atish Patra
><atish.patra@wdc.com>; Palmer Dabbelt <palmerdabbelt@google.com>; Bin
>Meng <bmeng.cn@gmail.com>; Paul Walmsley <paul.walmsley@sifive.com>;
>Troy Benjegerdes <troy.benjegerdes@sifive.com>; Anup Patel
><anup.patel@wdc.com>; Sagar Kadam <sagar.kadam@sifive.com>; Rick Chen
><rick@andestech.com>; Palmer Dabbelt <palmer@sifive.com>; Joe
>Hershberger <joe.hershberger@ni.com>
>Subject: Re: [PATCH v8 18/21] configs: fu540: Add config options for U-Boot
>SPL
>
>[External Email] Do not click links or attachments unless you recognize the
>sender and know the content is safe
>
>On Sat, May 9, 2020 at 8:02 PM Pragnesh Patel <pragnesh.patel@sifive.com>
>wrote:
>>
>> With sifive_fu540_defconfig:
>>
>> User can use FSBL or u-boot-spl.bin anyone at a time.
>>
>> For FSBL,
>> fsbl->fw_payload.bin (opensbi + U-Boot)
>>
>> For u-boot-spl.bin,
>> u-boot-spl.bin->FIT image (opensbi + U-Boot + dtb)
>
>s/U-Boot/U-Boot proper
Will update in v9.
>
>>
>> U-Boot SPL will be loaded by ZSBL from SD card (replace fsbl.bin with
>> u-boot-spl.bin) and runs in L2 LIM in machine mode and then load FIT
>> image u-boot.itb from SD card into RAM.
>>
>> U-Boot SPL expects u-boot.itb FIT image at the starting of SD card
>> sector number (0x822) of GUID type "2E54B353-1271-4842-806F-
>E436D6AF6985"
>>
>> Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
>> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
>> ---
>
>Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH v8 19/21] sifive: dts: fu540: Enable L2 Cache in U-Boot
2020-05-10 15:14 ` Jagan Teki
@ 2020-05-11 6:06 ` Pragnesh Patel
0 siblings, 0 replies; 31+ messages in thread
From: Pragnesh Patel @ 2020-05-11 6:06 UTC (permalink / raw)
To: u-boot
>-----Original Message-----
>From: Jagan Teki <jagan@amarulasolutions.com>
>Sent: 10 May 2020 20:44
>To: Pragnesh Patel <pragnesh.patel@sifive.com>
>Cc: U-Boot-Denx <u-boot@lists.denx.de>; Atish Patra
><atish.patra@wdc.com>; Palmer Dabbelt <palmerdabbelt@google.com>; Bin
>Meng <bmeng.cn@gmail.com>; Paul Walmsley <paul.walmsley@sifive.com>;
>Troy Benjegerdes <troy.benjegerdes@sifive.com>; Anup Patel
><anup.patel@wdc.com>; Sagar Kadam <sagar.kadam@sifive.com>; Rick Chen
><rick@andestech.com>
>Subject: Re: [PATCH v8 19/21] sifive: dts: fu540: Enable L2 Cache in U-Boot
>
>[External Email] Do not click links or attachments unless you recognize the
>sender and know the content is safe
>
>On Sat, May 9, 2020 at 8:02 PM Pragnesh Patel <pragnesh.patel@sifive.com>
>wrote:
>>
>> Add L2 cache node to enable cache ways from U-Boot
>>
>> Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
>> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
>> ---
>> arch/riscv/dts/fu540-c000-u-boot.dtsi | 4 ++++
>> 1 file changed, 4 insertions(+)
>>
>> diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi b/arch/riscv/dts/fu540-
>c000-u-boot.dtsi
>> index fc91a7c987..42e43522ed 100644
>> --- a/arch/riscv/dts/fu540-c000-u-boot.dtsi
>> +++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi
>> @@ -82,3 +82,7 @@
>> &qspi2 {
>> u-boot,dm-spl;
>> };
>> +
>> +&l2cache {
>> + status = "okay";
>> +};
>
>Squash with next commit.
Will update in v9.
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH v8 15/21] riscv: sifive: fu540: add SPL configuration
2020-05-09 14:30 ` [PATCH v8 15/21] riscv: sifive: fu540: add SPL configuration Pragnesh Patel
@ 2020-05-11 9:00 ` Jagan Teki
2020-05-11 9:44 ` Pragnesh Patel
0 siblings, 1 reply; 31+ messages in thread
From: Jagan Teki @ 2020-05-11 9:00 UTC (permalink / raw)
To: u-boot
On Sat, May 9, 2020 at 8:02 PM Pragnesh Patel <pragnesh.patel@sifive.com> wrote:
>
> Add a support for SPL which will boot from L2 LIM (0x0800_0000) and
> then SPL will boot U-Boot FIT image (OpenSBI FW_DYNAMIC + u-boot.bin)
> from MMC boot devices.
>
> SPL related code is leveraged from FSBL
> (https://github.com/sifive/freedom-u540-c000-bootloader.git)
>
> Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> Tested-by: Bin Meng <bmeng.cn@gmail.com>
> ---
> arch/riscv/cpu/fu540/Makefile | 4 ++
> arch/riscv/cpu/fu540/spl.c | 23 ++++++
> .../dts/hifive-unleashed-a00-u-boot.dtsi | 5 ++
> arch/riscv/include/asm/arch-fu540/spl.h | 14 ++++
> board/sifive/fu540/Kconfig | 12 +++-
> board/sifive/fu540/Makefile | 4 ++
> board/sifive/fu540/fu540.c | 24 +++++++
> board/sifive/fu540/spl.c | 72 +++++++++++++++++++
> include/configs/sifive-fu540.h | 18 +++++
> 9 files changed, 174 insertions(+), 2 deletions(-)
> create mode 100644 arch/riscv/cpu/fu540/spl.c
> create mode 100644 arch/riscv/include/asm/arch-fu540/spl.h
> create mode 100644 board/sifive/fu540/spl.c
>
> diff --git a/arch/riscv/cpu/fu540/Makefile b/arch/riscv/cpu/fu540/Makefile
> index 44700d998c..043fb961a5 100644
> --- a/arch/riscv/cpu/fu540/Makefile
> +++ b/arch/riscv/cpu/fu540/Makefile
> @@ -3,5 +3,9 @@
> # Copyright (C) 2020 SiFive, Inc
> # Pragnesh Patel <pragnesh.patel@sifive.com>
>
> +ifeq ($(CONFIG_SPL_BUILD),y)
> +obj-y += spl.o
> +else
> obj-y += dram.o
> obj-y += cpu.o
> +endif
> diff --git a/arch/riscv/cpu/fu540/spl.c b/arch/riscv/cpu/fu540/spl.c
> new file mode 100644
> index 0000000000..2e05d8a6e2
> --- /dev/null
> +++ b/arch/riscv/cpu/fu540/spl.c
> @@ -0,0 +1,23 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2020 SiFive, Inc
> + * Pragnesh Patel <pragnesh.patel@sifive.com>
> + */
> +
> +#include <common.h>
> +#include <dm.h>
> +
> +int soc_spl_init(void)
> +{
> + int ret;
> + struct udevice *dev;
> +
> + /* DDR init */
> + ret = uclass_get_device(UCLASS_RAM, 0, &dev);
> + if (ret) {
> + debug("DRAM init failed: %d\n", ret);
> + return ret;
> + }
> +
> + return 0;
> +}
> diff --git a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
> index 9787332bf1..37de015de6 100644
> --- a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
> +++ b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
> @@ -4,6 +4,7 @@
> */
>
> #include "fu540-c000-u-boot.dtsi"
> +#include "fu540-hifive-unleashed-a00-sdram-ddr4.dtsi"
>
> / {
> aliases {
> @@ -26,3 +27,7 @@
> u-boot,dm-spl;
> };
> };
> +
> +&gpio {
> + u-boot,dm-spl;
> +};
> diff --git a/arch/riscv/include/asm/arch-fu540/spl.h b/arch/riscv/include/asm/arch-fu540/spl.h
> new file mode 100644
> index 0000000000..0c188be747
> --- /dev/null
> +++ b/arch/riscv/include/asm/arch-fu540/spl.h
> @@ -0,0 +1,14 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (C) 2020 SiFive, Inc.
> + *
> + * Authors:
> + * Pragnesh Patel <pragnesh.patel@sifve.com>
> + */
> +
> +#ifndef _SPL_SIFIVE_H
> +#define _SPL_SIFIVE_H
> +
> +int soc_spl_init(void);
> +
> +#endif /* _SPL_SIFIVE_H */
> diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig
> index d41c305227..4a77a2a37b 100644
> --- a/board/sifive/fu540/Kconfig
> +++ b/board/sifive/fu540/Kconfig
> @@ -7,18 +7,26 @@ config SYS_VENDOR
> default "sifive"
>
> config SYS_CPU
> - default "generic"
> + default "fu540"
>
> config SYS_CONFIG_NAME
> default "sifive-fu540"
>
> config SYS_TEXT_BASE
> + default 0x80200000 if SPL
> default 0x80000000 if !RISCV_SMODE
> default 0x80200000 if RISCV_SMODE
>
> +config SPL_TEXT_BASE
> + default 0x08000000
> +
> +config SPL_OPENSBI_LOAD_ADDR
> + default 0x80000000
> +
> config BOARD_SPECIFIC_OPTIONS # dummy
> def_bool y
> - select GENERIC_RISCV
> + select SIFIVE_FU540
> + select SUPPORT_SPL
> select RAM
> select SPL_RAM if SPL
> imply CMD_DHCP
> diff --git a/board/sifive/fu540/Makefile b/board/sifive/fu540/Makefile
> index 6e1862c475..b05e2f5807 100644
> --- a/board/sifive/fu540/Makefile
> +++ b/board/sifive/fu540/Makefile
> @@ -3,3 +3,7 @@
> # Copyright (c) 2019 Western Digital Corporation or its affiliates.
>
> obj-y += fu540.o
> +
> +ifdef CONFIG_SPL_BUILD
> +obj-y += spl.o
> +endif
> diff --git a/board/sifive/fu540/fu540.c b/board/sifive/fu540/fu540.c
> index 540638c919..d05529a86b 100644
> --- a/board/sifive/fu540/fu540.c
> +++ b/board/sifive/fu540/fu540.c
> @@ -11,6 +11,7 @@
> #include <linux/delay.h>
> #include <linux/io.h>
> #include <misc.h>
> +#include <spl.h>
>
> /*
> * This define is a value used for error/unknown serial.
> @@ -114,3 +115,26 @@ int board_init(void)
>
> return 0;
> }
> +
> +#ifdef CONFIG_SPL
> +void board_boot_order(u32 *spl_boot_list)
> +{
> + u8 i;
> + u32 boot_devices[] = {
> +#ifdef CONFIG_SPL_MMC_SUPPORT
> + BOOT_DEVICE_MMC1,
> +#endif
> + };
> +
> + for (i = 0; i < ARRAY_SIZE(boot_devices); i++)
> + spl_boot_list[i] = boot_devices[i];
> +}
> +#endif
Board has static jumpers to set boot mode, so boot order won't be
possible so add spl_boot_device by assigning MMC boot device for now.
Otherwise,
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH v8 15/21] riscv: sifive: fu540: add SPL configuration
2020-05-11 9:00 ` Jagan Teki
@ 2020-05-11 9:44 ` Pragnesh Patel
0 siblings, 0 replies; 31+ messages in thread
From: Pragnesh Patel @ 2020-05-11 9:44 UTC (permalink / raw)
To: u-boot
>-----Original Message-----
>From: Jagan Teki <jagan@amarulasolutions.com>
>Sent: 11 May 2020 14:30
>To: Pragnesh Patel <pragnesh.patel@sifive.com>
>Cc: U-Boot-Denx <u-boot@lists.denx.de>; Atish Patra
><atish.patra@wdc.com>; Palmer Dabbelt <palmerdabbelt@google.com>; Bin
>Meng <bmeng.cn@gmail.com>; Paul Walmsley <paul.walmsley@sifive.com>;
>Troy Benjegerdes <troy.benjegerdes@sifive.com>; Anup Patel
><anup.patel@wdc.com>; Sagar Kadam <sagar.kadam@sifive.com>; Rick Chen
><rick@andestech.com>; Palmer Dabbelt <palmer@sifive.com>
>Subject: Re: [PATCH v8 15/21] riscv: sifive: fu540: add SPL configuration
>
>[External Email] Do not click links or attachments unless you recognize the
>sender and know the content is safe
>
>On Sat, May 9, 2020 at 8:02 PM Pragnesh Patel <pragnesh.patel@sifive.com>
>wrote:
>>
>> Add a support for SPL which will boot from L2 LIM (0x0800_0000) and
>> then SPL will boot U-Boot FIT image (OpenSBI FW_DYNAMIC + u-boot.bin)
>> from MMC boot devices.
>>
>> SPL related code is leveraged from FSBL
>> (https://github.com/sifive/freedom-u540-c000-bootloader.git)
>>
>> Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
>> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
>> Tested-by: Bin Meng <bmeng.cn@gmail.com>
>> ---
>> arch/riscv/cpu/fu540/Makefile | 4 ++
>> arch/riscv/cpu/fu540/spl.c | 23 ++++++
>> .../dts/hifive-unleashed-a00-u-boot.dtsi | 5 ++
>> arch/riscv/include/asm/arch-fu540/spl.h | 14 ++++
>> board/sifive/fu540/Kconfig | 12 +++-
>> board/sifive/fu540/Makefile | 4 ++
>> board/sifive/fu540/fu540.c | 24 +++++++
>> board/sifive/fu540/spl.c | 72 +++++++++++++++++++
>> include/configs/sifive-fu540.h | 18 +++++
>> 9 files changed, 174 insertions(+), 2 deletions(-) create mode
>> 100644 arch/riscv/cpu/fu540/spl.c create mode 100644
>> arch/riscv/include/asm/arch-fu540/spl.h
>> create mode 100644 board/sifive/fu540/spl.c
>>
>> diff --git a/arch/riscv/cpu/fu540/Makefile
>> b/arch/riscv/cpu/fu540/Makefile index 44700d998c..043fb961a5 100644
>> --- a/arch/riscv/cpu/fu540/Makefile
>> +++ b/arch/riscv/cpu/fu540/Makefile
>> @@ -3,5 +3,9 @@
>> # Copyright (C) 2020 SiFive, Inc
>> # Pragnesh Patel <pragnesh.patel@sifive.com>
>>
>> +ifeq ($(CONFIG_SPL_BUILD),y)
>> +obj-y += spl.o
>> +else
>> obj-y += dram.o
>> obj-y += cpu.o
>> +endif
>> diff --git a/arch/riscv/cpu/fu540/spl.c b/arch/riscv/cpu/fu540/spl.c
>> new file mode 100644 index 0000000000..2e05d8a6e2
>> --- /dev/null
>> +++ b/arch/riscv/cpu/fu540/spl.c
>> @@ -0,0 +1,23 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * Copyright (C) 2020 SiFive, Inc
>> + * Pragnesh Patel <pragnesh.patel@sifive.com> */
>> +
>> +#include <common.h>
>> +#include <dm.h>
>> +
>> +int soc_spl_init(void)
>> +{
>> + int ret;
>> + struct udevice *dev;
>> +
>> + /* DDR init */
>> + ret = uclass_get_device(UCLASS_RAM, 0, &dev);
>> + if (ret) {
>> + debug("DRAM init failed: %d\n", ret);
>> + return ret;
>> + }
>> +
>> + return 0;
>> +}
>> diff --git a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
>> b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
>> index 9787332bf1..37de015de6 100644
>> --- a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
>> +++ b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
>> @@ -4,6 +4,7 @@
>> */
>>
>> #include "fu540-c000-u-boot.dtsi"
>> +#include "fu540-hifive-unleashed-a00-sdram-ddr4.dtsi"
>>
>> / {
>> aliases {
>> @@ -26,3 +27,7 @@
>> u-boot,dm-spl;
>> };
>> };
>> +
>> +&gpio {
>> + u-boot,dm-spl;
>> +};
>> diff --git a/arch/riscv/include/asm/arch-fu540/spl.h
>> b/arch/riscv/include/asm/arch-fu540/spl.h
>> new file mode 100644
>> index 0000000000..0c188be747
>> --- /dev/null
>> +++ b/arch/riscv/include/asm/arch-fu540/spl.h
>> @@ -0,0 +1,14 @@
>> +/* SPDX-License-Identifier: GPL-2.0+ */
>> +/*
>> + * Copyright (C) 2020 SiFive, Inc.
>> + *
>> + * Authors:
>> + * Pragnesh Patel <pragnesh.patel@sifve.com>
>> + */
>> +
>> +#ifndef _SPL_SIFIVE_H
>> +#define _SPL_SIFIVE_H
>> +
>> +int soc_spl_init(void);
>> +
>> +#endif /* _SPL_SIFIVE_H */
>> diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig
>> index d41c305227..4a77a2a37b 100644
>> --- a/board/sifive/fu540/Kconfig
>> +++ b/board/sifive/fu540/Kconfig
>> @@ -7,18 +7,26 @@ config SYS_VENDOR
>> default "sifive"
>>
>> config SYS_CPU
>> - default "generic"
>> + default "fu540"
>>
>> config SYS_CONFIG_NAME
>> default "sifive-fu540"
>>
>> config SYS_TEXT_BASE
>> + default 0x80200000 if SPL
>> default 0x80000000 if !RISCV_SMODE
>> default 0x80200000 if RISCV_SMODE
>>
>> +config SPL_TEXT_BASE
>> + default 0x08000000
>> +
>> +config SPL_OPENSBI_LOAD_ADDR
>> + default 0x80000000
>> +
>> config BOARD_SPECIFIC_OPTIONS # dummy
>> def_bool y
>> - select GENERIC_RISCV
>> + select SIFIVE_FU540
>> + select SUPPORT_SPL
>> select RAM
>> select SPL_RAM if SPL
>> imply CMD_DHCP
>> diff --git a/board/sifive/fu540/Makefile b/board/sifive/fu540/Makefile
>> index 6e1862c475..b05e2f5807 100644
>> --- a/board/sifive/fu540/Makefile
>> +++ b/board/sifive/fu540/Makefile
>> @@ -3,3 +3,7 @@
>> # Copyright (c) 2019 Western Digital Corporation or its affiliates.
>>
>> obj-y += fu540.o
>> +
>> +ifdef CONFIG_SPL_BUILD
>> +obj-y += spl.o
>> +endif
>> diff --git a/board/sifive/fu540/fu540.c b/board/sifive/fu540/fu540.c
>> index 540638c919..d05529a86b 100644
>> --- a/board/sifive/fu540/fu540.c
>> +++ b/board/sifive/fu540/fu540.c
>> @@ -11,6 +11,7 @@
>> #include <linux/delay.h>
>> #include <linux/io.h>
>> #include <misc.h>
>> +#include <spl.h>
>>
>> /*
>> * This define is a value used for error/unknown serial.
>> @@ -114,3 +115,26 @@ int board_init(void)
>>
>> return 0;
>> }
>> +
>> +#ifdef CONFIG_SPL
>> +void board_boot_order(u32 *spl_boot_list) {
>> + u8 i;
>> + u32 boot_devices[] = {
>> +#ifdef CONFIG_SPL_MMC_SUPPORT
>> + BOOT_DEVICE_MMC1,
>> +#endif
>> + };
>> +
>> + for (i = 0; i < ARRAY_SIZE(boot_devices); i++)
>> + spl_boot_list[i] = boot_devices[i]; } #endif
>
>Board has static jumpers to set boot mode, so boot order won't be possible so
>add spl_boot_device by assigning MMC boot device for now.
Will update in v9, thanks for the review.
>
>Otherwise,
>
>Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
^ permalink raw reply [flat|nested] 31+ messages in thread
end of thread, other threads:[~2020-05-11 9:44 UTC | newest]
Thread overview: 31+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-05-09 14:30 [PATCH v8 00/21] RISC-V SiFive FU540 support SPL Pragnesh Patel
2020-05-09 14:30 ` [PATCH v8 01/21] misc: add driver for the SiFive otp controller Pragnesh Patel
2020-05-09 14:30 ` [PATCH v8 02/21] riscv: sifive: fu540: Use OTP DM driver for serial environment variable Pragnesh Patel
2020-05-09 14:30 ` [PATCH v8 03/21] riscv: Add _image_binary_end for SPL Pragnesh Patel
2020-05-09 14:30 ` [PATCH v8 04/21] lib: Makefile: build crc7.c when CONFIG_MMC_SPI Pragnesh Patel
2020-05-09 14:30 ` [PATCH v8 05/21] riscv: sifive: dts: fu540: Add board -u-boot.dtsi files Pragnesh Patel
2020-05-09 14:30 ` [PATCH v8 06/21] sifive: fu540: add ddr driver Pragnesh Patel
2020-05-09 19:47 ` Giulio Benetti
2020-05-10 6:18 ` Pragnesh Patel
2020-05-10 6:35 ` Pragnesh Patel
2020-05-09 14:30 ` [PATCH v8 07/21] sifive: dts: fu540: Add DDR controller and phy register settings Pragnesh Patel
2020-05-09 14:30 ` [PATCH v8 08/21] riscv: sifive: dts: fu540: add U-Boot dmc node Pragnesh Patel
2020-05-09 14:30 ` [PATCH v8 09/21] clk: sifive: fu540-prci: Add clock enable and disable ops Pragnesh Patel
2020-05-09 14:30 ` [PATCH v8 10/21] clk: sifive: fu540-prci: Add ddr clock initialization in SPL Pragnesh Patel
2020-05-09 14:30 ` [PATCH v8 11/21] clk: sifive: fu540-prci: Add ehternet " Pragnesh Patel
2020-05-09 14:30 ` [PATCH v8 12/21] riscv: dts: sifive: Sync hifive-unleashed-a00 dts from linux Pragnesh Patel
2020-05-09 14:30 ` [PATCH v8 13/21] riscv: cpu: fu540: Add support for cpu fu540 Pragnesh Patel
2020-05-09 14:30 ` [PATCH v8 14/21] riscv: Add place-holder for driver compilation Pragnesh Patel
2020-05-09 14:30 ` [PATCH v8 15/21] riscv: sifive: fu540: add SPL configuration Pragnesh Patel
2020-05-11 9:00 ` Jagan Teki
2020-05-11 9:44 ` Pragnesh Patel
2020-05-09 14:30 ` [PATCH v8 16/21] sifive: fu540: Add sample SD gpt partition layout Pragnesh Patel
2020-05-09 14:30 ` [PATCH v8 17/21] sifive: fu540: Add U-Boot proper sector start Pragnesh Patel
2020-05-09 14:30 ` [PATCH v8 18/21] configs: fu540: Add config options for U-Boot SPL Pragnesh Patel
2020-05-10 9:20 ` Jagan Teki
2020-05-11 5:59 ` Pragnesh Patel
2020-05-09 14:30 ` [PATCH v8 19/21] sifive: dts: fu540: Enable L2 Cache in U-Boot Pragnesh Patel
2020-05-10 15:14 ` Jagan Teki
2020-05-11 6:06 ` Pragnesh Patel
2020-05-09 14:30 ` [PATCH v8 20/21] riscv: sifive: fu540: enable all cache ways from U-Boot proper Pragnesh Patel
2020-05-09 14:30 ` [PATCH v8 21/21] doc: sifive: fu540: Add description for OpenSBI generic platform Pragnesh Patel
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