From mboxrd@z Thu Jan 1 00:00:00 1970 From: Pragnesh Patel Date: Sat, 9 May 2020 20:00:26 +0530 Subject: [PATCH v8 11/21] clk: sifive: fu540-prci: Add ehternet clock initialization in SPL In-Reply-To: <20200509143037.26009-1-pragnesh.patel@sifive.com> References: <20200509143037.26009-1-pragnesh.patel@sifive.com> Message-ID: <20200509143037.26009-12-pragnesh.patel@sifive.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Add ehternet clock initialization for SPL Signed-off-by: Pragnesh Patel --- drivers/clk/sifive/fu540-prci.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/drivers/clk/sifive/fu540-prci.c b/drivers/clk/sifive/fu540-prci.c index 033562274e..e7ceda0dcf 100644 --- a/drivers/clk/sifive/fu540-prci.c +++ b/drivers/clk/sifive/fu540-prci.c @@ -41,6 +41,8 @@ #include #include +#define MHz 1000000 + /* * EXPECTED_CLK_PARENT_COUNT: how many parent clocks this driver expects: * hfclk and rtcclk @@ -709,6 +711,29 @@ static int sifive_fu540_prci_disable(struct clk *clk) return ret; } +#ifdef CONFIG_SPL_BUILD +static void ethernet_init(struct udevice *dev) +{ + u32 v; + struct clk clock; + struct __prci_data *pd = dev_get_priv(dev); + + /* GEMGXL init */ + clock.id = PRCI_CLK_GEMGXLPLL; + sifive_fu540_prci_set_rate(&clock, 125UL * MHz); + sifive_fu540_prci_clock_enable(&__prci_init_clocks[clock.id], 1); + + /* Release GEMGXL reset */ + v = __prci_readl(pd, PRCI_DEVICESRESETREG_OFFSET); + v |= PRCI_DEVICESRESETREG_GEMGXL_RST_N_MASK; + __prci_writel(v, PRCI_DEVICESRESETREG_OFFSET, pd); + + /* Procmon => core clock */ + __prci_writel(PRCI_PROCMONCFG_CORE_CLOCK_MASK, PRCI_PROCMONCFG_OFFSET, + pd); +} +#endif + static int sifive_fu540_prci_probe(struct udevice *dev) { int i, err; @@ -734,6 +759,10 @@ static int sifive_fu540_prci_probe(struct udevice *dev) __prci_wrpll_read_cfg0(pd, pc->pwd); } +#ifdef CONFIG_SPL_BUILD + ethernet_init(dev); +#endif + return 0; } -- 2.17.1