From: Sudeep Holla <sudeep.holla@arm.com>
To: Aaron Chou <zhoubb.aaron@gmail.com>
Cc: lorenzo.pieralisi@arm.com, guohanjun@huawei.com,
linux-acpi@vger.kernel.org, Sudeep Holla <sudeep.holla@arm.com>
Subject: Re: [ARM64 ACPI] different CPU L3 cache size reported by /sys/device/ and dmidecode
Date: Mon, 11 May 2020 09:18:28 +0100 [thread overview]
Message-ID: <20200511081818.GA9532@bogus> (raw)
In-Reply-To: <CAMpQs4JoyZcHQLahh4w8OaowQ1y3pkTCTYvDn+dkVNOQ4zDpHQ@mail.gmail.com>
On Mon, May 11, 2020 at 03:30:51PM +0800, Aaron Chou wrote:
> In the system, I can get the L3 cache size from two or more ways.
>
Which platform is this ? More details would help.
> Firstly, I can get it from the kernel interface, such as the `lscpu` command.
> Also, I can cat the file `/sys/devices/system/cpu/cpu3/cache/index3/size`.
>
IIRC, lscpu parse the above mentioned sysfs files and the above result
match the expectation.
> The way above can give me the L3 cache size is 32768K.
>
OK
> Now if I use the `dmidecode -t cache` command, I get the L3 cache size
> is 24576K.
>
Ah, that's bad.
> And the real size of the L3 cache is 24576K.
>
OK
> Why is it? who can explain it to me?
>
ACPI reads these cache information from PPTT. The firmware which populates
the ACPI PPTT must read it from DMI entries and keep them in sync. On
this system, looks like the firmware tried to be more imaginative and
populated PPTT with wrong values. Get that firmware fixed please!
--
Regards,
Sudeep
next prev parent reply other threads:[~2020-05-11 8:18 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-11 7:30 [ARM64 ACPI] different CPU L3 cache size reported by /sys/device/ and dmidecode Aaron Chou
2020-05-11 8:10 ` Hanjun Guo
2020-05-11 8:18 ` Sudeep Holla [this message]
2020-05-11 8:38 ` Aaron Chou
-- strict thread matches above, loose matches on Subject: below --
2020-05-11 7:28 Aaron Chou
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