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From: Sylwester Nawrocki <s.nawrocki@samsung.com>
To: u-boot@lists.denx.de
Subject: [PATCH v3 2/9] usb: xhci: Use only 32-bit accesses in xhci_writeq/xhci_readq
Date: Tue, 12 May 2020 20:47:09 +0200	[thread overview]
Message-ID: <20200512184716.2869-3-s.nawrocki@samsung.com> (raw)
In-Reply-To: <20200512184716.2869-1-s.nawrocki@samsung.com>

There might be hardware configurations where 64-bit data accesses
to XHCI registers are not supported properly.  This patch removes
the readq/writeq so always two 32-bit accesses are used to read/write
64-bit XHCI registers, similarly as it is done in Linux kernel.

This patch fixes operation of the XHCI controller on RPI4 Broadcom
BCM2711 SoC based board, where the VL805 USB XHCI controller is
connected to the PCIe Root Complex, which is attached to the system
through the SCB bridge.

Even though the architecture is 64-bit the PCIe BAR is 32-bit and likely
the 64-bit wide register accesses initiated by the CPU are not properly
translated to a sequence of 32-bit PCIe accesses.
xhci_readq(), for example, always returns same value in upper and lower
32-bits, e.g. 0xabcd1234abcd1234 instead of 0x00000000abcd1234.

Cc: Sergey Temerkhanov <s.temerkhanov@gmail.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
---
Changes since v1:
 - none.
Changes since RFC:
 - dropped Kconfig option, switched to not using readq/writeq
   unconditionally.
---
 include/usb/xhci.h | 8 --------
 1 file changed, 8 deletions(-)

diff --git a/include/usb/xhci.h b/include/usb/xhci.h
index 6017504..c16106a 100644
--- a/include/usb/xhci.h
+++ b/include/usb/xhci.h
@@ -1111,28 +1111,20 @@ static inline void xhci_writel(uint32_t volatile *regs, const unsigned int val)
  */
 static inline u64 xhci_readq(__le64 volatile *regs)
 {
-#if BITS_PER_LONG == 64
-	return readq(regs);
-#else
 	__u32 *ptr = (__u32 *)regs;
 	u64 val_lo = readl(ptr);
 	u64 val_hi = readl(ptr + 1);
 	return val_lo + (val_hi << 32);
-#endif
 }
 
 static inline void xhci_writeq(__le64 volatile *regs, const u64 val)
 {
-#if BITS_PER_LONG == 64
-	writeq(val, regs);
-#else
 	__u32 *ptr = (__u32 *)regs;
 	u32 val_lo = lower_32_bits(val);
 	/* FIXME */
 	u32 val_hi = upper_32_bits(val);
 	writel(val_lo, ptr);
 	writel(val_hi, ptr + 1);
-#endif
 }
 
 int xhci_hcd_init(int index, struct xhci_hccr **ret_hccr,
-- 
2.7.4

  parent reply	other threads:[~2020-05-12 18:47 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <CGME20200512184724eucas1p24bb9730834234cebf5061a614c2c8c54@eucas1p2.samsung.com>
2020-05-12 18:47 ` [PATCH v3 0/9] USB host support for Raspberry Pi 4 board (64-bit) Sylwester Nawrocki
     [not found]   ` <CGME20200512184740eucas1p2912f07b9e34cc769604d641adb0e13c9@eucas1p2.samsung.com>
2020-05-12 18:47     ` [PATCH v3 1/9] usb: xhci: Add missing cache flush in the scratchpad array initialization Sylwester Nawrocki
     [not found]   ` <CGME20200512184743eucas1p28e9d93ba5e46ed900a88bf0bf85fda58@eucas1p2.samsung.com>
2020-05-12 18:47     ` Sylwester Nawrocki [this message]
     [not found]   ` <CGME20200512184747eucas1p25ed7fb872416271dd34806ccfb4197e5@eucas1p2.samsung.com>
2020-05-12 18:47     ` [PATCH v3 3/9] pci: Move some PCIe register offset definitions to a common header Sylwester Nawrocki
     [not found]   ` <CGME20200512184829eucas1p10c67592f9af7879f51eee9bff8fa76d7@eucas1p1.samsung.com>
2020-05-12 18:47     ` [PATCH v3 4/9] rpi4: shorten a mapping for the DRAM Sylwester Nawrocki
     [not found]   ` <CGME20200512184830eucas1p198b1439122e2da299c563726fe17f9ef@eucas1p1.samsung.com>
2020-05-12 18:47     ` [PATCH v3 5/9] rpi4: add a mapping for the PCIe XHCI controller MMIO registers (ARM 64bit) Sylwester Nawrocki
     [not found]   ` <CGME20200512184832eucas1p1b75fca7f5ed42e3cb38f98410f51f1ad@eucas1p1.samsung.com>
2020-05-12 18:47     ` [PATCH v3 6/9] linux/bitfield.h: Add primitives for manipulating bitfields both in host- and fixed-endian Sylwester Nawrocki
     [not found]       ` <CGME20200512190442eucas1p278509fbc3a5d4bc7303797e5b8b284d6@eucas1p2.samsung.com>
2020-05-12 19:04         ` [RESEND PATCH " Sylwester Nawrocki
     [not found]   ` <CGME20200512184836eucas1p2f357a332cd99d6e287a74405d75c0985@eucas1p2.samsung.com>
2020-05-12 18:47     ` [PATCH v3 7/9] pci: Add some PCI Express capability register offset definitions Sylwester Nawrocki
     [not found]   ` <CGME20200512184838eucas1p249588f9ee76dcb5a10209fcb7de01fae@eucas1p2.samsung.com>
2020-05-12 18:47     ` [PATCH v3 8/9] pci: Add driver for Broadcom BCM2711 SoC PCIe controller Sylwester Nawrocki
     [not found]   ` <CGME20200512184842eucas1p1b2edc2128ddf134553805db77451648f@eucas1p1.samsung.com>
2020-05-12 18:47     ` [PATCH v3 9/9] configs: Enable support for the XHCI controller on RPI4 board (ARM 64-bit) Sylwester Nawrocki
2020-05-13  9:21       ` Sylwester Nawrocki
2020-05-24 18:30         ` Matthias Brugger
2020-05-25  9:25           ` Sylwester Nawrocki

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