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From: Sylwester Nawrocki <s.nawrocki@samsung.com>
To: u-boot@lists.denx.de
Subject: [PATCH v3 3/9] pci: Move some PCIe register offset definitions to a common header
Date: Tue, 12 May 2020 20:47:10 +0200	[thread overview]
Message-ID: <20200512184716.2869-4-s.nawrocki@samsung.com> (raw)
In-Reply-To: <20200512184716.2869-1-s.nawrocki@samsung.com>

Some PCI Express register offsets are currently defined in multiple
drivers, move them to a common header to avoid re-definitions and
as a pre-requisite for adding new PCIe driver.
While at it replace some spaces with tabs.

Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
---
Changes since v1:
 - none.
Changes since RFC:
 - whitespace clean up.
---
 drivers/pci/pci-rcar-gen3.c   |  8 --------
 drivers/pci/pcie_intel_fpga.c |  3 ---
 include/pci.h                 | 13 +++++++++++--
 3 files changed, 11 insertions(+), 13 deletions(-)

diff --git a/drivers/pci/pci-rcar-gen3.c b/drivers/pci/pci-rcar-gen3.c
index 30eff67..393f1c9 100644
--- a/drivers/pci/pci-rcar-gen3.c
+++ b/drivers/pci/pci-rcar-gen3.c
@@ -117,14 +117,6 @@
 #define RCAR_PCI_MAX_RESOURCES	4
 #define MAX_NR_INBOUND_MAPS	6
 
-#define PCI_EXP_FLAGS		2		/* Capabilities register */
-#define PCI_EXP_FLAGS_TYPE	0x00f0		/* Device/Port type */
-#define PCI_EXP_TYPE_ROOT_PORT	0x4		/* Root Port */
-#define PCI_EXP_LNKCAP		12		/* Link Capabilities */
-#define PCI_EXP_LNKCAP_DLLLARC	0x00100000	/* Data Link Layer Link Active Reporting Capable */
-#define PCI_EXP_SLTCAP		20		/* Slot Capabilities */
-#define PCI_EXP_SLTCAP_PSN	0xfff80000	/* Physical Slot Number */
-
 enum {
 	RCAR_PCI_ACCESS_READ,
 	RCAR_PCI_ACCESS_WRITE,
diff --git a/drivers/pci/pcie_intel_fpga.c b/drivers/pci/pcie_intel_fpga.c
index 6a9f29c..69363a0 100644
--- a/drivers/pci/pcie_intel_fpga.c
+++ b/drivers/pci/pcie_intel_fpga.c
@@ -65,9 +65,6 @@
 #define IS_ROOT_PORT(pcie, bdf)				\
 		((PCI_BUS(bdf) == pcie->first_busno) ? true : false)
 
-#define PCI_EXP_LNKSTA		18	/* Link Status */
-#define PCI_EXP_LNKSTA_DLLLA	0x2000	/* Data Link Layer Link Active */
-
 /**
  * struct intel_fpga_pcie - Intel FPGA PCIe controller state
  * @bus: Pointer to the PCI bus
diff --git a/include/pci.h b/include/pci.h
index aff56b2..dfdbb32 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -471,10 +471,19 @@
 #define  PCI_EA_FIELD_MASK	0xfffffffc	/* For Base & Max Offset */
 
 /* PCI Express capabilities */
+#define PCI_EXP_FLAGS		2	/* Capabilities register */
+#define  PCI_EXP_FLAGS_TYPE	0x00f0	/* Device/Port type */
+#define  PCI_EXP_TYPE_ROOT_PORT 0x4	/* Root Port */
 #define PCI_EXP_DEVCAP		4	/* Device capabilities */
-#define  PCI_EXP_DEVCAP_FLR     0x10000000 /* Function Level Reset */
+#define  PCI_EXP_DEVCAP_FLR	0x10000000 /* Function Level Reset */
 #define PCI_EXP_DEVCTL		8	/* Device Control */
-#define  PCI_EXP_DEVCTL_BCR_FLR 0x8000  /* Bridge Configuration Retry / FLR */
+#define  PCI_EXP_DEVCTL_BCR_FLR	0x8000  /* Bridge Configuration Retry / FLR */
+#define PCI_EXP_LNKCAP		12	/* Link Capabilities */
+#define  PCI_EXP_LNKCAP_DLLLARC	0x00100000 /* Data Link Layer Link Active Reporting Capable */
+#define PCI_EXP_LNKSTA		18	/* Link Status */
+#define  PCI_EXP_LNKSTA_DLLLA	0x2000	/* Data Link Layer Link Active */
+#define PCI_EXP_SLTCAP		20	/* Slot Capabilities */
+#define  PCI_EXP_SLTCAP_PSN	0xfff80000 /* Physical Slot Number */
 
 /* Include the ID list */
 
-- 
2.7.4

  parent reply	other threads:[~2020-05-12 18:47 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <CGME20200512184724eucas1p24bb9730834234cebf5061a614c2c8c54@eucas1p2.samsung.com>
2020-05-12 18:47 ` [PATCH v3 0/9] USB host support for Raspberry Pi 4 board (64-bit) Sylwester Nawrocki
     [not found]   ` <CGME20200512184740eucas1p2912f07b9e34cc769604d641adb0e13c9@eucas1p2.samsung.com>
2020-05-12 18:47     ` [PATCH v3 1/9] usb: xhci: Add missing cache flush in the scratchpad array initialization Sylwester Nawrocki
     [not found]   ` <CGME20200512184743eucas1p28e9d93ba5e46ed900a88bf0bf85fda58@eucas1p2.samsung.com>
2020-05-12 18:47     ` [PATCH v3 2/9] usb: xhci: Use only 32-bit accesses in xhci_writeq/xhci_readq Sylwester Nawrocki
     [not found]   ` <CGME20200512184747eucas1p25ed7fb872416271dd34806ccfb4197e5@eucas1p2.samsung.com>
2020-05-12 18:47     ` Sylwester Nawrocki [this message]
     [not found]   ` <CGME20200512184829eucas1p10c67592f9af7879f51eee9bff8fa76d7@eucas1p1.samsung.com>
2020-05-12 18:47     ` [PATCH v3 4/9] rpi4: shorten a mapping for the DRAM Sylwester Nawrocki
     [not found]   ` <CGME20200512184830eucas1p198b1439122e2da299c563726fe17f9ef@eucas1p1.samsung.com>
2020-05-12 18:47     ` [PATCH v3 5/9] rpi4: add a mapping for the PCIe XHCI controller MMIO registers (ARM 64bit) Sylwester Nawrocki
     [not found]   ` <CGME20200512184832eucas1p1b75fca7f5ed42e3cb38f98410f51f1ad@eucas1p1.samsung.com>
2020-05-12 18:47     ` [PATCH v3 6/9] linux/bitfield.h: Add primitives for manipulating bitfields both in host- and fixed-endian Sylwester Nawrocki
     [not found]       ` <CGME20200512190442eucas1p278509fbc3a5d4bc7303797e5b8b284d6@eucas1p2.samsung.com>
2020-05-12 19:04         ` [RESEND PATCH " Sylwester Nawrocki
     [not found]   ` <CGME20200512184836eucas1p2f357a332cd99d6e287a74405d75c0985@eucas1p2.samsung.com>
2020-05-12 18:47     ` [PATCH v3 7/9] pci: Add some PCI Express capability register offset definitions Sylwester Nawrocki
     [not found]   ` <CGME20200512184838eucas1p249588f9ee76dcb5a10209fcb7de01fae@eucas1p2.samsung.com>
2020-05-12 18:47     ` [PATCH v3 8/9] pci: Add driver for Broadcom BCM2711 SoC PCIe controller Sylwester Nawrocki
     [not found]   ` <CGME20200512184842eucas1p1b2edc2128ddf134553805db77451648f@eucas1p1.samsung.com>
2020-05-12 18:47     ` [PATCH v3 9/9] configs: Enable support for the XHCI controller on RPI4 board (ARM 64-bit) Sylwester Nawrocki
2020-05-13  9:21       ` Sylwester Nawrocki
2020-05-24 18:30         ` Matthias Brugger
2020-05-25  9:25           ` Sylwester Nawrocki

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