On Wed, May 13, 2020 at 04:00:26PM +0200, Lars Povlsen wrote:

> +config SPI_DW_MCHP
> +	tristate "Memory-mapped io interface driver using DW SPI core of MSCC SoCs"
> +	default y if ARCH_SPARX5
> +	default y if SOC_VCOREIII

Why the default ys?

> +++ b/drivers/spi/Makefile
> @@ -37,6 +37,7 @@ obj-$(CONFIG_SPI_DAVINCI)		+= spi-davinci.o
>  obj-$(CONFIG_SPI_DLN2)			+= spi-dln2.o
>  obj-$(CONFIG_SPI_DESIGNWARE)		+= spi-dw.o
>  obj-$(CONFIG_SPI_DW_MMIO)		+= spi-dw-mmio.o
> +obj-$(CONFIG_SPI_DW_MCHP)		+= spi-dw-mchp.o
>  obj-$(CONFIG_SPI_DW_PCI)		+= spi-dw-midpci.o
>  spi-dw-midpci-objs			:= spi-dw-pci.o spi-dw-mid.o
>  obj-$(CONFIG_SPI_EFM32)			+= spi-efm32.o

Please keep the file alphabetically sorted.

> +++ b/drivers/spi/spi-dw-mchp.c
> @@ -0,0 +1,232 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Memory-mapped interface driver for MSCC SoCs
> + *

Please make the entire comment a C++ one so things look more
intentional.

> +#define MAX_CS		4

This should be namespaced.

> +	rx_sample_dly = 0;
> +	device_property_read_u32(&pdev->dev, "spi-rx-delay-us", &rx_sample_dly);
> +	dws->rx_sample_dly = DIV_ROUND_UP(rx_sample_dly,
> +					  (dws->max_freq / 1000000));

If this is a standard feature of the DesignWare IP why parse it here and
not in the generic code?