From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A4A4BC433DF for ; Thu, 14 May 2020 06:03:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7B102206BE for ; Thu, 14 May 2020 06:03:08 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b="KZ+QEA3b" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725951AbgENGDH (ORCPT ); Thu, 14 May 2020 02:03:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40900 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1725806AbgENGDH (ORCPT ); Thu, 14 May 2020 02:03:07 -0400 Received: from mail-pl1-x641.google.com (mail-pl1-x641.google.com [IPv6:2607:f8b0:4864:20::641]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EB6C6C061A0C for ; Wed, 13 May 2020 23:03:06 -0700 (PDT) Received: by mail-pl1-x641.google.com with SMTP id y9so763069plk.10 for ; Wed, 13 May 2020 23:03:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=TPeI8RuAZy8pzAoL6foqpsMRTCi6RDeQb0PfZ8BZJ7U=; b=KZ+QEA3bF0HYQ7RCcHSNf5tGen8Wqfu5/++/v5YjZ6caB3VB6B1Py20Hr2cfeDTv1o 6ldf2Eo8zZj56RIyUzjNHIiOWTOqMQRqB8x/LSZsvMQjKc6xAfpag7SDAKP9SMJRL4VK VlnetIW4laPTdmw3XiNz68qsZXWLt4qPBYGYrcv+Zcwn/mtoJ6mKb3Nn/ZXVkbui8bPy NPOkinb4i1Jqz5n0oC2NAbWGfQ555kOt+AYOa1zRP0qFiKnBSUGF3R0N3in+apbBwv2W 72XE/cBOw86Zz4GQuJOXdVpja2N26ut/rKp97xJVunWPCg+C11+rb/TG8glVIdOSsIan f7mQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=TPeI8RuAZy8pzAoL6foqpsMRTCi6RDeQb0PfZ8BZJ7U=; b=syzjayFytgUFlGNksXBheoBHhVX+GHmChjFJAMIj6/345EjIsM8kyeH7C7Bugy3cGS Q5itI5Jh/+R0DnkBZGB/SUAzYPCjc85jYJSzOSKze/yahm9u0BK4zGl54t+zmJRH/Onf MQSDbX6wOcrefXPcRWFYKdDL29gXf1HM1kMbUq+MCfd94QKjilZgiW3Y3aeRydBO8hDI s43GZS27TVbxj9BIDBtgnj+kVwBuFuPW43rUSLqwIUdLtDfE7XZ6u987++Sht5KlO8hS SmrucN+UCLflPq4pVA7W2ANRp3M0wMmPOG7gF6zKH91/OarbHNufIi8Yx8ARV0kDJQQx RBWA== X-Gm-Message-State: AGi0Pua09qAPYL8Q/0YLiMM3qDJPRnxmIVap9MljD9AEk+se7gMrLfsi fvqQE3d3rTO873+Onfh2leo4EA== X-Google-Smtp-Source: APiQypKS0f2mmUEu7BEa8P6mPQkMckB+1UyKwXYrHoeDGxB2hTW6TJ6Z44jhprlTISi2/kMDG00Z5w== X-Received: by 2002:a17:90b:30cb:: with SMTP id hi11mr38401195pjb.103.1589436186242; Wed, 13 May 2020 23:03:06 -0700 (PDT) Received: from hsinchu02.internal.sifive.com (114-34-229-221.HINET-IP.hinet.net. [114.34.229.221]) by smtp.gmail.com with ESMTPSA id d10sm1202671pgo.10.2020.05.13.23.03.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 May 2020 23:03:05 -0700 (PDT) From: Zong Li To: paul.walmsley@sifive.com, palmer@dabbelt.com, akpm@linux-foundation.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Zong Li , Greentime Hu Subject: [PATCH] riscv: perf: fix build error for dependency issue Date: Thu, 14 May 2020 14:02:43 +0800 Message-Id: <20200514060243.106976-1-zong.li@sifive.com> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org CONFIG_RISCV_BASE_PMU can be selected or unselected, but in fact, CONFIG_RISCV_BASE_PMU must be always selected when selecting CONFIG_PERF_EVENTS on current perf implementation, otherwise, it would cause the build error when only selecting CONFIG_PERF_EVENTS. The build case is applied randconfig which generated by kbuild test. This patch removes the unnecessary configuration and implementations. Eventually, the number of counters should be determinated at runtime, such as DTB, so we don't need to re-build kernel for various platform which has got different number of hpmcounters. Signed-off-by: Zong Li Signed-off-by: Greentime Hu --- arch/riscv/Kconfig | 13 ------------- arch/riscv/include/asm/perf_event.h | 16 +++------------- 2 files changed, 3 insertions(+), 26 deletions(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 74f82cf4f781..7d5123576953 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -283,19 +283,6 @@ config RISCV_ISA_C If you don't know what to do here, say Y. -menu "supported PMU type" - depends on PERF_EVENTS - -config RISCV_BASE_PMU - bool "Base Performance Monitoring Unit" - def_bool y - help - A base PMU that serves as a reference implementation and has limited - feature of perf. It can run on any RISC-V machines so serves as the - fallback, but this option can also be disable to reduce kernel size. - -endmenu - config FPU bool "FPU support" default y diff --git a/arch/riscv/include/asm/perf_event.h b/arch/riscv/include/asm/perf_event.h index 0234048b12bc..8e5b1d81112c 100644 --- a/arch/riscv/include/asm/perf_event.h +++ b/arch/riscv/include/asm/perf_event.h @@ -16,15 +16,11 @@ /* * The RISCV_MAX_COUNTERS parameter should be specified. + * Currently, we only support base PMU, so just make + * RISCV_MAX_COUNTERS be equal to RISCV_BASE_COUNTERS. */ -#ifdef CONFIG_RISCV_BASE_PMU -#define RISCV_MAX_COUNTERS 2 -#endif - -#ifndef RISCV_MAX_COUNTERS -#error "Please provide a valid RISCV_MAX_COUNTERS for the PMU." -#endif +#define RISCV_MAX_COUNTERS RISCV_BASE_COUNTERS /* * These are the indexes of bits in counteren register *minus* 1, @@ -38,12 +34,6 @@ */ #define RISCV_PMU_CYCLE 0 #define RISCV_PMU_INSTRET 1 -#define RISCV_PMU_MHPMCOUNTER3 2 -#define RISCV_PMU_MHPMCOUNTER4 3 -#define RISCV_PMU_MHPMCOUNTER5 4 -#define RISCV_PMU_MHPMCOUNTER6 5 -#define RISCV_PMU_MHPMCOUNTER7 6 -#define RISCV_PMU_MHPMCOUNTER8 7 #define RISCV_OP_UNSUPP (-EOPNOTSUPP) -- 2.26.2 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D9A1CC433DF for ; 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[114.34.229.221]) by smtp.gmail.com with ESMTPSA id d10sm1202671pgo.10.2020.05.13.23.03.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 May 2020 23:03:05 -0700 (PDT) From: Zong Li To: paul.walmsley@sifive.com, palmer@dabbelt.com, akpm@linux-foundation.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH] riscv: perf: fix build error for dependency issue Date: Thu, 14 May 2020 14:02:43 +0800 Message-Id: <20200514060243.106976-1-zong.li@sifive.com> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200513_230307_755251_1AB4F4EF X-CRM114-Status: GOOD ( 11.61 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Greentime Hu , Zong Li Sender: "linux-riscv" Errors-To: linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org CONFIG_RISCV_BASE_PMU can be selected or unselected, but in fact, CONFIG_RISCV_BASE_PMU must be always selected when selecting CONFIG_PERF_EVENTS on current perf implementation, otherwise, it would cause the build error when only selecting CONFIG_PERF_EVENTS. The build case is applied randconfig which generated by kbuild test. This patch removes the unnecessary configuration and implementations. Eventually, the number of counters should be determinated at runtime, such as DTB, so we don't need to re-build kernel for various platform which has got different number of hpmcounters. Signed-off-by: Zong Li Signed-off-by: Greentime Hu --- arch/riscv/Kconfig | 13 ------------- arch/riscv/include/asm/perf_event.h | 16 +++------------- 2 files changed, 3 insertions(+), 26 deletions(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 74f82cf4f781..7d5123576953 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -283,19 +283,6 @@ config RISCV_ISA_C If you don't know what to do here, say Y. -menu "supported PMU type" - depends on PERF_EVENTS - -config RISCV_BASE_PMU - bool "Base Performance Monitoring Unit" - def_bool y - help - A base PMU that serves as a reference implementation and has limited - feature of perf. It can run on any RISC-V machines so serves as the - fallback, but this option can also be disable to reduce kernel size. - -endmenu - config FPU bool "FPU support" default y diff --git a/arch/riscv/include/asm/perf_event.h b/arch/riscv/include/asm/perf_event.h index 0234048b12bc..8e5b1d81112c 100644 --- a/arch/riscv/include/asm/perf_event.h +++ b/arch/riscv/include/asm/perf_event.h @@ -16,15 +16,11 @@ /* * The RISCV_MAX_COUNTERS parameter should be specified. + * Currently, we only support base PMU, so just make + * RISCV_MAX_COUNTERS be equal to RISCV_BASE_COUNTERS. */ -#ifdef CONFIG_RISCV_BASE_PMU -#define RISCV_MAX_COUNTERS 2 -#endif - -#ifndef RISCV_MAX_COUNTERS -#error "Please provide a valid RISCV_MAX_COUNTERS for the PMU." -#endif +#define RISCV_MAX_COUNTERS RISCV_BASE_COUNTERS /* * These are the indexes of bits in counteren register *minus* 1, @@ -38,12 +34,6 @@ */ #define RISCV_PMU_CYCLE 0 #define RISCV_PMU_INSTRET 1 -#define RISCV_PMU_MHPMCOUNTER3 2 -#define RISCV_PMU_MHPMCOUNTER4 3 -#define RISCV_PMU_MHPMCOUNTER5 4 -#define RISCV_PMU_MHPMCOUNTER6 5 -#define RISCV_PMU_MHPMCOUNTER7 6 -#define RISCV_PMU_MHPMCOUNTER8 7 #define RISCV_OP_UNSUPP (-EOPNOTSUPP) -- 2.26.2