* [Intel-gfx] [PATCH v12 00/14] In order to readout DP SDPs, refactors the handling of DP SDPs
@ 2020-05-14 6:07 ` Gwan-gyeong Mun
0 siblings, 0 replies; 73+ messages in thread
From: Gwan-gyeong Mun @ 2020-05-14 6:07 UTC (permalink / raw)
To: intel-gfx; +Cc: linux-fbdev, dri-devel, laurent.pinchart
In order to readout DP SDPs (Secondary Data Packet: DP HDR Metadata
Infoframe SDP, DP VSC SDP), it refactors handling DP SDPs codes.
It adds new compute routines for DP HDR Metadata Infoframe SDP
and DP VSC SDP.
And new writing routines of DP SDPs (Secondary Data Packet) that uses
computed configs.
New reading routines of DP SDPs are added for readout.
It adds a logging function for DP VSC SDP.
When receiving video it is very useful to be able to log DP VSC SDP.
This greatly simplifies debugging.
In order to use a common VSC SDP Colorimetry calculating code on PSR,
it uses a new psr vsc sdp compute routine.
v2: Minor style fix
v3:
- Add a new drm data structure for DP VSC SDP
- Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp
- Move logging functions to drm core [Jani N]
And use drm core's DP VSC SDP logging function
- Explicitly disable unused DIPs (AVI, GCP, VS, SPD, DRM. They will be
used for HDMI), when intel_dp_set_infoframes() function will be called.
v4:
- Use struct drm_device logging macros
- Rebased
v5:
- Use intel_de_*() functions for register access
- Add warning where a bpc is 6 and a pixel format is RGB.
- Addressed review comments from Uma
Add kernel docs for added data structures
Rename enum dp_colorspace to dp_pixelformat
Polish commit message and comments
Combine the if checks of sdp.HB2 and sdp.HB3
Add 6bpc to packining and unpacking of VSC SDP
v6: Fix enabled infoframe states of lspcon
v7: Fix the wrong check of combination bpc 6 and RGB pixelformat
v8: Rebased
v9: Add clear comments to hdmi_drm_infoframe_unpack_only() and
hdmi_drm_infoframe_unpack() (Laurent Pinchart)
v10:
- Fix packing of VSC SDP where Pixel Encoding/Colorimetry Format is not
supported
- When a PSR is enabled, it needs to add DP_SDP_VSC to infoframes.enable.
- Change a checking of PSR state.
- Skip checking of VSC SDP when a crtc config has psr.
- Rebased
v11: If PSR is disabled by flag, it don't enable psr on pipe compute
v12: Fix an inconsistent indenting
Gwan-gyeong Mun (14):
video/hdmi: Add Unpack only function for DRM infoframe
drm/i915/dp: Read out DP SDPs
drm: Add logging function for DP VSC SDP
drm/i915: Include HDMI DRM infoframe in the crtc state dump
drm/i915: Include DP HDR Metadata Infoframe SDP in the crtc state dump
drm/i915: Include DP VSC SDP in the crtc state dump
drm/i915: Program DP SDPs with computed configs
drm/i915: Add state readout for DP HDR Metadata Infoframe SDP
drm/i915: Add state readout for DP VSC SDP
drm/i915: Fix enabled infoframe states of lspcon
drm/i915: Program DP SDPs on pipe updates
drm/i915: Stop sending DP SDPs on ddi disable
drm/i915/dp: Add compute routine for DP PSR VSC SDP
drm/i915/psr: Use new DP VSC SDP compute routine on PSR
drivers/gpu/drm/drm_dp_helper.c | 174 ++++++++
drivers/gpu/drm/i915/display/intel_ddi.c | 19 +-
drivers/gpu/drm/i915/display/intel_display.c | 63 +++
drivers/gpu/drm/i915/display/intel_dp.c | 406 ++++++++++---------
drivers/gpu/drm/i915/display/intel_dp.h | 15 +-
drivers/gpu/drm/i915/display/intel_lspcon.c | 2 +-
drivers/gpu/drm/i915/display/intel_psr.c | 58 +--
drivers/gpu/drm/i915/display/intel_psr.h | 6 +-
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/video/hdmi.c | 65 ++-
include/drm/drm_dp_helper.h | 3 +
include/linux/hdmi.h | 2 +
12 files changed, 551 insertions(+), 263 deletions(-)
--
2.25.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 73+ messages in thread* [PATCH v12 00/14] In order to readout DP SDPs, refactors the handling of DP SDPs
@ 2020-05-14 6:07 ` Gwan-gyeong Mun
0 siblings, 0 replies; 73+ messages in thread
From: Gwan-gyeong Mun @ 2020-05-14 6:07 UTC (permalink / raw)
To: intel-gfx; +Cc: linux-fbdev, dri-devel, laurent.pinchart
In order to readout DP SDPs (Secondary Data Packet: DP HDR Metadata
Infoframe SDP, DP VSC SDP), it refactors handling DP SDPs codes.
It adds new compute routines for DP HDR Metadata Infoframe SDP
and DP VSC SDP.
And new writing routines of DP SDPs (Secondary Data Packet) that uses
computed configs.
New reading routines of DP SDPs are added for readout.
It adds a logging function for DP VSC SDP.
When receiving video it is very useful to be able to log DP VSC SDP.
This greatly simplifies debugging.
In order to use a common VSC SDP Colorimetry calculating code on PSR,
it uses a new psr vsc sdp compute routine.
v2: Minor style fix
v3:
- Add a new drm data structure for DP VSC SDP
- Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp
- Move logging functions to drm core [Jani N]
And use drm core's DP VSC SDP logging function
- Explicitly disable unused DIPs (AVI, GCP, VS, SPD, DRM. They will be
used for HDMI), when intel_dp_set_infoframes() function will be called.
v4:
- Use struct drm_device logging macros
- Rebased
v5:
- Use intel_de_*() functions for register access
- Add warning where a bpc is 6 and a pixel format is RGB.
- Addressed review comments from Uma
Add kernel docs for added data structures
Rename enum dp_colorspace to dp_pixelformat
Polish commit message and comments
Combine the if checks of sdp.HB2 and sdp.HB3
Add 6bpc to packining and unpacking of VSC SDP
v6: Fix enabled infoframe states of lspcon
v7: Fix the wrong check of combination bpc 6 and RGB pixelformat
v8: Rebased
v9: Add clear comments to hdmi_drm_infoframe_unpack_only() and
hdmi_drm_infoframe_unpack() (Laurent Pinchart)
v10:
- Fix packing of VSC SDP where Pixel Encoding/Colorimetry Format is not
supported
- When a PSR is enabled, it needs to add DP_SDP_VSC to infoframes.enable.
- Change a checking of PSR state.
- Skip checking of VSC SDP when a crtc config has psr.
- Rebased
v11: If PSR is disabled by flag, it don't enable psr on pipe compute
v12: Fix an inconsistent indenting
Gwan-gyeong Mun (14):
video/hdmi: Add Unpack only function for DRM infoframe
drm/i915/dp: Read out DP SDPs
drm: Add logging function for DP VSC SDP
drm/i915: Include HDMI DRM infoframe in the crtc state dump
drm/i915: Include DP HDR Metadata Infoframe SDP in the crtc state dump
drm/i915: Include DP VSC SDP in the crtc state dump
drm/i915: Program DP SDPs with computed configs
drm/i915: Add state readout for DP HDR Metadata Infoframe SDP
drm/i915: Add state readout for DP VSC SDP
drm/i915: Fix enabled infoframe states of lspcon
drm/i915: Program DP SDPs on pipe updates
drm/i915: Stop sending DP SDPs on ddi disable
drm/i915/dp: Add compute routine for DP PSR VSC SDP
drm/i915/psr: Use new DP VSC SDP compute routine on PSR
drivers/gpu/drm/drm_dp_helper.c | 174 ++++++++
drivers/gpu/drm/i915/display/intel_ddi.c | 19 +-
drivers/gpu/drm/i915/display/intel_display.c | 63 +++
drivers/gpu/drm/i915/display/intel_dp.c | 406 ++++++++++---------
drivers/gpu/drm/i915/display/intel_dp.h | 15 +-
drivers/gpu/drm/i915/display/intel_lspcon.c | 2 +-
drivers/gpu/drm/i915/display/intel_psr.c | 58 +--
drivers/gpu/drm/i915/display/intel_psr.h | 6 +-
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/video/hdmi.c | 65 ++-
include/drm/drm_dp_helper.h | 3 +
include/linux/hdmi.h | 2 +
12 files changed, 551 insertions(+), 263 deletions(-)
--
2.25.0
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 73+ messages in thread* [PATCH v12 01/14] video/hdmi: Add Unpack only function for DRM infoframe
2020-05-14 6:07 ` Gwan-gyeong Mun
(?)
@ 2020-05-14 6:07 ` Gwan-gyeong Mun
-1 siblings, 0 replies; 73+ messages in thread
From: Gwan-gyeong Mun @ 2020-05-14 6:07 UTC (permalink / raw)
To: intel-gfx; +Cc: linux-fbdev, dri-devel, laurent.pinchart
It adds an unpack only function for DRM infoframe for dynamic range and
mastering infoframe readout.
It unpacks the information data block contained in the binary buffer into
a structured frame of the HDMI Dynamic Range and Mastering (DRM)
information frame.
In contrast to hdmi_drm_infoframe_unpack() function, it does not verify
a checksum.
It can be used for unpacking a DP HDR Metadata Infoframe SDP case.
DP HDR Metadata Infoframe SDP uses the same Dynamic Range and Mastering
(DRM) information (CTA-861-G spec.) such as HDMI DRM infoframe.
But DP SDP header and payload structure are different from HDMI DRM
Infoframe. Therefore unpacking DRM infoframe for DP requires skipping of
a verifying checksum.
v9: Add clear comments to hdmi_drm_infoframe_unpack_only() and
hdmi_drm_infoframe_unpack() (Laurent Pinchart)
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
---
drivers/video/hdmi.c | 65 +++++++++++++++++++++++++++++++-------------
include/linux/hdmi.h | 2 ++
2 files changed, 48 insertions(+), 19 deletions(-)
diff --git a/drivers/video/hdmi.c b/drivers/video/hdmi.c
index 856a8c4e84a2..e70792b3e367 100644
--- a/drivers/video/hdmi.c
+++ b/drivers/video/hdmi.c
@@ -1768,20 +1768,21 @@ hdmi_vendor_any_infoframe_unpack(union hdmi_vendor_any_infoframe *frame,
}
/**
- * hdmi_drm_infoframe_unpack() - unpack binary buffer to a HDMI DRM infoframe
+ * hdmi_drm_infoframe_unpack_only() - unpack binary buffer of CTA-861-G DRM
+ * infoframe DataBytes to a HDMI DRM
+ * infoframe
* @frame: HDMI DRM infoframe
* @buffer: source buffer
* @size: size of buffer
*
- * Unpacks the information contained in binary @buffer into a structured
- * @frame of the HDMI Dynamic Range and Mastering (DRM) information frame.
- * Also verifies the checksum as required by section 5.3.5 of the HDMI 1.4
- * specification.
+ * Unpacks CTA-861-G DRM infoframe DataBytes contained in the binary @buffer
+ * into a structured @frame of the HDMI Dynamic Range and Mastering (DRM)
+ * infoframe.
*
* Returns 0 on success or a negative error code on failure.
*/
-static int hdmi_drm_infoframe_unpack(struct hdmi_drm_infoframe *frame,
- const void *buffer, size_t size)
+int hdmi_drm_infoframe_unpack_only(struct hdmi_drm_infoframe *frame,
+ const void *buffer, size_t size)
{
const u8 *ptr = buffer;
const u8 *temp;
@@ -1790,23 +1791,13 @@ static int hdmi_drm_infoframe_unpack(struct hdmi_drm_infoframe *frame,
int ret;
int i;
- if (size < HDMI_INFOFRAME_SIZE(DRM))
- return -EINVAL;
-
- if (ptr[0] != HDMI_INFOFRAME_TYPE_DRM ||
- ptr[1] != 1 ||
- ptr[2] != HDMI_DRM_INFOFRAME_SIZE)
- return -EINVAL;
-
- if (hdmi_infoframe_checksum(buffer, HDMI_INFOFRAME_SIZE(DRM)) != 0)
+ if (size < HDMI_DRM_INFOFRAME_SIZE)
return -EINVAL;
ret = hdmi_drm_infoframe_init(frame);
if (ret)
return ret;
- ptr += HDMI_INFOFRAME_HEADER_SIZE;
-
frame->eotf = ptr[0] & 0x7;
frame->metadata_type = ptr[1] & 0x7;
@@ -1814,7 +1805,7 @@ static int hdmi_drm_infoframe_unpack(struct hdmi_drm_infoframe *frame,
for (i = 0; i < 3; i++) {
x_lsb = *temp++;
x_msb = *temp++;
- frame->display_primaries[i].x = (x_msb << 8) | x_lsb;
+ frame->display_primaries[i].x = (x_msb << 8) | x_lsb;
y_lsb = *temp++;
y_msb = *temp++;
frame->display_primaries[i].y = (y_msb << 8) | y_lsb;
@@ -1830,6 +1821,42 @@ static int hdmi_drm_infoframe_unpack(struct hdmi_drm_infoframe *frame,
return 0;
}
+EXPORT_SYMBOL(hdmi_drm_infoframe_unpack_only);
+
+/**
+ * hdmi_drm_infoframe_unpack() - unpack binary buffer to a HDMI DRM infoframe
+ * @frame: HDMI DRM infoframe
+ * @buffer: source buffer
+ * @size: size of buffer
+ *
+ * Unpacks the CTA-861-G DRM infoframe contained in the binary @buffer into
+ * a structured @frame of the HDMI Dynamic Range and Mastering (DRM)
+ * infoframe. It also verifies the checksum as required by section 5.3.5 of
+ * the HDMI 1.4 specification.
+ *
+ * Returns 0 on success or a negative error code on failure.
+ */
+static int hdmi_drm_infoframe_unpack(struct hdmi_drm_infoframe *frame,
+ const void *buffer, size_t size)
+{
+ const u8 *ptr = buffer;
+ int ret;
+
+ if (size < HDMI_INFOFRAME_SIZE(DRM))
+ return -EINVAL;
+
+ if (ptr[0] != HDMI_INFOFRAME_TYPE_DRM ||
+ ptr[1] != 1 ||
+ ptr[2] != HDMI_DRM_INFOFRAME_SIZE)
+ return -EINVAL;
+
+ if (hdmi_infoframe_checksum(buffer, HDMI_INFOFRAME_SIZE(DRM)) != 0)
+ return -EINVAL;
+
+ ret = hdmi_drm_infoframe_unpack_only(frame, ptr + HDMI_INFOFRAME_HEADER_SIZE,
+ size - HDMI_INFOFRAME_HEADER_SIZE);
+ return ret;
+}
/**
* hdmi_infoframe_unpack() - unpack binary buffer to a HDMI infoframe
diff --git a/include/linux/hdmi.h b/include/linux/hdmi.h
index 9613d796cfb1..50c31f1a0a2d 100644
--- a/include/linux/hdmi.h
+++ b/include/linux/hdmi.h
@@ -219,6 +219,8 @@ ssize_t hdmi_drm_infoframe_pack(struct hdmi_drm_infoframe *frame, void *buffer,
ssize_t hdmi_drm_infoframe_pack_only(const struct hdmi_drm_infoframe *frame,
void *buffer, size_t size);
int hdmi_drm_infoframe_check(struct hdmi_drm_infoframe *frame);
+int hdmi_drm_infoframe_unpack_only(struct hdmi_drm_infoframe *frame,
+ const void *buffer, size_t size);
enum hdmi_spd_sdi {
HDMI_SPD_SDI_UNKNOWN,
--
2.25.0
^ permalink raw reply related [flat|nested] 73+ messages in thread* [Intel-gfx] [PATCH v12 01/14] video/hdmi: Add Unpack only function for DRM infoframe
@ 2020-05-14 6:07 ` Gwan-gyeong Mun
0 siblings, 0 replies; 73+ messages in thread
From: Gwan-gyeong Mun @ 2020-05-14 6:07 UTC (permalink / raw)
To: intel-gfx; +Cc: linux-fbdev, dri-devel, laurent.pinchart
It adds an unpack only function for DRM infoframe for dynamic range and
mastering infoframe readout.
It unpacks the information data block contained in the binary buffer into
a structured frame of the HDMI Dynamic Range and Mastering (DRM)
information frame.
In contrast to hdmi_drm_infoframe_unpack() function, it does not verify
a checksum.
It can be used for unpacking a DP HDR Metadata Infoframe SDP case.
DP HDR Metadata Infoframe SDP uses the same Dynamic Range and Mastering
(DRM) information (CTA-861-G spec.) such as HDMI DRM infoframe.
But DP SDP header and payload structure are different from HDMI DRM
Infoframe. Therefore unpacking DRM infoframe for DP requires skipping of
a verifying checksum.
v9: Add clear comments to hdmi_drm_infoframe_unpack_only() and
hdmi_drm_infoframe_unpack() (Laurent Pinchart)
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
---
drivers/video/hdmi.c | 65 +++++++++++++++++++++++++++++++-------------
include/linux/hdmi.h | 2 ++
2 files changed, 48 insertions(+), 19 deletions(-)
diff --git a/drivers/video/hdmi.c b/drivers/video/hdmi.c
index 856a8c4e84a2..e70792b3e367 100644
--- a/drivers/video/hdmi.c
+++ b/drivers/video/hdmi.c
@@ -1768,20 +1768,21 @@ hdmi_vendor_any_infoframe_unpack(union hdmi_vendor_any_infoframe *frame,
}
/**
- * hdmi_drm_infoframe_unpack() - unpack binary buffer to a HDMI DRM infoframe
+ * hdmi_drm_infoframe_unpack_only() - unpack binary buffer of CTA-861-G DRM
+ * infoframe DataBytes to a HDMI DRM
+ * infoframe
* @frame: HDMI DRM infoframe
* @buffer: source buffer
* @size: size of buffer
*
- * Unpacks the information contained in binary @buffer into a structured
- * @frame of the HDMI Dynamic Range and Mastering (DRM) information frame.
- * Also verifies the checksum as required by section 5.3.5 of the HDMI 1.4
- * specification.
+ * Unpacks CTA-861-G DRM infoframe DataBytes contained in the binary @buffer
+ * into a structured @frame of the HDMI Dynamic Range and Mastering (DRM)
+ * infoframe.
*
* Returns 0 on success or a negative error code on failure.
*/
-static int hdmi_drm_infoframe_unpack(struct hdmi_drm_infoframe *frame,
- const void *buffer, size_t size)
+int hdmi_drm_infoframe_unpack_only(struct hdmi_drm_infoframe *frame,
+ const void *buffer, size_t size)
{
const u8 *ptr = buffer;
const u8 *temp;
@@ -1790,23 +1791,13 @@ static int hdmi_drm_infoframe_unpack(struct hdmi_drm_infoframe *frame,
int ret;
int i;
- if (size < HDMI_INFOFRAME_SIZE(DRM))
- return -EINVAL;
-
- if (ptr[0] != HDMI_INFOFRAME_TYPE_DRM ||
- ptr[1] != 1 ||
- ptr[2] != HDMI_DRM_INFOFRAME_SIZE)
- return -EINVAL;
-
- if (hdmi_infoframe_checksum(buffer, HDMI_INFOFRAME_SIZE(DRM)) != 0)
+ if (size < HDMI_DRM_INFOFRAME_SIZE)
return -EINVAL;
ret = hdmi_drm_infoframe_init(frame);
if (ret)
return ret;
- ptr += HDMI_INFOFRAME_HEADER_SIZE;
-
frame->eotf = ptr[0] & 0x7;
frame->metadata_type = ptr[1] & 0x7;
@@ -1814,7 +1805,7 @@ static int hdmi_drm_infoframe_unpack(struct hdmi_drm_infoframe *frame,
for (i = 0; i < 3; i++) {
x_lsb = *temp++;
x_msb = *temp++;
- frame->display_primaries[i].x = (x_msb << 8) | x_lsb;
+ frame->display_primaries[i].x = (x_msb << 8) | x_lsb;
y_lsb = *temp++;
y_msb = *temp++;
frame->display_primaries[i].y = (y_msb << 8) | y_lsb;
@@ -1830,6 +1821,42 @@ static int hdmi_drm_infoframe_unpack(struct hdmi_drm_infoframe *frame,
return 0;
}
+EXPORT_SYMBOL(hdmi_drm_infoframe_unpack_only);
+
+/**
+ * hdmi_drm_infoframe_unpack() - unpack binary buffer to a HDMI DRM infoframe
+ * @frame: HDMI DRM infoframe
+ * @buffer: source buffer
+ * @size: size of buffer
+ *
+ * Unpacks the CTA-861-G DRM infoframe contained in the binary @buffer into
+ * a structured @frame of the HDMI Dynamic Range and Mastering (DRM)
+ * infoframe. It also verifies the checksum as required by section 5.3.5 of
+ * the HDMI 1.4 specification.
+ *
+ * Returns 0 on success or a negative error code on failure.
+ */
+static int hdmi_drm_infoframe_unpack(struct hdmi_drm_infoframe *frame,
+ const void *buffer, size_t size)
+{
+ const u8 *ptr = buffer;
+ int ret;
+
+ if (size < HDMI_INFOFRAME_SIZE(DRM))
+ return -EINVAL;
+
+ if (ptr[0] != HDMI_INFOFRAME_TYPE_DRM ||
+ ptr[1] != 1 ||
+ ptr[2] != HDMI_DRM_INFOFRAME_SIZE)
+ return -EINVAL;
+
+ if (hdmi_infoframe_checksum(buffer, HDMI_INFOFRAME_SIZE(DRM)) != 0)
+ return -EINVAL;
+
+ ret = hdmi_drm_infoframe_unpack_only(frame, ptr + HDMI_INFOFRAME_HEADER_SIZE,
+ size - HDMI_INFOFRAME_HEADER_SIZE);
+ return ret;
+}
/**
* hdmi_infoframe_unpack() - unpack binary buffer to a HDMI infoframe
diff --git a/include/linux/hdmi.h b/include/linux/hdmi.h
index 9613d796cfb1..50c31f1a0a2d 100644
--- a/include/linux/hdmi.h
+++ b/include/linux/hdmi.h
@@ -219,6 +219,8 @@ ssize_t hdmi_drm_infoframe_pack(struct hdmi_drm_infoframe *frame, void *buffer,
ssize_t hdmi_drm_infoframe_pack_only(const struct hdmi_drm_infoframe *frame,
void *buffer, size_t size);
int hdmi_drm_infoframe_check(struct hdmi_drm_infoframe *frame);
+int hdmi_drm_infoframe_unpack_only(struct hdmi_drm_infoframe *frame,
+ const void *buffer, size_t size);
enum hdmi_spd_sdi {
HDMI_SPD_SDI_UNKNOWN,
--
2.25.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 73+ messages in thread* [PATCH v12 01/14] video/hdmi: Add Unpack only function for DRM infoframe
@ 2020-05-14 6:07 ` Gwan-gyeong Mun
0 siblings, 0 replies; 73+ messages in thread
From: Gwan-gyeong Mun @ 2020-05-14 6:07 UTC (permalink / raw)
To: intel-gfx; +Cc: linux-fbdev, dri-devel, laurent.pinchart
It adds an unpack only function for DRM infoframe for dynamic range and
mastering infoframe readout.
It unpacks the information data block contained in the binary buffer into
a structured frame of the HDMI Dynamic Range and Mastering (DRM)
information frame.
In contrast to hdmi_drm_infoframe_unpack() function, it does not verify
a checksum.
It can be used for unpacking a DP HDR Metadata Infoframe SDP case.
DP HDR Metadata Infoframe SDP uses the same Dynamic Range and Mastering
(DRM) information (CTA-861-G spec.) such as HDMI DRM infoframe.
But DP SDP header and payload structure are different from HDMI DRM
Infoframe. Therefore unpacking DRM infoframe for DP requires skipping of
a verifying checksum.
v9: Add clear comments to hdmi_drm_infoframe_unpack_only() and
hdmi_drm_infoframe_unpack() (Laurent Pinchart)
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
---
drivers/video/hdmi.c | 65 +++++++++++++++++++++++++++++++-------------
include/linux/hdmi.h | 2 ++
2 files changed, 48 insertions(+), 19 deletions(-)
diff --git a/drivers/video/hdmi.c b/drivers/video/hdmi.c
index 856a8c4e84a2..e70792b3e367 100644
--- a/drivers/video/hdmi.c
+++ b/drivers/video/hdmi.c
@@ -1768,20 +1768,21 @@ hdmi_vendor_any_infoframe_unpack(union hdmi_vendor_any_infoframe *frame,
}
/**
- * hdmi_drm_infoframe_unpack() - unpack binary buffer to a HDMI DRM infoframe
+ * hdmi_drm_infoframe_unpack_only() - unpack binary buffer of CTA-861-G DRM
+ * infoframe DataBytes to a HDMI DRM
+ * infoframe
* @frame: HDMI DRM infoframe
* @buffer: source buffer
* @size: size of buffer
*
- * Unpacks the information contained in binary @buffer into a structured
- * @frame of the HDMI Dynamic Range and Mastering (DRM) information frame.
- * Also verifies the checksum as required by section 5.3.5 of the HDMI 1.4
- * specification.
+ * Unpacks CTA-861-G DRM infoframe DataBytes contained in the binary @buffer
+ * into a structured @frame of the HDMI Dynamic Range and Mastering (DRM)
+ * infoframe.
*
* Returns 0 on success or a negative error code on failure.
*/
-static int hdmi_drm_infoframe_unpack(struct hdmi_drm_infoframe *frame,
- const void *buffer, size_t size)
+int hdmi_drm_infoframe_unpack_only(struct hdmi_drm_infoframe *frame,
+ const void *buffer, size_t size)
{
const u8 *ptr = buffer;
const u8 *temp;
@@ -1790,23 +1791,13 @@ static int hdmi_drm_infoframe_unpack(struct hdmi_drm_infoframe *frame,
int ret;
int i;
- if (size < HDMI_INFOFRAME_SIZE(DRM))
- return -EINVAL;
-
- if (ptr[0] != HDMI_INFOFRAME_TYPE_DRM ||
- ptr[1] != 1 ||
- ptr[2] != HDMI_DRM_INFOFRAME_SIZE)
- return -EINVAL;
-
- if (hdmi_infoframe_checksum(buffer, HDMI_INFOFRAME_SIZE(DRM)) != 0)
+ if (size < HDMI_DRM_INFOFRAME_SIZE)
return -EINVAL;
ret = hdmi_drm_infoframe_init(frame);
if (ret)
return ret;
- ptr += HDMI_INFOFRAME_HEADER_SIZE;
-
frame->eotf = ptr[0] & 0x7;
frame->metadata_type = ptr[1] & 0x7;
@@ -1814,7 +1805,7 @@ static int hdmi_drm_infoframe_unpack(struct hdmi_drm_infoframe *frame,
for (i = 0; i < 3; i++) {
x_lsb = *temp++;
x_msb = *temp++;
- frame->display_primaries[i].x = (x_msb << 8) | x_lsb;
+ frame->display_primaries[i].x = (x_msb << 8) | x_lsb;
y_lsb = *temp++;
y_msb = *temp++;
frame->display_primaries[i].y = (y_msb << 8) | y_lsb;
@@ -1830,6 +1821,42 @@ static int hdmi_drm_infoframe_unpack(struct hdmi_drm_infoframe *frame,
return 0;
}
+EXPORT_SYMBOL(hdmi_drm_infoframe_unpack_only);
+
+/**
+ * hdmi_drm_infoframe_unpack() - unpack binary buffer to a HDMI DRM infoframe
+ * @frame: HDMI DRM infoframe
+ * @buffer: source buffer
+ * @size: size of buffer
+ *
+ * Unpacks the CTA-861-G DRM infoframe contained in the binary @buffer into
+ * a structured @frame of the HDMI Dynamic Range and Mastering (DRM)
+ * infoframe. It also verifies the checksum as required by section 5.3.5 of
+ * the HDMI 1.4 specification.
+ *
+ * Returns 0 on success or a negative error code on failure.
+ */
+static int hdmi_drm_infoframe_unpack(struct hdmi_drm_infoframe *frame,
+ const void *buffer, size_t size)
+{
+ const u8 *ptr = buffer;
+ int ret;
+
+ if (size < HDMI_INFOFRAME_SIZE(DRM))
+ return -EINVAL;
+
+ if (ptr[0] != HDMI_INFOFRAME_TYPE_DRM ||
+ ptr[1] != 1 ||
+ ptr[2] != HDMI_DRM_INFOFRAME_SIZE)
+ return -EINVAL;
+
+ if (hdmi_infoframe_checksum(buffer, HDMI_INFOFRAME_SIZE(DRM)) != 0)
+ return -EINVAL;
+
+ ret = hdmi_drm_infoframe_unpack_only(frame, ptr + HDMI_INFOFRAME_HEADER_SIZE,
+ size - HDMI_INFOFRAME_HEADER_SIZE);
+ return ret;
+}
/**
* hdmi_infoframe_unpack() - unpack binary buffer to a HDMI infoframe
diff --git a/include/linux/hdmi.h b/include/linux/hdmi.h
index 9613d796cfb1..50c31f1a0a2d 100644
--- a/include/linux/hdmi.h
+++ b/include/linux/hdmi.h
@@ -219,6 +219,8 @@ ssize_t hdmi_drm_infoframe_pack(struct hdmi_drm_infoframe *frame, void *buffer,
ssize_t hdmi_drm_infoframe_pack_only(const struct hdmi_drm_infoframe *frame,
void *buffer, size_t size);
int hdmi_drm_infoframe_check(struct hdmi_drm_infoframe *frame);
+int hdmi_drm_infoframe_unpack_only(struct hdmi_drm_infoframe *frame,
+ const void *buffer, size_t size);
enum hdmi_spd_sdi {
HDMI_SPD_SDI_UNKNOWN,
--
2.25.0
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 73+ messages in thread* Re: [Intel-gfx] [PATCH v12 01/14] video/hdmi: Add Unpack only function for DRM infoframe
2020-05-14 6:07 ` Gwan-gyeong Mun
(?)
@ 2020-05-14 6:23 ` Mun, Gwan-gyeong
-1 siblings, 0 replies; 73+ messages in thread
From: Mun, Gwan-gyeong @ 2020-05-14 6:23 UTC (permalink / raw)
To: b.zolnierkie; +Cc: linux-fbdev, intel-gfx, laurent.pinchart, dri-devel
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^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [Intel-gfx] [PATCH v12 01/14] video/hdmi: Add Unpack only function for DRM infoframe
@ 2020-05-14 6:23 ` Mun, Gwan-gyeong
0 siblings, 0 replies; 73+ messages in thread
From: Mun, Gwan-gyeong @ 2020-05-14 6:23 UTC (permalink / raw)
To: b.zolnierkie; +Cc: linux-fbdev, intel-gfx, laurent.pinchart, dri-devel
Hi Bartlomiej and Laurent Pinchart, can I have your ack for merging
this via drm-intel along
with the rest of the series, please?
BR,
G.G.
On Thu, 2020-05-14 at 09:07 +0300, Gwan-gyeong Mun wrote:
> It adds an unpack only function for DRM infoframe for dynamic range
> and
> mastering infoframe readout.
> It unpacks the information data block contained in the binary buffer
> into
> a structured frame of the HDMI Dynamic Range and Mastering (DRM)
> information frame.
>
> In contrast to hdmi_drm_infoframe_unpack() function, it does not
> verify
> a checksum.
>
> It can be used for unpacking a DP HDR Metadata Infoframe SDP case.
> DP HDR Metadata Infoframe SDP uses the same Dynamic Range and
> Mastering
> (DRM) information (CTA-861-G spec.) such as HDMI DRM infoframe.
> But DP SDP header and payload structure are different from HDMI DRM
> Infoframe. Therefore unpacking DRM infoframe for DP requires skipping
> of
> a verifying checksum.
>
> v9: Add clear comments to hdmi_drm_infoframe_unpack_only() and
> hdmi_drm_infoframe_unpack() (Laurent Pinchart)
>
> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> ---
> drivers/video/hdmi.c | 65 +++++++++++++++++++++++++++++++-----------
> --
> include/linux/hdmi.h | 2 ++
> 2 files changed, 48 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/video/hdmi.c b/drivers/video/hdmi.c
> index 856a8c4e84a2..e70792b3e367 100644
> --- a/drivers/video/hdmi.c
> +++ b/drivers/video/hdmi.c
> @@ -1768,20 +1768,21 @@ hdmi_vendor_any_infoframe_unpack(union
> hdmi_vendor_any_infoframe *frame,
> }
>
> /**
> - * hdmi_drm_infoframe_unpack() - unpack binary buffer to a HDMI DRM
> infoframe
> + * hdmi_drm_infoframe_unpack_only() - unpack binary buffer of CTA-
> 861-G DRM
> + * infoframe DataBytes to a HDMI
> DRM
> + * infoframe
> * @frame: HDMI DRM infoframe
> * @buffer: source buffer
> * @size: size of buffer
> *
> - * Unpacks the information contained in binary @buffer into a
> structured
> - * @frame of the HDMI Dynamic Range and Mastering (DRM) information
> frame.
> - * Also verifies the checksum as required by section 5.3.5 of the
> HDMI 1.4
> - * specification.
> + * Unpacks CTA-861-G DRM infoframe DataBytes contained in the binary
> @buffer
> + * into a structured @frame of the HDMI Dynamic Range and Mastering
> (DRM)
> + * infoframe.
> *
> * Returns 0 on success or a negative error code on failure.
> */
> -static int hdmi_drm_infoframe_unpack(struct hdmi_drm_infoframe
> *frame,
> - const void *buffer, size_t size)
> +int hdmi_drm_infoframe_unpack_only(struct hdmi_drm_infoframe *frame,
> + const void *buffer, size_t size)
> {
> const u8 *ptr = buffer;
> const u8 *temp;
> @@ -1790,23 +1791,13 @@ static int hdmi_drm_infoframe_unpack(struct
> hdmi_drm_infoframe *frame,
> int ret;
> int i;
>
> - if (size < HDMI_INFOFRAME_SIZE(DRM))
> - return -EINVAL;
> -
> - if (ptr[0] != HDMI_INFOFRAME_TYPE_DRM ||
> - ptr[1] != 1 ||
> - ptr[2] != HDMI_DRM_INFOFRAME_SIZE)
> - return -EINVAL;
> -
> - if (hdmi_infoframe_checksum(buffer, HDMI_INFOFRAME_SIZE(DRM))
> != 0)
> + if (size < HDMI_DRM_INFOFRAME_SIZE)
> return -EINVAL;
>
> ret = hdmi_drm_infoframe_init(frame);
> if (ret)
> return ret;
>
> - ptr += HDMI_INFOFRAME_HEADER_SIZE;
> -
> frame->eotf = ptr[0] & 0x7;
> frame->metadata_type = ptr[1] & 0x7;
>
> @@ -1814,7 +1805,7 @@ static int hdmi_drm_infoframe_unpack(struct
> hdmi_drm_infoframe *frame,
> for (i = 0; i < 3; i++) {
> x_lsb = *temp++;
> x_msb = *temp++;
> - frame->display_primaries[i].x = (x_msb << 8) | x_lsb;
> + frame->display_primaries[i].x = (x_msb << 8) | x_lsb;
> y_lsb = *temp++;
> y_msb = *temp++;
> frame->display_primaries[i].y = (y_msb << 8) | y_lsb;
> @@ -1830,6 +1821,42 @@ static int hdmi_drm_infoframe_unpack(struct
> hdmi_drm_infoframe *frame,
>
> return 0;
> }
> +EXPORT_SYMBOL(hdmi_drm_infoframe_unpack_only);
> +
> +/**
> + * hdmi_drm_infoframe_unpack() - unpack binary buffer to a HDMI DRM
> infoframe
> + * @frame: HDMI DRM infoframe
> + * @buffer: source buffer
> + * @size: size of buffer
> + *
> + * Unpacks the CTA-861-G DRM infoframe contained in the binary
> @buffer into
> + * a structured @frame of the HDMI Dynamic Range and Mastering (DRM)
> + * infoframe. It also verifies the checksum as required by section
> 5.3.5 of
> + * the HDMI 1.4 specification.
> + *
> + * Returns 0 on success or a negative error code on failure.
> + */
> +static int hdmi_drm_infoframe_unpack(struct hdmi_drm_infoframe
> *frame,
> + const void *buffer, size_t size)
> +{
> + const u8 *ptr = buffer;
> + int ret;
> +
> + if (size < HDMI_INFOFRAME_SIZE(DRM))
> + return -EINVAL;
> +
> + if (ptr[0] != HDMI_INFOFRAME_TYPE_DRM ||
> + ptr[1] != 1 ||
> + ptr[2] != HDMI_DRM_INFOFRAME_SIZE)
> + return -EINVAL;
> +
> + if (hdmi_infoframe_checksum(buffer, HDMI_INFOFRAME_SIZE(DRM))
> != 0)
> + return -EINVAL;
> +
> + ret = hdmi_drm_infoframe_unpack_only(frame, ptr +
> HDMI_INFOFRAME_HEADER_SIZE,
> + size -
> HDMI_INFOFRAME_HEADER_SIZE);
> + return ret;
> +}
>
> /**
> * hdmi_infoframe_unpack() - unpack binary buffer to a HDMI
> infoframe
> diff --git a/include/linux/hdmi.h b/include/linux/hdmi.h
> index 9613d796cfb1..50c31f1a0a2d 100644
> --- a/include/linux/hdmi.h
> +++ b/include/linux/hdmi.h
> @@ -219,6 +219,8 @@ ssize_t hdmi_drm_infoframe_pack(struct
> hdmi_drm_infoframe *frame, void *buffer,
> ssize_t hdmi_drm_infoframe_pack_only(const struct hdmi_drm_infoframe
> *frame,
> void *buffer, size_t size);
> int hdmi_drm_infoframe_check(struct hdmi_drm_infoframe *frame);
> +int hdmi_drm_infoframe_unpack_only(struct hdmi_drm_infoframe *frame,
> + const void *buffer, size_t size);
>
> enum hdmi_spd_sdi {
> HDMI_SPD_SDI_UNKNOWN,
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^ permalink raw reply [flat|nested] 73+ messages in thread* Re: [Intel-gfx] [PATCH v12 01/14] video/hdmi: Add Unpack only function for DRM infoframe
@ 2020-05-14 6:23 ` Mun, Gwan-gyeong
0 siblings, 0 replies; 73+ messages in thread
From: Mun, Gwan-gyeong @ 2020-05-14 6:23 UTC (permalink / raw)
To: b.zolnierkie; +Cc: linux-fbdev, intel-gfx, laurent.pinchart, dri-devel
Hi Bartlomiej and Laurent Pinchart, can I have your ack for merging
this via drm-intel along
with the rest of the series, please?
BR,
G.G.
On Thu, 2020-05-14 at 09:07 +0300, Gwan-gyeong Mun wrote:
> It adds an unpack only function for DRM infoframe for dynamic range
> and
> mastering infoframe readout.
> It unpacks the information data block contained in the binary buffer
> into
> a structured frame of the HDMI Dynamic Range and Mastering (DRM)
> information frame.
>
> In contrast to hdmi_drm_infoframe_unpack() function, it does not
> verify
> a checksum.
>
> It can be used for unpacking a DP HDR Metadata Infoframe SDP case.
> DP HDR Metadata Infoframe SDP uses the same Dynamic Range and
> Mastering
> (DRM) information (CTA-861-G spec.) such as HDMI DRM infoframe.
> But DP SDP header and payload structure are different from HDMI DRM
> Infoframe. Therefore unpacking DRM infoframe for DP requires skipping
> of
> a verifying checksum.
>
> v9: Add clear comments to hdmi_drm_infoframe_unpack_only() and
> hdmi_drm_infoframe_unpack() (Laurent Pinchart)
>
> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> ---
> drivers/video/hdmi.c | 65 +++++++++++++++++++++++++++++++-----------
> --
> include/linux/hdmi.h | 2 ++
> 2 files changed, 48 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/video/hdmi.c b/drivers/video/hdmi.c
> index 856a8c4e84a2..e70792b3e367 100644
> --- a/drivers/video/hdmi.c
> +++ b/drivers/video/hdmi.c
> @@ -1768,20 +1768,21 @@ hdmi_vendor_any_infoframe_unpack(union
> hdmi_vendor_any_infoframe *frame,
> }
>
> /**
> - * hdmi_drm_infoframe_unpack() - unpack binary buffer to a HDMI DRM
> infoframe
> + * hdmi_drm_infoframe_unpack_only() - unpack binary buffer of CTA-
> 861-G DRM
> + * infoframe DataBytes to a HDMI
> DRM
> + * infoframe
> * @frame: HDMI DRM infoframe
> * @buffer: source buffer
> * @size: size of buffer
> *
> - * Unpacks the information contained in binary @buffer into a
> structured
> - * @frame of the HDMI Dynamic Range and Mastering (DRM) information
> frame.
> - * Also verifies the checksum as required by section 5.3.5 of the
> HDMI 1.4
> - * specification.
> + * Unpacks CTA-861-G DRM infoframe DataBytes contained in the binary
> @buffer
> + * into a structured @frame of the HDMI Dynamic Range and Mastering
> (DRM)
> + * infoframe.
> *
> * Returns 0 on success or a negative error code on failure.
> */
> -static int hdmi_drm_infoframe_unpack(struct hdmi_drm_infoframe
> *frame,
> - const void *buffer, size_t size)
> +int hdmi_drm_infoframe_unpack_only(struct hdmi_drm_infoframe *frame,
> + const void *buffer, size_t size)
> {
> const u8 *ptr = buffer;
> const u8 *temp;
> @@ -1790,23 +1791,13 @@ static int hdmi_drm_infoframe_unpack(struct
> hdmi_drm_infoframe *frame,
> int ret;
> int i;
>
> - if (size < HDMI_INFOFRAME_SIZE(DRM))
> - return -EINVAL;
> -
> - if (ptr[0] != HDMI_INFOFRAME_TYPE_DRM ||
> - ptr[1] != 1 ||
> - ptr[2] != HDMI_DRM_INFOFRAME_SIZE)
> - return -EINVAL;
> -
> - if (hdmi_infoframe_checksum(buffer, HDMI_INFOFRAME_SIZE(DRM))
> != 0)
> + if (size < HDMI_DRM_INFOFRAME_SIZE)
> return -EINVAL;
>
> ret = hdmi_drm_infoframe_init(frame);
> if (ret)
> return ret;
>
> - ptr += HDMI_INFOFRAME_HEADER_SIZE;
> -
> frame->eotf = ptr[0] & 0x7;
> frame->metadata_type = ptr[1] & 0x7;
>
> @@ -1814,7 +1805,7 @@ static int hdmi_drm_infoframe_unpack(struct
> hdmi_drm_infoframe *frame,
> for (i = 0; i < 3; i++) {
> x_lsb = *temp++;
> x_msb = *temp++;
> - frame->display_primaries[i].x = (x_msb << 8) | x_lsb;
> + frame->display_primaries[i].x = (x_msb << 8) | x_lsb;
> y_lsb = *temp++;
> y_msb = *temp++;
> frame->display_primaries[i].y = (y_msb << 8) | y_lsb;
> @@ -1830,6 +1821,42 @@ static int hdmi_drm_infoframe_unpack(struct
> hdmi_drm_infoframe *frame,
>
> return 0;
> }
> +EXPORT_SYMBOL(hdmi_drm_infoframe_unpack_only);
> +
> +/**
> + * hdmi_drm_infoframe_unpack() - unpack binary buffer to a HDMI DRM
> infoframe
> + * @frame: HDMI DRM infoframe
> + * @buffer: source buffer
> + * @size: size of buffer
> + *
> + * Unpacks the CTA-861-G DRM infoframe contained in the binary
> @buffer into
> + * a structured @frame of the HDMI Dynamic Range and Mastering (DRM)
> + * infoframe. It also verifies the checksum as required by section
> 5.3.5 of
> + * the HDMI 1.4 specification.
> + *
> + * Returns 0 on success or a negative error code on failure.
> + */
> +static int hdmi_drm_infoframe_unpack(struct hdmi_drm_infoframe
> *frame,
> + const void *buffer, size_t size)
> +{
> + const u8 *ptr = buffer;
> + int ret;
> +
> + if (size < HDMI_INFOFRAME_SIZE(DRM))
> + return -EINVAL;
> +
> + if (ptr[0] != HDMI_INFOFRAME_TYPE_DRM ||
> + ptr[1] != 1 ||
> + ptr[2] != HDMI_DRM_INFOFRAME_SIZE)
> + return -EINVAL;
> +
> + if (hdmi_infoframe_checksum(buffer, HDMI_INFOFRAME_SIZE(DRM))
> != 0)
> + return -EINVAL;
> +
> + ret = hdmi_drm_infoframe_unpack_only(frame, ptr +
> HDMI_INFOFRAME_HEADER_SIZE,
> + size -
> HDMI_INFOFRAME_HEADER_SIZE);
> + return ret;
> +}
>
> /**
> * hdmi_infoframe_unpack() - unpack binary buffer to a HDMI
> infoframe
> diff --git a/include/linux/hdmi.h b/include/linux/hdmi.h
> index 9613d796cfb1..50c31f1a0a2d 100644
> --- a/include/linux/hdmi.h
> +++ b/include/linux/hdmi.h
> @@ -219,6 +219,8 @@ ssize_t hdmi_drm_infoframe_pack(struct
> hdmi_drm_infoframe *frame, void *buffer,
> ssize_t hdmi_drm_infoframe_pack_only(const struct hdmi_drm_infoframe
> *frame,
> void *buffer, size_t size);
> int hdmi_drm_infoframe_check(struct hdmi_drm_infoframe *frame);
> +int hdmi_drm_infoframe_unpack_only(struct hdmi_drm_infoframe *frame,
> + const void *buffer, size_t size);
>
> enum hdmi_spd_sdi {
> HDMI_SPD_SDI_UNKNOWN,
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^ permalink raw reply [flat|nested] 73+ messages in thread
* [PATCH v12 02/14] drm/i915/dp: Read out DP SDPs
2020-05-14 6:07 ` Gwan-gyeong Mun
(?)
@ 2020-05-14 6:07 ` Gwan-gyeong Mun
-1 siblings, 0 replies; 73+ messages in thread
From: Gwan-gyeong Mun @ 2020-05-14 6:07 UTC (permalink / raw)
To: intel-gfx; +Cc: linux-fbdev, dri-devel, laurent.pinchart
It adds code to read the DP SDPs from the video DIP and unpack them into
the crtc state.
It adds routines that read out DP VSC SDP and DP HDR Metadata Infoframe SDP
In order to unpack DP VSC SDP, it adds intel_dp_vsc_sdp_unpack() function.
It follows DP 1.4a spec. [Table 2-116: VSC SDP Header Bytes] and
[Table 2-117: VSC SDP Payload for DB16 through DB18]
In order to unpack DP HDR Metadata Infoframe SDP, it adds
intel_dp_hdr_metadata_infoframe_sdp_unpack(). And it follows DP 1.4a spec.
([Table 2-125: INFOFRAME SDP v1.2 Header Bytes] and
[Table 2-126: INFOFRAME SDP v1.2 Payload Data Bytes - DB0 through DB31])
and CTA-861-G spec. [Table-42 Dynamic Range and Mastering InfoFrame].
A naming rule and style of intel_read_dp_sdp() function references
intel_read_infoframe() function of intel_hdmi.c
v2: Minor style fix
v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp
v4: Use struct drm_device logging macros
v5: Addressed review comments from Uma
- Polish commit message and comments
- Combine the if checks of sdp.HB2 and sdp.HB3
- Add 6bpc to unpacking of VSC SDP
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 187 ++++++++++++++++++++++++
drivers/gpu/drm/i915/display/intel_dp.h | 3 +
2 files changed, 190 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 67723dede1d1..84c0105be61b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4971,6 +4971,193 @@ void intel_dp_set_infoframes(struct intel_encoder *encoder,
intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA);
}
+static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc,
+ const void *buffer, size_t size)
+{
+ const struct dp_sdp *sdp = buffer;
+
+ if (size < sizeof(struct dp_sdp))
+ return -EINVAL;
+
+ memset(vsc, 0, size);
+
+ if (sdp->sdp_header.HB0 != 0)
+ return -EINVAL;
+
+ if (sdp->sdp_header.HB1 != DP_SDP_VSC)
+ return -EINVAL;
+
+ vsc->sdp_type = sdp->sdp_header.HB1;
+ vsc->revision = sdp->sdp_header.HB2;
+ vsc->length = sdp->sdp_header.HB3;
+
+ if ((sdp->sdp_header.HB2 = 0x2 && sdp->sdp_header.HB3 = 0x8) ||
+ (sdp->sdp_header.HB2 = 0x4 && sdp->sdp_header.HB3 = 0xe)) {
+ /*
+ * - HB2 = 0x2, HB3 = 0x8
+ * VSC SDP supporting 3D stereo + PSR
+ * - HB2 = 0x4, HB3 = 0xe
+ * VSC SDP supporting 3D stereo + PSR2 with Y-coordinate of
+ * first scan line of the SU region (applies to eDP v1.4b
+ * and higher).
+ */
+ return 0;
+ } else if (sdp->sdp_header.HB2 = 0x5 && sdp->sdp_header.HB3 = 0x13) {
+ /*
+ * - HB2 = 0x5, HB3 = 0x13
+ * VSC SDP supporting 3D stereo + PSR2 + Pixel Encoding/Colorimetry
+ * Format.
+ */
+ vsc->pixelformat = (sdp->db[16] >> 4) & 0xf;
+ vsc->colorimetry = sdp->db[16] & 0xf;
+ vsc->dynamic_range = (sdp->db[17] >> 7) & 0x1;
+
+ switch (sdp->db[17] & 0x7) {
+ case 0x0:
+ vsc->bpc = 6;
+ break;
+ case 0x1:
+ vsc->bpc = 8;
+ break;
+ case 0x2:
+ vsc->bpc = 10;
+ break;
+ case 0x3:
+ vsc->bpc = 12;
+ break;
+ case 0x4:
+ vsc->bpc = 16;
+ break;
+ default:
+ MISSING_CASE(sdp->db[17] & 0x7);
+ return -EINVAL;
+ }
+
+ vsc->content_type = sdp->db[18] & 0x7;
+ } else {
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int
+intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe *drm_infoframe,
+ const void *buffer, size_t size)
+{
+ int ret;
+
+ const struct dp_sdp *sdp = buffer;
+
+ if (size < sizeof(struct dp_sdp))
+ return -EINVAL;
+
+ if (sdp->sdp_header.HB0 != 0)
+ return -EINVAL;
+
+ if (sdp->sdp_header.HB1 != HDMI_INFOFRAME_TYPE_DRM)
+ return -EINVAL;
+
+ /*
+ * Least Significant Eight Bits of (Data Byte Count – 1)
+ * 1Dh (i.e., Data Byte Count = 30 bytes).
+ */
+ if (sdp->sdp_header.HB2 != 0x1D)
+ return -EINVAL;
+
+ /* Most Significant Two Bits of (Data Byte Count – 1), Clear to 00b. */
+ if ((sdp->sdp_header.HB3 & 0x3) != 0)
+ return -EINVAL;
+
+ /* INFOFRAME SDP Version Number */
+ if (((sdp->sdp_header.HB3 >> 2) & 0x3f) != 0x13)
+ return -EINVAL;
+
+ /* CTA Header Byte 2 (INFOFRAME Version Number) */
+ if (sdp->db[0] != 1)
+ return -EINVAL;
+
+ /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
+ if (sdp->db[1] != HDMI_DRM_INFOFRAME_SIZE)
+ return -EINVAL;
+
+ ret = hdmi_drm_infoframe_unpack_only(drm_infoframe, &sdp->db[2],
+ HDMI_DRM_INFOFRAME_SIZE);
+
+ return ret;
+}
+
+static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state,
+ struct drm_dp_vsc_sdp *vsc)
+{
+ struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ unsigned int type = DP_SDP_VSC;
+ struct dp_sdp sdp = {};
+ int ret;
+
+ /* When PSR is enabled, VSC SDP is handled by PSR routine */
+ if (intel_psr_enabled(intel_dp))
+ return;
+
+ if ((crtc_state->infoframes.enable &
+ intel_hdmi_infoframe_enable(type)) = 0)
+ return;
+
+ intel_dig_port->read_infoframe(encoder, crtc_state, type, &sdp, sizeof(sdp));
+
+ ret = intel_dp_vsc_sdp_unpack(vsc, &sdp, sizeof(sdp));
+
+ if (ret)
+ drm_dbg_kms(&dev_priv->drm, "Failed to unpack DP VSC SDP\n");
+}
+
+static void intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state,
+ struct hdmi_drm_infoframe *drm_infoframe)
+{
+ struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ unsigned int type = HDMI_PACKET_TYPE_GAMUT_METADATA;
+ struct dp_sdp sdp = {};
+ int ret;
+
+ if ((crtc_state->infoframes.enable &
+ intel_hdmi_infoframe_enable(type)) = 0)
+ return;
+
+ intel_dig_port->read_infoframe(encoder, crtc_state, type, &sdp,
+ sizeof(sdp));
+
+ ret = intel_dp_hdr_metadata_infoframe_sdp_unpack(drm_infoframe, &sdp,
+ sizeof(sdp));
+
+ if (ret)
+ drm_dbg_kms(&dev_priv->drm,
+ "Failed to unpack DP HDR Metadata Infoframe SDP\n");
+}
+
+void intel_read_dp_sdp(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state,
+ unsigned int type)
+{
+ switch (type) {
+ case DP_SDP_VSC:
+ intel_read_dp_vsc_sdp(encoder, crtc_state,
+ &crtc_state->infoframes.vsc);
+ break;
+ case HDMI_PACKET_TYPE_GAMUT_METADATA:
+ intel_read_dp_hdr_metadata_infoframe_sdp(encoder, crtc_state,
+ &crtc_state->infoframes.drm.drm);
+ break;
+ default:
+ MISSING_CASE(type);
+ break;
+ }
+}
+
static void
intel_dp_setup_vsc_sdp(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state,
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 6659ce15a693..faa2a3c5ee4e 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -117,6 +117,9 @@ void intel_dp_hdr_metadata_enable(struct intel_dp *intel_dp,
void intel_dp_set_infoframes(struct intel_encoder *encoder, bool enable,
const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state);
+void intel_read_dp_sdp(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state,
+ unsigned int type);
bool intel_digital_port_connected(struct intel_encoder *encoder);
void intel_dp_process_phy_request(struct intel_dp *intel_dp);
--
2.25.0
^ permalink raw reply related [flat|nested] 73+ messages in thread* [Intel-gfx] [PATCH v12 02/14] drm/i915/dp: Read out DP SDPs
@ 2020-05-14 6:07 ` Gwan-gyeong Mun
0 siblings, 0 replies; 73+ messages in thread
From: Gwan-gyeong Mun @ 2020-05-14 6:07 UTC (permalink / raw)
To: intel-gfx; +Cc: linux-fbdev, dri-devel, laurent.pinchart
It adds code to read the DP SDPs from the video DIP and unpack them into
the crtc state.
It adds routines that read out DP VSC SDP and DP HDR Metadata Infoframe SDP
In order to unpack DP VSC SDP, it adds intel_dp_vsc_sdp_unpack() function.
It follows DP 1.4a spec. [Table 2-116: VSC SDP Header Bytes] and
[Table 2-117: VSC SDP Payload for DB16 through DB18]
In order to unpack DP HDR Metadata Infoframe SDP, it adds
intel_dp_hdr_metadata_infoframe_sdp_unpack(). And it follows DP 1.4a spec.
([Table 2-125: INFOFRAME SDP v1.2 Header Bytes] and
[Table 2-126: INFOFRAME SDP v1.2 Payload Data Bytes - DB0 through DB31])
and CTA-861-G spec. [Table-42 Dynamic Range and Mastering InfoFrame].
A naming rule and style of intel_read_dp_sdp() function references
intel_read_infoframe() function of intel_hdmi.c
v2: Minor style fix
v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp
v4: Use struct drm_device logging macros
v5: Addressed review comments from Uma
- Polish commit message and comments
- Combine the if checks of sdp.HB2 and sdp.HB3
- Add 6bpc to unpacking of VSC SDP
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 187 ++++++++++++++++++++++++
drivers/gpu/drm/i915/display/intel_dp.h | 3 +
2 files changed, 190 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 67723dede1d1..84c0105be61b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4971,6 +4971,193 @@ void intel_dp_set_infoframes(struct intel_encoder *encoder,
intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA);
}
+static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc,
+ const void *buffer, size_t size)
+{
+ const struct dp_sdp *sdp = buffer;
+
+ if (size < sizeof(struct dp_sdp))
+ return -EINVAL;
+
+ memset(vsc, 0, size);
+
+ if (sdp->sdp_header.HB0 != 0)
+ return -EINVAL;
+
+ if (sdp->sdp_header.HB1 != DP_SDP_VSC)
+ return -EINVAL;
+
+ vsc->sdp_type = sdp->sdp_header.HB1;
+ vsc->revision = sdp->sdp_header.HB2;
+ vsc->length = sdp->sdp_header.HB3;
+
+ if ((sdp->sdp_header.HB2 == 0x2 && sdp->sdp_header.HB3 == 0x8) ||
+ (sdp->sdp_header.HB2 == 0x4 && sdp->sdp_header.HB3 == 0xe)) {
+ /*
+ * - HB2 = 0x2, HB3 = 0x8
+ * VSC SDP supporting 3D stereo + PSR
+ * - HB2 = 0x4, HB3 = 0xe
+ * VSC SDP supporting 3D stereo + PSR2 with Y-coordinate of
+ * first scan line of the SU region (applies to eDP v1.4b
+ * and higher).
+ */
+ return 0;
+ } else if (sdp->sdp_header.HB2 == 0x5 && sdp->sdp_header.HB3 == 0x13) {
+ /*
+ * - HB2 = 0x5, HB3 = 0x13
+ * VSC SDP supporting 3D stereo + PSR2 + Pixel Encoding/Colorimetry
+ * Format.
+ */
+ vsc->pixelformat = (sdp->db[16] >> 4) & 0xf;
+ vsc->colorimetry = sdp->db[16] & 0xf;
+ vsc->dynamic_range = (sdp->db[17] >> 7) & 0x1;
+
+ switch (sdp->db[17] & 0x7) {
+ case 0x0:
+ vsc->bpc = 6;
+ break;
+ case 0x1:
+ vsc->bpc = 8;
+ break;
+ case 0x2:
+ vsc->bpc = 10;
+ break;
+ case 0x3:
+ vsc->bpc = 12;
+ break;
+ case 0x4:
+ vsc->bpc = 16;
+ break;
+ default:
+ MISSING_CASE(sdp->db[17] & 0x7);
+ return -EINVAL;
+ }
+
+ vsc->content_type = sdp->db[18] & 0x7;
+ } else {
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int
+intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe *drm_infoframe,
+ const void *buffer, size_t size)
+{
+ int ret;
+
+ const struct dp_sdp *sdp = buffer;
+
+ if (size < sizeof(struct dp_sdp))
+ return -EINVAL;
+
+ if (sdp->sdp_header.HB0 != 0)
+ return -EINVAL;
+
+ if (sdp->sdp_header.HB1 != HDMI_INFOFRAME_TYPE_DRM)
+ return -EINVAL;
+
+ /*
+ * Least Significant Eight Bits of (Data Byte Count – 1)
+ * 1Dh (i.e., Data Byte Count = 30 bytes).
+ */
+ if (sdp->sdp_header.HB2 != 0x1D)
+ return -EINVAL;
+
+ /* Most Significant Two Bits of (Data Byte Count – 1), Clear to 00b. */
+ if ((sdp->sdp_header.HB3 & 0x3) != 0)
+ return -EINVAL;
+
+ /* INFOFRAME SDP Version Number */
+ if (((sdp->sdp_header.HB3 >> 2) & 0x3f) != 0x13)
+ return -EINVAL;
+
+ /* CTA Header Byte 2 (INFOFRAME Version Number) */
+ if (sdp->db[0] != 1)
+ return -EINVAL;
+
+ /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
+ if (sdp->db[1] != HDMI_DRM_INFOFRAME_SIZE)
+ return -EINVAL;
+
+ ret = hdmi_drm_infoframe_unpack_only(drm_infoframe, &sdp->db[2],
+ HDMI_DRM_INFOFRAME_SIZE);
+
+ return ret;
+}
+
+static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state,
+ struct drm_dp_vsc_sdp *vsc)
+{
+ struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ unsigned int type = DP_SDP_VSC;
+ struct dp_sdp sdp = {};
+ int ret;
+
+ /* When PSR is enabled, VSC SDP is handled by PSR routine */
+ if (intel_psr_enabled(intel_dp))
+ return;
+
+ if ((crtc_state->infoframes.enable &
+ intel_hdmi_infoframe_enable(type)) == 0)
+ return;
+
+ intel_dig_port->read_infoframe(encoder, crtc_state, type, &sdp, sizeof(sdp));
+
+ ret = intel_dp_vsc_sdp_unpack(vsc, &sdp, sizeof(sdp));
+
+ if (ret)
+ drm_dbg_kms(&dev_priv->drm, "Failed to unpack DP VSC SDP\n");
+}
+
+static void intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state,
+ struct hdmi_drm_infoframe *drm_infoframe)
+{
+ struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ unsigned int type = HDMI_PACKET_TYPE_GAMUT_METADATA;
+ struct dp_sdp sdp = {};
+ int ret;
+
+ if ((crtc_state->infoframes.enable &
+ intel_hdmi_infoframe_enable(type)) == 0)
+ return;
+
+ intel_dig_port->read_infoframe(encoder, crtc_state, type, &sdp,
+ sizeof(sdp));
+
+ ret = intel_dp_hdr_metadata_infoframe_sdp_unpack(drm_infoframe, &sdp,
+ sizeof(sdp));
+
+ if (ret)
+ drm_dbg_kms(&dev_priv->drm,
+ "Failed to unpack DP HDR Metadata Infoframe SDP\n");
+}
+
+void intel_read_dp_sdp(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state,
+ unsigned int type)
+{
+ switch (type) {
+ case DP_SDP_VSC:
+ intel_read_dp_vsc_sdp(encoder, crtc_state,
+ &crtc_state->infoframes.vsc);
+ break;
+ case HDMI_PACKET_TYPE_GAMUT_METADATA:
+ intel_read_dp_hdr_metadata_infoframe_sdp(encoder, crtc_state,
+ &crtc_state->infoframes.drm.drm);
+ break;
+ default:
+ MISSING_CASE(type);
+ break;
+ }
+}
+
static void
intel_dp_setup_vsc_sdp(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state,
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 6659ce15a693..faa2a3c5ee4e 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -117,6 +117,9 @@ void intel_dp_hdr_metadata_enable(struct intel_dp *intel_dp,
void intel_dp_set_infoframes(struct intel_encoder *encoder, bool enable,
const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state);
+void intel_read_dp_sdp(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state,
+ unsigned int type);
bool intel_digital_port_connected(struct intel_encoder *encoder);
void intel_dp_process_phy_request(struct intel_dp *intel_dp);
--
2.25.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 73+ messages in thread* [PATCH v12 02/14] drm/i915/dp: Read out DP SDPs
@ 2020-05-14 6:07 ` Gwan-gyeong Mun
0 siblings, 0 replies; 73+ messages in thread
From: Gwan-gyeong Mun @ 2020-05-14 6:07 UTC (permalink / raw)
To: intel-gfx; +Cc: linux-fbdev, dri-devel, laurent.pinchart
It adds code to read the DP SDPs from the video DIP and unpack them into
the crtc state.
It adds routines that read out DP VSC SDP and DP HDR Metadata Infoframe SDP
In order to unpack DP VSC SDP, it adds intel_dp_vsc_sdp_unpack() function.
It follows DP 1.4a spec. [Table 2-116: VSC SDP Header Bytes] and
[Table 2-117: VSC SDP Payload for DB16 through DB18]
In order to unpack DP HDR Metadata Infoframe SDP, it adds
intel_dp_hdr_metadata_infoframe_sdp_unpack(). And it follows DP 1.4a spec.
([Table 2-125: INFOFRAME SDP v1.2 Header Bytes] and
[Table 2-126: INFOFRAME SDP v1.2 Payload Data Bytes - DB0 through DB31])
and CTA-861-G spec. [Table-42 Dynamic Range and Mastering InfoFrame].
A naming rule and style of intel_read_dp_sdp() function references
intel_read_infoframe() function of intel_hdmi.c
v2: Minor style fix
v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp
v4: Use struct drm_device logging macros
v5: Addressed review comments from Uma
- Polish commit message and comments
- Combine the if checks of sdp.HB2 and sdp.HB3
- Add 6bpc to unpacking of VSC SDP
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 187 ++++++++++++++++++++++++
drivers/gpu/drm/i915/display/intel_dp.h | 3 +
2 files changed, 190 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 67723dede1d1..84c0105be61b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4971,6 +4971,193 @@ void intel_dp_set_infoframes(struct intel_encoder *encoder,
intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA);
}
+static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc,
+ const void *buffer, size_t size)
+{
+ const struct dp_sdp *sdp = buffer;
+
+ if (size < sizeof(struct dp_sdp))
+ return -EINVAL;
+
+ memset(vsc, 0, size);
+
+ if (sdp->sdp_header.HB0 != 0)
+ return -EINVAL;
+
+ if (sdp->sdp_header.HB1 != DP_SDP_VSC)
+ return -EINVAL;
+
+ vsc->sdp_type = sdp->sdp_header.HB1;
+ vsc->revision = sdp->sdp_header.HB2;
+ vsc->length = sdp->sdp_header.HB3;
+
+ if ((sdp->sdp_header.HB2 == 0x2 && sdp->sdp_header.HB3 == 0x8) ||
+ (sdp->sdp_header.HB2 == 0x4 && sdp->sdp_header.HB3 == 0xe)) {
+ /*
+ * - HB2 = 0x2, HB3 = 0x8
+ * VSC SDP supporting 3D stereo + PSR
+ * - HB2 = 0x4, HB3 = 0xe
+ * VSC SDP supporting 3D stereo + PSR2 with Y-coordinate of
+ * first scan line of the SU region (applies to eDP v1.4b
+ * and higher).
+ */
+ return 0;
+ } else if (sdp->sdp_header.HB2 == 0x5 && sdp->sdp_header.HB3 == 0x13) {
+ /*
+ * - HB2 = 0x5, HB3 = 0x13
+ * VSC SDP supporting 3D stereo + PSR2 + Pixel Encoding/Colorimetry
+ * Format.
+ */
+ vsc->pixelformat = (sdp->db[16] >> 4) & 0xf;
+ vsc->colorimetry = sdp->db[16] & 0xf;
+ vsc->dynamic_range = (sdp->db[17] >> 7) & 0x1;
+
+ switch (sdp->db[17] & 0x7) {
+ case 0x0:
+ vsc->bpc = 6;
+ break;
+ case 0x1:
+ vsc->bpc = 8;
+ break;
+ case 0x2:
+ vsc->bpc = 10;
+ break;
+ case 0x3:
+ vsc->bpc = 12;
+ break;
+ case 0x4:
+ vsc->bpc = 16;
+ break;
+ default:
+ MISSING_CASE(sdp->db[17] & 0x7);
+ return -EINVAL;
+ }
+
+ vsc->content_type = sdp->db[18] & 0x7;
+ } else {
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int
+intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe *drm_infoframe,
+ const void *buffer, size_t size)
+{
+ int ret;
+
+ const struct dp_sdp *sdp = buffer;
+
+ if (size < sizeof(struct dp_sdp))
+ return -EINVAL;
+
+ if (sdp->sdp_header.HB0 != 0)
+ return -EINVAL;
+
+ if (sdp->sdp_header.HB1 != HDMI_INFOFRAME_TYPE_DRM)
+ return -EINVAL;
+
+ /*
+ * Least Significant Eight Bits of (Data Byte Count – 1)
+ * 1Dh (i.e., Data Byte Count = 30 bytes).
+ */
+ if (sdp->sdp_header.HB2 != 0x1D)
+ return -EINVAL;
+
+ /* Most Significant Two Bits of (Data Byte Count – 1), Clear to 00b. */
+ if ((sdp->sdp_header.HB3 & 0x3) != 0)
+ return -EINVAL;
+
+ /* INFOFRAME SDP Version Number */
+ if (((sdp->sdp_header.HB3 >> 2) & 0x3f) != 0x13)
+ return -EINVAL;
+
+ /* CTA Header Byte 2 (INFOFRAME Version Number) */
+ if (sdp->db[0] != 1)
+ return -EINVAL;
+
+ /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
+ if (sdp->db[1] != HDMI_DRM_INFOFRAME_SIZE)
+ return -EINVAL;
+
+ ret = hdmi_drm_infoframe_unpack_only(drm_infoframe, &sdp->db[2],
+ HDMI_DRM_INFOFRAME_SIZE);
+
+ return ret;
+}
+
+static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state,
+ struct drm_dp_vsc_sdp *vsc)
+{
+ struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ unsigned int type = DP_SDP_VSC;
+ struct dp_sdp sdp = {};
+ int ret;
+
+ /* When PSR is enabled, VSC SDP is handled by PSR routine */
+ if (intel_psr_enabled(intel_dp))
+ return;
+
+ if ((crtc_state->infoframes.enable &
+ intel_hdmi_infoframe_enable(type)) == 0)
+ return;
+
+ intel_dig_port->read_infoframe(encoder, crtc_state, type, &sdp, sizeof(sdp));
+
+ ret = intel_dp_vsc_sdp_unpack(vsc, &sdp, sizeof(sdp));
+
+ if (ret)
+ drm_dbg_kms(&dev_priv->drm, "Failed to unpack DP VSC SDP\n");
+}
+
+static void intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state,
+ struct hdmi_drm_infoframe *drm_infoframe)
+{
+ struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ unsigned int type = HDMI_PACKET_TYPE_GAMUT_METADATA;
+ struct dp_sdp sdp = {};
+ int ret;
+
+ if ((crtc_state->infoframes.enable &
+ intel_hdmi_infoframe_enable(type)) == 0)
+ return;
+
+ intel_dig_port->read_infoframe(encoder, crtc_state, type, &sdp,
+ sizeof(sdp));
+
+ ret = intel_dp_hdr_metadata_infoframe_sdp_unpack(drm_infoframe, &sdp,
+ sizeof(sdp));
+
+ if (ret)
+ drm_dbg_kms(&dev_priv->drm,
+ "Failed to unpack DP HDR Metadata Infoframe SDP\n");
+}
+
+void intel_read_dp_sdp(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state,
+ unsigned int type)
+{
+ switch (type) {
+ case DP_SDP_VSC:
+ intel_read_dp_vsc_sdp(encoder, crtc_state,
+ &crtc_state->infoframes.vsc);
+ break;
+ case HDMI_PACKET_TYPE_GAMUT_METADATA:
+ intel_read_dp_hdr_metadata_infoframe_sdp(encoder, crtc_state,
+ &crtc_state->infoframes.drm.drm);
+ break;
+ default:
+ MISSING_CASE(type);
+ break;
+ }
+}
+
static void
intel_dp_setup_vsc_sdp(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state,
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 6659ce15a693..faa2a3c5ee4e 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -117,6 +117,9 @@ void intel_dp_hdr_metadata_enable(struct intel_dp *intel_dp,
void intel_dp_set_infoframes(struct intel_encoder *encoder, bool enable,
const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state);
+void intel_read_dp_sdp(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state,
+ unsigned int type);
bool intel_digital_port_connected(struct intel_encoder *encoder);
void intel_dp_process_phy_request(struct intel_dp *intel_dp);
--
2.25.0
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [PATCH v12 03/14] drm: Add logging function for DP VSC SDP
2020-05-14 6:07 ` Gwan-gyeong Mun
(?)
@ 2020-05-14 6:07 ` Gwan-gyeong Mun
-1 siblings, 0 replies; 73+ messages in thread
From: Gwan-gyeong Mun @ 2020-05-14 6:07 UTC (permalink / raw)
To: intel-gfx; +Cc: linux-fbdev, dri-devel, laurent.pinchart
When receiving video it is very useful to be able to log DP VSC SDP.
This greatly simplifies debugging.
v2: Minor style fix
v3: Move logging functions to drm core [Jani N]
v5: Rebased
v10: Rebased
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/drm_dp_helper.c | 174 ++++++++++++++++++++++++++++++++
include/drm/drm_dp_helper.h | 3 +
2 files changed, 177 insertions(+)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 612a59ec8116..43e57632b00a 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -1629,3 +1629,177 @@ int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
return 0;
}
EXPORT_SYMBOL(drm_dp_set_phy_test_pattern);
+
+static const char *dp_pixelformat_get_name(enum dp_pixelformat pixelformat)
+{
+ if (pixelformat < 0 || pixelformat > DP_PIXELFORMAT_RESERVED)
+ return "Invalid";
+
+ switch (pixelformat) {
+ case DP_PIXELFORMAT_RGB:
+ return "RGB";
+ case DP_PIXELFORMAT_YUV444:
+ return "YUV444";
+ case DP_PIXELFORMAT_YUV422:
+ return "YUV422";
+ case DP_PIXELFORMAT_YUV420:
+ return "YUV420";
+ case DP_PIXELFORMAT_Y_ONLY:
+ return "Y_ONLY";
+ case DP_PIXELFORMAT_RAW:
+ return "RAW";
+ default:
+ return "Reserved";
+ }
+}
+
+static const char *dp_colorimetry_get_name(enum dp_pixelformat pixelformat,
+ enum dp_colorimetry colorimetry)
+{
+ if (pixelformat < 0 || pixelformat > DP_PIXELFORMAT_RESERVED)
+ return "Invalid";
+
+ switch (colorimetry) {
+ case DP_COLORIMETRY_DEFAULT:
+ switch (pixelformat) {
+ case DP_PIXELFORMAT_RGB:
+ return "sRGB";
+ case DP_PIXELFORMAT_YUV444:
+ case DP_PIXELFORMAT_YUV422:
+ case DP_PIXELFORMAT_YUV420:
+ return "BT.601";
+ case DP_PIXELFORMAT_Y_ONLY:
+ return "DICOM PS3.14";
+ case DP_PIXELFORMAT_RAW:
+ return "Custom Color Profile";
+ default:
+ return "Reserved";
+ }
+ case DP_COLORIMETRY_RGB_WIDE_FIXED: /* and DP_COLORIMETRY_BT709_YCC */
+ switch (pixelformat) {
+ case DP_PIXELFORMAT_RGB:
+ return "Wide Fixed";
+ case DP_PIXELFORMAT_YUV444:
+ case DP_PIXELFORMAT_YUV422:
+ case DP_PIXELFORMAT_YUV420:
+ return "BT.709";
+ default:
+ return "Reserved";
+ }
+ case DP_COLORIMETRY_RGB_WIDE_FLOAT: /* and DP_COLORIMETRY_XVYCC_601 */
+ switch (pixelformat) {
+ case DP_PIXELFORMAT_RGB:
+ return "Wide Float";
+ case DP_PIXELFORMAT_YUV444:
+ case DP_PIXELFORMAT_YUV422:
+ case DP_PIXELFORMAT_YUV420:
+ return "xvYCC 601";
+ default:
+ return "Reserved";
+ }
+ case DP_COLORIMETRY_OPRGB: /* and DP_COLORIMETRY_XVYCC_709 */
+ switch (pixelformat) {
+ case DP_PIXELFORMAT_RGB:
+ return "OpRGB";
+ case DP_PIXELFORMAT_YUV444:
+ case DP_PIXELFORMAT_YUV422:
+ case DP_PIXELFORMAT_YUV420:
+ return "xvYCC 709";
+ default:
+ return "Reserved";
+ }
+ case DP_COLORIMETRY_DCI_P3_RGB: /* and DP_COLORIMETRY_SYCC_601 */
+ switch (pixelformat) {
+ case DP_PIXELFORMAT_RGB:
+ return "DCI-P3";
+ case DP_PIXELFORMAT_YUV444:
+ case DP_PIXELFORMAT_YUV422:
+ case DP_PIXELFORMAT_YUV420:
+ return "sYCC 601";
+ default:
+ return "Reserved";
+ }
+ case DP_COLORIMETRY_RGB_CUSTOM: /* and DP_COLORIMETRY_OPYCC_601 */
+ switch (pixelformat) {
+ case DP_PIXELFORMAT_RGB:
+ return "Custom Profile";
+ case DP_PIXELFORMAT_YUV444:
+ case DP_PIXELFORMAT_YUV422:
+ case DP_PIXELFORMAT_YUV420:
+ return "OpYCC 601";
+ default:
+ return "Reserved";
+ }
+ case DP_COLORIMETRY_BT2020_RGB: /* and DP_COLORIMETRY_BT2020_CYCC */
+ switch (pixelformat) {
+ case DP_PIXELFORMAT_RGB:
+ return "BT.2020 RGB";
+ case DP_PIXELFORMAT_YUV444:
+ case DP_PIXELFORMAT_YUV422:
+ case DP_PIXELFORMAT_YUV420:
+ return "BT.2020 CYCC";
+ default:
+ return "Reserved";
+ }
+ case DP_COLORIMETRY_BT2020_YCC:
+ switch (pixelformat) {
+ case DP_PIXELFORMAT_YUV444:
+ case DP_PIXELFORMAT_YUV422:
+ case DP_PIXELFORMAT_YUV420:
+ return "BT.2020 YCC";
+ default:
+ return "Reserved";
+ }
+ default:
+ return "Invalid";
+ }
+}
+
+static const char *dp_dynamic_range_get_name(enum dp_dynamic_range dynamic_range)
+{
+ switch (dynamic_range) {
+ case DP_DYNAMIC_RANGE_VESA:
+ return "VESA range";
+ case DP_DYNAMIC_RANGE_CTA:
+ return "CTA range";
+ default:
+ return "Invalid";
+ }
+}
+
+static const char *dp_content_type_get_name(enum dp_content_type content_type)
+{
+ switch (content_type) {
+ case DP_CONTENT_TYPE_NOT_DEFINED:
+ return "Not defined";
+ case DP_CONTENT_TYPE_GRAPHICS:
+ return "Graphics";
+ case DP_CONTENT_TYPE_PHOTO:
+ return "Photo";
+ case DP_CONTENT_TYPE_VIDEO:
+ return "Video";
+ case DP_CONTENT_TYPE_GAME:
+ return "Game";
+ default:
+ return "Reserved";
+ }
+}
+
+void drm_dp_vsc_sdp_log(const char *level, struct device *dev,
+ const struct drm_dp_vsc_sdp *vsc)
+{
+#define DP_SDP_LOG(fmt, ...) dev_printk(level, dev, fmt, ##__VA_ARGS__)
+ DP_SDP_LOG("DP SDP: %s, revision %u, length %u\n", "VSC",
+ vsc->revision, vsc->length);
+ DP_SDP_LOG(" pixelformat: %s\n",
+ dp_pixelformat_get_name(vsc->pixelformat));
+ DP_SDP_LOG(" colorimetry: %s\n",
+ dp_colorimetry_get_name(vsc->pixelformat, vsc->colorimetry));
+ DP_SDP_LOG(" bpc: %u\n", vsc->bpc);
+ DP_SDP_LOG(" dynamic range: %s\n",
+ dp_dynamic_range_get_name(vsc->dynamic_range));
+ DP_SDP_LOG(" content type: %s\n",
+ dp_content_type_get_name(vsc->content_type));
+#undef DP_SDP_LOG
+}
+EXPORT_SYMBOL(drm_dp_vsc_sdp_log);
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 6c4b53dcb851..2035ac44afde 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -1348,6 +1348,9 @@ struct drm_dp_vsc_sdp {
enum dp_content_type content_type;
};
+void drm_dp_vsc_sdp_log(const char *level, struct device *dev,
+ const struct drm_dp_vsc_sdp *vsc);
+
int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]);
static inline int
--
2.25.0
^ permalink raw reply related [flat|nested] 73+ messages in thread* [Intel-gfx] [PATCH v12 03/14] drm: Add logging function for DP VSC SDP
@ 2020-05-14 6:07 ` Gwan-gyeong Mun
0 siblings, 0 replies; 73+ messages in thread
From: Gwan-gyeong Mun @ 2020-05-14 6:07 UTC (permalink / raw)
To: intel-gfx; +Cc: linux-fbdev, dri-devel, laurent.pinchart
When receiving video it is very useful to be able to log DP VSC SDP.
This greatly simplifies debugging.
v2: Minor style fix
v3: Move logging functions to drm core [Jani N]
v5: Rebased
v10: Rebased
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/drm_dp_helper.c | 174 ++++++++++++++++++++++++++++++++
include/drm/drm_dp_helper.h | 3 +
2 files changed, 177 insertions(+)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 612a59ec8116..43e57632b00a 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -1629,3 +1629,177 @@ int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
return 0;
}
EXPORT_SYMBOL(drm_dp_set_phy_test_pattern);
+
+static const char *dp_pixelformat_get_name(enum dp_pixelformat pixelformat)
+{
+ if (pixelformat < 0 || pixelformat > DP_PIXELFORMAT_RESERVED)
+ return "Invalid";
+
+ switch (pixelformat) {
+ case DP_PIXELFORMAT_RGB:
+ return "RGB";
+ case DP_PIXELFORMAT_YUV444:
+ return "YUV444";
+ case DP_PIXELFORMAT_YUV422:
+ return "YUV422";
+ case DP_PIXELFORMAT_YUV420:
+ return "YUV420";
+ case DP_PIXELFORMAT_Y_ONLY:
+ return "Y_ONLY";
+ case DP_PIXELFORMAT_RAW:
+ return "RAW";
+ default:
+ return "Reserved";
+ }
+}
+
+static const char *dp_colorimetry_get_name(enum dp_pixelformat pixelformat,
+ enum dp_colorimetry colorimetry)
+{
+ if (pixelformat < 0 || pixelformat > DP_PIXELFORMAT_RESERVED)
+ return "Invalid";
+
+ switch (colorimetry) {
+ case DP_COLORIMETRY_DEFAULT:
+ switch (pixelformat) {
+ case DP_PIXELFORMAT_RGB:
+ return "sRGB";
+ case DP_PIXELFORMAT_YUV444:
+ case DP_PIXELFORMAT_YUV422:
+ case DP_PIXELFORMAT_YUV420:
+ return "BT.601";
+ case DP_PIXELFORMAT_Y_ONLY:
+ return "DICOM PS3.14";
+ case DP_PIXELFORMAT_RAW:
+ return "Custom Color Profile";
+ default:
+ return "Reserved";
+ }
+ case DP_COLORIMETRY_RGB_WIDE_FIXED: /* and DP_COLORIMETRY_BT709_YCC */
+ switch (pixelformat) {
+ case DP_PIXELFORMAT_RGB:
+ return "Wide Fixed";
+ case DP_PIXELFORMAT_YUV444:
+ case DP_PIXELFORMAT_YUV422:
+ case DP_PIXELFORMAT_YUV420:
+ return "BT.709";
+ default:
+ return "Reserved";
+ }
+ case DP_COLORIMETRY_RGB_WIDE_FLOAT: /* and DP_COLORIMETRY_XVYCC_601 */
+ switch (pixelformat) {
+ case DP_PIXELFORMAT_RGB:
+ return "Wide Float";
+ case DP_PIXELFORMAT_YUV444:
+ case DP_PIXELFORMAT_YUV422:
+ case DP_PIXELFORMAT_YUV420:
+ return "xvYCC 601";
+ default:
+ return "Reserved";
+ }
+ case DP_COLORIMETRY_OPRGB: /* and DP_COLORIMETRY_XVYCC_709 */
+ switch (pixelformat) {
+ case DP_PIXELFORMAT_RGB:
+ return "OpRGB";
+ case DP_PIXELFORMAT_YUV444:
+ case DP_PIXELFORMAT_YUV422:
+ case DP_PIXELFORMAT_YUV420:
+ return "xvYCC 709";
+ default:
+ return "Reserved";
+ }
+ case DP_COLORIMETRY_DCI_P3_RGB: /* and DP_COLORIMETRY_SYCC_601 */
+ switch (pixelformat) {
+ case DP_PIXELFORMAT_RGB:
+ return "DCI-P3";
+ case DP_PIXELFORMAT_YUV444:
+ case DP_PIXELFORMAT_YUV422:
+ case DP_PIXELFORMAT_YUV420:
+ return "sYCC 601";
+ default:
+ return "Reserved";
+ }
+ case DP_COLORIMETRY_RGB_CUSTOM: /* and DP_COLORIMETRY_OPYCC_601 */
+ switch (pixelformat) {
+ case DP_PIXELFORMAT_RGB:
+ return "Custom Profile";
+ case DP_PIXELFORMAT_YUV444:
+ case DP_PIXELFORMAT_YUV422:
+ case DP_PIXELFORMAT_YUV420:
+ return "OpYCC 601";
+ default:
+ return "Reserved";
+ }
+ case DP_COLORIMETRY_BT2020_RGB: /* and DP_COLORIMETRY_BT2020_CYCC */
+ switch (pixelformat) {
+ case DP_PIXELFORMAT_RGB:
+ return "BT.2020 RGB";
+ case DP_PIXELFORMAT_YUV444:
+ case DP_PIXELFORMAT_YUV422:
+ case DP_PIXELFORMAT_YUV420:
+ return "BT.2020 CYCC";
+ default:
+ return "Reserved";
+ }
+ case DP_COLORIMETRY_BT2020_YCC:
+ switch (pixelformat) {
+ case DP_PIXELFORMAT_YUV444:
+ case DP_PIXELFORMAT_YUV422:
+ case DP_PIXELFORMAT_YUV420:
+ return "BT.2020 YCC";
+ default:
+ return "Reserved";
+ }
+ default:
+ return "Invalid";
+ }
+}
+
+static const char *dp_dynamic_range_get_name(enum dp_dynamic_range dynamic_range)
+{
+ switch (dynamic_range) {
+ case DP_DYNAMIC_RANGE_VESA:
+ return "VESA range";
+ case DP_DYNAMIC_RANGE_CTA:
+ return "CTA range";
+ default:
+ return "Invalid";
+ }
+}
+
+static const char *dp_content_type_get_name(enum dp_content_type content_type)
+{
+ switch (content_type) {
+ case DP_CONTENT_TYPE_NOT_DEFINED:
+ return "Not defined";
+ case DP_CONTENT_TYPE_GRAPHICS:
+ return "Graphics";
+ case DP_CONTENT_TYPE_PHOTO:
+ return "Photo";
+ case DP_CONTENT_TYPE_VIDEO:
+ return "Video";
+ case DP_CONTENT_TYPE_GAME:
+ return "Game";
+ default:
+ return "Reserved";
+ }
+}
+
+void drm_dp_vsc_sdp_log(const char *level, struct device *dev,
+ const struct drm_dp_vsc_sdp *vsc)
+{
+#define DP_SDP_LOG(fmt, ...) dev_printk(level, dev, fmt, ##__VA_ARGS__)
+ DP_SDP_LOG("DP SDP: %s, revision %u, length %u\n", "VSC",
+ vsc->revision, vsc->length);
+ DP_SDP_LOG(" pixelformat: %s\n",
+ dp_pixelformat_get_name(vsc->pixelformat));
+ DP_SDP_LOG(" colorimetry: %s\n",
+ dp_colorimetry_get_name(vsc->pixelformat, vsc->colorimetry));
+ DP_SDP_LOG(" bpc: %u\n", vsc->bpc);
+ DP_SDP_LOG(" dynamic range: %s\n",
+ dp_dynamic_range_get_name(vsc->dynamic_range));
+ DP_SDP_LOG(" content type: %s\n",
+ dp_content_type_get_name(vsc->content_type));
+#undef DP_SDP_LOG
+}
+EXPORT_SYMBOL(drm_dp_vsc_sdp_log);
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 6c4b53dcb851..2035ac44afde 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -1348,6 +1348,9 @@ struct drm_dp_vsc_sdp {
enum dp_content_type content_type;
};
+void drm_dp_vsc_sdp_log(const char *level, struct device *dev,
+ const struct drm_dp_vsc_sdp *vsc);
+
int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]);
static inline int
--
2.25.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 73+ messages in thread* [PATCH v12 03/14] drm: Add logging function for DP VSC SDP
@ 2020-05-14 6:07 ` Gwan-gyeong Mun
0 siblings, 0 replies; 73+ messages in thread
From: Gwan-gyeong Mun @ 2020-05-14 6:07 UTC (permalink / raw)
To: intel-gfx; +Cc: linux-fbdev, dri-devel, laurent.pinchart
When receiving video it is very useful to be able to log DP VSC SDP.
This greatly simplifies debugging.
v2: Minor style fix
v3: Move logging functions to drm core [Jani N]
v5: Rebased
v10: Rebased
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/drm_dp_helper.c | 174 ++++++++++++++++++++++++++++++++
include/drm/drm_dp_helper.h | 3 +
2 files changed, 177 insertions(+)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 612a59ec8116..43e57632b00a 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -1629,3 +1629,177 @@ int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
return 0;
}
EXPORT_SYMBOL(drm_dp_set_phy_test_pattern);
+
+static const char *dp_pixelformat_get_name(enum dp_pixelformat pixelformat)
+{
+ if (pixelformat < 0 || pixelformat > DP_PIXELFORMAT_RESERVED)
+ return "Invalid";
+
+ switch (pixelformat) {
+ case DP_PIXELFORMAT_RGB:
+ return "RGB";
+ case DP_PIXELFORMAT_YUV444:
+ return "YUV444";
+ case DP_PIXELFORMAT_YUV422:
+ return "YUV422";
+ case DP_PIXELFORMAT_YUV420:
+ return "YUV420";
+ case DP_PIXELFORMAT_Y_ONLY:
+ return "Y_ONLY";
+ case DP_PIXELFORMAT_RAW:
+ return "RAW";
+ default:
+ return "Reserved";
+ }
+}
+
+static const char *dp_colorimetry_get_name(enum dp_pixelformat pixelformat,
+ enum dp_colorimetry colorimetry)
+{
+ if (pixelformat < 0 || pixelformat > DP_PIXELFORMAT_RESERVED)
+ return "Invalid";
+
+ switch (colorimetry) {
+ case DP_COLORIMETRY_DEFAULT:
+ switch (pixelformat) {
+ case DP_PIXELFORMAT_RGB:
+ return "sRGB";
+ case DP_PIXELFORMAT_YUV444:
+ case DP_PIXELFORMAT_YUV422:
+ case DP_PIXELFORMAT_YUV420:
+ return "BT.601";
+ case DP_PIXELFORMAT_Y_ONLY:
+ return "DICOM PS3.14";
+ case DP_PIXELFORMAT_RAW:
+ return "Custom Color Profile";
+ default:
+ return "Reserved";
+ }
+ case DP_COLORIMETRY_RGB_WIDE_FIXED: /* and DP_COLORIMETRY_BT709_YCC */
+ switch (pixelformat) {
+ case DP_PIXELFORMAT_RGB:
+ return "Wide Fixed";
+ case DP_PIXELFORMAT_YUV444:
+ case DP_PIXELFORMAT_YUV422:
+ case DP_PIXELFORMAT_YUV420:
+ return "BT.709";
+ default:
+ return "Reserved";
+ }
+ case DP_COLORIMETRY_RGB_WIDE_FLOAT: /* and DP_COLORIMETRY_XVYCC_601 */
+ switch (pixelformat) {
+ case DP_PIXELFORMAT_RGB:
+ return "Wide Float";
+ case DP_PIXELFORMAT_YUV444:
+ case DP_PIXELFORMAT_YUV422:
+ case DP_PIXELFORMAT_YUV420:
+ return "xvYCC 601";
+ default:
+ return "Reserved";
+ }
+ case DP_COLORIMETRY_OPRGB: /* and DP_COLORIMETRY_XVYCC_709 */
+ switch (pixelformat) {
+ case DP_PIXELFORMAT_RGB:
+ return "OpRGB";
+ case DP_PIXELFORMAT_YUV444:
+ case DP_PIXELFORMAT_YUV422:
+ case DP_PIXELFORMAT_YUV420:
+ return "xvYCC 709";
+ default:
+ return "Reserved";
+ }
+ case DP_COLORIMETRY_DCI_P3_RGB: /* and DP_COLORIMETRY_SYCC_601 */
+ switch (pixelformat) {
+ case DP_PIXELFORMAT_RGB:
+ return "DCI-P3";
+ case DP_PIXELFORMAT_YUV444:
+ case DP_PIXELFORMAT_YUV422:
+ case DP_PIXELFORMAT_YUV420:
+ return "sYCC 601";
+ default:
+ return "Reserved";
+ }
+ case DP_COLORIMETRY_RGB_CUSTOM: /* and DP_COLORIMETRY_OPYCC_601 */
+ switch (pixelformat) {
+ case DP_PIXELFORMAT_RGB:
+ return "Custom Profile";
+ case DP_PIXELFORMAT_YUV444:
+ case DP_PIXELFORMAT_YUV422:
+ case DP_PIXELFORMAT_YUV420:
+ return "OpYCC 601";
+ default:
+ return "Reserved";
+ }
+ case DP_COLORIMETRY_BT2020_RGB: /* and DP_COLORIMETRY_BT2020_CYCC */
+ switch (pixelformat) {
+ case DP_PIXELFORMAT_RGB:
+ return "BT.2020 RGB";
+ case DP_PIXELFORMAT_YUV444:
+ case DP_PIXELFORMAT_YUV422:
+ case DP_PIXELFORMAT_YUV420:
+ return "BT.2020 CYCC";
+ default:
+ return "Reserved";
+ }
+ case DP_COLORIMETRY_BT2020_YCC:
+ switch (pixelformat) {
+ case DP_PIXELFORMAT_YUV444:
+ case DP_PIXELFORMAT_YUV422:
+ case DP_PIXELFORMAT_YUV420:
+ return "BT.2020 YCC";
+ default:
+ return "Reserved";
+ }
+ default:
+ return "Invalid";
+ }
+}
+
+static const char *dp_dynamic_range_get_name(enum dp_dynamic_range dynamic_range)
+{
+ switch (dynamic_range) {
+ case DP_DYNAMIC_RANGE_VESA:
+ return "VESA range";
+ case DP_DYNAMIC_RANGE_CTA:
+ return "CTA range";
+ default:
+ return "Invalid";
+ }
+}
+
+static const char *dp_content_type_get_name(enum dp_content_type content_type)
+{
+ switch (content_type) {
+ case DP_CONTENT_TYPE_NOT_DEFINED:
+ return "Not defined";
+ case DP_CONTENT_TYPE_GRAPHICS:
+ return "Graphics";
+ case DP_CONTENT_TYPE_PHOTO:
+ return "Photo";
+ case DP_CONTENT_TYPE_VIDEO:
+ return "Video";
+ case DP_CONTENT_TYPE_GAME:
+ return "Game";
+ default:
+ return "Reserved";
+ }
+}
+
+void drm_dp_vsc_sdp_log(const char *level, struct device *dev,
+ const struct drm_dp_vsc_sdp *vsc)
+{
+#define DP_SDP_LOG(fmt, ...) dev_printk(level, dev, fmt, ##__VA_ARGS__)
+ DP_SDP_LOG("DP SDP: %s, revision %u, length %u\n", "VSC",
+ vsc->revision, vsc->length);
+ DP_SDP_LOG(" pixelformat: %s\n",
+ dp_pixelformat_get_name(vsc->pixelformat));
+ DP_SDP_LOG(" colorimetry: %s\n",
+ dp_colorimetry_get_name(vsc->pixelformat, vsc->colorimetry));
+ DP_SDP_LOG(" bpc: %u\n", vsc->bpc);
+ DP_SDP_LOG(" dynamic range: %s\n",
+ dp_dynamic_range_get_name(vsc->dynamic_range));
+ DP_SDP_LOG(" content type: %s\n",
+ dp_content_type_get_name(vsc->content_type));
+#undef DP_SDP_LOG
+}
+EXPORT_SYMBOL(drm_dp_vsc_sdp_log);
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 6c4b53dcb851..2035ac44afde 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -1348,6 +1348,9 @@ struct drm_dp_vsc_sdp {
enum dp_content_type content_type;
};
+void drm_dp_vsc_sdp_log(const char *level, struct device *dev,
+ const struct drm_dp_vsc_sdp *vsc);
+
int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]);
static inline int
--
2.25.0
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [PATCH v12 04/14] drm/i915: Include HDMI DRM infoframe in the crtc state dump
2020-05-14 6:07 ` Gwan-gyeong Mun
(?)
@ 2020-05-14 6:07 ` Gwan-gyeong Mun
-1 siblings, 0 replies; 73+ messages in thread
From: Gwan-gyeong Mun @ 2020-05-14 6:07 UTC (permalink / raw)
To: intel-gfx; +Cc: linux-fbdev, dri-devel, laurent.pinchart
Dump out the HDMI Dynamic Range and Mastering (DRM) infoframe in the
normal crtc state dump.
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 432b4eeaf9f6..80b1439c0d88 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13023,6 +13023,9 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
if (pipe_config->infoframes.enable &
intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR))
intel_dump_infoframe(dev_priv, &pipe_config->infoframes.hdmi);
+ if (pipe_config->infoframes.enable &
+ intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM))
+ intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
drm_dbg_kms(&dev_priv->drm, "requested mode:\n");
drm_mode_debug_printmodeline(&pipe_config->hw.mode);
--
2.25.0
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [Intel-gfx] [PATCH v12 04/14] drm/i915: Include HDMI DRM infoframe in the crtc state dump
@ 2020-05-14 6:07 ` Gwan-gyeong Mun
0 siblings, 0 replies; 73+ messages in thread
From: Gwan-gyeong Mun @ 2020-05-14 6:07 UTC (permalink / raw)
To: intel-gfx; +Cc: linux-fbdev, dri-devel, laurent.pinchart
Dump out the HDMI Dynamic Range and Mastering (DRM) infoframe in the
normal crtc state dump.
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 432b4eeaf9f6..80b1439c0d88 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13023,6 +13023,9 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
if (pipe_config->infoframes.enable &
intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR))
intel_dump_infoframe(dev_priv, &pipe_config->infoframes.hdmi);
+ if (pipe_config->infoframes.enable &
+ intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM))
+ intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
drm_dbg_kms(&dev_priv->drm, "requested mode:\n");
drm_mode_debug_printmodeline(&pipe_config->hw.mode);
--
2.25.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [PATCH v12 04/14] drm/i915: Include HDMI DRM infoframe in the crtc state dump
@ 2020-05-14 6:07 ` Gwan-gyeong Mun
0 siblings, 0 replies; 73+ messages in thread
From: Gwan-gyeong Mun @ 2020-05-14 6:07 UTC (permalink / raw)
To: intel-gfx; +Cc: linux-fbdev, dri-devel, laurent.pinchart
Dump out the HDMI Dynamic Range and Mastering (DRM) infoframe in the
normal crtc state dump.
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 432b4eeaf9f6..80b1439c0d88 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13023,6 +13023,9 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
if (pipe_config->infoframes.enable &
intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR))
intel_dump_infoframe(dev_priv, &pipe_config->infoframes.hdmi);
+ if (pipe_config->infoframes.enable &
+ intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM))
+ intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
drm_dbg_kms(&dev_priv->drm, "requested mode:\n");
drm_mode_debug_printmodeline(&pipe_config->hw.mode);
--
2.25.0
_______________________________________________
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [PATCH v12 05/14] drm/i915: Include DP HDR Metadata Infoframe SDP in the crtc state dump
2020-05-14 6:07 ` Gwan-gyeong Mun
(?)
@ 2020-05-14 6:07 ` Gwan-gyeong Mun
-1 siblings, 0 replies; 73+ messages in thread
From: Gwan-gyeong Mun @ 2020-05-14 6:07 UTC (permalink / raw)
To: intel-gfx; +Cc: linux-fbdev, dri-devel, laurent.pinchart
Dump out the DP HDR Metadata Infoframe SDP in the normal crtc state dump.
HDMI Dynamic Range and Mastering (DRM) infoframe and DP HDR Metadata
Infoframe SDP use the same member variable in infoframes of crtc state.
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 80b1439c0d88..eb3ab77bc559 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13026,6 +13026,9 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
if (pipe_config->infoframes.enable &
intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM))
intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
+ if (pipe_config->infoframes.enable &
+ intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA))
+ intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
drm_dbg_kms(&dev_priv->drm, "requested mode:\n");
drm_mode_debug_printmodeline(&pipe_config->hw.mode);
--
2.25.0
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [Intel-gfx] [PATCH v12 05/14] drm/i915: Include DP HDR Metadata Infoframe SDP in the crtc state dump
@ 2020-05-14 6:07 ` Gwan-gyeong Mun
0 siblings, 0 replies; 73+ messages in thread
From: Gwan-gyeong Mun @ 2020-05-14 6:07 UTC (permalink / raw)
To: intel-gfx; +Cc: linux-fbdev, dri-devel, laurent.pinchart
Dump out the DP HDR Metadata Infoframe SDP in the normal crtc state dump.
HDMI Dynamic Range and Mastering (DRM) infoframe and DP HDR Metadata
Infoframe SDP use the same member variable in infoframes of crtc state.
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 80b1439c0d88..eb3ab77bc559 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13026,6 +13026,9 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
if (pipe_config->infoframes.enable &
intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM))
intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
+ if (pipe_config->infoframes.enable &
+ intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA))
+ intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
drm_dbg_kms(&dev_priv->drm, "requested mode:\n");
drm_mode_debug_printmodeline(&pipe_config->hw.mode);
--
2.25.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [PATCH v12 05/14] drm/i915: Include DP HDR Metadata Infoframe SDP in the crtc state dump
@ 2020-05-14 6:07 ` Gwan-gyeong Mun
0 siblings, 0 replies; 73+ messages in thread
From: Gwan-gyeong Mun @ 2020-05-14 6:07 UTC (permalink / raw)
To: intel-gfx; +Cc: linux-fbdev, dri-devel, laurent.pinchart
Dump out the DP HDR Metadata Infoframe SDP in the normal crtc state dump.
HDMI Dynamic Range and Mastering (DRM) infoframe and DP HDR Metadata
Infoframe SDP use the same member variable in infoframes of crtc state.
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 80b1439c0d88..eb3ab77bc559 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13026,6 +13026,9 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
if (pipe_config->infoframes.enable &
intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM))
intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
+ if (pipe_config->infoframes.enable &
+ intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA))
+ intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
drm_dbg_kms(&dev_priv->drm, "requested mode:\n");
drm_mode_debug_printmodeline(&pipe_config->hw.mode);
--
2.25.0
_______________________________________________
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [PATCH v12 06/14] drm/i915: Include DP VSC SDP in the crtc state dump
2020-05-14 6:07 ` Gwan-gyeong Mun
(?)
@ 2020-05-14 6:07 ` Gwan-gyeong Mun
-1 siblings, 0 replies; 73+ messages in thread
From: Gwan-gyeong Mun @ 2020-05-14 6:07 UTC (permalink / raw)
To: intel-gfx; +Cc: linux-fbdev, dri-devel, laurent.pinchart
Dump out the DP VSC SDP in the normal crtc state dump
v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp
Use drm core's DP VSC SDP logging function
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index eb3ab77bc559..5484c8f3f8ff 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -12866,6 +12866,16 @@ intel_dump_infoframe(struct drm_i915_private *dev_priv,
hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, frame);
}
+static void
+intel_dump_dp_vsc_sdp(struct drm_i915_private *dev_priv,
+ const struct drm_dp_vsc_sdp *vsc)
+{
+ if (!drm_debug_enabled(DRM_UT_KMS))
+ return;
+
+ drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, vsc);
+}
+
#define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
static const char * const output_type_str[] = {
@@ -13029,6 +13039,9 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
if (pipe_config->infoframes.enable &
intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA))
intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
+ if (pipe_config->infoframes.enable &
+ intel_hdmi_infoframe_enable(DP_SDP_VSC))
+ intel_dump_dp_vsc_sdp(dev_priv, &pipe_config->infoframes.vsc);
drm_dbg_kms(&dev_priv->drm, "requested mode:\n");
drm_mode_debug_printmodeline(&pipe_config->hw.mode);
--
2.25.0
^ permalink raw reply related [flat|nested] 73+ messages in thread* [Intel-gfx] [PATCH v12 06/14] drm/i915: Include DP VSC SDP in the crtc state dump
@ 2020-05-14 6:07 ` Gwan-gyeong Mun
0 siblings, 0 replies; 73+ messages in thread
From: Gwan-gyeong Mun @ 2020-05-14 6:07 UTC (permalink / raw)
To: intel-gfx; +Cc: linux-fbdev, dri-devel, laurent.pinchart
Dump out the DP VSC SDP in the normal crtc state dump
v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp
Use drm core's DP VSC SDP logging function
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index eb3ab77bc559..5484c8f3f8ff 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -12866,6 +12866,16 @@ intel_dump_infoframe(struct drm_i915_private *dev_priv,
hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, frame);
}
+static void
+intel_dump_dp_vsc_sdp(struct drm_i915_private *dev_priv,
+ const struct drm_dp_vsc_sdp *vsc)
+{
+ if (!drm_debug_enabled(DRM_UT_KMS))
+ return;
+
+ drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, vsc);
+}
+
#define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
static const char * const output_type_str[] = {
@@ -13029,6 +13039,9 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
if (pipe_config->infoframes.enable &
intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA))
intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
+ if (pipe_config->infoframes.enable &
+ intel_hdmi_infoframe_enable(DP_SDP_VSC))
+ intel_dump_dp_vsc_sdp(dev_priv, &pipe_config->infoframes.vsc);
drm_dbg_kms(&dev_priv->drm, "requested mode:\n");
drm_mode_debug_printmodeline(&pipe_config->hw.mode);
--
2.25.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 73+ messages in thread* [PATCH v12 06/14] drm/i915: Include DP VSC SDP in the crtc state dump
@ 2020-05-14 6:07 ` Gwan-gyeong Mun
0 siblings, 0 replies; 73+ messages in thread
From: Gwan-gyeong Mun @ 2020-05-14 6:07 UTC (permalink / raw)
To: intel-gfx; +Cc: linux-fbdev, dri-devel, laurent.pinchart
Dump out the DP VSC SDP in the normal crtc state dump
v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp
Use drm core's DP VSC SDP logging function
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index eb3ab77bc559..5484c8f3f8ff 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -12866,6 +12866,16 @@ intel_dump_infoframe(struct drm_i915_private *dev_priv,
hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, frame);
}
+static void
+intel_dump_dp_vsc_sdp(struct drm_i915_private *dev_priv,
+ const struct drm_dp_vsc_sdp *vsc)
+{
+ if (!drm_debug_enabled(DRM_UT_KMS))
+ return;
+
+ drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, vsc);
+}
+
#define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
static const char * const output_type_str[] = {
@@ -13029,6 +13039,9 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
if (pipe_config->infoframes.enable &
intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA))
intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
+ if (pipe_config->infoframes.enable &
+ intel_hdmi_infoframe_enable(DP_SDP_VSC))
+ intel_dump_dp_vsc_sdp(dev_priv, &pipe_config->infoframes.vsc);
drm_dbg_kms(&dev_priv->drm, "requested mode:\n");
drm_mode_debug_printmodeline(&pipe_config->hw.mode);
--
2.25.0
_______________________________________________
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [PATCH v12 07/14] drm/i915: Program DP SDPs with computed configs
2020-05-14 6:07 ` Gwan-gyeong Mun
(?)
@ 2020-05-14 6:07 ` Gwan-gyeong Mun
-1 siblings, 0 replies; 73+ messages in thread
From: Gwan-gyeong Mun @ 2020-05-14 6:07 UTC (permalink / raw)
To: intel-gfx; +Cc: linux-fbdev, dri-devel, laurent.pinchart
In order to use computed config for DP SDPs (DP VSC SDP and DP HDR Metadata
Infoframe SDP), it replaces intel_dp_vsc_enable() function and
intel_dp_hdr_metadata_enable() function to intel_dp_set_infoframes()
function.
And it removes unused functions.
Before:
intel_dp_vsc_enable() and intel_dp_hdr_metadata_enable() compute sdp
configs and program sdp registers on enable callback of encoder.
After:
It separates computing of sdp configs and programming of sdp register.
The compute config callback of encoder calls computing sdp configs.
The enable callback of encoder calls programming sdp register.
v3: Rebased
v5: Polish commit message [Uma]
v10: Rebased
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 3 +-
drivers/gpu/drm/i915/display/intel_dp.c | 229 -----------------------
drivers/gpu/drm/i915/display/intel_dp.h | 6 -
3 files changed, 1 insertion(+), 237 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 798889f72495..75c7ffb1874c 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3681,8 +3681,7 @@ static void intel_enable_ddi_dp(struct intel_atomic_state *state,
intel_edp_backlight_on(crtc_state, conn_state);
intel_psr_enable(intel_dp, crtc_state);
- intel_dp_vsc_enable(intel_dp, crtc_state, conn_state);
- intel_dp_hdr_metadata_enable(intel_dp, crtc_state, conn_state);
+ intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
intel_edp_drrs_enable(intel_dp, crtc_state);
if (crtc_state->has_audio)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 84c0105be61b..4ccd6b7a3d83 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5158,235 +5158,6 @@ void intel_read_dp_sdp(struct intel_encoder *encoder,
}
}
-static void
-intel_dp_setup_vsc_sdp(struct intel_dp *intel_dp,
- const struct intel_crtc_state *crtc_state,
- const struct drm_connector_state *conn_state)
-{
- struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
- struct dp_sdp vsc_sdp = {};
-
- /* Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119 */
- vsc_sdp.sdp_header.HB0 = 0;
- vsc_sdp.sdp_header.HB1 = 0x7;
-
- /*
- * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
- * Colorimetry Format indication.
- */
- vsc_sdp.sdp_header.HB2 = 0x5;
-
- /*
- * VSC SDP supporting 3D stereo, + PSR2, + Pixel Encoding/
- * Colorimetry Format indication (HB2 = 05h).
- */
- vsc_sdp.sdp_header.HB3 = 0x13;
-
- /* DP 1.4a spec, Table 2-120 */
- switch (crtc_state->output_format) {
- case INTEL_OUTPUT_FORMAT_YCBCR444:
- vsc_sdp.db[16] = 0x1 << 4; /* YCbCr 444 : DB16[7:4] = 1h */
- break;
- case INTEL_OUTPUT_FORMAT_YCBCR420:
- vsc_sdp.db[16] = 0x3 << 4; /* YCbCr 420 : DB16[7:4] = 3h */
- break;
- case INTEL_OUTPUT_FORMAT_RGB:
- default:
- /* RGB: DB16[7:4] = 0h */
- break;
- }
-
- switch (conn_state->colorspace) {
- case DRM_MODE_COLORIMETRY_BT709_YCC:
- vsc_sdp.db[16] |= 0x1;
- break;
- case DRM_MODE_COLORIMETRY_XVYCC_601:
- vsc_sdp.db[16] |= 0x2;
- break;
- case DRM_MODE_COLORIMETRY_XVYCC_709:
- vsc_sdp.db[16] |= 0x3;
- break;
- case DRM_MODE_COLORIMETRY_SYCC_601:
- vsc_sdp.db[16] |= 0x4;
- break;
- case DRM_MODE_COLORIMETRY_OPYCC_601:
- vsc_sdp.db[16] |= 0x5;
- break;
- case DRM_MODE_COLORIMETRY_BT2020_CYCC:
- case DRM_MODE_COLORIMETRY_BT2020_RGB:
- vsc_sdp.db[16] |= 0x6;
- break;
- case DRM_MODE_COLORIMETRY_BT2020_YCC:
- vsc_sdp.db[16] |= 0x7;
- break;
- case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
- case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
- vsc_sdp.db[16] |= 0x4; /* DCI-P3 (SMPTE RP 431-2) */
- break;
- default:
- /* sRGB (IEC 61966-2-1) / ITU-R BT.601: DB16[0:3] = 0h */
-
- /* RGB->YCBCR color conversion uses the BT.709 color space. */
- if (crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR420)
- vsc_sdp.db[16] |= 0x1; /* 0x1, ITU-R BT.709 */
- break;
- }
-
- /*
- * For pixel encoding formats YCbCr444, YCbCr422, YCbCr420, and Y Only,
- * the following Component Bit Depth values are defined:
- * 001b = 8bpc.
- * 010b = 10bpc.
- * 011b = 12bpc.
- * 100b = 16bpc.
- */
- switch (crtc_state->pipe_bpp) {
- case 24: /* 8bpc */
- vsc_sdp.db[17] = 0x1;
- break;
- case 30: /* 10bpc */
- vsc_sdp.db[17] = 0x2;
- break;
- case 36: /* 12bpc */
- vsc_sdp.db[17] = 0x3;
- break;
- case 48: /* 16bpc */
- vsc_sdp.db[17] = 0x4;
- break;
- default:
- MISSING_CASE(crtc_state->pipe_bpp);
- break;
- }
-
- /*
- * Dynamic Range (Bit 7)
- * 0 = VESA range, 1 = CTA range.
- * all YCbCr are always limited range
- */
- vsc_sdp.db[17] |= 0x80;
-
- /*
- * Content Type (Bits 2:0)
- * 000b = Not defined.
- * 001b = Graphics.
- * 010b = Photo.
- * 011b = Video.
- * 100b = Game
- * All other values are RESERVED.
- * Note: See CTA-861-G for the definition and expected
- * processing by a stream sink for the above contect types.
- */
- vsc_sdp.db[18] = 0;
-
- intel_dig_port->write_infoframe(&intel_dig_port->base,
- crtc_state, DP_SDP_VSC, &vsc_sdp, sizeof(vsc_sdp));
-}
-
-static void
-intel_dp_setup_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
- const struct intel_crtc_state *crtc_state,
- const struct drm_connector_state *conn_state)
-{
- struct drm_i915_private *i915 = dp_to_i915(intel_dp);
- struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
- struct dp_sdp infoframe_sdp = {};
- struct hdmi_drm_infoframe drm_infoframe = {};
- const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE;
- unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE];
- ssize_t len;
- int ret;
-
- ret = drm_hdmi_infoframe_set_hdr_metadata(&drm_infoframe, conn_state);
- if (ret) {
- drm_dbg_kms(&i915->drm,
- "couldn't set HDR metadata in infoframe\n");
- return;
- }
-
- len = hdmi_drm_infoframe_pack_only(&drm_infoframe, buf, sizeof(buf));
- if (len < 0) {
- drm_dbg_kms(&i915->drm,
- "buffer size is smaller than hdr metadata infoframe\n");
- return;
- }
-
- if (len != infoframe_size) {
- drm_dbg_kms(&i915->drm, "wrong static hdr metadata size\n");
- return;
- }
-
- /*
- * Set up the infoframe sdp packet for HDR static metadata.
- * Prepare VSC Header for SU as per DP 1.4a spec,
- * Table 2-100 and Table 2-101
- */
-
- /* Packet ID, 00h for non-Audio INFOFRAME */
- infoframe_sdp.sdp_header.HB0 = 0;
- /*
- * Packet Type 80h + Non-audio INFOFRAME Type value
- * HDMI_INFOFRAME_TYPE_DRM: 0x87,
- */
- infoframe_sdp.sdp_header.HB1 = drm_infoframe.type;
- /*
- * Least Significant Eight Bits of (Data Byte Count – 1)
- * infoframe_size - 1,
- */
- infoframe_sdp.sdp_header.HB2 = 0x1D;
- /* INFOFRAME SDP Version Number */
- infoframe_sdp.sdp_header.HB3 = (0x13 << 2);
- /* CTA Header Byte 2 (INFOFRAME Version Number) */
- infoframe_sdp.db[0] = drm_infoframe.version;
- /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
- infoframe_sdp.db[1] = drm_infoframe.length;
- /*
- * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after
- * HDMI_INFOFRAME_HEADER_SIZE
- */
- BUILD_BUG_ON(sizeof(infoframe_sdp.db) < HDMI_DRM_INFOFRAME_SIZE + 2);
- memcpy(&infoframe_sdp.db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE],
- HDMI_DRM_INFOFRAME_SIZE);
-
- /*
- * Size of DP infoframe sdp packet for HDR static metadata is consist of
- * - DP SDP Header(struct dp_sdp_header): 4 bytes
- * - Two Data Blocks: 2 bytes
- * CTA Header Byte2 (INFOFRAME Version Number)
- * CTA Header Byte3 (Length of INFOFRAME)
- * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes
- *
- * Prior to GEN11's GMP register size is identical to DP HDR static metadata
- * infoframe size. But GEN11+ has larger than that size, write_infoframe
- * will pad rest of the size.
- */
- intel_dig_port->write_infoframe(&intel_dig_port->base, crtc_state,
- HDMI_PACKET_TYPE_GAMUT_METADATA,
- &infoframe_sdp,
- sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE);
-}
-
-void intel_dp_vsc_enable(struct intel_dp *intel_dp,
- const struct intel_crtc_state *crtc_state,
- const struct drm_connector_state *conn_state)
-{
- if (!intel_dp_needs_vsc_sdp(crtc_state, conn_state))
- return;
-
- intel_dp_setup_vsc_sdp(intel_dp, crtc_state, conn_state);
-}
-
-void intel_dp_hdr_metadata_enable(struct intel_dp *intel_dp,
- const struct intel_crtc_state *crtc_state,
- const struct drm_connector_state *conn_state)
-{
- if (!conn_state->hdr_output_metadata)
- return;
-
- intel_dp_setup_hdr_metadata_infoframe_sdp(intel_dp,
- crtc_state,
- conn_state);
-}
-
static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index faa2a3c5ee4e..0d2de15703c3 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -108,12 +108,6 @@ int intel_dp_link_required(int pixel_clock, int bpp);
int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
bool intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state);
-void intel_dp_vsc_enable(struct intel_dp *intel_dp,
- const struct intel_crtc_state *crtc_state,
- const struct drm_connector_state *conn_state);
-void intel_dp_hdr_metadata_enable(struct intel_dp *intel_dp,
- const struct intel_crtc_state *crtc_state,
- const struct drm_connector_state *conn_state);
void intel_dp_set_infoframes(struct intel_encoder *encoder, bool enable,
const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state);
--
2.25.0
^ permalink raw reply related [flat|nested] 73+ messages in thread* [Intel-gfx] [PATCH v12 07/14] drm/i915: Program DP SDPs with computed configs
@ 2020-05-14 6:07 ` Gwan-gyeong Mun
0 siblings, 0 replies; 73+ messages in thread
From: Gwan-gyeong Mun @ 2020-05-14 6:07 UTC (permalink / raw)
To: intel-gfx; +Cc: linux-fbdev, dri-devel, laurent.pinchart
In order to use computed config for DP SDPs (DP VSC SDP and DP HDR Metadata
Infoframe SDP), it replaces intel_dp_vsc_enable() function and
intel_dp_hdr_metadata_enable() function to intel_dp_set_infoframes()
function.
And it removes unused functions.
Before:
intel_dp_vsc_enable() and intel_dp_hdr_metadata_enable() compute sdp
configs and program sdp registers on enable callback of encoder.
After:
It separates computing of sdp configs and programming of sdp register.
The compute config callback of encoder calls computing sdp configs.
The enable callback of encoder calls programming sdp register.
v3: Rebased
v5: Polish commit message [Uma]
v10: Rebased
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 3 +-
drivers/gpu/drm/i915/display/intel_dp.c | 229 -----------------------
drivers/gpu/drm/i915/display/intel_dp.h | 6 -
3 files changed, 1 insertion(+), 237 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 798889f72495..75c7ffb1874c 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3681,8 +3681,7 @@ static void intel_enable_ddi_dp(struct intel_atomic_state *state,
intel_edp_backlight_on(crtc_state, conn_state);
intel_psr_enable(intel_dp, crtc_state);
- intel_dp_vsc_enable(intel_dp, crtc_state, conn_state);
- intel_dp_hdr_metadata_enable(intel_dp, crtc_state, conn_state);
+ intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
intel_edp_drrs_enable(intel_dp, crtc_state);
if (crtc_state->has_audio)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 84c0105be61b..4ccd6b7a3d83 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5158,235 +5158,6 @@ void intel_read_dp_sdp(struct intel_encoder *encoder,
}
}
-static void
-intel_dp_setup_vsc_sdp(struct intel_dp *intel_dp,
- const struct intel_crtc_state *crtc_state,
- const struct drm_connector_state *conn_state)
-{
- struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
- struct dp_sdp vsc_sdp = {};
-
- /* Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119 */
- vsc_sdp.sdp_header.HB0 = 0;
- vsc_sdp.sdp_header.HB1 = 0x7;
-
- /*
- * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
- * Colorimetry Format indication.
- */
- vsc_sdp.sdp_header.HB2 = 0x5;
-
- /*
- * VSC SDP supporting 3D stereo, + PSR2, + Pixel Encoding/
- * Colorimetry Format indication (HB2 = 05h).
- */
- vsc_sdp.sdp_header.HB3 = 0x13;
-
- /* DP 1.4a spec, Table 2-120 */
- switch (crtc_state->output_format) {
- case INTEL_OUTPUT_FORMAT_YCBCR444:
- vsc_sdp.db[16] = 0x1 << 4; /* YCbCr 444 : DB16[7:4] = 1h */
- break;
- case INTEL_OUTPUT_FORMAT_YCBCR420:
- vsc_sdp.db[16] = 0x3 << 4; /* YCbCr 420 : DB16[7:4] = 3h */
- break;
- case INTEL_OUTPUT_FORMAT_RGB:
- default:
- /* RGB: DB16[7:4] = 0h */
- break;
- }
-
- switch (conn_state->colorspace) {
- case DRM_MODE_COLORIMETRY_BT709_YCC:
- vsc_sdp.db[16] |= 0x1;
- break;
- case DRM_MODE_COLORIMETRY_XVYCC_601:
- vsc_sdp.db[16] |= 0x2;
- break;
- case DRM_MODE_COLORIMETRY_XVYCC_709:
- vsc_sdp.db[16] |= 0x3;
- break;
- case DRM_MODE_COLORIMETRY_SYCC_601:
- vsc_sdp.db[16] |= 0x4;
- break;
- case DRM_MODE_COLORIMETRY_OPYCC_601:
- vsc_sdp.db[16] |= 0x5;
- break;
- case DRM_MODE_COLORIMETRY_BT2020_CYCC:
- case DRM_MODE_COLORIMETRY_BT2020_RGB:
- vsc_sdp.db[16] |= 0x6;
- break;
- case DRM_MODE_COLORIMETRY_BT2020_YCC:
- vsc_sdp.db[16] |= 0x7;
- break;
- case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
- case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
- vsc_sdp.db[16] |= 0x4; /* DCI-P3 (SMPTE RP 431-2) */
- break;
- default:
- /* sRGB (IEC 61966-2-1) / ITU-R BT.601: DB16[0:3] = 0h */
-
- /* RGB->YCBCR color conversion uses the BT.709 color space. */
- if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
- vsc_sdp.db[16] |= 0x1; /* 0x1, ITU-R BT.709 */
- break;
- }
-
- /*
- * For pixel encoding formats YCbCr444, YCbCr422, YCbCr420, and Y Only,
- * the following Component Bit Depth values are defined:
- * 001b = 8bpc.
- * 010b = 10bpc.
- * 011b = 12bpc.
- * 100b = 16bpc.
- */
- switch (crtc_state->pipe_bpp) {
- case 24: /* 8bpc */
- vsc_sdp.db[17] = 0x1;
- break;
- case 30: /* 10bpc */
- vsc_sdp.db[17] = 0x2;
- break;
- case 36: /* 12bpc */
- vsc_sdp.db[17] = 0x3;
- break;
- case 48: /* 16bpc */
- vsc_sdp.db[17] = 0x4;
- break;
- default:
- MISSING_CASE(crtc_state->pipe_bpp);
- break;
- }
-
- /*
- * Dynamic Range (Bit 7)
- * 0 = VESA range, 1 = CTA range.
- * all YCbCr are always limited range
- */
- vsc_sdp.db[17] |= 0x80;
-
- /*
- * Content Type (Bits 2:0)
- * 000b = Not defined.
- * 001b = Graphics.
- * 010b = Photo.
- * 011b = Video.
- * 100b = Game
- * All other values are RESERVED.
- * Note: See CTA-861-G for the definition and expected
- * processing by a stream sink for the above contect types.
- */
- vsc_sdp.db[18] = 0;
-
- intel_dig_port->write_infoframe(&intel_dig_port->base,
- crtc_state, DP_SDP_VSC, &vsc_sdp, sizeof(vsc_sdp));
-}
-
-static void
-intel_dp_setup_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
- const struct intel_crtc_state *crtc_state,
- const struct drm_connector_state *conn_state)
-{
- struct drm_i915_private *i915 = dp_to_i915(intel_dp);
- struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
- struct dp_sdp infoframe_sdp = {};
- struct hdmi_drm_infoframe drm_infoframe = {};
- const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE;
- unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE];
- ssize_t len;
- int ret;
-
- ret = drm_hdmi_infoframe_set_hdr_metadata(&drm_infoframe, conn_state);
- if (ret) {
- drm_dbg_kms(&i915->drm,
- "couldn't set HDR metadata in infoframe\n");
- return;
- }
-
- len = hdmi_drm_infoframe_pack_only(&drm_infoframe, buf, sizeof(buf));
- if (len < 0) {
- drm_dbg_kms(&i915->drm,
- "buffer size is smaller than hdr metadata infoframe\n");
- return;
- }
-
- if (len != infoframe_size) {
- drm_dbg_kms(&i915->drm, "wrong static hdr metadata size\n");
- return;
- }
-
- /*
- * Set up the infoframe sdp packet for HDR static metadata.
- * Prepare VSC Header for SU as per DP 1.4a spec,
- * Table 2-100 and Table 2-101
- */
-
- /* Packet ID, 00h for non-Audio INFOFRAME */
- infoframe_sdp.sdp_header.HB0 = 0;
- /*
- * Packet Type 80h + Non-audio INFOFRAME Type value
- * HDMI_INFOFRAME_TYPE_DRM: 0x87,
- */
- infoframe_sdp.sdp_header.HB1 = drm_infoframe.type;
- /*
- * Least Significant Eight Bits of (Data Byte Count – 1)
- * infoframe_size - 1,
- */
- infoframe_sdp.sdp_header.HB2 = 0x1D;
- /* INFOFRAME SDP Version Number */
- infoframe_sdp.sdp_header.HB3 = (0x13 << 2);
- /* CTA Header Byte 2 (INFOFRAME Version Number) */
- infoframe_sdp.db[0] = drm_infoframe.version;
- /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
- infoframe_sdp.db[1] = drm_infoframe.length;
- /*
- * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after
- * HDMI_INFOFRAME_HEADER_SIZE
- */
- BUILD_BUG_ON(sizeof(infoframe_sdp.db) < HDMI_DRM_INFOFRAME_SIZE + 2);
- memcpy(&infoframe_sdp.db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE],
- HDMI_DRM_INFOFRAME_SIZE);
-
- /*
- * Size of DP infoframe sdp packet for HDR static metadata is consist of
- * - DP SDP Header(struct dp_sdp_header): 4 bytes
- * - Two Data Blocks: 2 bytes
- * CTA Header Byte2 (INFOFRAME Version Number)
- * CTA Header Byte3 (Length of INFOFRAME)
- * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes
- *
- * Prior to GEN11's GMP register size is identical to DP HDR static metadata
- * infoframe size. But GEN11+ has larger than that size, write_infoframe
- * will pad rest of the size.
- */
- intel_dig_port->write_infoframe(&intel_dig_port->base, crtc_state,
- HDMI_PACKET_TYPE_GAMUT_METADATA,
- &infoframe_sdp,
- sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE);
-}
-
-void intel_dp_vsc_enable(struct intel_dp *intel_dp,
- const struct intel_crtc_state *crtc_state,
- const struct drm_connector_state *conn_state)
-{
- if (!intel_dp_needs_vsc_sdp(crtc_state, conn_state))
- return;
-
- intel_dp_setup_vsc_sdp(intel_dp, crtc_state, conn_state);
-}
-
-void intel_dp_hdr_metadata_enable(struct intel_dp *intel_dp,
- const struct intel_crtc_state *crtc_state,
- const struct drm_connector_state *conn_state)
-{
- if (!conn_state->hdr_output_metadata)
- return;
-
- intel_dp_setup_hdr_metadata_infoframe_sdp(intel_dp,
- crtc_state,
- conn_state);
-}
-
static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index faa2a3c5ee4e..0d2de15703c3 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -108,12 +108,6 @@ int intel_dp_link_required(int pixel_clock, int bpp);
int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
bool intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state);
-void intel_dp_vsc_enable(struct intel_dp *intel_dp,
- const struct intel_crtc_state *crtc_state,
- const struct drm_connector_state *conn_state);
-void intel_dp_hdr_metadata_enable(struct intel_dp *intel_dp,
- const struct intel_crtc_state *crtc_state,
- const struct drm_connector_state *conn_state);
void intel_dp_set_infoframes(struct intel_encoder *encoder, bool enable,
const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state);
--
2.25.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 73+ messages in thread* [PATCH v12 07/14] drm/i915: Program DP SDPs with computed configs
@ 2020-05-14 6:07 ` Gwan-gyeong Mun
0 siblings, 0 replies; 73+ messages in thread
From: Gwan-gyeong Mun @ 2020-05-14 6:07 UTC (permalink / raw)
To: intel-gfx; +Cc: linux-fbdev, dri-devel, laurent.pinchart
In order to use computed config for DP SDPs (DP VSC SDP and DP HDR Metadata
Infoframe SDP), it replaces intel_dp_vsc_enable() function and
intel_dp_hdr_metadata_enable() function to intel_dp_set_infoframes()
function.
And it removes unused functions.
Before:
intel_dp_vsc_enable() and intel_dp_hdr_metadata_enable() compute sdp
configs and program sdp registers on enable callback of encoder.
After:
It separates computing of sdp configs and programming of sdp register.
The compute config callback of encoder calls computing sdp configs.
The enable callback of encoder calls programming sdp register.
v3: Rebased
v5: Polish commit message [Uma]
v10: Rebased
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 3 +-
drivers/gpu/drm/i915/display/intel_dp.c | 229 -----------------------
drivers/gpu/drm/i915/display/intel_dp.h | 6 -
3 files changed, 1 insertion(+), 237 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 798889f72495..75c7ffb1874c 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3681,8 +3681,7 @@ static void intel_enable_ddi_dp(struct intel_atomic_state *state,
intel_edp_backlight_on(crtc_state, conn_state);
intel_psr_enable(intel_dp, crtc_state);
- intel_dp_vsc_enable(intel_dp, crtc_state, conn_state);
- intel_dp_hdr_metadata_enable(intel_dp, crtc_state, conn_state);
+ intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
intel_edp_drrs_enable(intel_dp, crtc_state);
if (crtc_state->has_audio)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 84c0105be61b..4ccd6b7a3d83 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5158,235 +5158,6 @@ void intel_read_dp_sdp(struct intel_encoder *encoder,
}
}
-static void
-intel_dp_setup_vsc_sdp(struct intel_dp *intel_dp,
- const struct intel_crtc_state *crtc_state,
- const struct drm_connector_state *conn_state)
-{
- struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
- struct dp_sdp vsc_sdp = {};
-
- /* Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119 */
- vsc_sdp.sdp_header.HB0 = 0;
- vsc_sdp.sdp_header.HB1 = 0x7;
-
- /*
- * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
- * Colorimetry Format indication.
- */
- vsc_sdp.sdp_header.HB2 = 0x5;
-
- /*
- * VSC SDP supporting 3D stereo, + PSR2, + Pixel Encoding/
- * Colorimetry Format indication (HB2 = 05h).
- */
- vsc_sdp.sdp_header.HB3 = 0x13;
-
- /* DP 1.4a spec, Table 2-120 */
- switch (crtc_state->output_format) {
- case INTEL_OUTPUT_FORMAT_YCBCR444:
- vsc_sdp.db[16] = 0x1 << 4; /* YCbCr 444 : DB16[7:4] = 1h */
- break;
- case INTEL_OUTPUT_FORMAT_YCBCR420:
- vsc_sdp.db[16] = 0x3 << 4; /* YCbCr 420 : DB16[7:4] = 3h */
- break;
- case INTEL_OUTPUT_FORMAT_RGB:
- default:
- /* RGB: DB16[7:4] = 0h */
- break;
- }
-
- switch (conn_state->colorspace) {
- case DRM_MODE_COLORIMETRY_BT709_YCC:
- vsc_sdp.db[16] |= 0x1;
- break;
- case DRM_MODE_COLORIMETRY_XVYCC_601:
- vsc_sdp.db[16] |= 0x2;
- break;
- case DRM_MODE_COLORIMETRY_XVYCC_709:
- vsc_sdp.db[16] |= 0x3;
- break;
- case DRM_MODE_COLORIMETRY_SYCC_601:
- vsc_sdp.db[16] |= 0x4;
- break;
- case DRM_MODE_COLORIMETRY_OPYCC_601:
- vsc_sdp.db[16] |= 0x5;
- break;
- case DRM_MODE_COLORIMETRY_BT2020_CYCC:
- case DRM_MODE_COLORIMETRY_BT2020_RGB:
- vsc_sdp.db[16] |= 0x6;
- break;
- case DRM_MODE_COLORIMETRY_BT2020_YCC:
- vsc_sdp.db[16] |= 0x7;
- break;
- case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
- case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
- vsc_sdp.db[16] |= 0x4; /* DCI-P3 (SMPTE RP 431-2) */
- break;
- default:
- /* sRGB (IEC 61966-2-1) / ITU-R BT.601: DB16[0:3] = 0h */
-
- /* RGB->YCBCR color conversion uses the BT.709 color space. */
- if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
- vsc_sdp.db[16] |= 0x1; /* 0x1, ITU-R BT.709 */
- break;
- }
-
- /*
- * For pixel encoding formats YCbCr444, YCbCr422, YCbCr420, and Y Only,
- * the following Component Bit Depth values are defined:
- * 001b = 8bpc.
- * 010b = 10bpc.
- * 011b = 12bpc.
- * 100b = 16bpc.
- */
- switch (crtc_state->pipe_bpp) {
- case 24: /* 8bpc */
- vsc_sdp.db[17] = 0x1;
- break;
- case 30: /* 10bpc */
- vsc_sdp.db[17] = 0x2;
- break;
- case 36: /* 12bpc */
- vsc_sdp.db[17] = 0x3;
- break;
- case 48: /* 16bpc */
- vsc_sdp.db[17] = 0x4;
- break;
- default:
- MISSING_CASE(crtc_state->pipe_bpp);
- break;
- }
-
- /*
- * Dynamic Range (Bit 7)
- * 0 = VESA range, 1 = CTA range.
- * all YCbCr are always limited range
- */
- vsc_sdp.db[17] |= 0x80;
-
- /*
- * Content Type (Bits 2:0)
- * 000b = Not defined.
- * 001b = Graphics.
- * 010b = Photo.
- * 011b = Video.
- * 100b = Game
- * All other values are RESERVED.
- * Note: See CTA-861-G for the definition and expected
- * processing by a stream sink for the above contect types.
- */
- vsc_sdp.db[18] = 0;
-
- intel_dig_port->write_infoframe(&intel_dig_port->base,
- crtc_state, DP_SDP_VSC, &vsc_sdp, sizeof(vsc_sdp));
-}
-
-static void
-intel_dp_setup_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
- const struct intel_crtc_state *crtc_state,
- const struct drm_connector_state *conn_state)
-{
- struct drm_i915_private *i915 = dp_to_i915(intel_dp);
- struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
- struct dp_sdp infoframe_sdp = {};
- struct hdmi_drm_infoframe drm_infoframe = {};
- const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE;
- unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE];
- ssize_t len;
- int ret;
-
- ret = drm_hdmi_infoframe_set_hdr_metadata(&drm_infoframe, conn_state);
- if (ret) {
- drm_dbg_kms(&i915->drm,
- "couldn't set HDR metadata in infoframe\n");
- return;
- }
-
- len = hdmi_drm_infoframe_pack_only(&drm_infoframe, buf, sizeof(buf));
- if (len < 0) {
- drm_dbg_kms(&i915->drm,
- "buffer size is smaller than hdr metadata infoframe\n");
- return;
- }
-
- if (len != infoframe_size) {
- drm_dbg_kms(&i915->drm, "wrong static hdr metadata size\n");
- return;
- }
-
- /*
- * Set up the infoframe sdp packet for HDR static metadata.
- * Prepare VSC Header for SU as per DP 1.4a spec,
- * Table 2-100 and Table 2-101
- */
-
- /* Packet ID, 00h for non-Audio INFOFRAME */
- infoframe_sdp.sdp_header.HB0 = 0;
- /*
- * Packet Type 80h + Non-audio INFOFRAME Type value
- * HDMI_INFOFRAME_TYPE_DRM: 0x87,
- */
- infoframe_sdp.sdp_header.HB1 = drm_infoframe.type;
- /*
- * Least Significant Eight Bits of (Data Byte Count – 1)
- * infoframe_size - 1,
- */
- infoframe_sdp.sdp_header.HB2 = 0x1D;
- /* INFOFRAME SDP Version Number */
- infoframe_sdp.sdp_header.HB3 = (0x13 << 2);
- /* CTA Header Byte 2 (INFOFRAME Version Number) */
- infoframe_sdp.db[0] = drm_infoframe.version;
- /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
- infoframe_sdp.db[1] = drm_infoframe.length;
- /*
- * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after
- * HDMI_INFOFRAME_HEADER_SIZE
- */
- BUILD_BUG_ON(sizeof(infoframe_sdp.db) < HDMI_DRM_INFOFRAME_SIZE + 2);
- memcpy(&infoframe_sdp.db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE],
- HDMI_DRM_INFOFRAME_SIZE);
-
- /*
- * Size of DP infoframe sdp packet for HDR static metadata is consist of
- * - DP SDP Header(struct dp_sdp_header): 4 bytes
- * - Two Data Blocks: 2 bytes
- * CTA Header Byte2 (INFOFRAME Version Number)
- * CTA Header Byte3 (Length of INFOFRAME)
- * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes
- *
- * Prior to GEN11's GMP register size is identical to DP HDR static metadata
- * infoframe size. But GEN11+ has larger than that size, write_infoframe
- * will pad rest of the size.
- */
- intel_dig_port->write_infoframe(&intel_dig_port->base, crtc_state,
- HDMI_PACKET_TYPE_GAMUT_METADATA,
- &infoframe_sdp,
- sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE);
-}
-
-void intel_dp_vsc_enable(struct intel_dp *intel_dp,
- const struct intel_crtc_state *crtc_state,
- const struct drm_connector_state *conn_state)
-{
- if (!intel_dp_needs_vsc_sdp(crtc_state, conn_state))
- return;
-
- intel_dp_setup_vsc_sdp(intel_dp, crtc_state, conn_state);
-}
-
-void intel_dp_hdr_metadata_enable(struct intel_dp *intel_dp,
- const struct intel_crtc_state *crtc_state,
- const struct drm_connector_state *conn_state)
-{
- if (!conn_state->hdr_output_metadata)
- return;
-
- intel_dp_setup_hdr_metadata_infoframe_sdp(intel_dp,
- crtc_state,
- conn_state);
-}
-
static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index faa2a3c5ee4e..0d2de15703c3 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -108,12 +108,6 @@ int intel_dp_link_required(int pixel_clock, int bpp);
int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
bool intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state);
-void intel_dp_vsc_enable(struct intel_dp *intel_dp,
- const struct intel_crtc_state *crtc_state,
- const struct drm_connector_state *conn_state);
-void intel_dp_hdr_metadata_enable(struct intel_dp *intel_dp,
- const struct intel_crtc_state *crtc_state,
- const struct drm_connector_state *conn_state);
void intel_dp_set_infoframes(struct intel_encoder *encoder, bool enable,
const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state);
--
2.25.0
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [PATCH v12 08/14] drm/i915: Add state readout for DP HDR Metadata Infoframe SDP
2020-05-14 6:07 ` Gwan-gyeong Mun
(?)
@ 2020-05-14 6:07 ` Gwan-gyeong Mun
-1 siblings, 0 replies; 73+ messages in thread
From: Gwan-gyeong Mun @ 2020-05-14 6:07 UTC (permalink / raw)
To: intel-gfx; +Cc: linux-fbdev, dri-devel, laurent.pinchart
Added state readout for DP HDR Metadata Infoframe SDP.
v9: Rebased
v10: Rebased
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 75c7ffb1874c..f2bb7527ba0c 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4234,6 +4234,9 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
pipe_config->fec_enable);
}
+ pipe_config->infoframes.enable |+ intel_hdmi_infoframes_enabled(encoder, pipe_config);
+
break;
case TRANS_DDI_MODE_SELECT_DP_MST:
pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
@@ -4245,6 +4248,9 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp);
intel_dp_get_m_n(intel_crtc, pipe_config);
+
+ pipe_config->infoframes.enable |+ intel_hdmi_infoframes_enabled(encoder, pipe_config);
break;
default:
break;
@@ -4299,6 +4305,8 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
if (INTEL_GEN(dev_priv) >= 8)
bdw_get_trans_port_sync_config(pipe_config);
+
+ intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA);
}
static enum intel_output_type
--
2.25.0
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [Intel-gfx] [PATCH v12 08/14] drm/i915: Add state readout for DP HDR Metadata Infoframe SDP
@ 2020-05-14 6:07 ` Gwan-gyeong Mun
0 siblings, 0 replies; 73+ messages in thread
From: Gwan-gyeong Mun @ 2020-05-14 6:07 UTC (permalink / raw)
To: intel-gfx; +Cc: linux-fbdev, dri-devel, laurent.pinchart
Added state readout for DP HDR Metadata Infoframe SDP.
v9: Rebased
v10: Rebased
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 75c7ffb1874c..f2bb7527ba0c 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4234,6 +4234,9 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
pipe_config->fec_enable);
}
+ pipe_config->infoframes.enable |=
+ intel_hdmi_infoframes_enabled(encoder, pipe_config);
+
break;
case TRANS_DDI_MODE_SELECT_DP_MST:
pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
@@ -4245,6 +4248,9 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp);
intel_dp_get_m_n(intel_crtc, pipe_config);
+
+ pipe_config->infoframes.enable |=
+ intel_hdmi_infoframes_enabled(encoder, pipe_config);
break;
default:
break;
@@ -4299,6 +4305,8 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
if (INTEL_GEN(dev_priv) >= 8)
bdw_get_trans_port_sync_config(pipe_config);
+
+ intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA);
}
static enum intel_output_type
--
2.25.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [PATCH v12 08/14] drm/i915: Add state readout for DP HDR Metadata Infoframe SDP
@ 2020-05-14 6:07 ` Gwan-gyeong Mun
0 siblings, 0 replies; 73+ messages in thread
From: Gwan-gyeong Mun @ 2020-05-14 6:07 UTC (permalink / raw)
To: intel-gfx; +Cc: linux-fbdev, dri-devel, laurent.pinchart
Added state readout for DP HDR Metadata Infoframe SDP.
v9: Rebased
v10: Rebased
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 75c7ffb1874c..f2bb7527ba0c 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4234,6 +4234,9 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
pipe_config->fec_enable);
}
+ pipe_config->infoframes.enable |=
+ intel_hdmi_infoframes_enabled(encoder, pipe_config);
+
break;
case TRANS_DDI_MODE_SELECT_DP_MST:
pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
@@ -4245,6 +4248,9 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp);
intel_dp_get_m_n(intel_crtc, pipe_config);
+
+ pipe_config->infoframes.enable |=
+ intel_hdmi_infoframes_enabled(encoder, pipe_config);
break;
default:
break;
@@ -4299,6 +4305,8 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
if (INTEL_GEN(dev_priv) >= 8)
bdw_get_trans_port_sync_config(pipe_config);
+
+ intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA);
}
static enum intel_output_type
--
2.25.0
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [PATCH v12 09/14] drm/i915: Add state readout for DP VSC SDP
2020-05-14 6:07 ` Gwan-gyeong Mun
(?)
@ 2020-05-14 6:07 ` Gwan-gyeong Mun
-1 siblings, 0 replies; 73+ messages in thread
From: Gwan-gyeong Mun @ 2020-05-14 6:07 UTC (permalink / raw)
To: intel-gfx; +Cc: linux-fbdev, dri-devel, laurent.pinchart
Added state readout for DP VSC SDP and enabled state validation
for DP VSC SDP.
v2: Minor style fix
v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp
v4: Use struct drm_device logging macros
v10: Skip checking of VSC SDP when a crtc config has psr.
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 1 +
drivers/gpu/drm/i915/display/intel_display.c | 44 ++++++++++++++++++++
2 files changed, 45 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index f2bb7527ba0c..2b54ea47e822 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4307,6 +4307,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
bdw_get_trans_port_sync_config(pipe_config);
intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA);
+ intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
}
static enum intel_output_type
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 5484c8f3f8ff..ab621926def1 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13489,6 +13489,13 @@ intel_compare_infoframe(const union hdmi_infoframe *a,
return memcmp(a, b, sizeof(*a)) = 0;
}
+static bool
+intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a,
+ const struct drm_dp_vsc_sdp *b)
+{
+ return memcmp(a, b, sizeof(*a)) = 0;
+}
+
static void
pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv,
bool fastset, const char *name,
@@ -13514,6 +13521,31 @@ pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv,
}
}
+static void
+pipe_config_dp_vsc_sdp_mismatch(struct drm_i915_private *dev_priv,
+ bool fastset, const char *name,
+ const struct drm_dp_vsc_sdp *a,
+ const struct drm_dp_vsc_sdp *b)
+{
+ if (fastset) {
+ if (!drm_debug_enabled(DRM_UT_KMS))
+ return;
+
+ drm_dbg_kms(&dev_priv->drm,
+ "fastset mismatch in %s dp sdp\n", name);
+ drm_dbg_kms(&dev_priv->drm, "expected:\n");
+ drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, a);
+ drm_dbg_kms(&dev_priv->drm, "found:\n");
+ drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, b);
+ } else {
+ drm_err(&dev_priv->drm, "mismatch in %s dp sdp\n", name);
+ drm_err(&dev_priv->drm, "expected:\n");
+ drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, a);
+ drm_err(&dev_priv->drm, "found:\n");
+ drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, b);
+ }
+}
+
static void __printf(4, 5)
pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc,
const char *name, const char *format, ...)
@@ -13715,6 +13747,17 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
} \
} while (0)
+#define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \
+ if (!current_config->has_psr && !pipe_config->has_psr && \
+ !intel_compare_dp_vsc_sdp(¤t_config->infoframes.name, \
+ &pipe_config->infoframes.name)) { \
+ pipe_config_dp_vsc_sdp_mismatch(dev_priv, fastset, __stringify(name), \
+ ¤t_config->infoframes.name, \
+ &pipe_config->infoframes.name); \
+ ret = false; \
+ } \
+} while (0)
+
#define PIPE_CONF_CHECK_COLOR_LUT(name1, name2, bit_precision) do { \
if (current_config->name1 != pipe_config->name1) { \
pipe_config_mismatch(fastset, crtc, __stringify(name1), \
@@ -13892,6 +13935,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
PIPE_CONF_CHECK_INFOFRAME(spd);
PIPE_CONF_CHECK_INFOFRAME(hdmi);
PIPE_CONF_CHECK_INFOFRAME(drm);
+ PIPE_CONF_CHECK_DP_VSC_SDP(vsc);
PIPE_CONF_CHECK_X(sync_mode_slaves_mask);
PIPE_CONF_CHECK_I(master_transcoder);
--
2.25.0
^ permalink raw reply related [flat|nested] 73+ messages in thread* [Intel-gfx] [PATCH v12 09/14] drm/i915: Add state readout for DP VSC SDP
@ 2020-05-14 6:07 ` Gwan-gyeong Mun
0 siblings, 0 replies; 73+ messages in thread
From: Gwan-gyeong Mun @ 2020-05-14 6:07 UTC (permalink / raw)
To: intel-gfx; +Cc: linux-fbdev, dri-devel, laurent.pinchart
Added state readout for DP VSC SDP and enabled state validation
for DP VSC SDP.
v2: Minor style fix
v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp
v4: Use struct drm_device logging macros
v10: Skip checking of VSC SDP when a crtc config has psr.
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 1 +
drivers/gpu/drm/i915/display/intel_display.c | 44 ++++++++++++++++++++
2 files changed, 45 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index f2bb7527ba0c..2b54ea47e822 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4307,6 +4307,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
bdw_get_trans_port_sync_config(pipe_config);
intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA);
+ intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
}
static enum intel_output_type
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 5484c8f3f8ff..ab621926def1 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13489,6 +13489,13 @@ intel_compare_infoframe(const union hdmi_infoframe *a,
return memcmp(a, b, sizeof(*a)) == 0;
}
+static bool
+intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a,
+ const struct drm_dp_vsc_sdp *b)
+{
+ return memcmp(a, b, sizeof(*a)) == 0;
+}
+
static void
pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv,
bool fastset, const char *name,
@@ -13514,6 +13521,31 @@ pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv,
}
}
+static void
+pipe_config_dp_vsc_sdp_mismatch(struct drm_i915_private *dev_priv,
+ bool fastset, const char *name,
+ const struct drm_dp_vsc_sdp *a,
+ const struct drm_dp_vsc_sdp *b)
+{
+ if (fastset) {
+ if (!drm_debug_enabled(DRM_UT_KMS))
+ return;
+
+ drm_dbg_kms(&dev_priv->drm,
+ "fastset mismatch in %s dp sdp\n", name);
+ drm_dbg_kms(&dev_priv->drm, "expected:\n");
+ drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, a);
+ drm_dbg_kms(&dev_priv->drm, "found:\n");
+ drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, b);
+ } else {
+ drm_err(&dev_priv->drm, "mismatch in %s dp sdp\n", name);
+ drm_err(&dev_priv->drm, "expected:\n");
+ drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, a);
+ drm_err(&dev_priv->drm, "found:\n");
+ drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, b);
+ }
+}
+
static void __printf(4, 5)
pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc,
const char *name, const char *format, ...)
@@ -13715,6 +13747,17 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
} \
} while (0)
+#define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \
+ if (!current_config->has_psr && !pipe_config->has_psr && \
+ !intel_compare_dp_vsc_sdp(¤t_config->infoframes.name, \
+ &pipe_config->infoframes.name)) { \
+ pipe_config_dp_vsc_sdp_mismatch(dev_priv, fastset, __stringify(name), \
+ ¤t_config->infoframes.name, \
+ &pipe_config->infoframes.name); \
+ ret = false; \
+ } \
+} while (0)
+
#define PIPE_CONF_CHECK_COLOR_LUT(name1, name2, bit_precision) do { \
if (current_config->name1 != pipe_config->name1) { \
pipe_config_mismatch(fastset, crtc, __stringify(name1), \
@@ -13892,6 +13935,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
PIPE_CONF_CHECK_INFOFRAME(spd);
PIPE_CONF_CHECK_INFOFRAME(hdmi);
PIPE_CONF_CHECK_INFOFRAME(drm);
+ PIPE_CONF_CHECK_DP_VSC_SDP(vsc);
PIPE_CONF_CHECK_X(sync_mode_slaves_mask);
PIPE_CONF_CHECK_I(master_transcoder);
--
2.25.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 73+ messages in thread* [PATCH v12 09/14] drm/i915: Add state readout for DP VSC SDP
@ 2020-05-14 6:07 ` Gwan-gyeong Mun
0 siblings, 0 replies; 73+ messages in thread
From: Gwan-gyeong Mun @ 2020-05-14 6:07 UTC (permalink / raw)
To: intel-gfx; +Cc: linux-fbdev, dri-devel, laurent.pinchart
Added state readout for DP VSC SDP and enabled state validation
for DP VSC SDP.
v2: Minor style fix
v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp
v4: Use struct drm_device logging macros
v10: Skip checking of VSC SDP when a crtc config has psr.
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 1 +
drivers/gpu/drm/i915/display/intel_display.c | 44 ++++++++++++++++++++
2 files changed, 45 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index f2bb7527ba0c..2b54ea47e822 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4307,6 +4307,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
bdw_get_trans_port_sync_config(pipe_config);
intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA);
+ intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
}
static enum intel_output_type
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 5484c8f3f8ff..ab621926def1 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13489,6 +13489,13 @@ intel_compare_infoframe(const union hdmi_infoframe *a,
return memcmp(a, b, sizeof(*a)) == 0;
}
+static bool
+intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a,
+ const struct drm_dp_vsc_sdp *b)
+{
+ return memcmp(a, b, sizeof(*a)) == 0;
+}
+
static void
pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv,
bool fastset, const char *name,
@@ -13514,6 +13521,31 @@ pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv,
}
}
+static void
+pipe_config_dp_vsc_sdp_mismatch(struct drm_i915_private *dev_priv,
+ bool fastset, const char *name,
+ const struct drm_dp_vsc_sdp *a,
+ const struct drm_dp_vsc_sdp *b)
+{
+ if (fastset) {
+ if (!drm_debug_enabled(DRM_UT_KMS))
+ return;
+
+ drm_dbg_kms(&dev_priv->drm,
+ "fastset mismatch in %s dp sdp\n", name);
+ drm_dbg_kms(&dev_priv->drm, "expected:\n");
+ drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, a);
+ drm_dbg_kms(&dev_priv->drm, "found:\n");
+ drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, b);
+ } else {
+ drm_err(&dev_priv->drm, "mismatch in %s dp sdp\n", name);
+ drm_err(&dev_priv->drm, "expected:\n");
+ drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, a);
+ drm_err(&dev_priv->drm, "found:\n");
+ drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, b);
+ }
+}
+
static void __printf(4, 5)
pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc,
const char *name, const char *format, ...)
@@ -13715,6 +13747,17 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
} \
} while (0)
+#define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \
+ if (!current_config->has_psr && !pipe_config->has_psr && \
+ !intel_compare_dp_vsc_sdp(¤t_config->infoframes.name, \
+ &pipe_config->infoframes.name)) { \
+ pipe_config_dp_vsc_sdp_mismatch(dev_priv, fastset, __stringify(name), \
+ ¤t_config->infoframes.name, \
+ &pipe_config->infoframes.name); \
+ ret = false; \
+ } \
+} while (0)
+
#define PIPE_CONF_CHECK_COLOR_LUT(name1, name2, bit_precision) do { \
if (current_config->name1 != pipe_config->name1) { \
pipe_config_mismatch(fastset, crtc, __stringify(name1), \
@@ -13892,6 +13935,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
PIPE_CONF_CHECK_INFOFRAME(spd);
PIPE_CONF_CHECK_INFOFRAME(hdmi);
PIPE_CONF_CHECK_INFOFRAME(drm);
+ PIPE_CONF_CHECK_DP_VSC_SDP(vsc);
PIPE_CONF_CHECK_X(sync_mode_slaves_mask);
PIPE_CONF_CHECK_I(master_transcoder);
--
2.25.0
_______________________________________________
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [PATCH v12 10/14] drm/i915: Fix enabled infoframe states of lspcon
2020-05-14 6:07 ` Gwan-gyeong Mun
(?)
@ 2020-05-14 6:07 ` Gwan-gyeong Mun
-1 siblings, 0 replies; 73+ messages in thread
From: Gwan-gyeong Mun @ 2020-05-14 6:07 UTC (permalink / raw)
To: intel-gfx; +Cc: linux-fbdev, dri-devel, laurent.pinchart
Compared to implementation of DP and HDMI's encoder->infoframes_enabled,
the lspcon's implementation returns its active state. (we expect enabled
infoframe states of HW.) It leads to pipe state mismatch error
when ddi_get_config is called.
Because the current implementation of lspcon is not ready to support
readout infoframes, we need to return 0 here.
In order to support readout to lspcon, we need to implement read_infoframe
and infoframes_enabled. And set_infoframes also have to set an appropriate
bit on crtc_state->infoframes.enable
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_lspcon.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c
index d807c5648c87..6ff7b226f0a1 100644
--- a/drivers/gpu/drm/i915/display/intel_lspcon.c
+++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
@@ -522,7 +522,7 @@ u32 lspcon_infoframes_enabled(struct intel_encoder *encoder,
const struct intel_crtc_state *pipe_config)
{
/* FIXME actually read this from the hw */
- return enc_to_intel_lspcon(encoder)->active;
+ return 0;
}
void lspcon_resume(struct intel_lspcon *lspcon)
--
2.25.0
^ permalink raw reply related [flat|nested] 73+ messages in thread* [Intel-gfx] [PATCH v12 10/14] drm/i915: Fix enabled infoframe states of lspcon
@ 2020-05-14 6:07 ` Gwan-gyeong Mun
0 siblings, 0 replies; 73+ messages in thread
From: Gwan-gyeong Mun @ 2020-05-14 6:07 UTC (permalink / raw)
To: intel-gfx; +Cc: linux-fbdev, dri-devel, laurent.pinchart
Compared to implementation of DP and HDMI's encoder->infoframes_enabled,
the lspcon's implementation returns its active state. (we expect enabled
infoframe states of HW.) It leads to pipe state mismatch error
when ddi_get_config is called.
Because the current implementation of lspcon is not ready to support
readout infoframes, we need to return 0 here.
In order to support readout to lspcon, we need to implement read_infoframe
and infoframes_enabled. And set_infoframes also have to set an appropriate
bit on crtc_state->infoframes.enable
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_lspcon.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c
index d807c5648c87..6ff7b226f0a1 100644
--- a/drivers/gpu/drm/i915/display/intel_lspcon.c
+++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
@@ -522,7 +522,7 @@ u32 lspcon_infoframes_enabled(struct intel_encoder *encoder,
const struct intel_crtc_state *pipe_config)
{
/* FIXME actually read this from the hw */
- return enc_to_intel_lspcon(encoder)->active;
+ return 0;
}
void lspcon_resume(struct intel_lspcon *lspcon)
--
2.25.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 73+ messages in thread* [PATCH v12 10/14] drm/i915: Fix enabled infoframe states of lspcon
@ 2020-05-14 6:07 ` Gwan-gyeong Mun
0 siblings, 0 replies; 73+ messages in thread
From: Gwan-gyeong Mun @ 2020-05-14 6:07 UTC (permalink / raw)
To: intel-gfx; +Cc: linux-fbdev, dri-devel, laurent.pinchart
Compared to implementation of DP and HDMI's encoder->infoframes_enabled,
the lspcon's implementation returns its active state. (we expect enabled
infoframe states of HW.) It leads to pipe state mismatch error
when ddi_get_config is called.
Because the current implementation of lspcon is not ready to support
readout infoframes, we need to return 0 here.
In order to support readout to lspcon, we need to implement read_infoframe
and infoframes_enabled. And set_infoframes also have to set an appropriate
bit on crtc_state->infoframes.enable
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_lspcon.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c
index d807c5648c87..6ff7b226f0a1 100644
--- a/drivers/gpu/drm/i915/display/intel_lspcon.c
+++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
@@ -522,7 +522,7 @@ u32 lspcon_infoframes_enabled(struct intel_encoder *encoder,
const struct intel_crtc_state *pipe_config)
{
/* FIXME actually read this from the hw */
- return enc_to_intel_lspcon(encoder)->active;
+ return 0;
}
void lspcon_resume(struct intel_lspcon *lspcon)
--
2.25.0
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https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [PATCH v12 11/14] drm/i915: Program DP SDPs on pipe updates
2020-05-14 6:07 ` Gwan-gyeong Mun
(?)
@ 2020-05-14 6:07 ` Gwan-gyeong Mun
-1 siblings, 0 replies; 73+ messages in thread
From: Gwan-gyeong Mun @ 2020-05-14 6:07 UTC (permalink / raw)
To: intel-gfx; +Cc: linux-fbdev, dri-devel, laurent.pinchart
Call intel_dp_set_infoframes() function on pipe updates to make sure
that we send VSC SDP and HDR Metadata Infoframe SDP (when applicable)
on fastsets.
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 2b54ea47e822..e3f5db787343 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3864,6 +3864,7 @@ static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state,
intel_ddi_set_dp_msa(crtc_state, conn_state);
intel_psr_update(intel_dp, crtc_state);
+ intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
intel_edp_drrs_enable(intel_dp, crtc_state);
intel_panel_update_backlight(state, encoder, crtc_state, conn_state);
--
2.25.0
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [Intel-gfx] [PATCH v12 11/14] drm/i915: Program DP SDPs on pipe updates
@ 2020-05-14 6:07 ` Gwan-gyeong Mun
0 siblings, 0 replies; 73+ messages in thread
From: Gwan-gyeong Mun @ 2020-05-14 6:07 UTC (permalink / raw)
To: intel-gfx; +Cc: linux-fbdev, dri-devel, laurent.pinchart
Call intel_dp_set_infoframes() function on pipe updates to make sure
that we send VSC SDP and HDR Metadata Infoframe SDP (when applicable)
on fastsets.
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 2b54ea47e822..e3f5db787343 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3864,6 +3864,7 @@ static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state,
intel_ddi_set_dp_msa(crtc_state, conn_state);
intel_psr_update(intel_dp, crtc_state);
+ intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
intel_edp_drrs_enable(intel_dp, crtc_state);
intel_panel_update_backlight(state, encoder, crtc_state, conn_state);
--
2.25.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [PATCH v12 11/14] drm/i915: Program DP SDPs on pipe updates
@ 2020-05-14 6:07 ` Gwan-gyeong Mun
0 siblings, 0 replies; 73+ messages in thread
From: Gwan-gyeong Mun @ 2020-05-14 6:07 UTC (permalink / raw)
To: intel-gfx; +Cc: linux-fbdev, dri-devel, laurent.pinchart
Call intel_dp_set_infoframes() function on pipe updates to make sure
that we send VSC SDP and HDR Metadata Infoframe SDP (when applicable)
on fastsets.
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 2b54ea47e822..e3f5db787343 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3864,6 +3864,7 @@ static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state,
intel_ddi_set_dp_msa(crtc_state, conn_state);
intel_psr_update(intel_dp, crtc_state);
+ intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
intel_edp_drrs_enable(intel_dp, crtc_state);
intel_panel_update_backlight(state, encoder, crtc_state, conn_state);
--
2.25.0
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [PATCH v12 12/14] drm/i915: Stop sending DP SDPs on ddi disable
2020-05-14 6:07 ` Gwan-gyeong Mun
(?)
@ 2020-05-14 6:07 ` Gwan-gyeong Mun
-1 siblings, 0 replies; 73+ messages in thread
From: Gwan-gyeong Mun @ 2020-05-14 6:07 UTC (permalink / raw)
To: intel-gfx; +Cc: linux-fbdev, dri-devel, laurent.pinchart
Call intel_dp_set_infoframes(false) function on intel_ddi_post_disable_dp()
to make sure not to send VSC SDP and HDR Metadata Infoframe SDP.
v5: Polish commit message [Uma]
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index e3f5db787343..a5eb8b89946b 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3472,6 +3472,8 @@ static void intel_ddi_post_disable_dp(struct intel_atomic_state *state,
INTEL_OUTPUT_DP_MST);
enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
+ intel_dp_set_infoframes(encoder, false, old_crtc_state, old_conn_state);
+
/*
* Power down sink before disabling the port, otherwise we end
* up getting interrupts from the sink on detecting link loss.
--
2.25.0
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [Intel-gfx] [PATCH v12 12/14] drm/i915: Stop sending DP SDPs on ddi disable
@ 2020-05-14 6:07 ` Gwan-gyeong Mun
0 siblings, 0 replies; 73+ messages in thread
From: Gwan-gyeong Mun @ 2020-05-14 6:07 UTC (permalink / raw)
To: intel-gfx; +Cc: linux-fbdev, dri-devel, laurent.pinchart
Call intel_dp_set_infoframes(false) function on intel_ddi_post_disable_dp()
to make sure not to send VSC SDP and HDR Metadata Infoframe SDP.
v5: Polish commit message [Uma]
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index e3f5db787343..a5eb8b89946b 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3472,6 +3472,8 @@ static void intel_ddi_post_disable_dp(struct intel_atomic_state *state,
INTEL_OUTPUT_DP_MST);
enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
+ intel_dp_set_infoframes(encoder, false, old_crtc_state, old_conn_state);
+
/*
* Power down sink before disabling the port, otherwise we end
* up getting interrupts from the sink on detecting link loss.
--
2.25.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [PATCH v12 12/14] drm/i915: Stop sending DP SDPs on ddi disable
@ 2020-05-14 6:07 ` Gwan-gyeong Mun
0 siblings, 0 replies; 73+ messages in thread
From: Gwan-gyeong Mun @ 2020-05-14 6:07 UTC (permalink / raw)
To: intel-gfx; +Cc: linux-fbdev, dri-devel, laurent.pinchart
Call intel_dp_set_infoframes(false) function on intel_ddi_post_disable_dp()
to make sure not to send VSC SDP and HDR Metadata Infoframe SDP.
v5: Polish commit message [Uma]
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index e3f5db787343..a5eb8b89946b 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3472,6 +3472,8 @@ static void intel_ddi_post_disable_dp(struct intel_atomic_state *state,
INTEL_OUTPUT_DP_MST);
enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
+ intel_dp_set_infoframes(encoder, false, old_crtc_state, old_conn_state);
+
/*
* Power down sink before disabling the port, otherwise we end
* up getting interrupts from the sink on detecting link loss.
--
2.25.0
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [PATCH v12 13/14] drm/i915/dp: Add compute routine for DP PSR VSC SDP
2020-05-14 6:07 ` Gwan-gyeong Mun
(?)
@ 2020-05-14 6:07 ` Gwan-gyeong Mun
-1 siblings, 0 replies; 73+ messages in thread
From: Gwan-gyeong Mun @ 2020-05-14 6:07 UTC (permalink / raw)
To: intel-gfx; +Cc: linux-fbdev, dri-devel, laurent.pinchart
In order to use a common VSC SDP Colorimetry calculating code on PSR,
it adds a compute routine for PSR VSC SDP.
As PSR routine can not use infoframes.vsc of crtc state, it also adds new
writing of DP SDPs (Secondary Data Packet) for PSR.
PSR routine has its own scenario and timings of writing a VSC SDP.
v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp
v4: Use struct drm_device logging macros
v10: 1) Fix packing of VSC SDP where Pixel Encoding/Colorimetry Format is
not supported.
2) Change a checking of PSR state.
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 66 ++++++++++++++++++++++++-
drivers/gpu/drm/i915/display/intel_dp.h | 8 +++
2 files changed, 72 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 4ccd6b7a3d83..408c3c1c5e81 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2487,8 +2487,8 @@ static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
{
struct drm_dp_vsc_sdp *vsc = &crtc_state->infoframes.vsc;
- /* When PSR is enabled, VSC SDP is handled by PSR routine */
- if (intel_psr_enabled(intel_dp))
+ /* When a crtc state has PSR, VSC SDP will be handled by PSR routine */
+ if (crtc_state->has_psr)
return;
if (!intel_dp_needs_vsc_sdp(crtc_state, conn_state))
@@ -2500,6 +2500,42 @@ static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
&crtc_state->infoframes.vsc);
}
+void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state,
+ const struct drm_connector_state *conn_state,
+ struct drm_dp_vsc_sdp *vsc)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+
+ vsc->sdp_type = DP_SDP_VSC;
+
+ if (dev_priv->psr.psr2_enabled) {
+ if (dev_priv->psr.colorimetry_support &&
+ intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
+ /* [PSR2, +Colorimetry] */
+ intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
+ vsc);
+ } else {
+ /*
+ * [PSR2, -Colorimetry]
+ * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11
+ * 3D stereo + PSR/PSR2 + Y-coordinate.
+ */
+ vsc->revision = 0x4;
+ vsc->length = 0xe;
+ }
+ } else {
+ /*
+ * [PSR1]
+ * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
+ * VSC SDP supporting 3D stereo + PSR (applies to eDP v1.3 or
+ * higher).
+ */
+ vsc->revision = 0x2;
+ vsc->length = 0x8;
+ }
+}
+
static void
intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
struct intel_crtc_state *crtc_state,
@@ -4791,6 +4827,13 @@ static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */
sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
+ /*
+ * Only revision 0x5 supports Pixel Encoding/Colorimetry Format as
+ * per DP 1.4a spec.
+ */
+ if (vsc->revision != 0x5)
+ goto out;
+
/* VSC SDP Payload for DB16 through DB18 */
/* Pixel Encoding and Colorimetry Formats */
sdp->db[16] = (vsc->pixelformat & 0xf) << 4; /* DB16[7:4] */
@@ -4823,6 +4866,7 @@ static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
/* Content Type */
sdp->db[18] = vsc->content_type & 0x7;
+out:
return length;
}
@@ -4935,6 +4979,24 @@ static void intel_write_dp_sdp(struct intel_encoder *encoder,
intel_dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len);
}
+void intel_write_dp_vsc_sdp(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
+ struct drm_dp_vsc_sdp *vsc)
+{
+ struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct dp_sdp sdp = {};
+ ssize_t len;
+
+ len = intel_dp_vsc_sdp_pack(vsc, &sdp, sizeof(sdp));
+
+ if (drm_WARN_ON(&dev_priv->drm, len < 0))
+ return;
+
+ intel_dig_port->write_infoframe(encoder, crtc_state, DP_SDP_VSC,
+ &sdp, len);
+}
+
void intel_dp_set_infoframes(struct intel_encoder *encoder,
bool enable,
const struct intel_crtc_state *crtc_state,
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 0d2de15703c3..1702959ca079 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -16,6 +16,7 @@ struct drm_connector_state;
struct drm_encoder;
struct drm_i915_private;
struct drm_modeset_acquire_ctx;
+struct drm_dp_vsc_sdp;
struct intel_connector;
struct intel_crtc_state;
struct intel_digital_port;
@@ -108,6 +109,13 @@ int intel_dp_link_required(int pixel_clock, int bpp);
int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
bool intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state);
+void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state,
+ const struct drm_connector_state *conn_state,
+ struct drm_dp_vsc_sdp *vsc);
+void intel_write_dp_vsc_sdp(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
+ struct drm_dp_vsc_sdp *vsc);
void intel_dp_set_infoframes(struct intel_encoder *encoder, bool enable,
const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state);
--
2.25.0
^ permalink raw reply related [flat|nested] 73+ messages in thread* [Intel-gfx] [PATCH v12 13/14] drm/i915/dp: Add compute routine for DP PSR VSC SDP
@ 2020-05-14 6:07 ` Gwan-gyeong Mun
0 siblings, 0 replies; 73+ messages in thread
From: Gwan-gyeong Mun @ 2020-05-14 6:07 UTC (permalink / raw)
To: intel-gfx; +Cc: linux-fbdev, dri-devel, laurent.pinchart
In order to use a common VSC SDP Colorimetry calculating code on PSR,
it adds a compute routine for PSR VSC SDP.
As PSR routine can not use infoframes.vsc of crtc state, it also adds new
writing of DP SDPs (Secondary Data Packet) for PSR.
PSR routine has its own scenario and timings of writing a VSC SDP.
v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp
v4: Use struct drm_device logging macros
v10: 1) Fix packing of VSC SDP where Pixel Encoding/Colorimetry Format is
not supported.
2) Change a checking of PSR state.
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 66 ++++++++++++++++++++++++-
drivers/gpu/drm/i915/display/intel_dp.h | 8 +++
2 files changed, 72 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 4ccd6b7a3d83..408c3c1c5e81 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2487,8 +2487,8 @@ static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
{
struct drm_dp_vsc_sdp *vsc = &crtc_state->infoframes.vsc;
- /* When PSR is enabled, VSC SDP is handled by PSR routine */
- if (intel_psr_enabled(intel_dp))
+ /* When a crtc state has PSR, VSC SDP will be handled by PSR routine */
+ if (crtc_state->has_psr)
return;
if (!intel_dp_needs_vsc_sdp(crtc_state, conn_state))
@@ -2500,6 +2500,42 @@ static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
&crtc_state->infoframes.vsc);
}
+void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state,
+ const struct drm_connector_state *conn_state,
+ struct drm_dp_vsc_sdp *vsc)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+
+ vsc->sdp_type = DP_SDP_VSC;
+
+ if (dev_priv->psr.psr2_enabled) {
+ if (dev_priv->psr.colorimetry_support &&
+ intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
+ /* [PSR2, +Colorimetry] */
+ intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
+ vsc);
+ } else {
+ /*
+ * [PSR2, -Colorimetry]
+ * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11
+ * 3D stereo + PSR/PSR2 + Y-coordinate.
+ */
+ vsc->revision = 0x4;
+ vsc->length = 0xe;
+ }
+ } else {
+ /*
+ * [PSR1]
+ * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
+ * VSC SDP supporting 3D stereo + PSR (applies to eDP v1.3 or
+ * higher).
+ */
+ vsc->revision = 0x2;
+ vsc->length = 0x8;
+ }
+}
+
static void
intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
struct intel_crtc_state *crtc_state,
@@ -4791,6 +4827,13 @@ static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */
sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
+ /*
+ * Only revision 0x5 supports Pixel Encoding/Colorimetry Format as
+ * per DP 1.4a spec.
+ */
+ if (vsc->revision != 0x5)
+ goto out;
+
/* VSC SDP Payload for DB16 through DB18 */
/* Pixel Encoding and Colorimetry Formats */
sdp->db[16] = (vsc->pixelformat & 0xf) << 4; /* DB16[7:4] */
@@ -4823,6 +4866,7 @@ static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
/* Content Type */
sdp->db[18] = vsc->content_type & 0x7;
+out:
return length;
}
@@ -4935,6 +4979,24 @@ static void intel_write_dp_sdp(struct intel_encoder *encoder,
intel_dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len);
}
+void intel_write_dp_vsc_sdp(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
+ struct drm_dp_vsc_sdp *vsc)
+{
+ struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct dp_sdp sdp = {};
+ ssize_t len;
+
+ len = intel_dp_vsc_sdp_pack(vsc, &sdp, sizeof(sdp));
+
+ if (drm_WARN_ON(&dev_priv->drm, len < 0))
+ return;
+
+ intel_dig_port->write_infoframe(encoder, crtc_state, DP_SDP_VSC,
+ &sdp, len);
+}
+
void intel_dp_set_infoframes(struct intel_encoder *encoder,
bool enable,
const struct intel_crtc_state *crtc_state,
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 0d2de15703c3..1702959ca079 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -16,6 +16,7 @@ struct drm_connector_state;
struct drm_encoder;
struct drm_i915_private;
struct drm_modeset_acquire_ctx;
+struct drm_dp_vsc_sdp;
struct intel_connector;
struct intel_crtc_state;
struct intel_digital_port;
@@ -108,6 +109,13 @@ int intel_dp_link_required(int pixel_clock, int bpp);
int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
bool intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state);
+void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state,
+ const struct drm_connector_state *conn_state,
+ struct drm_dp_vsc_sdp *vsc);
+void intel_write_dp_vsc_sdp(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
+ struct drm_dp_vsc_sdp *vsc);
void intel_dp_set_infoframes(struct intel_encoder *encoder, bool enable,
const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state);
--
2.25.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 73+ messages in thread* [PATCH v12 13/14] drm/i915/dp: Add compute routine for DP PSR VSC SDP
@ 2020-05-14 6:07 ` Gwan-gyeong Mun
0 siblings, 0 replies; 73+ messages in thread
From: Gwan-gyeong Mun @ 2020-05-14 6:07 UTC (permalink / raw)
To: intel-gfx; +Cc: linux-fbdev, dri-devel, laurent.pinchart
In order to use a common VSC SDP Colorimetry calculating code on PSR,
it adds a compute routine for PSR VSC SDP.
As PSR routine can not use infoframes.vsc of crtc state, it also adds new
writing of DP SDPs (Secondary Data Packet) for PSR.
PSR routine has its own scenario and timings of writing a VSC SDP.
v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp
v4: Use struct drm_device logging macros
v10: 1) Fix packing of VSC SDP where Pixel Encoding/Colorimetry Format is
not supported.
2) Change a checking of PSR state.
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 66 ++++++++++++++++++++++++-
drivers/gpu/drm/i915/display/intel_dp.h | 8 +++
2 files changed, 72 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 4ccd6b7a3d83..408c3c1c5e81 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2487,8 +2487,8 @@ static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
{
struct drm_dp_vsc_sdp *vsc = &crtc_state->infoframes.vsc;
- /* When PSR is enabled, VSC SDP is handled by PSR routine */
- if (intel_psr_enabled(intel_dp))
+ /* When a crtc state has PSR, VSC SDP will be handled by PSR routine */
+ if (crtc_state->has_psr)
return;
if (!intel_dp_needs_vsc_sdp(crtc_state, conn_state))
@@ -2500,6 +2500,42 @@ static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
&crtc_state->infoframes.vsc);
}
+void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state,
+ const struct drm_connector_state *conn_state,
+ struct drm_dp_vsc_sdp *vsc)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+
+ vsc->sdp_type = DP_SDP_VSC;
+
+ if (dev_priv->psr.psr2_enabled) {
+ if (dev_priv->psr.colorimetry_support &&
+ intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
+ /* [PSR2, +Colorimetry] */
+ intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
+ vsc);
+ } else {
+ /*
+ * [PSR2, -Colorimetry]
+ * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11
+ * 3D stereo + PSR/PSR2 + Y-coordinate.
+ */
+ vsc->revision = 0x4;
+ vsc->length = 0xe;
+ }
+ } else {
+ /*
+ * [PSR1]
+ * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
+ * VSC SDP supporting 3D stereo + PSR (applies to eDP v1.3 or
+ * higher).
+ */
+ vsc->revision = 0x2;
+ vsc->length = 0x8;
+ }
+}
+
static void
intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
struct intel_crtc_state *crtc_state,
@@ -4791,6 +4827,13 @@ static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */
sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
+ /*
+ * Only revision 0x5 supports Pixel Encoding/Colorimetry Format as
+ * per DP 1.4a spec.
+ */
+ if (vsc->revision != 0x5)
+ goto out;
+
/* VSC SDP Payload for DB16 through DB18 */
/* Pixel Encoding and Colorimetry Formats */
sdp->db[16] = (vsc->pixelformat & 0xf) << 4; /* DB16[7:4] */
@@ -4823,6 +4866,7 @@ static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
/* Content Type */
sdp->db[18] = vsc->content_type & 0x7;
+out:
return length;
}
@@ -4935,6 +4979,24 @@ static void intel_write_dp_sdp(struct intel_encoder *encoder,
intel_dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len);
}
+void intel_write_dp_vsc_sdp(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
+ struct drm_dp_vsc_sdp *vsc)
+{
+ struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct dp_sdp sdp = {};
+ ssize_t len;
+
+ len = intel_dp_vsc_sdp_pack(vsc, &sdp, sizeof(sdp));
+
+ if (drm_WARN_ON(&dev_priv->drm, len < 0))
+ return;
+
+ intel_dig_port->write_infoframe(encoder, crtc_state, DP_SDP_VSC,
+ &sdp, len);
+}
+
void intel_dp_set_infoframes(struct intel_encoder *encoder,
bool enable,
const struct intel_crtc_state *crtc_state,
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 0d2de15703c3..1702959ca079 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -16,6 +16,7 @@ struct drm_connector_state;
struct drm_encoder;
struct drm_i915_private;
struct drm_modeset_acquire_ctx;
+struct drm_dp_vsc_sdp;
struct intel_connector;
struct intel_crtc_state;
struct intel_digital_port;
@@ -108,6 +109,13 @@ int intel_dp_link_required(int pixel_clock, int bpp);
int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
bool intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state);
+void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state,
+ const struct drm_connector_state *conn_state,
+ struct drm_dp_vsc_sdp *vsc);
+void intel_write_dp_vsc_sdp(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
+ struct drm_dp_vsc_sdp *vsc);
void intel_dp_set_infoframes(struct intel_encoder *encoder, bool enable,
const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state);
--
2.25.0
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [PATCH v12 14/14] drm/i915/psr: Use new DP VSC SDP compute routine on PSR
2020-05-14 6:07 ` Gwan-gyeong Mun
(?)
@ 2020-05-14 6:07 ` Gwan-gyeong Mun
-1 siblings, 0 replies; 73+ messages in thread
From: Gwan-gyeong Mun @ 2020-05-14 6:07 UTC (permalink / raw)
To: intel-gfx; +Cc: linux-fbdev, dri-devel, laurent.pinchart
In order to use a common VSC SDP Colorimetry calculating code on PSR,
it uses a new psr vsc sdp compute routine.
Because PSR routine has its own scenario and timings of writing a VSC SDP,
the current PSR routine needs to have its own drm_dp_vsc_sdp structure
member variable on struct i915_psr.
In order to calculate colorimetry information, intel_psr_update()
function and intel_psr_enable() function extend a drm_connector_state
argument.
There are no changes to PSR mechanism.
v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp
v4: Rebased
v8: Rebased
v10: When a PSR is enabled, it needs to add DP_SDP_VSC to
infoframes.enable.
It is needed for comparing between HW and pipe_state of VSC_SDP.
v11: If PSR is disabled by flag, it don't enable psr on pipe compute.
v12: Fix an inconsistent indenting
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Reported-by: kbuild test robot <lkp@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 4 +-
drivers/gpu/drm/i915/display/intel_psr.c | 58 ++++++++----------------
drivers/gpu/drm/i915/display/intel_psr.h | 6 ++-
drivers/gpu/drm/i915/i915_drv.h | 1 +
4 files changed, 26 insertions(+), 43 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index a5eb8b89946b..aa22465bb56e 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3682,7 +3682,7 @@ static void intel_enable_ddi_dp(struct intel_atomic_state *state,
intel_dp_stop_link_train(intel_dp);
intel_edp_backlight_on(crtc_state, conn_state);
- intel_psr_enable(intel_dp, crtc_state);
+ intel_psr_enable(intel_dp, crtc_state, conn_state);
intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
intel_edp_drrs_enable(intel_dp, crtc_state);
@@ -3865,7 +3865,7 @@ static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state,
intel_ddi_set_dp_msa(crtc_state, conn_state);
- intel_psr_update(intel_dp, crtc_state);
+ intel_psr_update(intel_dp, crtc_state, conn_state);
intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
intel_edp_drrs_enable(intel_dp, crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index a0569fdfeb16..b7a2c102648a 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -30,6 +30,7 @@
#include "intel_display_types.h"
#include "intel_psr.h"
#include "intel_sprite.h"
+#include "intel_hdmi.h"
/**
* DOC: Panel Self Refresh (PSR/SRD)
@@ -357,39 +358,6 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
}
}
-static void intel_psr_setup_vsc(struct intel_dp *intel_dp,
- const struct intel_crtc_state *crtc_state)
-{
- struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- struct dp_sdp psr_vsc;
-
- if (dev_priv->psr.psr2_enabled) {
- /* Prepare VSC Header for SU as per EDP 1.4 spec, Table 6.11 */
- memset(&psr_vsc, 0, sizeof(psr_vsc));
- psr_vsc.sdp_header.HB0 = 0;
- psr_vsc.sdp_header.HB1 = 0x7;
- if (dev_priv->psr.colorimetry_support) {
- psr_vsc.sdp_header.HB2 = 0x5;
- psr_vsc.sdp_header.HB3 = 0x13;
- } else {
- psr_vsc.sdp_header.HB2 = 0x4;
- psr_vsc.sdp_header.HB3 = 0xe;
- }
- } else {
- /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
- memset(&psr_vsc, 0, sizeof(psr_vsc));
- psr_vsc.sdp_header.HB0 = 0;
- psr_vsc.sdp_header.HB1 = 0x7;
- psr_vsc.sdp_header.HB2 = 0x2;
- psr_vsc.sdp_header.HB3 = 0x8;
- }
-
- intel_dig_port->write_infoframe(&intel_dig_port->base,
- crtc_state,
- DP_SDP_VSC, &psr_vsc, sizeof(psr_vsc));
-}
-
static void hsw_psr_setup_aux(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
@@ -756,6 +724,8 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
if (intel_dp != dev_priv->psr.dp)
return;
+ if (!psr_global_enabled(dev_priv))
+ return;
/*
* HSW spec explicitly says PSR is tied to port A.
* BDW+ platforms have a instance of PSR registers per transcoder but
@@ -798,6 +768,7 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
crtc_state->has_psr = true;
crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state);
+ crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
}
static void intel_psr_activate(struct intel_dp *intel_dp)
@@ -880,9 +851,12 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
}
static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
- const struct intel_crtc_state *crtc_state)
+ const struct intel_crtc_state *crtc_state,
+ const struct drm_connector_state *conn_state)
{
struct intel_dp *intel_dp = dev_priv->psr.dp;
+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+ struct intel_encoder *encoder = &intel_dig_port->base;
u32 val;
drm_WARN_ON(&dev_priv->drm, dev_priv->psr.enabled);
@@ -921,7 +895,9 @@ static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n",
dev_priv->psr.psr2_enabled ? "2" : "1");
- intel_psr_setup_vsc(intel_dp, crtc_state);
+ intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state, conn_state,
+ &dev_priv->psr.vsc);
+ intel_write_dp_vsc_sdp(encoder, crtc_state, &dev_priv->psr.vsc);
intel_psr_enable_sink(intel_dp);
intel_psr_enable_source(intel_dp, crtc_state);
dev_priv->psr.enabled = true;
@@ -933,11 +909,13 @@ static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
* intel_psr_enable - Enable PSR
* @intel_dp: Intel DP
* @crtc_state: new CRTC state
+ * @conn_state: new CONNECTOR state
*
* This function can only be called after the pipe is fully trained and enabled.
*/
void intel_psr_enable(struct intel_dp *intel_dp,
- const struct intel_crtc_state *crtc_state)
+ const struct intel_crtc_state *crtc_state,
+ const struct drm_connector_state *conn_state)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
@@ -958,7 +936,7 @@ void intel_psr_enable(struct intel_dp *intel_dp,
goto unlock;
}
- intel_psr_enable_locked(dev_priv, crtc_state);
+ intel_psr_enable_locked(dev_priv, crtc_state, conn_state);
unlock:
mutex_unlock(&dev_priv->psr.lock);
@@ -1091,13 +1069,15 @@ static void psr_force_hw_tracking_exit(struct drm_i915_private *dev_priv)
* intel_psr_update - Update PSR state
* @intel_dp: Intel DP
* @crtc_state: new CRTC state
+ * @conn_state: new CONNECTOR state
*
* This functions will update PSR states, disabling, enabling or switching PSR
* version when executing fastsets. For full modeset, intel_psr_disable() and
* intel_psr_enable() should be called instead.
*/
void intel_psr_update(struct intel_dp *intel_dp,
- const struct intel_crtc_state *crtc_state)
+ const struct intel_crtc_state *crtc_state,
+ const struct drm_connector_state *conn_state)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
struct i915_psr *psr = &dev_priv->psr;
@@ -1134,7 +1114,7 @@ void intel_psr_update(struct intel_dp *intel_dp,
intel_psr_disable_locked(intel_dp);
if (enable)
- intel_psr_enable_locked(dev_priv, crtc_state);
+ intel_psr_enable_locked(dev_priv, crtc_state, conn_state);
unlock:
mutex_unlock(&dev_priv->psr.lock);
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
index 274fc6bb6221..b4515186d5f4 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -17,11 +17,13 @@ struct intel_dp;
#define CAN_PSR(dev_priv) (HAS_PSR(dev_priv) && dev_priv->psr.sink_support)
void intel_psr_init_dpcd(struct intel_dp *intel_dp);
void intel_psr_enable(struct intel_dp *intel_dp,
- const struct intel_crtc_state *crtc_state);
+ const struct intel_crtc_state *crtc_state,
+ const struct drm_connector_state *conn_state);
void intel_psr_disable(struct intel_dp *intel_dp,
const struct intel_crtc_state *old_crtc_state);
void intel_psr_update(struct intel_dp *intel_dp,
- const struct intel_crtc_state *crtc_state);
+ const struct intel_crtc_state *crtc_state,
+ const struct drm_connector_state *conn_state);
int intel_psr_debug_set(struct drm_i915_private *dev_priv, u64 value);
void intel_psr_invalidate(struct drm_i915_private *dev_priv,
unsigned frontbuffer_bits,
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 631d31bc2313..a378d52341e6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -512,6 +512,7 @@ struct i915_psr {
u32 dc3co_exit_delay;
struct delayed_work dc3co_work;
bool force_mode_changed;
+ struct drm_dp_vsc_sdp vsc;
};
#define QUIRK_LVDS_SSC_DISABLE (1<<1)
--
2.25.0
^ permalink raw reply related [flat|nested] 73+ messages in thread* [Intel-gfx] [PATCH v12 14/14] drm/i915/psr: Use new DP VSC SDP compute routine on PSR
@ 2020-05-14 6:07 ` Gwan-gyeong Mun
0 siblings, 0 replies; 73+ messages in thread
From: Gwan-gyeong Mun @ 2020-05-14 6:07 UTC (permalink / raw)
To: intel-gfx; +Cc: linux-fbdev, dri-devel, laurent.pinchart
In order to use a common VSC SDP Colorimetry calculating code on PSR,
it uses a new psr vsc sdp compute routine.
Because PSR routine has its own scenario and timings of writing a VSC SDP,
the current PSR routine needs to have its own drm_dp_vsc_sdp structure
member variable on struct i915_psr.
In order to calculate colorimetry information, intel_psr_update()
function and intel_psr_enable() function extend a drm_connector_state
argument.
There are no changes to PSR mechanism.
v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp
v4: Rebased
v8: Rebased
v10: When a PSR is enabled, it needs to add DP_SDP_VSC to
infoframes.enable.
It is needed for comparing between HW and pipe_state of VSC_SDP.
v11: If PSR is disabled by flag, it don't enable psr on pipe compute.
v12: Fix an inconsistent indenting
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Reported-by: kbuild test robot <lkp@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 4 +-
drivers/gpu/drm/i915/display/intel_psr.c | 58 ++++++++----------------
drivers/gpu/drm/i915/display/intel_psr.h | 6 ++-
drivers/gpu/drm/i915/i915_drv.h | 1 +
4 files changed, 26 insertions(+), 43 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index a5eb8b89946b..aa22465bb56e 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3682,7 +3682,7 @@ static void intel_enable_ddi_dp(struct intel_atomic_state *state,
intel_dp_stop_link_train(intel_dp);
intel_edp_backlight_on(crtc_state, conn_state);
- intel_psr_enable(intel_dp, crtc_state);
+ intel_psr_enable(intel_dp, crtc_state, conn_state);
intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
intel_edp_drrs_enable(intel_dp, crtc_state);
@@ -3865,7 +3865,7 @@ static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state,
intel_ddi_set_dp_msa(crtc_state, conn_state);
- intel_psr_update(intel_dp, crtc_state);
+ intel_psr_update(intel_dp, crtc_state, conn_state);
intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
intel_edp_drrs_enable(intel_dp, crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index a0569fdfeb16..b7a2c102648a 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -30,6 +30,7 @@
#include "intel_display_types.h"
#include "intel_psr.h"
#include "intel_sprite.h"
+#include "intel_hdmi.h"
/**
* DOC: Panel Self Refresh (PSR/SRD)
@@ -357,39 +358,6 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
}
}
-static void intel_psr_setup_vsc(struct intel_dp *intel_dp,
- const struct intel_crtc_state *crtc_state)
-{
- struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- struct dp_sdp psr_vsc;
-
- if (dev_priv->psr.psr2_enabled) {
- /* Prepare VSC Header for SU as per EDP 1.4 spec, Table 6.11 */
- memset(&psr_vsc, 0, sizeof(psr_vsc));
- psr_vsc.sdp_header.HB0 = 0;
- psr_vsc.sdp_header.HB1 = 0x7;
- if (dev_priv->psr.colorimetry_support) {
- psr_vsc.sdp_header.HB2 = 0x5;
- psr_vsc.sdp_header.HB3 = 0x13;
- } else {
- psr_vsc.sdp_header.HB2 = 0x4;
- psr_vsc.sdp_header.HB3 = 0xe;
- }
- } else {
- /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
- memset(&psr_vsc, 0, sizeof(psr_vsc));
- psr_vsc.sdp_header.HB0 = 0;
- psr_vsc.sdp_header.HB1 = 0x7;
- psr_vsc.sdp_header.HB2 = 0x2;
- psr_vsc.sdp_header.HB3 = 0x8;
- }
-
- intel_dig_port->write_infoframe(&intel_dig_port->base,
- crtc_state,
- DP_SDP_VSC, &psr_vsc, sizeof(psr_vsc));
-}
-
static void hsw_psr_setup_aux(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
@@ -756,6 +724,8 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
if (intel_dp != dev_priv->psr.dp)
return;
+ if (!psr_global_enabled(dev_priv))
+ return;
/*
* HSW spec explicitly says PSR is tied to port A.
* BDW+ platforms have a instance of PSR registers per transcoder but
@@ -798,6 +768,7 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
crtc_state->has_psr = true;
crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state);
+ crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
}
static void intel_psr_activate(struct intel_dp *intel_dp)
@@ -880,9 +851,12 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
}
static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
- const struct intel_crtc_state *crtc_state)
+ const struct intel_crtc_state *crtc_state,
+ const struct drm_connector_state *conn_state)
{
struct intel_dp *intel_dp = dev_priv->psr.dp;
+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+ struct intel_encoder *encoder = &intel_dig_port->base;
u32 val;
drm_WARN_ON(&dev_priv->drm, dev_priv->psr.enabled);
@@ -921,7 +895,9 @@ static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n",
dev_priv->psr.psr2_enabled ? "2" : "1");
- intel_psr_setup_vsc(intel_dp, crtc_state);
+ intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state, conn_state,
+ &dev_priv->psr.vsc);
+ intel_write_dp_vsc_sdp(encoder, crtc_state, &dev_priv->psr.vsc);
intel_psr_enable_sink(intel_dp);
intel_psr_enable_source(intel_dp, crtc_state);
dev_priv->psr.enabled = true;
@@ -933,11 +909,13 @@ static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
* intel_psr_enable - Enable PSR
* @intel_dp: Intel DP
* @crtc_state: new CRTC state
+ * @conn_state: new CONNECTOR state
*
* This function can only be called after the pipe is fully trained and enabled.
*/
void intel_psr_enable(struct intel_dp *intel_dp,
- const struct intel_crtc_state *crtc_state)
+ const struct intel_crtc_state *crtc_state,
+ const struct drm_connector_state *conn_state)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
@@ -958,7 +936,7 @@ void intel_psr_enable(struct intel_dp *intel_dp,
goto unlock;
}
- intel_psr_enable_locked(dev_priv, crtc_state);
+ intel_psr_enable_locked(dev_priv, crtc_state, conn_state);
unlock:
mutex_unlock(&dev_priv->psr.lock);
@@ -1091,13 +1069,15 @@ static void psr_force_hw_tracking_exit(struct drm_i915_private *dev_priv)
* intel_psr_update - Update PSR state
* @intel_dp: Intel DP
* @crtc_state: new CRTC state
+ * @conn_state: new CONNECTOR state
*
* This functions will update PSR states, disabling, enabling or switching PSR
* version when executing fastsets. For full modeset, intel_psr_disable() and
* intel_psr_enable() should be called instead.
*/
void intel_psr_update(struct intel_dp *intel_dp,
- const struct intel_crtc_state *crtc_state)
+ const struct intel_crtc_state *crtc_state,
+ const struct drm_connector_state *conn_state)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
struct i915_psr *psr = &dev_priv->psr;
@@ -1134,7 +1114,7 @@ void intel_psr_update(struct intel_dp *intel_dp,
intel_psr_disable_locked(intel_dp);
if (enable)
- intel_psr_enable_locked(dev_priv, crtc_state);
+ intel_psr_enable_locked(dev_priv, crtc_state, conn_state);
unlock:
mutex_unlock(&dev_priv->psr.lock);
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
index 274fc6bb6221..b4515186d5f4 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -17,11 +17,13 @@ struct intel_dp;
#define CAN_PSR(dev_priv) (HAS_PSR(dev_priv) && dev_priv->psr.sink_support)
void intel_psr_init_dpcd(struct intel_dp *intel_dp);
void intel_psr_enable(struct intel_dp *intel_dp,
- const struct intel_crtc_state *crtc_state);
+ const struct intel_crtc_state *crtc_state,
+ const struct drm_connector_state *conn_state);
void intel_psr_disable(struct intel_dp *intel_dp,
const struct intel_crtc_state *old_crtc_state);
void intel_psr_update(struct intel_dp *intel_dp,
- const struct intel_crtc_state *crtc_state);
+ const struct intel_crtc_state *crtc_state,
+ const struct drm_connector_state *conn_state);
int intel_psr_debug_set(struct drm_i915_private *dev_priv, u64 value);
void intel_psr_invalidate(struct drm_i915_private *dev_priv,
unsigned frontbuffer_bits,
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 631d31bc2313..a378d52341e6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -512,6 +512,7 @@ struct i915_psr {
u32 dc3co_exit_delay;
struct delayed_work dc3co_work;
bool force_mode_changed;
+ struct drm_dp_vsc_sdp vsc;
};
#define QUIRK_LVDS_SSC_DISABLE (1<<1)
--
2.25.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 73+ messages in thread* [PATCH v12 14/14] drm/i915/psr: Use new DP VSC SDP compute routine on PSR
@ 2020-05-14 6:07 ` Gwan-gyeong Mun
0 siblings, 0 replies; 73+ messages in thread
From: Gwan-gyeong Mun @ 2020-05-14 6:07 UTC (permalink / raw)
To: intel-gfx; +Cc: linux-fbdev, dri-devel, laurent.pinchart
In order to use a common VSC SDP Colorimetry calculating code on PSR,
it uses a new psr vsc sdp compute routine.
Because PSR routine has its own scenario and timings of writing a VSC SDP,
the current PSR routine needs to have its own drm_dp_vsc_sdp structure
member variable on struct i915_psr.
In order to calculate colorimetry information, intel_psr_update()
function and intel_psr_enable() function extend a drm_connector_state
argument.
There are no changes to PSR mechanism.
v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp
v4: Rebased
v8: Rebased
v10: When a PSR is enabled, it needs to add DP_SDP_VSC to
infoframes.enable.
It is needed for comparing between HW and pipe_state of VSC_SDP.
v11: If PSR is disabled by flag, it don't enable psr on pipe compute.
v12: Fix an inconsistent indenting
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Reported-by: kbuild test robot <lkp@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 4 +-
drivers/gpu/drm/i915/display/intel_psr.c | 58 ++++++++----------------
drivers/gpu/drm/i915/display/intel_psr.h | 6 ++-
drivers/gpu/drm/i915/i915_drv.h | 1 +
4 files changed, 26 insertions(+), 43 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index a5eb8b89946b..aa22465bb56e 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3682,7 +3682,7 @@ static void intel_enable_ddi_dp(struct intel_atomic_state *state,
intel_dp_stop_link_train(intel_dp);
intel_edp_backlight_on(crtc_state, conn_state);
- intel_psr_enable(intel_dp, crtc_state);
+ intel_psr_enable(intel_dp, crtc_state, conn_state);
intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
intel_edp_drrs_enable(intel_dp, crtc_state);
@@ -3865,7 +3865,7 @@ static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state,
intel_ddi_set_dp_msa(crtc_state, conn_state);
- intel_psr_update(intel_dp, crtc_state);
+ intel_psr_update(intel_dp, crtc_state, conn_state);
intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
intel_edp_drrs_enable(intel_dp, crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index a0569fdfeb16..b7a2c102648a 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -30,6 +30,7 @@
#include "intel_display_types.h"
#include "intel_psr.h"
#include "intel_sprite.h"
+#include "intel_hdmi.h"
/**
* DOC: Panel Self Refresh (PSR/SRD)
@@ -357,39 +358,6 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
}
}
-static void intel_psr_setup_vsc(struct intel_dp *intel_dp,
- const struct intel_crtc_state *crtc_state)
-{
- struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- struct dp_sdp psr_vsc;
-
- if (dev_priv->psr.psr2_enabled) {
- /* Prepare VSC Header for SU as per EDP 1.4 spec, Table 6.11 */
- memset(&psr_vsc, 0, sizeof(psr_vsc));
- psr_vsc.sdp_header.HB0 = 0;
- psr_vsc.sdp_header.HB1 = 0x7;
- if (dev_priv->psr.colorimetry_support) {
- psr_vsc.sdp_header.HB2 = 0x5;
- psr_vsc.sdp_header.HB3 = 0x13;
- } else {
- psr_vsc.sdp_header.HB2 = 0x4;
- psr_vsc.sdp_header.HB3 = 0xe;
- }
- } else {
- /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
- memset(&psr_vsc, 0, sizeof(psr_vsc));
- psr_vsc.sdp_header.HB0 = 0;
- psr_vsc.sdp_header.HB1 = 0x7;
- psr_vsc.sdp_header.HB2 = 0x2;
- psr_vsc.sdp_header.HB3 = 0x8;
- }
-
- intel_dig_port->write_infoframe(&intel_dig_port->base,
- crtc_state,
- DP_SDP_VSC, &psr_vsc, sizeof(psr_vsc));
-}
-
static void hsw_psr_setup_aux(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
@@ -756,6 +724,8 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
if (intel_dp != dev_priv->psr.dp)
return;
+ if (!psr_global_enabled(dev_priv))
+ return;
/*
* HSW spec explicitly says PSR is tied to port A.
* BDW+ platforms have a instance of PSR registers per transcoder but
@@ -798,6 +768,7 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
crtc_state->has_psr = true;
crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state);
+ crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
}
static void intel_psr_activate(struct intel_dp *intel_dp)
@@ -880,9 +851,12 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
}
static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
- const struct intel_crtc_state *crtc_state)
+ const struct intel_crtc_state *crtc_state,
+ const struct drm_connector_state *conn_state)
{
struct intel_dp *intel_dp = dev_priv->psr.dp;
+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+ struct intel_encoder *encoder = &intel_dig_port->base;
u32 val;
drm_WARN_ON(&dev_priv->drm, dev_priv->psr.enabled);
@@ -921,7 +895,9 @@ static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n",
dev_priv->psr.psr2_enabled ? "2" : "1");
- intel_psr_setup_vsc(intel_dp, crtc_state);
+ intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state, conn_state,
+ &dev_priv->psr.vsc);
+ intel_write_dp_vsc_sdp(encoder, crtc_state, &dev_priv->psr.vsc);
intel_psr_enable_sink(intel_dp);
intel_psr_enable_source(intel_dp, crtc_state);
dev_priv->psr.enabled = true;
@@ -933,11 +909,13 @@ static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
* intel_psr_enable - Enable PSR
* @intel_dp: Intel DP
* @crtc_state: new CRTC state
+ * @conn_state: new CONNECTOR state
*
* This function can only be called after the pipe is fully trained and enabled.
*/
void intel_psr_enable(struct intel_dp *intel_dp,
- const struct intel_crtc_state *crtc_state)
+ const struct intel_crtc_state *crtc_state,
+ const struct drm_connector_state *conn_state)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
@@ -958,7 +936,7 @@ void intel_psr_enable(struct intel_dp *intel_dp,
goto unlock;
}
- intel_psr_enable_locked(dev_priv, crtc_state);
+ intel_psr_enable_locked(dev_priv, crtc_state, conn_state);
unlock:
mutex_unlock(&dev_priv->psr.lock);
@@ -1091,13 +1069,15 @@ static void psr_force_hw_tracking_exit(struct drm_i915_private *dev_priv)
* intel_psr_update - Update PSR state
* @intel_dp: Intel DP
* @crtc_state: new CRTC state
+ * @conn_state: new CONNECTOR state
*
* This functions will update PSR states, disabling, enabling or switching PSR
* version when executing fastsets. For full modeset, intel_psr_disable() and
* intel_psr_enable() should be called instead.
*/
void intel_psr_update(struct intel_dp *intel_dp,
- const struct intel_crtc_state *crtc_state)
+ const struct intel_crtc_state *crtc_state,
+ const struct drm_connector_state *conn_state)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
struct i915_psr *psr = &dev_priv->psr;
@@ -1134,7 +1114,7 @@ void intel_psr_update(struct intel_dp *intel_dp,
intel_psr_disable_locked(intel_dp);
if (enable)
- intel_psr_enable_locked(dev_priv, crtc_state);
+ intel_psr_enable_locked(dev_priv, crtc_state, conn_state);
unlock:
mutex_unlock(&dev_priv->psr.lock);
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
index 274fc6bb6221..b4515186d5f4 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -17,11 +17,13 @@ struct intel_dp;
#define CAN_PSR(dev_priv) (HAS_PSR(dev_priv) && dev_priv->psr.sink_support)
void intel_psr_init_dpcd(struct intel_dp *intel_dp);
void intel_psr_enable(struct intel_dp *intel_dp,
- const struct intel_crtc_state *crtc_state);
+ const struct intel_crtc_state *crtc_state,
+ const struct drm_connector_state *conn_state);
void intel_psr_disable(struct intel_dp *intel_dp,
const struct intel_crtc_state *old_crtc_state);
void intel_psr_update(struct intel_dp *intel_dp,
- const struct intel_crtc_state *crtc_state);
+ const struct intel_crtc_state *crtc_state,
+ const struct drm_connector_state *conn_state);
int intel_psr_debug_set(struct drm_i915_private *dev_priv, u64 value);
void intel_psr_invalidate(struct drm_i915_private *dev_priv,
unsigned frontbuffer_bits,
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 631d31bc2313..a378d52341e6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -512,6 +512,7 @@ struct i915_psr {
u32 dc3co_exit_delay;
struct delayed_work dc3co_work;
bool force_mode_changed;
+ struct drm_dp_vsc_sdp vsc;
};
#define QUIRK_LVDS_SSC_DISABLE (1<<1)
--
2.25.0
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for In order to readout DP SDPs, refactors the handling of DP SDPs (rev14)
2020-05-14 6:07 ` Gwan-gyeong Mun
` (15 preceding siblings ...)
(?)
@ 2020-05-14 6:24 ` Patchwork
-1 siblings, 0 replies; 73+ messages in thread
From: Patchwork @ 2020-05-14 6:24 UTC (permalink / raw)
To: Mun, Gwan-gyeong; +Cc: intel-gfx
== Series Details ==
Series: In order to readout DP SDPs, refactors the handling of DP SDPs (rev14)
URL : https://patchwork.freedesktop.org/series/72853/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
e1053fdca03e video/hdmi: Add Unpack only function for DRM infoframe
0a10f4cd6cbe drm/i915/dp: Read out DP SDPs
bf5fbd357375 drm: Add logging function for DP VSC SDP
b53f926b3fa5 drm/i915: Include HDMI DRM infoframe in the crtc state dump
af8b261a6986 drm/i915: Include DP HDR Metadata Infoframe SDP in the crtc state dump
2375c1f7c8e0 drm/i915: Include DP VSC SDP in the crtc state dump
c7d93732395b drm/i915: Program DP SDPs with computed configs
1723115921c6 drm/i915: Add state readout for DP HDR Metadata Infoframe SDP
99bcd01ba088 drm/i915: Add state readout for DP VSC SDP
-:83: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'name' - possible side-effects?
#83: FILE: drivers/gpu/drm/i915/display/intel_display.c:13750:
+#define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \
+ if (!current_config->has_psr && !pipe_config->has_psr && \
+ !intel_compare_dp_vsc_sdp(¤t_config->infoframes.name, \
+ &pipe_config->infoframes.name)) { \
+ pipe_config_dp_vsc_sdp_mismatch(dev_priv, fastset, __stringify(name), \
+ ¤t_config->infoframes.name, \
+ &pipe_config->infoframes.name); \
+ ret = false; \
+ } \
+} while (0)
total: 0 errors, 0 warnings, 1 checks, 75 lines checked
e373569ff8b1 drm/i915: Fix enabled infoframe states of lspcon
5ac865ae0f3c drm/i915: Program DP SDPs on pipe updates
f8d2eda49214 drm/i915: Stop sending DP SDPs on ddi disable
6d1aa4db1cc0 drm/i915/dp: Add compute routine for DP PSR VSC SDP
b391c6a63abc drm/i915/psr: Use new DP VSC SDP compute routine on PSR
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 73+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for In order to readout DP SDPs, refactors the handling of DP SDPs (rev14)
2020-05-14 6:07 ` Gwan-gyeong Mun
` (16 preceding siblings ...)
(?)
@ 2020-05-14 6:48 ` Patchwork
-1 siblings, 0 replies; 73+ messages in thread
From: Patchwork @ 2020-05-14 6:48 UTC (permalink / raw)
To: Mun, Gwan-gyeong; +Cc: intel-gfx
== Series Details ==
Series: In order to readout DP SDPs, refactors the handling of DP SDPs (rev14)
URL : https://patchwork.freedesktop.org/series/72853/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8481 -> Patchwork_17654
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17654/index.html
Known issues
------------
Here are the changes found in Patchwork_17654 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_pm_rpm@module-reload:
- fi-kbl-guc: [PASS][1] -> [SKIP][2] ([fdo#109271])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8481/fi-kbl-guc/igt@i915_pm_rpm@module-reload.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17654/fi-kbl-guc/igt@i915_pm_rpm@module-reload.html
#### Possible fixes ####
* igt@i915_selftest@live@execlists:
- fi-cml-u2: [INCOMPLETE][3] ([i915#656]) -> [PASS][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8481/fi-cml-u2/igt@i915_selftest@live@execlists.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17654/fi-cml-u2/igt@i915_selftest@live@execlists.html
- fi-kbl-soraka: [INCOMPLETE][5] ([CI#80] / [i915#656]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8481/fi-kbl-soraka/igt@i915_selftest@live@execlists.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17654/fi-kbl-soraka/igt@i915_selftest@live@execlists.html
[CI#80]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/80
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#656]: https://gitlab.freedesktop.org/drm/intel/issues/656
Participating hosts (48 -> 44)
------------------------------
Additional (1): fi-kbl-7560u
Missing (5): fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-hsw-4770 fi-byt-clapper
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_8481 -> Patchwork_17654
CI-20190529: 20190529
CI_DRM_8481: 46f34234505b4e0eb3332974b47a36f9b0825de0 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5654: 5637a466a0b09535517751608f5525a8b468a76b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17654: b391c6a63abcab4ee99c9606550d21a62cc85730 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
b391c6a63abc drm/i915/psr: Use new DP VSC SDP compute routine on PSR
6d1aa4db1cc0 drm/i915/dp: Add compute routine for DP PSR VSC SDP
f8d2eda49214 drm/i915: Stop sending DP SDPs on ddi disable
5ac865ae0f3c drm/i915: Program DP SDPs on pipe updates
e373569ff8b1 drm/i915: Fix enabled infoframe states of lspcon
99bcd01ba088 drm/i915: Add state readout for DP VSC SDP
1723115921c6 drm/i915: Add state readout for DP HDR Metadata Infoframe SDP
c7d93732395b drm/i915: Program DP SDPs with computed configs
2375c1f7c8e0 drm/i915: Include DP VSC SDP in the crtc state dump
af8b261a6986 drm/i915: Include DP HDR Metadata Infoframe SDP in the crtc state dump
b53f926b3fa5 drm/i915: Include HDMI DRM infoframe in the crtc state dump
bf5fbd357375 drm: Add logging function for DP VSC SDP
0a10f4cd6cbe drm/i915/dp: Read out DP SDPs
e1053fdca03e video/hdmi: Add Unpack only function for DRM infoframe
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17654/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 73+ messages in thread* [Intel-gfx] ✓ Fi.CI.IGT: success for In order to readout DP SDPs, refactors the handling of DP SDPs (rev14)
2020-05-14 6:07 ` Gwan-gyeong Mun
` (17 preceding siblings ...)
(?)
@ 2020-05-14 9:07 ` Patchwork
-1 siblings, 0 replies; 73+ messages in thread
From: Patchwork @ 2020-05-14 9:07 UTC (permalink / raw)
To: Mun, Gwan-gyeong; +Cc: intel-gfx
== Series Details ==
Series: In order to readout DP SDPs, refactors the handling of DP SDPs (rev14)
URL : https://patchwork.freedesktop.org/series/72853/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8481_full -> Patchwork_17654_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_17654_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_eio@in-flight-suspend:
- shard-kbl: [PASS][1] -> [DMESG-WARN][2] ([i915#180])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8481/shard-kbl6/igt@gem_eio@in-flight-suspend.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17654/shard-kbl2/igt@gem_eio@in-flight-suspend.html
* igt@kms_big_fb@linear-32bpp-rotate-0:
- shard-kbl: [PASS][3] -> [FAIL][4] ([i915#1119] / [i915#93] / [i915#95])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8481/shard-kbl3/igt@kms_big_fb@linear-32bpp-rotate-0.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17654/shard-kbl2/igt@kms_big_fb@linear-32bpp-rotate-0.html
- shard-apl: [PASS][5] -> [FAIL][6] ([i915#1119] / [i915#95])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8481/shard-apl6/igt@kms_big_fb@linear-32bpp-rotate-0.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17654/shard-apl2/igt@kms_big_fb@linear-32bpp-rotate-0.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
- shard-kbl: [PASS][7] -> [DMESG-WARN][8] ([i915#180] / [i915#93] / [i915#95])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8481/shard-kbl2/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17654/shard-kbl3/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
- shard-apl: [PASS][9] -> [DMESG-WARN][10] ([i915#180])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8481/shard-apl1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17654/shard-apl4/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [PASS][11] -> [FAIL][12] ([fdo#108145] / [i915#265])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8481/shard-skl8/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17654/shard-skl4/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_setmode@basic:
- shard-kbl: [PASS][13] -> [FAIL][14] ([i915#31])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8481/shard-kbl2/igt@kms_setmode@basic.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17654/shard-kbl3/igt@kms_setmode@basic.html
#### Possible fixes ####
* {igt@gem_ctx_isolation@preservation-s3@vecs0}:
- shard-kbl: [DMESG-WARN][15] ([i915#180]) -> [PASS][16] +4 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8481/shard-kbl3/igt@gem_ctx_isolation@preservation-s3@vecs0.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17654/shard-kbl3/igt@gem_ctx_isolation@preservation-s3@vecs0.html
* igt@gem_ctx_shared@q-smoketest-all:
- shard-tglb: [INCOMPLETE][17] -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8481/shard-tglb7/igt@gem_ctx_shared@q-smoketest-all.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17654/shard-tglb6/igt@gem_ctx_shared@q-smoketest-all.html
* igt@i915_suspend@fence-restore-tiled2untiled:
- shard-skl: [INCOMPLETE][19] ([i915#69]) -> [PASS][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8481/shard-skl10/igt@i915_suspend@fence-restore-tiled2untiled.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17654/shard-skl9/igt@i915_suspend@fence-restore-tiled2untiled.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-skl: [FAIL][21] ([IGT#5]) -> [PASS][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8481/shard-skl3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17654/shard-skl2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* {igt@kms_flip@flip-vs-suspend-interruptible@c-dp1}:
- shard-apl: [DMESG-WARN][23] ([i915#180]) -> [PASS][24] +1 similar issue
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8481/shard-apl8/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17654/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
* {igt@kms_flip@plain-flip-fb-recreate@c-edp1}:
- shard-skl: [FAIL][25] -> [PASS][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8481/shard-skl6/igt@kms_flip@plain-flip-fb-recreate@c-edp1.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17654/shard-skl3/igt@kms_flip@plain-flip-fb-recreate@c-edp1.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
- shard-skl: [FAIL][27] ([fdo#108145] / [i915#265]) -> [PASS][28]
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8481/shard-skl10/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17654/shard-skl10/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
* igt@kms_setmode@basic:
- shard-apl: [FAIL][29] ([i915#31]) -> [PASS][30]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8481/shard-apl6/igt@kms_setmode@basic.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17654/shard-apl8/igt@kms_setmode@basic.html
#### Warnings ####
* igt@i915_pm_dc@dc6-psr:
- shard-tglb: [FAIL][31] ([i915#454]) -> [SKIP][32] ([i915#468])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8481/shard-tglb5/igt@i915_pm_dc@dc6-psr.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17654/shard-tglb2/igt@i915_pm_dc@dc6-psr.html
* igt@i915_pm_rpm@debugfs-forcewake-user:
- shard-snb: [INCOMPLETE][33] ([i915#82]) -> [SKIP][34] ([fdo#109271])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8481/shard-snb1/igt@i915_pm_rpm@debugfs-forcewake-user.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17654/shard-snb5/igt@i915_pm_rpm@debugfs-forcewake-user.html
* igt@i915_selftest@live@gt_pm:
- shard-skl: [DMESG-FAIL][35] ([i915#1744]) -> [DMESG-FAIL][36] ([i915#1744] / [i915#1886])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8481/shard-skl4/igt@i915_selftest@live@gt_pm.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17654/shard-skl9/igt@i915_selftest@live@gt_pm.html
* igt@kms_content_protection@atomic:
- shard-apl: [DMESG-FAIL][37] ([fdo#110321]) -> [TIMEOUT][38] ([i915#1319]) +1 similar issue
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8481/shard-apl8/igt@kms_content_protection@atomic.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17654/shard-apl2/igt@kms_content_protection@atomic.html
* igt@kms_content_protection@atomic-dpms:
- shard-apl: [FAIL][39] ([fdo#110321] / [fdo#110336]) -> [TIMEOUT][40] ([i915#1319]) +1 similar issue
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8481/shard-apl2/igt@kms_content_protection@atomic-dpms.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17654/shard-apl3/igt@kms_content_protection@atomic-dpms.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-apl: [DMESG-FAIL][41] ([i915#180] / [i915#95]) -> [FAIL][42] ([i915#1121] / [i915#95])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8481/shard-apl4/igt@kms_fbcon_fbt@fbc-suspend.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17654/shard-apl7/igt@kms_fbcon_fbt@fbc-suspend.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[IGT#5]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/5
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321
[fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336
[i915#1119]: https://gitlab.freedesktop.org/drm/intel/issues/1119
[i915#1121]: https://gitlab.freedesktop.org/drm/intel/issues/1121
[i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
[i915#1744]: https://gitlab.freedesktop.org/drm/intel/issues/1744
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
[i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468
[i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69
[i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82
[i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (11 -> 11)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_8481 -> Patchwork_17654
CI-20190529: 20190529
CI_DRM_8481: 46f34234505b4e0eb3332974b47a36f9b0825de0 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5654: 5637a466a0b09535517751608f5525a8b468a76b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17654: b391c6a63abcab4ee99c9606550d21a62cc85730 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17654/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 73+ messages in thread* Re: [PATCH v12 00/14] In order to readout DP SDPs, refactors the handling of DP SDPs
2020-05-14 6:07 ` Gwan-gyeong Mun
(?)
@ 2020-05-14 11:19 ` Jani Nikula
-1 siblings, 0 replies; 73+ messages in thread
From: Jani Nikula @ 2020-05-14 11:19 UTC (permalink / raw)
To: Gwan-gyeong Mun, intel-gfx
Cc: linux-fbdev, laurent.pinchart, dri-devel, daniel.vetter
On Thu, 14 May 2020, Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> wrote:
> In order to readout DP SDPs (Secondary Data Packet: DP HDR Metadata
> Infoframe SDP, DP VSC SDP), it refactors handling DP SDPs codes.
> It adds new compute routines for DP HDR Metadata Infoframe SDP
> and DP VSC SDP.
> And new writing routines of DP SDPs (Secondary Data Packet) that uses
> computed configs.
> New reading routines of DP SDPs are added for readout.
> It adds a logging function for DP VSC SDP.
> When receiving video it is very useful to be able to log DP VSC SDP.
> This greatly simplifies debugging.
> In order to use a common VSC SDP Colorimetry calculating code on PSR,
> it uses a new psr vsc sdp compute routine.
Pushed the series to drm-intel-next-queued with Daniel's irc ack for
merging the two non-i915 patches that route too.
Thanks for the patches and review!
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [Intel-gfx] [PATCH v12 00/14] In order to readout DP SDPs, refactors the handling of DP SDPs
@ 2020-05-14 11:19 ` Jani Nikula
0 siblings, 0 replies; 73+ messages in thread
From: Jani Nikula @ 2020-05-14 11:19 UTC (permalink / raw)
To: Gwan-gyeong Mun, intel-gfx
Cc: linux-fbdev, laurent.pinchart, dri-devel, daniel.vetter
On Thu, 14 May 2020, Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> wrote:
> In order to readout DP SDPs (Secondary Data Packet: DP HDR Metadata
> Infoframe SDP, DP VSC SDP), it refactors handling DP SDPs codes.
> It adds new compute routines for DP HDR Metadata Infoframe SDP
> and DP VSC SDP.
> And new writing routines of DP SDPs (Secondary Data Packet) that uses
> computed configs.
> New reading routines of DP SDPs are added for readout.
> It adds a logging function for DP VSC SDP.
> When receiving video it is very useful to be able to log DP VSC SDP.
> This greatly simplifies debugging.
> In order to use a common VSC SDP Colorimetry calculating code on PSR,
> it uses a new psr vsc sdp compute routine.
Pushed the series to drm-intel-next-queued with Daniel's irc ack for
merging the two non-i915 patches that route too.
Thanks for the patches and review!
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [PATCH v12 00/14] In order to readout DP SDPs, refactors the handling of DP SDPs
@ 2020-05-14 11:19 ` Jani Nikula
0 siblings, 0 replies; 73+ messages in thread
From: Jani Nikula @ 2020-05-14 11:19 UTC (permalink / raw)
To: Gwan-gyeong Mun, intel-gfx
Cc: linux-fbdev, laurent.pinchart, dri-devel, daniel.vetter
On Thu, 14 May 2020, Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> wrote:
> In order to readout DP SDPs (Secondary Data Packet: DP HDR Metadata
> Infoframe SDP, DP VSC SDP), it refactors handling DP SDPs codes.
> It adds new compute routines for DP HDR Metadata Infoframe SDP
> and DP VSC SDP.
> And new writing routines of DP SDPs (Secondary Data Packet) that uses
> computed configs.
> New reading routines of DP SDPs are added for readout.
> It adds a logging function for DP VSC SDP.
> When receiving video it is very useful to be able to log DP VSC SDP.
> This greatly simplifies debugging.
> In order to use a common VSC SDP Colorimetry calculating code on PSR,
> it uses a new psr vsc sdp compute routine.
Pushed the series to drm-intel-next-queued with Daniel's irc ack for
merging the two non-i915 patches that route too.
Thanks for the patches and review!
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [PATCH v12 00/14] In order to readout DP SDPs, refactors the handling of DP SDPs
2020-05-14 11:19 ` Jani Nikula
(?)
@ 2020-05-15 13:06 ` Ville Syrjälä
-1 siblings, 0 replies; 73+ messages in thread
From: Ville Syrjälä @ 2020-05-15 13:06 UTC (permalink / raw)
To: Jani Nikula
Cc: linux-fbdev, daniel.vetter, intel-gfx, dri-devel,
Gwan-gyeong Mun, laurent.pinchart
On Thu, May 14, 2020 at 02:19:23PM +0300, Jani Nikula wrote:
> On Thu, 14 May 2020, Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> wrote:
> > In order to readout DP SDPs (Secondary Data Packet: DP HDR Metadata
> > Infoframe SDP, DP VSC SDP), it refactors handling DP SDPs codes.
> > It adds new compute routines for DP HDR Metadata Infoframe SDP
> > and DP VSC SDP.
> > And new writing routines of DP SDPs (Secondary Data Packet) that uses
> > computed configs.
> > New reading routines of DP SDPs are added for readout.
> > It adds a logging function for DP VSC SDP.
> > When receiving video it is very useful to be able to log DP VSC SDP.
> > This greatly simplifies debugging.
> > In order to use a common VSC SDP Colorimetry calculating code on PSR,
> > it uses a new psr vsc sdp compute routine.
>
> Pushed the series to drm-intel-next-queued with Daniel's irc ack for
> merging the two non-i915 patches that route too.
fi-hsw-4770 now oopses at boot:
<1>[ 3.736903] BUG: kernel NULL pointer dereference, address: 0000000000000000
<1>[ 3.736916] #PF: supervisor read access in kernel mode
<1>[ 3.736916] #PF: error_code(0x0000) - not-present page
<6>[ 3.736917] PGD 0 P4D 0
<4>[ 3.736919] Oops: 0000 [#1] PREEMPT SMP PTI
<4>[ 3.736921] CPU: 0 PID: 363 Comm: systemd-udevd Not tainted 5.7.0-rc5-CI-CI_DRM_8485+ #1
<4>[ 3.736922] Hardware name: LENOVO 10AGS00601/SHARKBAY, BIOS FBKT34AUS 04/24/2013
<4>[ 3.736986] RIP: 0010:intel_psr_enabled+0x8/0x70 [i915]
<4>[ 3.736988] Code: 18 48 c7 c6 40 09 79 a0 e8 e3 e2 04 e1 0f b6 44 24 03 e9 f4 fd ff ff 90 66 2e 0f 1f 84 00 00 00 00 00 41 54 55 53 48 83 ec 08 <48> 8b 9f d8 fe ff ff f6 83 5e 0d 00 00 20 74 09 80 bb 6c b6 00 00
<4>[ 3.737036] RSP: 0018:ffffc9000047f8a0 EFLAGS: 00010286
<4>[ 3.737042] RAX: 0000000000000002 RBX: ffff8883ffd04000 RCX: 0000000000000001
<4>[ 3.737048] RDX: 0000000000000007 RSI: ffff8883ffd04000 RDI: 0000000000000128
<4>[ 3.737055] RBP: ffff888406afe200 R08: 000000000000000f R09: 0000000000000001
<4>[ 3.737061] R10: 0000000000000000 R11: 0000000000000000 R12: 0000000000000000
<4>[ 3.737068] R13: ffff8883f75d0000 R14: ffff888406afe200 R15: ffff8883f75d0870
<4>[ 3.737075] FS: 00007f71618f9680(0000) GS:ffff88840ec00000(0000) knlGS:0000000000000000
<4>[ 3.737082] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
<4>[ 3.737088] CR2: 0000000000000000 CR3: 0000000402510002 CR4: 00000000001606f0
<4>[ 3.737094] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
<4>[ 3.737101] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
<4>[ 3.737107] Call Trace:
<4>[ 3.737175] intel_read_dp_sdp+0x1a4/0x380 [i915]
<4>[ 3.737246] hsw_crt_get_config+0x12/0x40 [i915]
<4>[ 3.737317] intel_modeset_setup_hw_state+0x3b3/0x16a0 [i915]
...
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [Intel-gfx] [PATCH v12 00/14] In order to readout DP SDPs, refactors the handling of DP SDPs
@ 2020-05-15 13:06 ` Ville Syrjälä
0 siblings, 0 replies; 73+ messages in thread
From: Ville Syrjälä @ 2020-05-15 13:06 UTC (permalink / raw)
To: Jani Nikula
Cc: linux-fbdev, daniel.vetter, intel-gfx, dri-devel, laurent.pinchart
On Thu, May 14, 2020 at 02:19:23PM +0300, Jani Nikula wrote:
> On Thu, 14 May 2020, Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> wrote:
> > In order to readout DP SDPs (Secondary Data Packet: DP HDR Metadata
> > Infoframe SDP, DP VSC SDP), it refactors handling DP SDPs codes.
> > It adds new compute routines for DP HDR Metadata Infoframe SDP
> > and DP VSC SDP.
> > And new writing routines of DP SDPs (Secondary Data Packet) that uses
> > computed configs.
> > New reading routines of DP SDPs are added for readout.
> > It adds a logging function for DP VSC SDP.
> > When receiving video it is very useful to be able to log DP VSC SDP.
> > This greatly simplifies debugging.
> > In order to use a common VSC SDP Colorimetry calculating code on PSR,
> > it uses a new psr vsc sdp compute routine.
>
> Pushed the series to drm-intel-next-queued with Daniel's irc ack for
> merging the two non-i915 patches that route too.
fi-hsw-4770 now oopses at boot:
<1>[ 3.736903] BUG: kernel NULL pointer dereference, address: 0000000000000000
<1>[ 3.736916] #PF: supervisor read access in kernel mode
<1>[ 3.736916] #PF: error_code(0x0000) - not-present page
<6>[ 3.736917] PGD 0 P4D 0
<4>[ 3.736919] Oops: 0000 [#1] PREEMPT SMP PTI
<4>[ 3.736921] CPU: 0 PID: 363 Comm: systemd-udevd Not tainted 5.7.0-rc5-CI-CI_DRM_8485+ #1
<4>[ 3.736922] Hardware name: LENOVO 10AGS00601/SHARKBAY, BIOS FBKT34AUS 04/24/2013
<4>[ 3.736986] RIP: 0010:intel_psr_enabled+0x8/0x70 [i915]
<4>[ 3.736988] Code: 18 48 c7 c6 40 09 79 a0 e8 e3 e2 04 e1 0f b6 44 24 03 e9 f4 fd ff ff 90 66 2e 0f 1f 84 00 00 00 00 00 41 54 55 53 48 83 ec 08 <48> 8b 9f d8 fe ff ff f6 83 5e 0d 00 00 20 74 09 80 bb 6c b6 00 00
<4>[ 3.737036] RSP: 0018:ffffc9000047f8a0 EFLAGS: 00010286
<4>[ 3.737042] RAX: 0000000000000002 RBX: ffff8883ffd04000 RCX: 0000000000000001
<4>[ 3.737048] RDX: 0000000000000007 RSI: ffff8883ffd04000 RDI: 0000000000000128
<4>[ 3.737055] RBP: ffff888406afe200 R08: 000000000000000f R09: 0000000000000001
<4>[ 3.737061] R10: 0000000000000000 R11: 0000000000000000 R12: 0000000000000000
<4>[ 3.737068] R13: ffff8883f75d0000 R14: ffff888406afe200 R15: ffff8883f75d0870
<4>[ 3.737075] FS: 00007f71618f9680(0000) GS:ffff88840ec00000(0000) knlGS:0000000000000000
<4>[ 3.737082] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
<4>[ 3.737088] CR2: 0000000000000000 CR3: 0000000402510002 CR4: 00000000001606f0
<4>[ 3.737094] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
<4>[ 3.737101] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
<4>[ 3.737107] Call Trace:
<4>[ 3.737175] intel_read_dp_sdp+0x1a4/0x380 [i915]
<4>[ 3.737246] hsw_crt_get_config+0x12/0x40 [i915]
<4>[ 3.737317] intel_modeset_setup_hw_state+0x3b3/0x16a0 [i915]
...
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [PATCH v12 00/14] In order to readout DP SDPs, refactors the handling of DP SDPs
@ 2020-05-15 13:06 ` Ville Syrjälä
0 siblings, 0 replies; 73+ messages in thread
From: Ville Syrjälä @ 2020-05-15 13:06 UTC (permalink / raw)
To: Jani Nikula
Cc: linux-fbdev, daniel.vetter, intel-gfx, dri-devel,
Gwan-gyeong Mun, laurent.pinchart
On Thu, May 14, 2020 at 02:19:23PM +0300, Jani Nikula wrote:
> On Thu, 14 May 2020, Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> wrote:
> > In order to readout DP SDPs (Secondary Data Packet: DP HDR Metadata
> > Infoframe SDP, DP VSC SDP), it refactors handling DP SDPs codes.
> > It adds new compute routines for DP HDR Metadata Infoframe SDP
> > and DP VSC SDP.
> > And new writing routines of DP SDPs (Secondary Data Packet) that uses
> > computed configs.
> > New reading routines of DP SDPs are added for readout.
> > It adds a logging function for DP VSC SDP.
> > When receiving video it is very useful to be able to log DP VSC SDP.
> > This greatly simplifies debugging.
> > In order to use a common VSC SDP Colorimetry calculating code on PSR,
> > it uses a new psr vsc sdp compute routine.
>
> Pushed the series to drm-intel-next-queued with Daniel's irc ack for
> merging the two non-i915 patches that route too.
fi-hsw-4770 now oopses at boot:
<1>[ 3.736903] BUG: kernel NULL pointer dereference, address: 0000000000000000
<1>[ 3.736916] #PF: supervisor read access in kernel mode
<1>[ 3.736916] #PF: error_code(0x0000) - not-present page
<6>[ 3.736917] PGD 0 P4D 0
<4>[ 3.736919] Oops: 0000 [#1] PREEMPT SMP PTI
<4>[ 3.736921] CPU: 0 PID: 363 Comm: systemd-udevd Not tainted 5.7.0-rc5-CI-CI_DRM_8485+ #1
<4>[ 3.736922] Hardware name: LENOVO 10AGS00601/SHARKBAY, BIOS FBKT34AUS 04/24/2013
<4>[ 3.736986] RIP: 0010:intel_psr_enabled+0x8/0x70 [i915]
<4>[ 3.736988] Code: 18 48 c7 c6 40 09 79 a0 e8 e3 e2 04 e1 0f b6 44 24 03 e9 f4 fd ff ff 90 66 2e 0f 1f 84 00 00 00 00 00 41 54 55 53 48 83 ec 08 <48> 8b 9f d8 fe ff ff f6 83 5e 0d 00 00 20 74 09 80 bb 6c b6 00 00
<4>[ 3.737036] RSP: 0018:ffffc9000047f8a0 EFLAGS: 00010286
<4>[ 3.737042] RAX: 0000000000000002 RBX: ffff8883ffd04000 RCX: 0000000000000001
<4>[ 3.737048] RDX: 0000000000000007 RSI: ffff8883ffd04000 RDI: 0000000000000128
<4>[ 3.737055] RBP: ffff888406afe200 R08: 000000000000000f R09: 0000000000000001
<4>[ 3.737061] R10: 0000000000000000 R11: 0000000000000000 R12: 0000000000000000
<4>[ 3.737068] R13: ffff8883f75d0000 R14: ffff888406afe200 R15: ffff8883f75d0870
<4>[ 3.737075] FS: 00007f71618f9680(0000) GS:ffff88840ec00000(0000) knlGS:0000000000000000
<4>[ 3.737082] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
<4>[ 3.737088] CR2: 0000000000000000 CR3: 0000000402510002 CR4: 00000000001606f0
<4>[ 3.737094] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
<4>[ 3.737101] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
<4>[ 3.737107] Call Trace:
<4>[ 3.737175] intel_read_dp_sdp+0x1a4/0x380 [i915]
<4>[ 3.737246] hsw_crt_get_config+0x12/0x40 [i915]
<4>[ 3.737317] intel_modeset_setup_hw_state+0x3b3/0x16a0 [i915]
...
--
Ville Syrjälä
Intel
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [PATCH v12 00/14] In order to readout DP SDPs, refactors the handling of DP SDPs
2020-05-15 13:06 ` Ville Syrjälä
(?)
@ 2020-05-15 13:13 ` Jani Nikula
-1 siblings, 0 replies; 73+ messages in thread
From: Jani Nikula @ 2020-05-15 13:13 UTC (permalink / raw)
To: Ville Syrjälä
Cc: linux-fbdev, daniel.vetter, intel-gfx, dri-devel,
Gwan-gyeong Mun, laurent.pinchart
On Fri, 15 May 2020, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Thu, May 14, 2020 at 02:19:23PM +0300, Jani Nikula wrote:
>> On Thu, 14 May 2020, Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> wrote:
>> > In order to readout DP SDPs (Secondary Data Packet: DP HDR Metadata
>> > Infoframe SDP, DP VSC SDP), it refactors handling DP SDPs codes.
>> > It adds new compute routines for DP HDR Metadata Infoframe SDP
>> > and DP VSC SDP.
>> > And new writing routines of DP SDPs (Secondary Data Packet) that uses
>> > computed configs.
>> > New reading routines of DP SDPs are added for readout.
>> > It adds a logging function for DP VSC SDP.
>> > When receiving video it is very useful to be able to log DP VSC SDP.
>> > This greatly simplifies debugging.
>> > In order to use a common VSC SDP Colorimetry calculating code on PSR,
>> > it uses a new psr vsc sdp compute routine.
>>
>> Pushed the series to drm-intel-next-queued with Daniel's irc ack for
>> merging the two non-i915 patches that route too.
>
> fi-hsw-4770 now oopses at boot:
/o\
What did I miss? What part about the CI report did I overlook?
BR,
Jani.
>
> <1>[ 3.736903] BUG: kernel NULL pointer dereference, address: 0000000000000000
> <1>[ 3.736916] #PF: supervisor read access in kernel mode
> <1>[ 3.736916] #PF: error_code(0x0000) - not-present page
> <6>[ 3.736917] PGD 0 P4D 0
> <4>[ 3.736919] Oops: 0000 [#1] PREEMPT SMP PTI
> <4>[ 3.736921] CPU: 0 PID: 363 Comm: systemd-udevd Not tainted 5.7.0-rc5-CI-CI_DRM_8485+ #1
> <4>[ 3.736922] Hardware name: LENOVO 10AGS00601/SHARKBAY, BIOS FBKT34AUS 04/24/2013
> <4>[ 3.736986] RIP: 0010:intel_psr_enabled+0x8/0x70 [i915]
> <4>[ 3.736988] Code: 18 48 c7 c6 40 09 79 a0 e8 e3 e2 04 e1 0f b6 44 24 03 e9 f4 fd ff ff 90 66 2e 0f 1f 84 00 00 00 00 00 41 54 55 53 48 83 ec 08 <48> 8b 9f d8 fe ff ff f6 83 5e 0d 00 00 20 74 09 80 bb 6c b6 00 00
> <4>[ 3.737036] RSP: 0018:ffffc9000047f8a0 EFLAGS: 00010286
> <4>[ 3.737042] RAX: 0000000000000002 RBX: ffff8883ffd04000 RCX: 0000000000000001
> <4>[ 3.737048] RDX: 0000000000000007 RSI: ffff8883ffd04000 RDI: 0000000000000128
> <4>[ 3.737055] RBP: ffff888406afe200 R08: 000000000000000f R09: 0000000000000001
> <4>[ 3.737061] R10: 0000000000000000 R11: 0000000000000000 R12: 0000000000000000
> <4>[ 3.737068] R13: ffff8883f75d0000 R14: ffff888406afe200 R15: ffff8883f75d0870
> <4>[ 3.737075] FS: 00007f71618f9680(0000) GS:ffff88840ec00000(0000) knlGS:0000000000000000
> <4>[ 3.737082] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
> <4>[ 3.737088] CR2: 0000000000000000 CR3: 0000000402510002 CR4: 00000000001606f0
> <4>[ 3.737094] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
> <4>[ 3.737101] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
> <4>[ 3.737107] Call Trace:
> <4>[ 3.737175] intel_read_dp_sdp+0x1a4/0x380 [i915]
> <4>[ 3.737246] hsw_crt_get_config+0x12/0x40 [i915]
> <4>[ 3.737317] intel_modeset_setup_hw_state+0x3b3/0x16a0 [i915]
> ...
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [Intel-gfx] [PATCH v12 00/14] In order to readout DP SDPs, refactors the handling of DP SDPs
@ 2020-05-15 13:13 ` Jani Nikula
0 siblings, 0 replies; 73+ messages in thread
From: Jani Nikula @ 2020-05-15 13:13 UTC (permalink / raw)
To: Ville Syrjälä
Cc: linux-fbdev, daniel.vetter, intel-gfx, dri-devel, laurent.pinchart
On Fri, 15 May 2020, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Thu, May 14, 2020 at 02:19:23PM +0300, Jani Nikula wrote:
>> On Thu, 14 May 2020, Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> wrote:
>> > In order to readout DP SDPs (Secondary Data Packet: DP HDR Metadata
>> > Infoframe SDP, DP VSC SDP), it refactors handling DP SDPs codes.
>> > It adds new compute routines for DP HDR Metadata Infoframe SDP
>> > and DP VSC SDP.
>> > And new writing routines of DP SDPs (Secondary Data Packet) that uses
>> > computed configs.
>> > New reading routines of DP SDPs are added for readout.
>> > It adds a logging function for DP VSC SDP.
>> > When receiving video it is very useful to be able to log DP VSC SDP.
>> > This greatly simplifies debugging.
>> > In order to use a common VSC SDP Colorimetry calculating code on PSR,
>> > it uses a new psr vsc sdp compute routine.
>>
>> Pushed the series to drm-intel-next-queued with Daniel's irc ack for
>> merging the two non-i915 patches that route too.
>
> fi-hsw-4770 now oopses at boot:
/o\
What did I miss? What part about the CI report did I overlook?
BR,
Jani.
>
> <1>[ 3.736903] BUG: kernel NULL pointer dereference, address: 0000000000000000
> <1>[ 3.736916] #PF: supervisor read access in kernel mode
> <1>[ 3.736916] #PF: error_code(0x0000) - not-present page
> <6>[ 3.736917] PGD 0 P4D 0
> <4>[ 3.736919] Oops: 0000 [#1] PREEMPT SMP PTI
> <4>[ 3.736921] CPU: 0 PID: 363 Comm: systemd-udevd Not tainted 5.7.0-rc5-CI-CI_DRM_8485+ #1
> <4>[ 3.736922] Hardware name: LENOVO 10AGS00601/SHARKBAY, BIOS FBKT34AUS 04/24/2013
> <4>[ 3.736986] RIP: 0010:intel_psr_enabled+0x8/0x70 [i915]
> <4>[ 3.736988] Code: 18 48 c7 c6 40 09 79 a0 e8 e3 e2 04 e1 0f b6 44 24 03 e9 f4 fd ff ff 90 66 2e 0f 1f 84 00 00 00 00 00 41 54 55 53 48 83 ec 08 <48> 8b 9f d8 fe ff ff f6 83 5e 0d 00 00 20 74 09 80 bb 6c b6 00 00
> <4>[ 3.737036] RSP: 0018:ffffc9000047f8a0 EFLAGS: 00010286
> <4>[ 3.737042] RAX: 0000000000000002 RBX: ffff8883ffd04000 RCX: 0000000000000001
> <4>[ 3.737048] RDX: 0000000000000007 RSI: ffff8883ffd04000 RDI: 0000000000000128
> <4>[ 3.737055] RBP: ffff888406afe200 R08: 000000000000000f R09: 0000000000000001
> <4>[ 3.737061] R10: 0000000000000000 R11: 0000000000000000 R12: 0000000000000000
> <4>[ 3.737068] R13: ffff8883f75d0000 R14: ffff888406afe200 R15: ffff8883f75d0870
> <4>[ 3.737075] FS: 00007f71618f9680(0000) GS:ffff88840ec00000(0000) knlGS:0000000000000000
> <4>[ 3.737082] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
> <4>[ 3.737088] CR2: 0000000000000000 CR3: 0000000402510002 CR4: 00000000001606f0
> <4>[ 3.737094] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
> <4>[ 3.737101] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
> <4>[ 3.737107] Call Trace:
> <4>[ 3.737175] intel_read_dp_sdp+0x1a4/0x380 [i915]
> <4>[ 3.737246] hsw_crt_get_config+0x12/0x40 [i915]
> <4>[ 3.737317] intel_modeset_setup_hw_state+0x3b3/0x16a0 [i915]
> ...
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [PATCH v12 00/14] In order to readout DP SDPs, refactors the handling of DP SDPs
@ 2020-05-15 13:13 ` Jani Nikula
0 siblings, 0 replies; 73+ messages in thread
From: Jani Nikula @ 2020-05-15 13:13 UTC (permalink / raw)
To: Ville Syrjälä
Cc: linux-fbdev, daniel.vetter, intel-gfx, dri-devel,
Gwan-gyeong Mun, laurent.pinchart
On Fri, 15 May 2020, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Thu, May 14, 2020 at 02:19:23PM +0300, Jani Nikula wrote:
>> On Thu, 14 May 2020, Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> wrote:
>> > In order to readout DP SDPs (Secondary Data Packet: DP HDR Metadata
>> > Infoframe SDP, DP VSC SDP), it refactors handling DP SDPs codes.
>> > It adds new compute routines for DP HDR Metadata Infoframe SDP
>> > and DP VSC SDP.
>> > And new writing routines of DP SDPs (Secondary Data Packet) that uses
>> > computed configs.
>> > New reading routines of DP SDPs are added for readout.
>> > It adds a logging function for DP VSC SDP.
>> > When receiving video it is very useful to be able to log DP VSC SDP.
>> > This greatly simplifies debugging.
>> > In order to use a common VSC SDP Colorimetry calculating code on PSR,
>> > it uses a new psr vsc sdp compute routine.
>>
>> Pushed the series to drm-intel-next-queued with Daniel's irc ack for
>> merging the two non-i915 patches that route too.
>
> fi-hsw-4770 now oopses at boot:
/o\
What did I miss? What part about the CI report did I overlook?
BR,
Jani.
>
> <1>[ 3.736903] BUG: kernel NULL pointer dereference, address: 0000000000000000
> <1>[ 3.736916] #PF: supervisor read access in kernel mode
> <1>[ 3.736916] #PF: error_code(0x0000) - not-present page
> <6>[ 3.736917] PGD 0 P4D 0
> <4>[ 3.736919] Oops: 0000 [#1] PREEMPT SMP PTI
> <4>[ 3.736921] CPU: 0 PID: 363 Comm: systemd-udevd Not tainted 5.7.0-rc5-CI-CI_DRM_8485+ #1
> <4>[ 3.736922] Hardware name: LENOVO 10AGS00601/SHARKBAY, BIOS FBKT34AUS 04/24/2013
> <4>[ 3.736986] RIP: 0010:intel_psr_enabled+0x8/0x70 [i915]
> <4>[ 3.736988] Code: 18 48 c7 c6 40 09 79 a0 e8 e3 e2 04 e1 0f b6 44 24 03 e9 f4 fd ff ff 90 66 2e 0f 1f 84 00 00 00 00 00 41 54 55 53 48 83 ec 08 <48> 8b 9f d8 fe ff ff f6 83 5e 0d 00 00 20 74 09 80 bb 6c b6 00 00
> <4>[ 3.737036] RSP: 0018:ffffc9000047f8a0 EFLAGS: 00010286
> <4>[ 3.737042] RAX: 0000000000000002 RBX: ffff8883ffd04000 RCX: 0000000000000001
> <4>[ 3.737048] RDX: 0000000000000007 RSI: ffff8883ffd04000 RDI: 0000000000000128
> <4>[ 3.737055] RBP: ffff888406afe200 R08: 000000000000000f R09: 0000000000000001
> <4>[ 3.737061] R10: 0000000000000000 R11: 0000000000000000 R12: 0000000000000000
> <4>[ 3.737068] R13: ffff8883f75d0000 R14: ffff888406afe200 R15: ffff8883f75d0870
> <4>[ 3.737075] FS: 00007f71618f9680(0000) GS:ffff88840ec00000(0000) knlGS:0000000000000000
> <4>[ 3.737082] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
> <4>[ 3.737088] CR2: 0000000000000000 CR3: 0000000402510002 CR4: 00000000001606f0
> <4>[ 3.737094] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
> <4>[ 3.737101] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
> <4>[ 3.737107] Call Trace:
> <4>[ 3.737175] intel_read_dp_sdp+0x1a4/0x380 [i915]
> <4>[ 3.737246] hsw_crt_get_config+0x12/0x40 [i915]
> <4>[ 3.737317] intel_modeset_setup_hw_state+0x3b3/0x16a0 [i915]
> ...
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [PATCH v12 00/14] In order to readout DP SDPs, refactors the handling of DP SDPs
2020-05-15 13:13 ` Jani Nikula
(?)
@ 2020-05-15 14:14 ` Daniel Vetter
-1 siblings, 0 replies; 73+ messages in thread
From: Daniel Vetter @ 2020-05-15 14:14 UTC (permalink / raw)
To: Jani Nikula
Cc: linux-fbdev, daniel.vetter, intel-gfx, dri-devel,
Gwan-gyeong Mun, laurent.pinchart
On Fri, May 15, 2020 at 04:13:18PM +0300, Jani Nikula wrote:
> On Fri, 15 May 2020, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> > On Thu, May 14, 2020 at 02:19:23PM +0300, Jani Nikula wrote:
> >> On Thu, 14 May 2020, Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> wrote:
> >> > In order to readout DP SDPs (Secondary Data Packet: DP HDR Metadata
> >> > Infoframe SDP, DP VSC SDP), it refactors handling DP SDPs codes.
> >> > It adds new compute routines for DP HDR Metadata Infoframe SDP
> >> > and DP VSC SDP.
> >> > And new writing routines of DP SDPs (Secondary Data Packet) that uses
> >> > computed configs.
> >> > New reading routines of DP SDPs are added for readout.
> >> > It adds a logging function for DP VSC SDP.
> >> > When receiving video it is very useful to be able to log DP VSC SDP.
> >> > This greatly simplifies debugging.
> >> > In order to use a common VSC SDP Colorimetry calculating code on PSR,
> >> > it uses a new psr vsc sdp compute routine.
> >>
> >> Pushed the series to drm-intel-next-queued with Daniel's irc ack for
> >> merging the two non-i915 patches that route too.
> >
> > fi-hsw-4770 now oopses at boot:
>
> /o\
>
> What did I miss? What part about the CI report did I overlook?
Participating hosts (48 -> 45)
------------------------------
Additional (1): fi-kbl-7560u
Missing (4): fi-byt-clapper fi-byt-squawks fi-bsw-cyan fi-hsw-4200u
You kill machines at boot, CI won't tell you.
This is (or at least was) because the network is shitty enough that we
have more spurious failures because the ethernet went into the ether than
because of people having killed the machine with their patches for real.
Also it's hard to grab logs if the thing doesn't work at all, so cant give
you any more data than the above.
Yes this sucks :-/
Cheers, Daniel
>
> BR,
> Jani.
>
>
> >
> > <1>[ 3.736903] BUG: kernel NULL pointer dereference, address: 0000000000000000
> > <1>[ 3.736916] #PF: supervisor read access in kernel mode
> > <1>[ 3.736916] #PF: error_code(0x0000) - not-present page
> > <6>[ 3.736917] PGD 0 P4D 0
> > <4>[ 3.736919] Oops: 0000 [#1] PREEMPT SMP PTI
> > <4>[ 3.736921] CPU: 0 PID: 363 Comm: systemd-udevd Not tainted 5.7.0-rc5-CI-CI_DRM_8485+ #1
> > <4>[ 3.736922] Hardware name: LENOVO 10AGS00601/SHARKBAY, BIOS FBKT34AUS 04/24/2013
> > <4>[ 3.736986] RIP: 0010:intel_psr_enabled+0x8/0x70 [i915]
> > <4>[ 3.736988] Code: 18 48 c7 c6 40 09 79 a0 e8 e3 e2 04 e1 0f b6 44 24 03 e9 f4 fd ff ff 90 66 2e 0f 1f 84 00 00 00 00 00 41 54 55 53 48 83 ec 08 <48> 8b 9f d8 fe ff ff f6 83 5e 0d 00 00 20 74 09 80 bb 6c b6 00 00
> > <4>[ 3.737036] RSP: 0018:ffffc9000047f8a0 EFLAGS: 00010286
> > <4>[ 3.737042] RAX: 0000000000000002 RBX: ffff8883ffd04000 RCX: 0000000000000001
> > <4>[ 3.737048] RDX: 0000000000000007 RSI: ffff8883ffd04000 RDI: 0000000000000128
> > <4>[ 3.737055] RBP: ffff888406afe200 R08: 000000000000000f R09: 0000000000000001
> > <4>[ 3.737061] R10: 0000000000000000 R11: 0000000000000000 R12: 0000000000000000
> > <4>[ 3.737068] R13: ffff8883f75d0000 R14: ffff888406afe200 R15: ffff8883f75d0870
> > <4>[ 3.737075] FS: 00007f71618f9680(0000) GS:ffff88840ec00000(0000) knlGS:0000000000000000
> > <4>[ 3.737082] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
> > <4>[ 3.737088] CR2: 0000000000000000 CR3: 0000000402510002 CR4: 00000000001606f0
> > <4>[ 3.737094] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
> > <4>[ 3.737101] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
> > <4>[ 3.737107] Call Trace:
> > <4>[ 3.737175] intel_read_dp_sdp+0x1a4/0x380 [i915]
> > <4>[ 3.737246] hsw_crt_get_config+0x12/0x40 [i915]
> > <4>[ 3.737317] intel_modeset_setup_hw_state+0x3b3/0x16a0 [i915]
> > ...
>
> --
> Jani Nikula, Intel Open Source Graphics Center
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [Intel-gfx] [PATCH v12 00/14] In order to readout DP SDPs, refactors the handling of DP SDPs
@ 2020-05-15 14:14 ` Daniel Vetter
0 siblings, 0 replies; 73+ messages in thread
From: Daniel Vetter @ 2020-05-15 14:14 UTC (permalink / raw)
To: Jani Nikula
Cc: linux-fbdev, daniel.vetter, intel-gfx, dri-devel, laurent.pinchart
On Fri, May 15, 2020 at 04:13:18PM +0300, Jani Nikula wrote:
> On Fri, 15 May 2020, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> > On Thu, May 14, 2020 at 02:19:23PM +0300, Jani Nikula wrote:
> >> On Thu, 14 May 2020, Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> wrote:
> >> > In order to readout DP SDPs (Secondary Data Packet: DP HDR Metadata
> >> > Infoframe SDP, DP VSC SDP), it refactors handling DP SDPs codes.
> >> > It adds new compute routines for DP HDR Metadata Infoframe SDP
> >> > and DP VSC SDP.
> >> > And new writing routines of DP SDPs (Secondary Data Packet) that uses
> >> > computed configs.
> >> > New reading routines of DP SDPs are added for readout.
> >> > It adds a logging function for DP VSC SDP.
> >> > When receiving video it is very useful to be able to log DP VSC SDP.
> >> > This greatly simplifies debugging.
> >> > In order to use a common VSC SDP Colorimetry calculating code on PSR,
> >> > it uses a new psr vsc sdp compute routine.
> >>
> >> Pushed the series to drm-intel-next-queued with Daniel's irc ack for
> >> merging the two non-i915 patches that route too.
> >
> > fi-hsw-4770 now oopses at boot:
>
> /o\
>
> What did I miss? What part about the CI report did I overlook?
Participating hosts (48 -> 45)
------------------------------
Additional (1): fi-kbl-7560u
Missing (4): fi-byt-clapper fi-byt-squawks fi-bsw-cyan fi-hsw-4200u
You kill machines at boot, CI won't tell you.
This is (or at least was) because the network is shitty enough that we
have more spurious failures because the ethernet went into the ether than
because of people having killed the machine with their patches for real.
Also it's hard to grab logs if the thing doesn't work at all, so cant give
you any more data than the above.
Yes this sucks :-/
Cheers, Daniel
>
> BR,
> Jani.
>
>
> >
> > <1>[ 3.736903] BUG: kernel NULL pointer dereference, address: 0000000000000000
> > <1>[ 3.736916] #PF: supervisor read access in kernel mode
> > <1>[ 3.736916] #PF: error_code(0x0000) - not-present page
> > <6>[ 3.736917] PGD 0 P4D 0
> > <4>[ 3.736919] Oops: 0000 [#1] PREEMPT SMP PTI
> > <4>[ 3.736921] CPU: 0 PID: 363 Comm: systemd-udevd Not tainted 5.7.0-rc5-CI-CI_DRM_8485+ #1
> > <4>[ 3.736922] Hardware name: LENOVO 10AGS00601/SHARKBAY, BIOS FBKT34AUS 04/24/2013
> > <4>[ 3.736986] RIP: 0010:intel_psr_enabled+0x8/0x70 [i915]
> > <4>[ 3.736988] Code: 18 48 c7 c6 40 09 79 a0 e8 e3 e2 04 e1 0f b6 44 24 03 e9 f4 fd ff ff 90 66 2e 0f 1f 84 00 00 00 00 00 41 54 55 53 48 83 ec 08 <48> 8b 9f d8 fe ff ff f6 83 5e 0d 00 00 20 74 09 80 bb 6c b6 00 00
> > <4>[ 3.737036] RSP: 0018:ffffc9000047f8a0 EFLAGS: 00010286
> > <4>[ 3.737042] RAX: 0000000000000002 RBX: ffff8883ffd04000 RCX: 0000000000000001
> > <4>[ 3.737048] RDX: 0000000000000007 RSI: ffff8883ffd04000 RDI: 0000000000000128
> > <4>[ 3.737055] RBP: ffff888406afe200 R08: 000000000000000f R09: 0000000000000001
> > <4>[ 3.737061] R10: 0000000000000000 R11: 0000000000000000 R12: 0000000000000000
> > <4>[ 3.737068] R13: ffff8883f75d0000 R14: ffff888406afe200 R15: ffff8883f75d0870
> > <4>[ 3.737075] FS: 00007f71618f9680(0000) GS:ffff88840ec00000(0000) knlGS:0000000000000000
> > <4>[ 3.737082] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
> > <4>[ 3.737088] CR2: 0000000000000000 CR3: 0000000402510002 CR4: 00000000001606f0
> > <4>[ 3.737094] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
> > <4>[ 3.737101] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
> > <4>[ 3.737107] Call Trace:
> > <4>[ 3.737175] intel_read_dp_sdp+0x1a4/0x380 [i915]
> > <4>[ 3.737246] hsw_crt_get_config+0x12/0x40 [i915]
> > <4>[ 3.737317] intel_modeset_setup_hw_state+0x3b3/0x16a0 [i915]
> > ...
>
> --
> Jani Nikula, Intel Open Source Graphics Center
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [PATCH v12 00/14] In order to readout DP SDPs, refactors the handling of DP SDPs
@ 2020-05-15 14:14 ` Daniel Vetter
0 siblings, 0 replies; 73+ messages in thread
From: Daniel Vetter @ 2020-05-15 14:14 UTC (permalink / raw)
To: Jani Nikula
Cc: linux-fbdev, daniel.vetter, intel-gfx, dri-devel,
Gwan-gyeong Mun, laurent.pinchart
On Fri, May 15, 2020 at 04:13:18PM +0300, Jani Nikula wrote:
> On Fri, 15 May 2020, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> > On Thu, May 14, 2020 at 02:19:23PM +0300, Jani Nikula wrote:
> >> On Thu, 14 May 2020, Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> wrote:
> >> > In order to readout DP SDPs (Secondary Data Packet: DP HDR Metadata
> >> > Infoframe SDP, DP VSC SDP), it refactors handling DP SDPs codes.
> >> > It adds new compute routines for DP HDR Metadata Infoframe SDP
> >> > and DP VSC SDP.
> >> > And new writing routines of DP SDPs (Secondary Data Packet) that uses
> >> > computed configs.
> >> > New reading routines of DP SDPs are added for readout.
> >> > It adds a logging function for DP VSC SDP.
> >> > When receiving video it is very useful to be able to log DP VSC SDP.
> >> > This greatly simplifies debugging.
> >> > In order to use a common VSC SDP Colorimetry calculating code on PSR,
> >> > it uses a new psr vsc sdp compute routine.
> >>
> >> Pushed the series to drm-intel-next-queued with Daniel's irc ack for
> >> merging the two non-i915 patches that route too.
> >
> > fi-hsw-4770 now oopses at boot:
>
> /o\
>
> What did I miss? What part about the CI report did I overlook?
Participating hosts (48 -> 45)
------------------------------
Additional (1): fi-kbl-7560u
Missing (4): fi-byt-clapper fi-byt-squawks fi-bsw-cyan fi-hsw-4200u
You kill machines at boot, CI won't tell you.
This is (or at least was) because the network is shitty enough that we
have more spurious failures because the ethernet went into the ether than
because of people having killed the machine with their patches for real.
Also it's hard to grab logs if the thing doesn't work at all, so cant give
you any more data than the above.
Yes this sucks :-/
Cheers, Daniel
>
> BR,
> Jani.
>
>
> >
> > <1>[ 3.736903] BUG: kernel NULL pointer dereference, address: 0000000000000000
> > <1>[ 3.736916] #PF: supervisor read access in kernel mode
> > <1>[ 3.736916] #PF: error_code(0x0000) - not-present page
> > <6>[ 3.736917] PGD 0 P4D 0
> > <4>[ 3.736919] Oops: 0000 [#1] PREEMPT SMP PTI
> > <4>[ 3.736921] CPU: 0 PID: 363 Comm: systemd-udevd Not tainted 5.7.0-rc5-CI-CI_DRM_8485+ #1
> > <4>[ 3.736922] Hardware name: LENOVO 10AGS00601/SHARKBAY, BIOS FBKT34AUS 04/24/2013
> > <4>[ 3.736986] RIP: 0010:intel_psr_enabled+0x8/0x70 [i915]
> > <4>[ 3.736988] Code: 18 48 c7 c6 40 09 79 a0 e8 e3 e2 04 e1 0f b6 44 24 03 e9 f4 fd ff ff 90 66 2e 0f 1f 84 00 00 00 00 00 41 54 55 53 48 83 ec 08 <48> 8b 9f d8 fe ff ff f6 83 5e 0d 00 00 20 74 09 80 bb 6c b6 00 00
> > <4>[ 3.737036] RSP: 0018:ffffc9000047f8a0 EFLAGS: 00010286
> > <4>[ 3.737042] RAX: 0000000000000002 RBX: ffff8883ffd04000 RCX: 0000000000000001
> > <4>[ 3.737048] RDX: 0000000000000007 RSI: ffff8883ffd04000 RDI: 0000000000000128
> > <4>[ 3.737055] RBP: ffff888406afe200 R08: 000000000000000f R09: 0000000000000001
> > <4>[ 3.737061] R10: 0000000000000000 R11: 0000000000000000 R12: 0000000000000000
> > <4>[ 3.737068] R13: ffff8883f75d0000 R14: ffff888406afe200 R15: ffff8883f75d0870
> > <4>[ 3.737075] FS: 00007f71618f9680(0000) GS:ffff88840ec00000(0000) knlGS:0000000000000000
> > <4>[ 3.737082] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
> > <4>[ 3.737088] CR2: 0000000000000000 CR3: 0000000402510002 CR4: 00000000001606f0
> > <4>[ 3.737094] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
> > <4>[ 3.737101] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
> > <4>[ 3.737107] Call Trace:
> > <4>[ 3.737175] intel_read_dp_sdp+0x1a4/0x380 [i915]
> > <4>[ 3.737246] hsw_crt_get_config+0x12/0x40 [i915]
> > <4>[ 3.737317] intel_modeset_setup_hw_state+0x3b3/0x16a0 [i915]
> > ...
>
> --
> Jani Nikula, Intel Open Source Graphics Center
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [PATCH v12 00/14] In order to readout DP SDPs, refactors the handling of DP SDPs
2020-05-15 14:14 ` Daniel Vetter
(?)
@ 2020-05-15 17:22 ` Mun, Gwan-gyeong
-1 siblings, 0 replies; 73+ messages in thread
From: Mun, Gwan-gyeong @ 2020-05-15 17:22 UTC (permalink / raw)
To: daniel, jani.nikula
Cc: linux-fbdev, daniel.vetter, intel-gfx, dri-devel, laurent.pinchart
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^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [Intel-gfx] [PATCH v12 00/14] In order to readout DP SDPs, refactors the handling of DP SDPs
@ 2020-05-15 17:22 ` Mun, Gwan-gyeong
0 siblings, 0 replies; 73+ messages in thread
From: Mun, Gwan-gyeong @ 2020-05-15 17:22 UTC (permalink / raw)
To: daniel, jani.nikula
Cc: linux-fbdev, daniel.vetter, intel-gfx, dri-devel, laurent.pinchart
Hi Ville,
Thank you for notifying me that. I definitely missed the crash.
Sorry for that.
Danial and Jani, I' under debugging the crash case.
If you are availabe please do not merge current version.
Br,
G.G.
>
On Fri, 2020-05-15 at 16:14 +0200, Daniel Vetter wrote:
> On Fri, May 15, 2020 at 04:13:18PM +0300, Jani Nikula wrote:
> > On Fri, 15 May 2020, Ville Syrjälä <ville.syrjala@linux.intel.com>
> > wrote:
> > > On Thu, May 14, 2020 at 02:19:23PM +0300, Jani Nikula wrote:
> > > > On Thu, 14 May 2020, Gwan-gyeong Mun <gwan-gyeong.mun@intel.com
> > > > > wrote:
> > > > > In order to readout DP SDPs (Secondary Data Packet: DP HDR
> > > > > Metadata
> > > > > Infoframe SDP, DP VSC SDP), it refactors handling DP SDPs
> > > > > codes.
> > > > > It adds new compute routines for DP HDR Metadata Infoframe
> > > > > SDP
> > > > > and DP VSC SDP.
> > > > > And new writing routines of DP SDPs (Secondary Data Packet)
> > > > > that uses
> > > > > computed configs.
> > > > > New reading routines of DP SDPs are added for readout.
> > > > > It adds a logging function for DP VSC SDP.
> > > > > When receiving video it is very useful to be able to log DP
> > > > > VSC SDP.
> > > > > This greatly simplifies debugging.
> > > > > In order to use a common VSC SDP Colorimetry calculating code
> > > > > on PSR,
> > > > > it uses a new psr vsc sdp compute routine.
> > > >
> > > > Pushed the series to drm-intel-next-queued with Daniel's irc
> > > > ack for
> > > > merging the two non-i915 patches that route too.
> > >
> > > fi-hsw-4770 now oopses at boot:
> >
> > /o\
> >
> > What did I miss? What part about the CI report did I overlook?
>
> Participating hosts (48 -> 45)
> ------------------------------
>
> Additional (1): fi-kbl-7560u
> Missing (4): fi-byt-clapper fi-byt-squawks fi-bsw-cyan fi-hsw-
> 4200u
>
>
> You kill machines at boot, CI won't tell you.
>
> This is (or at least was) because the network is shitty enough that
> we
> have more spurious failures because the ethernet went into the ether
> than
> because of people having killed the machine with their patches for
> real.
> Also it's hard to grab logs if the thing doesn't work at all, so cant
> give
> you any more data than the above.
>
> Yes this sucks :-/
>
> Cheers, Daniel
>
> > BR,
> > Jani.
> >
> >
> > > <1>[ 3.736903] BUG: kernel NULL pointer dereference, address:
> > > 0000000000000000
> > > <1>[ 3.736916] #PF: supervisor read access in kernel mode
> > > <1>[ 3.736916] #PF: error_code(0x0000) - not-present page
> > > <6>[ 3.736917] PGD 0 P4D 0
> > > <4>[ 3.736919] Oops: 0000 [#1] PREEMPT SMP PTI
> > > <4>[ 3.736921] CPU: 0 PID: 363 Comm: systemd-udevd Not tainted
> > > 5.7.0-rc5-CI-CI_DRM_8485+ #1
> > > <4>[ 3.736922] Hardware name: LENOVO 10AGS00601/SHARKBAY, BIOS
> > > FBKT34AUS 04/24/2013
> > > <4>[ 3.736986] RIP: 0010:intel_psr_enabled+0x8/0x70 [i915]
> > > <4>[ 3.736988] Code: 18 48 c7 c6 40 09 79 a0 e8 e3 e2 04 e1 0f
> > > b6 44 24 03 e9 f4 fd ff ff 90 66 2e 0f 1f 84 00 00 00 00 00 41 54
> > > 55 53 48 83 ec 08 <48> 8b 9f d8 fe ff ff f6 83 5e 0d 00 00 20 74
> > > 09 80 bb 6c b6 00 00
> > > <4>[ 3.737036] RSP: 0018:ffffc9000047f8a0 EFLAGS: 00010286
> > > <4>[ 3.737042] RAX: 0000000000000002 RBX: ffff8883ffd04000
> > > RCX: 0000000000000001
> > > <4>[ 3.737048] RDX: 0000000000000007 RSI: ffff8883ffd04000
> > > RDI: 0000000000000128
> > > <4>[ 3.737055] RBP: ffff888406afe200 R08: 000000000000000f
> > > R09: 0000000000000001
> > > <4>[ 3.737061] R10: 0000000000000000 R11: 0000000000000000
> > > R12: 0000000000000000
> > > <4>[ 3.737068] R13: ffff8883f75d0000 R14: ffff888406afe200
> > > R15: ffff8883f75d0870
> > > <4>[ 3.737075] FS: 00007f71618f9680(0000)
> > > GS:ffff88840ec00000(0000) knlGS:0000000000000000
> > > <4>[ 3.737082] CS: 0010 DS: 0000 ES: 0000 CR0:
> > > 0000000080050033
> > > <4>[ 3.737088] CR2: 0000000000000000 CR3: 0000000402510002
> > > CR4: 00000000001606f0
> > > <4>[ 3.737094] DR0: 0000000000000000 DR1: 0000000000000000
> > > DR2: 0000000000000000
> > > <4>[ 3.737101] DR3: 0000000000000000 DR6: 00000000fffe0ff0
> > > DR7: 0000000000000400
> > > <4>[ 3.737107] Call Trace:
> > > <4>[ 3.737175] intel_read_dp_sdp+0x1a4/0x380 [i915]
> > > <4>[ 3.737246] hsw_crt_get_config+0x12/0x40 [i915]
> > > <4>[ 3.737317] intel_modeset_setup_hw_state+0x3b3/0x16a0
> > > [i915]
> > > ...
> >
> > --
> > Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [PATCH v12 00/14] In order to readout DP SDPs, refactors the handling of DP SDPs
@ 2020-05-15 17:22 ` Mun, Gwan-gyeong
0 siblings, 0 replies; 73+ messages in thread
From: Mun, Gwan-gyeong @ 2020-05-15 17:22 UTC (permalink / raw)
To: daniel, jani.nikula
Cc: linux-fbdev, daniel.vetter, intel-gfx, dri-devel, laurent.pinchart
Hi Ville,
Thank you for notifying me that. I definitely missed the crash.
Sorry for that.
Danial and Jani, I' under debugging the crash case.
If you are availabe please do not merge current version.
Br,
G.G.
>
On Fri, 2020-05-15 at 16:14 +0200, Daniel Vetter wrote:
> On Fri, May 15, 2020 at 04:13:18PM +0300, Jani Nikula wrote:
> > On Fri, 15 May 2020, Ville Syrjälä <ville.syrjala@linux.intel.com>
> > wrote:
> > > On Thu, May 14, 2020 at 02:19:23PM +0300, Jani Nikula wrote:
> > > > On Thu, 14 May 2020, Gwan-gyeong Mun <gwan-gyeong.mun@intel.com
> > > > > wrote:
> > > > > In order to readout DP SDPs (Secondary Data Packet: DP HDR
> > > > > Metadata
> > > > > Infoframe SDP, DP VSC SDP), it refactors handling DP SDPs
> > > > > codes.
> > > > > It adds new compute routines for DP HDR Metadata Infoframe
> > > > > SDP
> > > > > and DP VSC SDP.
> > > > > And new writing routines of DP SDPs (Secondary Data Packet)
> > > > > that uses
> > > > > computed configs.
> > > > > New reading routines of DP SDPs are added for readout.
> > > > > It adds a logging function for DP VSC SDP.
> > > > > When receiving video it is very useful to be able to log DP
> > > > > VSC SDP.
> > > > > This greatly simplifies debugging.
> > > > > In order to use a common VSC SDP Colorimetry calculating code
> > > > > on PSR,
> > > > > it uses a new psr vsc sdp compute routine.
> > > >
> > > > Pushed the series to drm-intel-next-queued with Daniel's irc
> > > > ack for
> > > > merging the two non-i915 patches that route too.
> > >
> > > fi-hsw-4770 now oopses at boot:
> >
> > /o\
> >
> > What did I miss? What part about the CI report did I overlook?
>
> Participating hosts (48 -> 45)
> ------------------------------
>
> Additional (1): fi-kbl-7560u
> Missing (4): fi-byt-clapper fi-byt-squawks fi-bsw-cyan fi-hsw-
> 4200u
>
>
> You kill machines at boot, CI won't tell you.
>
> This is (or at least was) because the network is shitty enough that
> we
> have more spurious failures because the ethernet went into the ether
> than
> because of people having killed the machine with their patches for
> real.
> Also it's hard to grab logs if the thing doesn't work at all, so cant
> give
> you any more data than the above.
>
> Yes this sucks :-/
>
> Cheers, Daniel
>
> > BR,
> > Jani.
> >
> >
> > > <1>[ 3.736903] BUG: kernel NULL pointer dereference, address:
> > > 0000000000000000
> > > <1>[ 3.736916] #PF: supervisor read access in kernel mode
> > > <1>[ 3.736916] #PF: error_code(0x0000) - not-present page
> > > <6>[ 3.736917] PGD 0 P4D 0
> > > <4>[ 3.736919] Oops: 0000 [#1] PREEMPT SMP PTI
> > > <4>[ 3.736921] CPU: 0 PID: 363 Comm: systemd-udevd Not tainted
> > > 5.7.0-rc5-CI-CI_DRM_8485+ #1
> > > <4>[ 3.736922] Hardware name: LENOVO 10AGS00601/SHARKBAY, BIOS
> > > FBKT34AUS 04/24/2013
> > > <4>[ 3.736986] RIP: 0010:intel_psr_enabled+0x8/0x70 [i915]
> > > <4>[ 3.736988] Code: 18 48 c7 c6 40 09 79 a0 e8 e3 e2 04 e1 0f
> > > b6 44 24 03 e9 f4 fd ff ff 90 66 2e 0f 1f 84 00 00 00 00 00 41 54
> > > 55 53 48 83 ec 08 <48> 8b 9f d8 fe ff ff f6 83 5e 0d 00 00 20 74
> > > 09 80 bb 6c b6 00 00
> > > <4>[ 3.737036] RSP: 0018:ffffc9000047f8a0 EFLAGS: 00010286
> > > <4>[ 3.737042] RAX: 0000000000000002 RBX: ffff8883ffd04000
> > > RCX: 0000000000000001
> > > <4>[ 3.737048] RDX: 0000000000000007 RSI: ffff8883ffd04000
> > > RDI: 0000000000000128
> > > <4>[ 3.737055] RBP: ffff888406afe200 R08: 000000000000000f
> > > R09: 0000000000000001
> > > <4>[ 3.737061] R10: 0000000000000000 R11: 0000000000000000
> > > R12: 0000000000000000
> > > <4>[ 3.737068] R13: ffff8883f75d0000 R14: ffff888406afe200
> > > R15: ffff8883f75d0870
> > > <4>[ 3.737075] FS: 00007f71618f9680(0000)
> > > GS:ffff88840ec00000(0000) knlGS:0000000000000000
> > > <4>[ 3.737082] CS: 0010 DS: 0000 ES: 0000 CR0:
> > > 0000000080050033
> > > <4>[ 3.737088] CR2: 0000000000000000 CR3: 0000000402510002
> > > CR4: 00000000001606f0
> > > <4>[ 3.737094] DR0: 0000000000000000 DR1: 0000000000000000
> > > DR2: 0000000000000000
> > > <4>[ 3.737101] DR3: 0000000000000000 DR6: 00000000fffe0ff0
> > > DR7: 0000000000000400
> > > <4>[ 3.737107] Call Trace:
> > > <4>[ 3.737175] intel_read_dp_sdp+0x1a4/0x380 [i915]
> > > <4>[ 3.737246] hsw_crt_get_config+0x12/0x40 [i915]
> > > <4>[ 3.737317] intel_modeset_setup_hw_state+0x3b3/0x16a0
> > > [i915]
> > > ...
> >
> > --
> > Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [PATCH v12 00/14] In order to readout DP SDPs, refactors the handling of DP SDPs
2020-05-15 17:22 ` Mun, Gwan-gyeong
(?)
@ 2020-05-18 9:43 ` Jani Nikula
-1 siblings, 0 replies; 73+ messages in thread
From: Jani Nikula @ 2020-05-18 9:43 UTC (permalink / raw)
To: Mun, Gwan-gyeong, daniel
Cc: linux-fbdev, daniel.vetter, intel-gfx, dri-devel, laurent.pinchart
On Fri, 15 May 2020, "Mun, Gwan-gyeong" <gwan-gyeong.mun@intel.com> wrote:
> Hi Ville,
> Thank you for notifying me that. I definitely missed the crash.
> Sorry for that.
> Danial and Jani, I' under debugging the crash case.
> If you are availabe please do not merge current version.
It has been merged, and that's the oops is the main reason it got
noticed.
If you can produce a fairly quick fix, great, but otherwise we'll need
to revert enough commits to make this work again.
BR,
Jani.
>
> Br,
>
> G.G.
>
>>
> On Fri, 2020-05-15 at 16:14 +0200, Daniel Vetter wrote:
>> On Fri, May 15, 2020 at 04:13:18PM +0300, Jani Nikula wrote:
>> > On Fri, 15 May 2020, Ville Syrjälä <ville.syrjala@linux.intel.com>
>> > wrote:
>> > > On Thu, May 14, 2020 at 02:19:23PM +0300, Jani Nikula wrote:
>> > > > On Thu, 14 May 2020, Gwan-gyeong Mun <gwan-gyeong.mun@intel.com
>> > > > > wrote:
>> > > > > In order to readout DP SDPs (Secondary Data Packet: DP HDR
>> > > > > Metadata
>> > > > > Infoframe SDP, DP VSC SDP), it refactors handling DP SDPs
>> > > > > codes.
>> > > > > It adds new compute routines for DP HDR Metadata Infoframe
>> > > > > SDP
>> > > > > and DP VSC SDP.
>> > > > > And new writing routines of DP SDPs (Secondary Data Packet)
>> > > > > that uses
>> > > > > computed configs.
>> > > > > New reading routines of DP SDPs are added for readout.
>> > > > > It adds a logging function for DP VSC SDP.
>> > > > > When receiving video it is very useful to be able to log DP
>> > > > > VSC SDP.
>> > > > > This greatly simplifies debugging.
>> > > > > In order to use a common VSC SDP Colorimetry calculating code
>> > > > > on PSR,
>> > > > > it uses a new psr vsc sdp compute routine.
>> > > >
>> > > > Pushed the series to drm-intel-next-queued with Daniel's irc
>> > > > ack for
>> > > > merging the two non-i915 patches that route too.
>> > >
>> > > fi-hsw-4770 now oopses at boot:
>> >
>> > /o\
>> >
>> > What did I miss? What part about the CI report did I overlook?
>>
>> Participating hosts (48 -> 45)
>> ------------------------------
>>
>> Additional (1): fi-kbl-7560u
>> Missing (4): fi-byt-clapper fi-byt-squawks fi-bsw-cyan fi-hsw-
>> 4200u
>>
>>
>> You kill machines at boot, CI won't tell you.
>>
>> This is (or at least was) because the network is shitty enough that
>> we
>> have more spurious failures because the ethernet went into the ether
>> than
>> because of people having killed the machine with their patches for
>> real.
>> Also it's hard to grab logs if the thing doesn't work at all, so cant
>> give
>> you any more data than the above.
>>
>> Yes this sucks :-/
>>
>> Cheers, Daniel
>>
>> > BR,
>> > Jani.
>> >
>> >
>> > > <1>[ 3.736903] BUG: kernel NULL pointer dereference, address:
>> > > 0000000000000000
>> > > <1>[ 3.736916] #PF: supervisor read access in kernel mode
>> > > <1>[ 3.736916] #PF: error_code(0x0000) - not-present page
>> > > <6>[ 3.736917] PGD 0 P4D 0
>> > > <4>[ 3.736919] Oops: 0000 [#1] PREEMPT SMP PTI
>> > > <4>[ 3.736921] CPU: 0 PID: 363 Comm: systemd-udevd Not tainted
>> > > 5.7.0-rc5-CI-CI_DRM_8485+ #1
>> > > <4>[ 3.736922] Hardware name: LENOVO 10AGS00601/SHARKBAY, BIOS
>> > > FBKT34AUS 04/24/2013
>> > > <4>[ 3.736986] RIP: 0010:intel_psr_enabled+0x8/0x70 [i915]
>> > > <4>[ 3.736988] Code: 18 48 c7 c6 40 09 79 a0 e8 e3 e2 04 e1 0f
>> > > b6 44 24 03 e9 f4 fd ff ff 90 66 2e 0f 1f 84 00 00 00 00 00 41 54
>> > > 55 53 48 83 ec 08 <48> 8b 9f d8 fe ff ff f6 83 5e 0d 00 00 20 74
>> > > 09 80 bb 6c b6 00 00
>> > > <4>[ 3.737036] RSP: 0018:ffffc9000047f8a0 EFLAGS: 00010286
>> > > <4>[ 3.737042] RAX: 0000000000000002 RBX: ffff8883ffd04000
>> > > RCX: 0000000000000001
>> > > <4>[ 3.737048] RDX: 0000000000000007 RSI: ffff8883ffd04000
>> > > RDI: 0000000000000128
>> > > <4>[ 3.737055] RBP: ffff888406afe200 R08: 000000000000000f
>> > > R09: 0000000000000001
>> > > <4>[ 3.737061] R10: 0000000000000000 R11: 0000000000000000
>> > > R12: 0000000000000000
>> > > <4>[ 3.737068] R13: ffff8883f75d0000 R14: ffff888406afe200
>> > > R15: ffff8883f75d0870
>> > > <4>[ 3.737075] FS: 00007f71618f9680(0000)
>> > > GS:ffff88840ec00000(0000) knlGS:0000000000000000
>> > > <4>[ 3.737082] CS: 0010 DS: 0000 ES: 0000 CR0:
>> > > 0000000080050033
>> > > <4>[ 3.737088] CR2: 0000000000000000 CR3: 0000000402510002
>> > > CR4: 00000000001606f0
>> > > <4>[ 3.737094] DR0: 0000000000000000 DR1: 0000000000000000
>> > > DR2: 0000000000000000
>> > > <4>[ 3.737101] DR3: 0000000000000000 DR6: 00000000fffe0ff0
>> > > DR7: 0000000000000400
>> > > <4>[ 3.737107] Call Trace:
>> > > <4>[ 3.737175] intel_read_dp_sdp+0x1a4/0x380 [i915]
>> > > <4>[ 3.737246] hsw_crt_get_config+0x12/0x40 [i915]
>> > > <4>[ 3.737317] intel_modeset_setup_hw_state+0x3b3/0x16a0
>> > > [i915]
>> > > ...
>> >
>> > --
>> > Jani Nikula, Intel Open Source Graphics Center
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [Intel-gfx] [PATCH v12 00/14] In order to readout DP SDPs, refactors the handling of DP SDPs
@ 2020-05-18 9:43 ` Jani Nikula
0 siblings, 0 replies; 73+ messages in thread
From: Jani Nikula @ 2020-05-18 9:43 UTC (permalink / raw)
To: Mun, Gwan-gyeong, daniel
Cc: linux-fbdev, daniel.vetter, intel-gfx, dri-devel, laurent.pinchart
On Fri, 15 May 2020, "Mun, Gwan-gyeong" <gwan-gyeong.mun@intel.com> wrote:
> Hi Ville,
> Thank you for notifying me that. I definitely missed the crash.
> Sorry for that.
> Danial and Jani, I' under debugging the crash case.
> If you are availabe please do not merge current version.
It has been merged, and that's the oops is the main reason it got
noticed.
If you can produce a fairly quick fix, great, but otherwise we'll need
to revert enough commits to make this work again.
BR,
Jani.
>
> Br,
>
> G.G.
>
>>
> On Fri, 2020-05-15 at 16:14 +0200, Daniel Vetter wrote:
>> On Fri, May 15, 2020 at 04:13:18PM +0300, Jani Nikula wrote:
>> > On Fri, 15 May 2020, Ville Syrjälä <ville.syrjala@linux.intel.com>
>> > wrote:
>> > > On Thu, May 14, 2020 at 02:19:23PM +0300, Jani Nikula wrote:
>> > > > On Thu, 14 May 2020, Gwan-gyeong Mun <gwan-gyeong.mun@intel.com
>> > > > > wrote:
>> > > > > In order to readout DP SDPs (Secondary Data Packet: DP HDR
>> > > > > Metadata
>> > > > > Infoframe SDP, DP VSC SDP), it refactors handling DP SDPs
>> > > > > codes.
>> > > > > It adds new compute routines for DP HDR Metadata Infoframe
>> > > > > SDP
>> > > > > and DP VSC SDP.
>> > > > > And new writing routines of DP SDPs (Secondary Data Packet)
>> > > > > that uses
>> > > > > computed configs.
>> > > > > New reading routines of DP SDPs are added for readout.
>> > > > > It adds a logging function for DP VSC SDP.
>> > > > > When receiving video it is very useful to be able to log DP
>> > > > > VSC SDP.
>> > > > > This greatly simplifies debugging.
>> > > > > In order to use a common VSC SDP Colorimetry calculating code
>> > > > > on PSR,
>> > > > > it uses a new psr vsc sdp compute routine.
>> > > >
>> > > > Pushed the series to drm-intel-next-queued with Daniel's irc
>> > > > ack for
>> > > > merging the two non-i915 patches that route too.
>> > >
>> > > fi-hsw-4770 now oopses at boot:
>> >
>> > /o\
>> >
>> > What did I miss? What part about the CI report did I overlook?
>>
>> Participating hosts (48 -> 45)
>> ------------------------------
>>
>> Additional (1): fi-kbl-7560u
>> Missing (4): fi-byt-clapper fi-byt-squawks fi-bsw-cyan fi-hsw-
>> 4200u
>>
>>
>> You kill machines at boot, CI won't tell you.
>>
>> This is (or at least was) because the network is shitty enough that
>> we
>> have more spurious failures because the ethernet went into the ether
>> than
>> because of people having killed the machine with their patches for
>> real.
>> Also it's hard to grab logs if the thing doesn't work at all, so cant
>> give
>> you any more data than the above.
>>
>> Yes this sucks :-/
>>
>> Cheers, Daniel
>>
>> > BR,
>> > Jani.
>> >
>> >
>> > > <1>[ 3.736903] BUG: kernel NULL pointer dereference, address:
>> > > 0000000000000000
>> > > <1>[ 3.736916] #PF: supervisor read access in kernel mode
>> > > <1>[ 3.736916] #PF: error_code(0x0000) - not-present page
>> > > <6>[ 3.736917] PGD 0 P4D 0
>> > > <4>[ 3.736919] Oops: 0000 [#1] PREEMPT SMP PTI
>> > > <4>[ 3.736921] CPU: 0 PID: 363 Comm: systemd-udevd Not tainted
>> > > 5.7.0-rc5-CI-CI_DRM_8485+ #1
>> > > <4>[ 3.736922] Hardware name: LENOVO 10AGS00601/SHARKBAY, BIOS
>> > > FBKT34AUS 04/24/2013
>> > > <4>[ 3.736986] RIP: 0010:intel_psr_enabled+0x8/0x70 [i915]
>> > > <4>[ 3.736988] Code: 18 48 c7 c6 40 09 79 a0 e8 e3 e2 04 e1 0f
>> > > b6 44 24 03 e9 f4 fd ff ff 90 66 2e 0f 1f 84 00 00 00 00 00 41 54
>> > > 55 53 48 83 ec 08 <48> 8b 9f d8 fe ff ff f6 83 5e 0d 00 00 20 74
>> > > 09 80 bb 6c b6 00 00
>> > > <4>[ 3.737036] RSP: 0018:ffffc9000047f8a0 EFLAGS: 00010286
>> > > <4>[ 3.737042] RAX: 0000000000000002 RBX: ffff8883ffd04000
>> > > RCX: 0000000000000001
>> > > <4>[ 3.737048] RDX: 0000000000000007 RSI: ffff8883ffd04000
>> > > RDI: 0000000000000128
>> > > <4>[ 3.737055] RBP: ffff888406afe200 R08: 000000000000000f
>> > > R09: 0000000000000001
>> > > <4>[ 3.737061] R10: 0000000000000000 R11: 0000000000000000
>> > > R12: 0000000000000000
>> > > <4>[ 3.737068] R13: ffff8883f75d0000 R14: ffff888406afe200
>> > > R15: ffff8883f75d0870
>> > > <4>[ 3.737075] FS: 00007f71618f9680(0000)
>> > > GS:ffff88840ec00000(0000) knlGS:0000000000000000
>> > > <4>[ 3.737082] CS: 0010 DS: 0000 ES: 0000 CR0:
>> > > 0000000080050033
>> > > <4>[ 3.737088] CR2: 0000000000000000 CR3: 0000000402510002
>> > > CR4: 00000000001606f0
>> > > <4>[ 3.737094] DR0: 0000000000000000 DR1: 0000000000000000
>> > > DR2: 0000000000000000
>> > > <4>[ 3.737101] DR3: 0000000000000000 DR6: 00000000fffe0ff0
>> > > DR7: 0000000000000400
>> > > <4>[ 3.737107] Call Trace:
>> > > <4>[ 3.737175] intel_read_dp_sdp+0x1a4/0x380 [i915]
>> > > <4>[ 3.737246] hsw_crt_get_config+0x12/0x40 [i915]
>> > > <4>[ 3.737317] intel_modeset_setup_hw_state+0x3b3/0x16a0
>> > > [i915]
>> > > ...
>> >
>> > --
>> > Jani Nikula, Intel Open Source Graphics Center
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [PATCH v12 00/14] In order to readout DP SDPs, refactors the handling of DP SDPs
@ 2020-05-18 9:43 ` Jani Nikula
0 siblings, 0 replies; 73+ messages in thread
From: Jani Nikula @ 2020-05-18 9:43 UTC (permalink / raw)
To: Mun, Gwan-gyeong, daniel
Cc: linux-fbdev, daniel.vetter, intel-gfx, dri-devel, laurent.pinchart
On Fri, 15 May 2020, "Mun, Gwan-gyeong" <gwan-gyeong.mun@intel.com> wrote:
> Hi Ville,
> Thank you for notifying me that. I definitely missed the crash.
> Sorry for that.
> Danial and Jani, I' under debugging the crash case.
> If you are availabe please do not merge current version.
It has been merged, and that's the oops is the main reason it got
noticed.
If you can produce a fairly quick fix, great, but otherwise we'll need
to revert enough commits to make this work again.
BR,
Jani.
>
> Br,
>
> G.G.
>
>>
> On Fri, 2020-05-15 at 16:14 +0200, Daniel Vetter wrote:
>> On Fri, May 15, 2020 at 04:13:18PM +0300, Jani Nikula wrote:
>> > On Fri, 15 May 2020, Ville Syrjälä <ville.syrjala@linux.intel.com>
>> > wrote:
>> > > On Thu, May 14, 2020 at 02:19:23PM +0300, Jani Nikula wrote:
>> > > > On Thu, 14 May 2020, Gwan-gyeong Mun <gwan-gyeong.mun@intel.com
>> > > > > wrote:
>> > > > > In order to readout DP SDPs (Secondary Data Packet: DP HDR
>> > > > > Metadata
>> > > > > Infoframe SDP, DP VSC SDP), it refactors handling DP SDPs
>> > > > > codes.
>> > > > > It adds new compute routines for DP HDR Metadata Infoframe
>> > > > > SDP
>> > > > > and DP VSC SDP.
>> > > > > And new writing routines of DP SDPs (Secondary Data Packet)
>> > > > > that uses
>> > > > > computed configs.
>> > > > > New reading routines of DP SDPs are added for readout.
>> > > > > It adds a logging function for DP VSC SDP.
>> > > > > When receiving video it is very useful to be able to log DP
>> > > > > VSC SDP.
>> > > > > This greatly simplifies debugging.
>> > > > > In order to use a common VSC SDP Colorimetry calculating code
>> > > > > on PSR,
>> > > > > it uses a new psr vsc sdp compute routine.
>> > > >
>> > > > Pushed the series to drm-intel-next-queued with Daniel's irc
>> > > > ack for
>> > > > merging the two non-i915 patches that route too.
>> > >
>> > > fi-hsw-4770 now oopses at boot:
>> >
>> > /o\
>> >
>> > What did I miss? What part about the CI report did I overlook?
>>
>> Participating hosts (48 -> 45)
>> ------------------------------
>>
>> Additional (1): fi-kbl-7560u
>> Missing (4): fi-byt-clapper fi-byt-squawks fi-bsw-cyan fi-hsw-
>> 4200u
>>
>>
>> You kill machines at boot, CI won't tell you.
>>
>> This is (or at least was) because the network is shitty enough that
>> we
>> have more spurious failures because the ethernet went into the ether
>> than
>> because of people having killed the machine with their patches for
>> real.
>> Also it's hard to grab logs if the thing doesn't work at all, so cant
>> give
>> you any more data than the above.
>>
>> Yes this sucks :-/
>>
>> Cheers, Daniel
>>
>> > BR,
>> > Jani.
>> >
>> >
>> > > <1>[ 3.736903] BUG: kernel NULL pointer dereference, address:
>> > > 0000000000000000
>> > > <1>[ 3.736916] #PF: supervisor read access in kernel mode
>> > > <1>[ 3.736916] #PF: error_code(0x0000) - not-present page
>> > > <6>[ 3.736917] PGD 0 P4D 0
>> > > <4>[ 3.736919] Oops: 0000 [#1] PREEMPT SMP PTI
>> > > <4>[ 3.736921] CPU: 0 PID: 363 Comm: systemd-udevd Not tainted
>> > > 5.7.0-rc5-CI-CI_DRM_8485+ #1
>> > > <4>[ 3.736922] Hardware name: LENOVO 10AGS00601/SHARKBAY, BIOS
>> > > FBKT34AUS 04/24/2013
>> > > <4>[ 3.736986] RIP: 0010:intel_psr_enabled+0x8/0x70 [i915]
>> > > <4>[ 3.736988] Code: 18 48 c7 c6 40 09 79 a0 e8 e3 e2 04 e1 0f
>> > > b6 44 24 03 e9 f4 fd ff ff 90 66 2e 0f 1f 84 00 00 00 00 00 41 54
>> > > 55 53 48 83 ec 08 <48> 8b 9f d8 fe ff ff f6 83 5e 0d 00 00 20 74
>> > > 09 80 bb 6c b6 00 00
>> > > <4>[ 3.737036] RSP: 0018:ffffc9000047f8a0 EFLAGS: 00010286
>> > > <4>[ 3.737042] RAX: 0000000000000002 RBX: ffff8883ffd04000
>> > > RCX: 0000000000000001
>> > > <4>[ 3.737048] RDX: 0000000000000007 RSI: ffff8883ffd04000
>> > > RDI: 0000000000000128
>> > > <4>[ 3.737055] RBP: ffff888406afe200 R08: 000000000000000f
>> > > R09: 0000000000000001
>> > > <4>[ 3.737061] R10: 0000000000000000 R11: 0000000000000000
>> > > R12: 0000000000000000
>> > > <4>[ 3.737068] R13: ffff8883f75d0000 R14: ffff888406afe200
>> > > R15: ffff8883f75d0870
>> > > <4>[ 3.737075] FS: 00007f71618f9680(0000)
>> > > GS:ffff88840ec00000(0000) knlGS:0000000000000000
>> > > <4>[ 3.737082] CS: 0010 DS: 0000 ES: 0000 CR0:
>> > > 0000000080050033
>> > > <4>[ 3.737088] CR2: 0000000000000000 CR3: 0000000402510002
>> > > CR4: 00000000001606f0
>> > > <4>[ 3.737094] DR0: 0000000000000000 DR1: 0000000000000000
>> > > DR2: 0000000000000000
>> > > <4>[ 3.737101] DR3: 0000000000000000 DR6: 00000000fffe0ff0
>> > > DR7: 0000000000000400
>> > > <4>[ 3.737107] Call Trace:
>> > > <4>[ 3.737175] intel_read_dp_sdp+0x1a4/0x380 [i915]
>> > > <4>[ 3.737246] hsw_crt_get_config+0x12/0x40 [i915]
>> > > <4>[ 3.737317] intel_modeset_setup_hw_state+0x3b3/0x16a0
>> > > [i915]
>> > > ...
>> >
>> > --
>> > Jani Nikula, Intel Open Source Graphics Center
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 73+ messages in thread
* RE: [Intel-gfx] [PATCH v12 00/14] In order to readout DP SDPs, refactors the handling of DP SDPs
2020-05-15 13:13 ` Jani Nikula
(?)
@ 2020-05-15 14:25 ` Saarinen, Jani
-1 siblings, 0 replies; 73+ messages in thread
From: Saarinen, Jani @ 2020-05-15 14:25 UTC (permalink / raw)
To: Jani Nikula, Ville Syrjälä
Cc: daniel.vetter, linux-fbdev, intel-gfx, dri-devel, laurent.pinchart
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^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [Intel-gfx] [PATCH v12 00/14] In order to readout DP SDPs, refactors the handling of DP SDPs
@ 2020-05-15 14:25 ` Saarinen, Jani
0 siblings, 0 replies; 73+ messages in thread
From: Saarinen, Jani @ 2020-05-15 14:25 UTC (permalink / raw)
To: Jani Nikula, Ville Syrjälä
Cc: daniel.vetter, linux-fbdev, intel-gfx, dri-devel, laurent.pinchart
Hi,
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Jani Nikula
> Sent: perjantai 15. toukokuuta 2020 16.13
> To: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: linux-fbdev@vger.kernel.org; daniel.vetter@ffwll.ch; intel-
> gfx@lists.freedesktop.org; dri-devel@lists.freedesktop.org;
> laurent.pinchart@ideasonboard.com
> Subject: Re: [Intel-gfx] [PATCH v12 00/14] In order to readout DP SDPs, refactors the
> handling of DP SDPs
>
> On Fri, 15 May 2020, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> > On Thu, May 14, 2020 at 02:19:23PM +0300, Jani Nikula wrote:
> >> On Thu, 14 May 2020, Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> wrote:
> >> > In order to readout DP SDPs (Secondary Data Packet: DP HDR Metadata
> >> > Infoframe SDP, DP VSC SDP), it refactors handling DP SDPs codes.
> >> > It adds new compute routines for DP HDR Metadata Infoframe SDP and
> >> > DP VSC SDP.
> >> > And new writing routines of DP SDPs (Secondary Data Packet) that
> >> > uses computed configs.
> >> > New reading routines of DP SDPs are added for readout.
> >> > It adds a logging function for DP VSC SDP.
> >> > When receiving video it is very useful to be able to log DP VSC SDP.
> >> > This greatly simplifies debugging.
> >> > In order to use a common VSC SDP Colorimetry calculating code on
> >> > PSR, it uses a new psr vsc sdp compute routine.
> >>
> >> Pushed the series to drm-intel-next-queued with Daniel's irc ack for
> >> merging the two non-i915 patches that route too.
> >
> > fi-hsw-4770 now oopses at boot:
>
> /o\
>
> What did I miss? What part about the CI report did I overlook?
Damn, indeed:
https://patchwork.freedesktop.org/series/72853/
Ci results is success but it has:
Known issues
------------
Here are the changes found in Patchwork_17654 that come from known issues:
### CI changes ###
#### Issues hit ####
* boot:
- fi-hsw-4770: [PASS][1] -> [FAIL][2] ([CI#80])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8481/fi-hsw-4770/boot.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17654/fi-hsw-4770/boot.html
>
> BR,
> Jani.
>
>
> >
> > <1>[ 3.736903] BUG: kernel NULL pointer dereference, address:
> 0000000000000000
> > <1>[ 3.736916] #PF: supervisor read access in kernel mode
> > <1>[ 3.736916] #PF: error_code(0x0000) - not-present page
> > <6>[ 3.736917] PGD 0 P4D 0
> > <4>[ 3.736919] Oops: 0000 [#1] PREEMPT SMP PTI
> > <4>[ 3.736921] CPU: 0 PID: 363 Comm: systemd-udevd Not tainted 5.7.0-rc5-CI-
> CI_DRM_8485+ #1
> > <4>[ 3.736922] Hardware name: LENOVO 10AGS00601/SHARKBAY, BIOS
> FBKT34AUS 04/24/2013
> > <4>[ 3.736986] RIP: 0010:intel_psr_enabled+0x8/0x70 [i915]
> > <4>[ 3.736988] Code: 18 48 c7 c6 40 09 79 a0 e8 e3 e2 04 e1 0f b6 44 24 03 e9 f4
> fd ff ff 90 66 2e 0f 1f 84 00 00 00 00 00 41 54 55 53 48 83 ec 08 <48> 8b 9f d8 fe ff ff
> f6 83 5e 0d 00 00 20 74 09 80 bb 6c b6 00 00
> > <4>[ 3.737036] RSP: 0018:ffffc9000047f8a0 EFLAGS: 00010286
> > <4>[ 3.737042] RAX: 0000000000000002 RBX: ffff8883ffd04000 RCX:
> 0000000000000001
> > <4>[ 3.737048] RDX: 0000000000000007 RSI: ffff8883ffd04000 RDI:
> 0000000000000128
> > <4>[ 3.737055] RBP: ffff888406afe200 R08: 000000000000000f R09:
> 0000000000000001
> > <4>[ 3.737061] R10: 0000000000000000 R11: 0000000000000000 R12:
> 0000000000000000
> > <4>[ 3.737068] R13: ffff8883f75d0000 R14: ffff888406afe200 R15:
> ffff8883f75d0870
> > <4>[ 3.737075] FS: 00007f71618f9680(0000) GS:ffff88840ec00000(0000)
> knlGS:0000000000000000
> > <4>[ 3.737082] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
> > <4>[ 3.737088] CR2: 0000000000000000 CR3: 0000000402510002 CR4:
> 00000000001606f0
> > <4>[ 3.737094] DR0: 0000000000000000 DR1: 0000000000000000 DR2:
> 0000000000000000
> > <4>[ 3.737101] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7:
> 0000000000000400
> > <4>[ 3.737107] Call Trace:
> > <4>[ 3.737175] intel_read_dp_sdp+0x1a4/0x380 [i915]
> > <4>[ 3.737246] hsw_crt_get_config+0x12/0x40 [i915]
> > <4>[ 3.737317] intel_modeset_setup_hw_state+0x3b3/0x16a0 [i915]
> > ...
>
> --
> Jani Nikula, Intel Open Source Graphics Center
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 73+ messages in thread* RE: [Intel-gfx] [PATCH v12 00/14] In order to readout DP SDPs, refactors the handling of DP SDPs
@ 2020-05-15 14:25 ` Saarinen, Jani
0 siblings, 0 replies; 73+ messages in thread
From: Saarinen, Jani @ 2020-05-15 14:25 UTC (permalink / raw)
To: Jani Nikula, Ville Syrjälä
Cc: daniel.vetter, linux-fbdev, intel-gfx, dri-devel, laurent.pinchart
Hi,
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Jani Nikula
> Sent: perjantai 15. toukokuuta 2020 16.13
> To: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: linux-fbdev@vger.kernel.org; daniel.vetter@ffwll.ch; intel-
> gfx@lists.freedesktop.org; dri-devel@lists.freedesktop.org;
> laurent.pinchart@ideasonboard.com
> Subject: Re: [Intel-gfx] [PATCH v12 00/14] In order to readout DP SDPs, refactors the
> handling of DP SDPs
>
> On Fri, 15 May 2020, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> > On Thu, May 14, 2020 at 02:19:23PM +0300, Jani Nikula wrote:
> >> On Thu, 14 May 2020, Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> wrote:
> >> > In order to readout DP SDPs (Secondary Data Packet: DP HDR Metadata
> >> > Infoframe SDP, DP VSC SDP), it refactors handling DP SDPs codes.
> >> > It adds new compute routines for DP HDR Metadata Infoframe SDP and
> >> > DP VSC SDP.
> >> > And new writing routines of DP SDPs (Secondary Data Packet) that
> >> > uses computed configs.
> >> > New reading routines of DP SDPs are added for readout.
> >> > It adds a logging function for DP VSC SDP.
> >> > When receiving video it is very useful to be able to log DP VSC SDP.
> >> > This greatly simplifies debugging.
> >> > In order to use a common VSC SDP Colorimetry calculating code on
> >> > PSR, it uses a new psr vsc sdp compute routine.
> >>
> >> Pushed the series to drm-intel-next-queued with Daniel's irc ack for
> >> merging the two non-i915 patches that route too.
> >
> > fi-hsw-4770 now oopses at boot:
>
> /o\
>
> What did I miss? What part about the CI report did I overlook?
Damn, indeed:
https://patchwork.freedesktop.org/series/72853/
Ci results is success but it has:
Known issues
------------
Here are the changes found in Patchwork_17654 that come from known issues:
### CI changes ###
#### Issues hit ####
* boot:
- fi-hsw-4770: [PASS][1] -> [FAIL][2] ([CI#80])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8481/fi-hsw-4770/boot.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17654/fi-hsw-4770/boot.html
>
> BR,
> Jani.
>
>
> >
> > <1>[ 3.736903] BUG: kernel NULL pointer dereference, address:
> 0000000000000000
> > <1>[ 3.736916] #PF: supervisor read access in kernel mode
> > <1>[ 3.736916] #PF: error_code(0x0000) - not-present page
> > <6>[ 3.736917] PGD 0 P4D 0
> > <4>[ 3.736919] Oops: 0000 [#1] PREEMPT SMP PTI
> > <4>[ 3.736921] CPU: 0 PID: 363 Comm: systemd-udevd Not tainted 5.7.0-rc5-CI-
> CI_DRM_8485+ #1
> > <4>[ 3.736922] Hardware name: LENOVO 10AGS00601/SHARKBAY, BIOS
> FBKT34AUS 04/24/2013
> > <4>[ 3.736986] RIP: 0010:intel_psr_enabled+0x8/0x70 [i915]
> > <4>[ 3.736988] Code: 18 48 c7 c6 40 09 79 a0 e8 e3 e2 04 e1 0f b6 44 24 03 e9 f4
> fd ff ff 90 66 2e 0f 1f 84 00 00 00 00 00 41 54 55 53 48 83 ec 08 <48> 8b 9f d8 fe ff ff
> f6 83 5e 0d 00 00 20 74 09 80 bb 6c b6 00 00
> > <4>[ 3.737036] RSP: 0018:ffffc9000047f8a0 EFLAGS: 00010286
> > <4>[ 3.737042] RAX: 0000000000000002 RBX: ffff8883ffd04000 RCX:
> 0000000000000001
> > <4>[ 3.737048] RDX: 0000000000000007 RSI: ffff8883ffd04000 RDI:
> 0000000000000128
> > <4>[ 3.737055] RBP: ffff888406afe200 R08: 000000000000000f R09:
> 0000000000000001
> > <4>[ 3.737061] R10: 0000000000000000 R11: 0000000000000000 R12:
> 0000000000000000
> > <4>[ 3.737068] R13: ffff8883f75d0000 R14: ffff888406afe200 R15:
> ffff8883f75d0870
> > <4>[ 3.737075] FS: 00007f71618f9680(0000) GS:ffff88840ec00000(0000)
> knlGS:0000000000000000
> > <4>[ 3.737082] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
> > <4>[ 3.737088] CR2: 0000000000000000 CR3: 0000000402510002 CR4:
> 00000000001606f0
> > <4>[ 3.737094] DR0: 0000000000000000 DR1: 0000000000000000 DR2:
> 0000000000000000
> > <4>[ 3.737101] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7:
> 0000000000000400
> > <4>[ 3.737107] Call Trace:
> > <4>[ 3.737175] intel_read_dp_sdp+0x1a4/0x380 [i915]
> > <4>[ 3.737246] hsw_crt_get_config+0x12/0x40 [i915]
> > <4>[ 3.737317] intel_modeset_setup_hw_state+0x3b3/0x16a0 [i915]
> > ...
>
> --
> Jani Nikula, Intel Open Source Graphics Center
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 73+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for In order to readout DP SDPs, refactors the handling of DP SDPs (rev14)
2020-05-14 6:07 ` Gwan-gyeong Mun
` (19 preceding siblings ...)
(?)
@ 2020-05-15 14:11 ` Patchwork
-1 siblings, 0 replies; 73+ messages in thread
From: Patchwork @ 2020-05-15 14:11 UTC (permalink / raw)
To: Mun, Gwan-gyeong; +Cc: intel-gfx
== Series Details ==
Series: In order to readout DP SDPs, refactors the handling of DP SDPs (rev14)
URL : https://patchwork.freedesktop.org/series/72853/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8481 -> Patchwork_17654
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17654/index.html
Known issues
------------
Here are the changes found in Patchwork_17654 that come from known issues:
### CI changes ###
#### Issues hit ####
* boot:
- fi-hsw-4770: [PASS][1] -> [FAIL][2] ([CI#80])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8481/fi-hsw-4770/boot.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17654/fi-hsw-4770/boot.html
### IGT changes ###
#### Issues hit ####
* igt@i915_pm_rpm@module-reload:
- fi-kbl-guc: [PASS][3] -> [SKIP][4] ([fdo#109271])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8481/fi-kbl-guc/igt@i915_pm_rpm@module-reload.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17654/fi-kbl-guc/igt@i915_pm_rpm@module-reload.html
#### Possible fixes ####
* igt@i915_selftest@live@execlists:
- fi-cml-u2: [INCOMPLETE][5] ([i915#656]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8481/fi-cml-u2/igt@i915_selftest@live@execlists.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17654/fi-cml-u2/igt@i915_selftest@live@execlists.html
- fi-kbl-soraka: [INCOMPLETE][7] ([CI#80] / [i915#656]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8481/fi-kbl-soraka/igt@i915_selftest@live@execlists.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17654/fi-kbl-soraka/igt@i915_selftest@live@execlists.html
[CI#80]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/80
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#656]: https://gitlab.freedesktop.org/drm/intel/issues/656
Participating hosts (48 -> 45)
------------------------------
Additional (1): fi-kbl-7560u
Missing (4): fi-byt-clapper fi-byt-squawks fi-bsw-cyan fi-hsw-4200u
Build changes
-------------
* Linux: CI_DRM_8481 -> Patchwork_17654
CI-20190529: 20190529
CI_DRM_8481: 46f34234505b4e0eb3332974b47a36f9b0825de0 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5654: 5637a466a0b09535517751608f5525a8b468a76b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17654: b391c6a63abcab4ee99c9606550d21a62cc85730 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
b391c6a63abc drm/i915/psr: Use new DP VSC SDP compute routine on PSR
6d1aa4db1cc0 drm/i915/dp: Add compute routine for DP PSR VSC SDP
f8d2eda49214 drm/i915: Stop sending DP SDPs on ddi disable
5ac865ae0f3c drm/i915: Program DP SDPs on pipe updates
e373569ff8b1 drm/i915: Fix enabled infoframe states of lspcon
99bcd01ba088 drm/i915: Add state readout for DP VSC SDP
1723115921c6 drm/i915: Add state readout for DP HDR Metadata Infoframe SDP
c7d93732395b drm/i915: Program DP SDPs with computed configs
2375c1f7c8e0 drm/i915: Include DP VSC SDP in the crtc state dump
af8b261a6986 drm/i915: Include DP HDR Metadata Infoframe SDP in the crtc state dump
b53f926b3fa5 drm/i915: Include HDMI DRM infoframe in the crtc state dump
bf5fbd357375 drm: Add logging function for DP VSC SDP
0a10f4cd6cbe drm/i915/dp: Read out DP SDPs
e1053fdca03e video/hdmi: Add Unpack only function for DRM infoframe
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17654/index.html
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