From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stefan Roese Date: Thu, 14 May 2020 11:59:06 +0200 Subject: [PATCH v2 06/12] mips: traps: Set WG bit in EBase register on Octeon In-Reply-To: <20200514095912.14428-1-sr@denx.de> References: <20200514095912.14428-1-sr@denx.de> Message-ID: <20200514095912.14428-7-sr@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de WG (bit 11) needs to be set on Octeon to enable writing bits 63:30 of the exception base register. Signed-off-by: Stefan Roese --- Changes in v2: - Move bit macro definition to mipsregs.h arch/mips/include/asm/mipsregs.h | 1 + arch/mips/lib/traps.c | 4 ++++ 2 files changed, 5 insertions(+) diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index f80311e64e..998f84d0a1 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -365,6 +365,7 @@ * Bits in the coprocessor 0 EBase register. */ #define EBASE_CPUNUM 0x3ff +#define EBASE_WG (_ULCAST_(1) << 11) /* * Bits in the coprocessor 0 config register. diff --git a/arch/mips/lib/traps.c b/arch/mips/lib/traps.c index 8fff7541e3..dfef97dce3 100644 --- a/arch/mips/lib/traps.c +++ b/arch/mips/lib/traps.c @@ -106,6 +106,10 @@ void trap_init(ulong reloc_addr) saved_ebase = read_c0_ebase() & 0xfffff000; + /* Set WG bit on Octeon to enable writing to bits 63:30 */ + if (IS_ENABLED(CONFIG_ARCH_OCTEON)) + ebase |= EBASE_WG; + write_c0_ebase(ebase); clear_c0_status(ST0_BEV); execution_hazard_barrier(); -- 2.26.2