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From: Peter Zijlstra <peterz@infradead.org>
To: Stephane Eranian <eranian@google.com>
Cc: linux-kernel@vger.kernel.org, mingo@elte.hu, irogers@google.com,
	kim.phillips@amd.com, jolsa@redhat.com
Subject: Re: [PATCH 3/3] perf/x86/rapl: add AMD Fam17h RAPL support
Date: Mon, 18 May 2020 11:34:02 +0200	[thread overview]
Message-ID: <20200518093402.GB277222@hirez.programming.kicks-ass.net> (raw)
In-Reply-To: <20200515215733.20647-4-eranian@google.com>

On Fri, May 15, 2020 at 02:57:33PM -0700, Stephane Eranian wrote:

> +static struct perf_msr amd_rapl_msrs[] = {
> +	[PERF_RAPL_PP0]  = { 0, &rapl_events_cores_group, NULL},
> +	[PERF_RAPL_PKG]  = { MSR_AMD_PKG_ENERGY_STATUS,  &rapl_events_pkg_group,   test_msr },
> +	[PERF_RAPL_RAM]  = { 0, &rapl_events_ram_group,   NULL},
> +	[PERF_RAPL_PP1]  = { 0, &rapl_events_gpu_group,   NULL},
> +	[PERF_RAPL_PSYS] = { 0, &rapl_events_psys_group,  NULL},
> +};

Why have those !PKG things initialized? Wouldn't they default to 0
anyway? If not, surely { 0, } is sufficient.

  reply	other threads:[~2020-05-18  9:34 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-15 21:57 [PATCH 0/3] perf/x86/rapl: Enable RAPL for AMD Fam17h Stephane Eranian
2020-05-15 21:57 ` [PATCH 1/3] perf/x86/rapl: move RAPL support to common x86 code Stephane Eranian
2020-05-18  9:08   ` Peter Zijlstra
2020-05-15 21:57 ` [PATCH 2/3] perf/x86/rapl: refactor code for Intel/AMD sharing Stephane Eranian
2020-05-18  9:23   ` Peter Zijlstra
2020-05-15 21:57 ` [PATCH 3/3] perf/x86/rapl: add AMD Fam17h RAPL support Stephane Eranian
2020-05-18  9:34   ` Peter Zijlstra [this message]
2020-05-18 20:16     ` Stephane Eranian
2020-05-20  8:34       ` Stephane Eranian
2020-05-16 16:56 ` [PATCH 0/3] perf/x86/rapl: Enable RAPL for AMD Fam17h Alexander Monakov
2020-05-18  8:50 ` Jiri Olsa

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