From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.1 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E1E79C433DF for ; Mon, 18 May 2020 14:42:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B6126206D4 for ; Mon, 18 May 2020 14:42:49 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="P9UtLn9/" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727083AbgEROmt (ORCPT ); Mon, 18 May 2020 10:42:49 -0400 Received: from mail27.static.mailgun.info ([104.130.122.27]:18868 "EHLO mail27.static.mailgun.info" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726918AbgEROmt (ORCPT ); Mon, 18 May 2020 10:42:49 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1589812967; h=In-Reply-To: Content-Type: MIME-Version: References: Message-ID: Subject: Cc: To: From: Date: Sender; bh=BOJG45sKpRoyYeCu2iPA0P0NjKwkRXyqePBzMDunQaI=; b=P9UtLn9/lbQeARFepl60gHzNP09vAZFHQKU+C2KGm+VFK44b1ywelDcdSJAVyFicPprWJkze 02RD7eyAkRn/vNzDeGnBZrD59j3SlEvc2MvlH+JEnHZd74ALPsafYltpX+U1HJNPE+uVzsQf j5GxIKhRn87XzQ/LGHnF1Ivngrc= X-Mailgun-Sending-Ip: 104.130.122.27 X-Mailgun-Sid: WyI1MzIzYiIsICJsaW51eC1hcm0tbXNtQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by mxa.mailgun.org with ESMTP id 5ec29ee7.7fcd12958110-smtp-out-n03; Mon, 18 May 2020 14:42:47 -0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1001) id E5A9FC43636; Mon, 18 May 2020 14:42:46 +0000 (UTC) Received: from jcrouse1-lnx.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: jcrouse) by smtp.codeaurora.org (Postfix) with ESMTPSA id 2509DC432C2; Mon, 18 May 2020 14:42:45 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 2509DC432C2 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=jcrouse@codeaurora.org Date: Mon, 18 May 2020 08:42:43 -0600 From: Jordan Crouse To: Jonathan Marek Cc: freedreno@lists.freedesktop.org, David Airlie , "open list:DRM DRIVER FOR MSM ADRENO GPU" , open list , "open list:DRM DRIVER FOR MSM ADRENO GPU" , Rob Clark , Daniel Vetter , Sean Paul Subject: Re: [Freedreno] [PATCH v3 1/9] drm/msm: add msm_gem_get_and_pin_iova_range Message-ID: <20200518144243.GC3915@jcrouse1-lnx.qualcomm.com> Mail-Followup-To: Jonathan Marek , freedreno@lists.freedesktop.org, David Airlie , "open list:DRM DRIVER FOR MSM ADRENO GPU" , open list , "open list:DRM DRIVER FOR MSM ADRENO GPU" , Rob Clark , Daniel Vetter , Sean Paul References: <20200423210946.28867-1-jonathan@marek.ca> <20200423210946.28867-2-jonathan@marek.ca> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200423210946.28867-2-jonathan@marek.ca> User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Thu, Apr 23, 2020 at 05:09:13PM -0400, Jonathan Marek wrote: > This function allows pinning iova to a specific page range (for a6xx GMU). Reviewed-by: Jordan Crouse > Signed-off-by: Jonathan Marek > --- > drivers/gpu/drm/msm/msm_drv.h | 6 +++++- > drivers/gpu/drm/msm/msm_gem.c | 28 +++++++++++++++++++++------- > drivers/gpu/drm/msm/msm_gem_vma.c | 6 ++++-- > 3 files changed, 30 insertions(+), 10 deletions(-) > > diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h > index 194d900a460e..966fd9068c94 100644 > --- a/drivers/gpu/drm/msm/msm_drv.h > +++ b/drivers/gpu/drm/msm/msm_drv.h > @@ -236,7 +236,8 @@ int msm_crtc_enable_vblank(struct drm_crtc *crtc); > void msm_crtc_disable_vblank(struct drm_crtc *crtc); > > int msm_gem_init_vma(struct msm_gem_address_space *aspace, > - struct msm_gem_vma *vma, int npages); > + struct msm_gem_vma *vma, int npages, > + u64 range_start, u64 range_end); > void msm_gem_purge_vma(struct msm_gem_address_space *aspace, > struct msm_gem_vma *vma); > void msm_gem_unmap_vma(struct msm_gem_address_space *aspace, > @@ -276,6 +277,9 @@ vm_fault_t msm_gem_fault(struct vm_fault *vmf); > uint64_t msm_gem_mmap_offset(struct drm_gem_object *obj); > int msm_gem_get_iova(struct drm_gem_object *obj, > struct msm_gem_address_space *aspace, uint64_t *iova); > +int msm_gem_get_and_pin_iova_range(struct drm_gem_object *obj, > + struct msm_gem_address_space *aspace, uint64_t *iova, > + u64 range_start, u64 range_end); > int msm_gem_get_and_pin_iova(struct drm_gem_object *obj, > struct msm_gem_address_space *aspace, uint64_t *iova); > uint64_t msm_gem_iova(struct drm_gem_object *obj, > diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu/drm/msm/msm_gem.c > index 5a6a79fbc9d6..d8f56a34c117 100644 > --- a/drivers/gpu/drm/msm/msm_gem.c > +++ b/drivers/gpu/drm/msm/msm_gem.c > @@ -389,7 +389,8 @@ put_iova(struct drm_gem_object *obj) > } > > static int msm_gem_get_iova_locked(struct drm_gem_object *obj, > - struct msm_gem_address_space *aspace, uint64_t *iova) > + struct msm_gem_address_space *aspace, uint64_t *iova, > + u64 range_start, u64 range_end) > { > struct msm_gem_object *msm_obj = to_msm_bo(obj); > struct msm_gem_vma *vma; > @@ -404,7 +405,8 @@ static int msm_gem_get_iova_locked(struct drm_gem_object *obj, > if (IS_ERR(vma)) > return PTR_ERR(vma); > > - ret = msm_gem_init_vma(aspace, vma, obj->size >> PAGE_SHIFT); > + ret = msm_gem_init_vma(aspace, vma, obj->size >> PAGE_SHIFT, > + range_start, range_end); > if (ret) { > del_vma(vma); > return ret; > @@ -443,9 +445,13 @@ static int msm_gem_pin_iova(struct drm_gem_object *obj, > msm_obj->sgt, obj->size >> PAGE_SHIFT); > } > > -/* get iova and pin it. Should have a matching put */ > -int msm_gem_get_and_pin_iova(struct drm_gem_object *obj, > - struct msm_gem_address_space *aspace, uint64_t *iova) > +/* > + * get iova and pin it. Should have a matching put > + * limits iova to specified range (in pages) > + */ > +int msm_gem_get_and_pin_iova_range(struct drm_gem_object *obj, > + struct msm_gem_address_space *aspace, uint64_t *iova, > + u64 range_start, u64 range_end) > { > struct msm_gem_object *msm_obj = to_msm_bo(obj); > u64 local; > @@ -453,7 +459,8 @@ int msm_gem_get_and_pin_iova(struct drm_gem_object *obj, > > mutex_lock(&msm_obj->lock); > > - ret = msm_gem_get_iova_locked(obj, aspace, &local); > + ret = msm_gem_get_iova_locked(obj, aspace, &local, > + range_start, range_end); > > if (!ret) > ret = msm_gem_pin_iova(obj, aspace); > @@ -465,6 +472,13 @@ int msm_gem_get_and_pin_iova(struct drm_gem_object *obj, > return ret; > } > > +/* get iova and pin it. Should have a matching put */ > +int msm_gem_get_and_pin_iova(struct drm_gem_object *obj, > + struct msm_gem_address_space *aspace, uint64_t *iova) > +{ > + return msm_gem_get_and_pin_iova_range(obj, aspace, iova, 0, U64_MAX); > +} > + > /* > * Get an iova but don't pin it. Doesn't need a put because iovas are currently > * valid for the life of the object > @@ -476,7 +490,7 @@ int msm_gem_get_iova(struct drm_gem_object *obj, > int ret; > > mutex_lock(&msm_obj->lock); > - ret = msm_gem_get_iova_locked(obj, aspace, iova); > + ret = msm_gem_get_iova_locked(obj, aspace, iova, 0, U64_MAX); > mutex_unlock(&msm_obj->lock); > > return ret; > diff --git a/drivers/gpu/drm/msm/msm_gem_vma.c b/drivers/gpu/drm/msm/msm_gem_vma.c > index 1af5354bcd46..407b7ab82818 100644 > --- a/drivers/gpu/drm/msm/msm_gem_vma.c > +++ b/drivers/gpu/drm/msm/msm_gem_vma.c > @@ -103,7 +103,8 @@ void msm_gem_close_vma(struct msm_gem_address_space *aspace, > > /* Initialize a new vma and allocate an iova for it */ > int msm_gem_init_vma(struct msm_gem_address_space *aspace, > - struct msm_gem_vma *vma, int npages) > + struct msm_gem_vma *vma, int npages, > + u64 range_start, u64 range_end) > { > int ret; > > @@ -111,7 +112,8 @@ int msm_gem_init_vma(struct msm_gem_address_space *aspace, > return -EBUSY; > > spin_lock(&aspace->lock); > - ret = drm_mm_insert_node(&aspace->mm, &vma->node, npages); > + ret = drm_mm_insert_node_in_range(&aspace->mm, &vma->node, npages, 0, > + 0, range_start, range_end, 0); > spin_unlock(&aspace->lock); > > if (ret) > -- > 2.26.1 > > _______________________________________________ > Freedreno mailing list > Freedreno@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/freedreno -- The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.1 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B2AA1C433E0 for ; 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Mon, 18 May 2020 14:42:45 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 2509DC432C2 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=jcrouse@codeaurora.org Date: Mon, 18 May 2020 08:42:43 -0600 From: Jordan Crouse To: Jonathan Marek Subject: Re: [Freedreno] [PATCH v3 1/9] drm/msm: add msm_gem_get_and_pin_iova_range Message-ID: <20200518144243.GC3915@jcrouse1-lnx.qualcomm.com> Mail-Followup-To: Jonathan Marek , freedreno@lists.freedesktop.org, David Airlie , "open list:DRM DRIVER FOR MSM ADRENO GPU" , open list , "open list:DRM DRIVER FOR MSM ADRENO GPU" , Rob Clark , Daniel Vetter , Sean Paul References: <20200423210946.28867-1-jonathan@marek.ca> <20200423210946.28867-2-jonathan@marek.ca> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200423210946.28867-2-jonathan@marek.ca> User-Agent: Mutt/1.5.24 (2015-08-30) X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sean Paul , David Airlie , "open list:DRM DRIVER FOR MSM ADRENO GPU" , open list , "open list:DRM DRIVER FOR MSM ADRENO GPU" , freedreno@lists.freedesktop.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Thu, Apr 23, 2020 at 05:09:13PM -0400, Jonathan Marek wrote: > This function allows pinning iova to a specific page range (for a6xx GMU). Reviewed-by: Jordan Crouse > Signed-off-by: Jonathan Marek > --- > drivers/gpu/drm/msm/msm_drv.h | 6 +++++- > drivers/gpu/drm/msm/msm_gem.c | 28 +++++++++++++++++++++------- > drivers/gpu/drm/msm/msm_gem_vma.c | 6 ++++-- > 3 files changed, 30 insertions(+), 10 deletions(-) > > diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h > index 194d900a460e..966fd9068c94 100644 > --- a/drivers/gpu/drm/msm/msm_drv.h > +++ b/drivers/gpu/drm/msm/msm_drv.h > @@ -236,7 +236,8 @@ int msm_crtc_enable_vblank(struct drm_crtc *crtc); > void msm_crtc_disable_vblank(struct drm_crtc *crtc); > > int msm_gem_init_vma(struct msm_gem_address_space *aspace, > - struct msm_gem_vma *vma, int npages); > + struct msm_gem_vma *vma, int npages, > + u64 range_start, u64 range_end); > void msm_gem_purge_vma(struct msm_gem_address_space *aspace, > struct msm_gem_vma *vma); > void msm_gem_unmap_vma(struct msm_gem_address_space *aspace, > @@ -276,6 +277,9 @@ vm_fault_t msm_gem_fault(struct vm_fault *vmf); > uint64_t msm_gem_mmap_offset(struct drm_gem_object *obj); > int msm_gem_get_iova(struct drm_gem_object *obj, > struct msm_gem_address_space *aspace, uint64_t *iova); > +int msm_gem_get_and_pin_iova_range(struct drm_gem_object *obj, > + struct msm_gem_address_space *aspace, uint64_t *iova, > + u64 range_start, u64 range_end); > int msm_gem_get_and_pin_iova(struct drm_gem_object *obj, > struct msm_gem_address_space *aspace, uint64_t *iova); > uint64_t msm_gem_iova(struct drm_gem_object *obj, > diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu/drm/msm/msm_gem.c > index 5a6a79fbc9d6..d8f56a34c117 100644 > --- a/drivers/gpu/drm/msm/msm_gem.c > +++ b/drivers/gpu/drm/msm/msm_gem.c > @@ -389,7 +389,8 @@ put_iova(struct drm_gem_object *obj) > } > > static int msm_gem_get_iova_locked(struct drm_gem_object *obj, > - struct msm_gem_address_space *aspace, uint64_t *iova) > + struct msm_gem_address_space *aspace, uint64_t *iova, > + u64 range_start, u64 range_end) > { > struct msm_gem_object *msm_obj = to_msm_bo(obj); > struct msm_gem_vma *vma; > @@ -404,7 +405,8 @@ static int msm_gem_get_iova_locked(struct drm_gem_object *obj, > if (IS_ERR(vma)) > return PTR_ERR(vma); > > - ret = msm_gem_init_vma(aspace, vma, obj->size >> PAGE_SHIFT); > + ret = msm_gem_init_vma(aspace, vma, obj->size >> PAGE_SHIFT, > + range_start, range_end); > if (ret) { > del_vma(vma); > return ret; > @@ -443,9 +445,13 @@ static int msm_gem_pin_iova(struct drm_gem_object *obj, > msm_obj->sgt, obj->size >> PAGE_SHIFT); > } > > -/* get iova and pin it. Should have a matching put */ > -int msm_gem_get_and_pin_iova(struct drm_gem_object *obj, > - struct msm_gem_address_space *aspace, uint64_t *iova) > +/* > + * get iova and pin it. Should have a matching put > + * limits iova to specified range (in pages) > + */ > +int msm_gem_get_and_pin_iova_range(struct drm_gem_object *obj, > + struct msm_gem_address_space *aspace, uint64_t *iova, > + u64 range_start, u64 range_end) > { > struct msm_gem_object *msm_obj = to_msm_bo(obj); > u64 local; > @@ -453,7 +459,8 @@ int msm_gem_get_and_pin_iova(struct drm_gem_object *obj, > > mutex_lock(&msm_obj->lock); > > - ret = msm_gem_get_iova_locked(obj, aspace, &local); > + ret = msm_gem_get_iova_locked(obj, aspace, &local, > + range_start, range_end); > > if (!ret) > ret = msm_gem_pin_iova(obj, aspace); > @@ -465,6 +472,13 @@ int msm_gem_get_and_pin_iova(struct drm_gem_object *obj, > return ret; > } > > +/* get iova and pin it. Should have a matching put */ > +int msm_gem_get_and_pin_iova(struct drm_gem_object *obj, > + struct msm_gem_address_space *aspace, uint64_t *iova) > +{ > + return msm_gem_get_and_pin_iova_range(obj, aspace, iova, 0, U64_MAX); > +} > + > /* > * Get an iova but don't pin it. Doesn't need a put because iovas are currently > * valid for the life of the object > @@ -476,7 +490,7 @@ int msm_gem_get_iova(struct drm_gem_object *obj, > int ret; > > mutex_lock(&msm_obj->lock); > - ret = msm_gem_get_iova_locked(obj, aspace, iova); > + ret = msm_gem_get_iova_locked(obj, aspace, iova, 0, U64_MAX); > mutex_unlock(&msm_obj->lock); > > return ret; > diff --git a/drivers/gpu/drm/msm/msm_gem_vma.c b/drivers/gpu/drm/msm/msm_gem_vma.c > index 1af5354bcd46..407b7ab82818 100644 > --- a/drivers/gpu/drm/msm/msm_gem_vma.c > +++ b/drivers/gpu/drm/msm/msm_gem_vma.c > @@ -103,7 +103,8 @@ void msm_gem_close_vma(struct msm_gem_address_space *aspace, > > /* Initialize a new vma and allocate an iova for it */ > int msm_gem_init_vma(struct msm_gem_address_space *aspace, > - struct msm_gem_vma *vma, int npages) > + struct msm_gem_vma *vma, int npages, > + u64 range_start, u64 range_end) > { > int ret; > > @@ -111,7 +112,8 @@ int msm_gem_init_vma(struct msm_gem_address_space *aspace, > return -EBUSY; > > spin_lock(&aspace->lock); > - ret = drm_mm_insert_node(&aspace->mm, &vma->node, npages); > + ret = drm_mm_insert_node_in_range(&aspace->mm, &vma->node, npages, 0, > + 0, range_start, range_end, 0); > spin_unlock(&aspace->lock); > > if (ret) > -- > 2.26.1 > > _______________________________________________ > Freedreno mailing list > Freedreno@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/freedreno -- The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel