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From: Will Deacon <will@kernel.org>
To: Linu Cherian <linuc.decode@gmail.com>
Cc: maz@kernel.org, Linu Cherian <lcherian@marvell.com>,
	linux-arm-kernel@lists.infradead.org
Subject: Re: Clarification on necessary barriers before generating IPI
Date: Wed, 20 May 2020 09:28:57 +0100	[thread overview]
Message-ID: <20200520082856.GA24293@willie-the-truck> (raw)
In-Reply-To: <CAAHhmWiezrmtChuowQ4gyn8qhSUnfjc574P_riqHzTqifZK=dg@mail.gmail.com>

On Wed, May 20, 2020 at 01:38:24PM +0530, Linu Cherian wrote:
> How is it ensured that system register write using msr instruction(gic_send_sgi)
> doesnt get reordered before the stores to IPI call processing
> list(call_single_queue in kernel/smp.c), so that IPI is guaranteed to
> be generated after the stores get completed.

I think the flow is:

	<store to memory>
	DSB	ST
	MSR	SGI1R
	ISB

and then on the receiver:

	<interrupt; implicit ISB/context sync>
	MRS	IAR
	DSB	SY
	<control dependency>
	MSR	EOIR
	ISB
	<handle IPI>

> CMIIW, Dont we need an isb() in addition to to the wmb() in the below code ?

There is an isb?() in the code, after the loop. Are you saying it should be
somewhere else? If so, why?

Will

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  reply	other threads:[~2020-05-20  8:29 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-20  8:08 Clarification on necessary barriers before generating IPI Linu Cherian
2020-05-20  8:28 ` Will Deacon [this message]
2020-05-20  8:53   ` Linu Cherian
2020-05-20  9:03     ` Will Deacon
2020-05-20 17:37       ` Linu Cherian

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