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Wed, 20 May 2020 14:44:46 +0000 (UTC) Authentication-Results: garm.ovh; auth=pass (GARM-105G0065a90287b-f85a-4872-a28b-d452051a3724,D4AE9CB3A4750E3488E7135F1D4D455A9A9A4933) smtp.auth=groug@kaod.org Date: Wed, 20 May 2020 16:44:45 +0200 From: Greg Kurz To: =?UTF-8?B?Q8OpZHJpYw==?= Le Goater Subject: Re: [PATCH 7/9] ppc/pnv: Add POWER10 quads Message-ID: <20200520164445.1c8a03a1@bahia.lan> In-Reply-To: <20200513151109.453530-8-clg@kaod.org> References: <20200513151109.453530-1-clg@kaod.org> <20200513151109.453530-8-clg@kaod.org> X-Mailer: Claws Mail 3.17.4 (GTK+ 2.24.32; x86_64-redhat-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-Ovh-Tracer-Id: 4783385756989364619 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeduhedruddtledgjeejucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmnecujfgurhepfffhvffukfgjfhfogggtgfesthhqredtredtjeenucfhrhhomhepifhrvghgucfmuhhriicuoehgrhhouhhgsehkrghougdrohhrgheqnecuggftrfgrthhtvghrnhepueekjeekiefffedtveeukedvteejgeeivefhgfejgfdtleduvdfgfeelkeeuveeunecukfhppedtrddtrddtrddtpdekvddrvdehfedrvddtkedrvdegkeenucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepmhhouggvpehsmhhtphdqohhuthdphhgvlhhopehplhgrhigvrhejvdeirdhhrgdrohhvhhdrnhgvthdpihhnvghtpedtrddtrddtrddtpdhmrghilhhfrhhomhepghhrohhugheskhgrohgurdhorhhgpdhrtghpthhtohepqhgvmhhuqdguvghvvghlsehnohhnghhnuhdrohhrgh Received-SPF: pass client-ip=46.105.44.159; envelope-from=groug@kaod.org; helo=7.mo173.mail-out.ovh.net X-detected-operating-system: by eggs.gnu.org: First seen = 2020/05/20 10:44:51 X-ACL-Warn: Detected OS = Linux 3.11 and newer X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Wed, 13 May 2020 17:11:07 +0200 C=C3=A9dric Le Goater wrote: > Still needs some refinements on the XSCOM registers. >=20 > Signed-off-by: C=C3=A9dric Le Goater > --- > include/hw/ppc/pnv.h | 4 ++++ > hw/ppc/pnv.c | 33 +++++++++++++++++++++++++++++++++ > 2 files changed, 37 insertions(+) >=20 > diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h > index 3ff610a9c7b5..86bfa2107a8c 100644 > --- a/include/hw/ppc/pnv.h > +++ b/include/hw/ppc/pnv.h > @@ -123,6 +123,10 @@ typedef struct Pnv10Chip { > Pnv9Psi psi; > PnvLpcController lpc; > PnvOCC occ; > + > + uint32_t nr_quads; > + PnvQuad *quads; > + > } Pnv10Chip; > =20 > #define PNV10_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf) > diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c > index 9f1698a74467..fc751dd575d4 100644 > --- a/hw/ppc/pnv.c > +++ b/hw/ppc/pnv.c > @@ -1621,6 +1621,33 @@ static void pnv_chip_power10_instance_init(Object = *obj) > TYPE_PNV10_OCC, &error_abort, NULL); > } > =20 > + > +static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **err= p) > +{ > + PnvChip *chip =3D PNV_CHIP(chip10); > + int i; > + > + chip10->nr_quads =3D DIV_ROUND_UP(chip->nr_cores, 4); > + chip10->quads =3D g_new0(PnvQuad, chip10->nr_quads); > + > + for (i =3D 0; i < chip10->nr_quads; i++) { > + char eq_name[32]; > + PnvQuad *eq =3D &chip10->quads[i]; > + PnvCore *pnv_core =3D chip->cores[i * 4]; > + int core_id =3D CPU_CORE(pnv_core)->core_id; > + > + snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id); > + object_initialize_child(OBJECT(chip), eq_name, eq, sizeof(*eq), > + TYPE_PNV_QUAD, &error_fatal, NULL); > + > + object_property_set_int(OBJECT(eq), core_id, "id", &error_fatal); > + object_property_set_bool(OBJECT(eq), true, "realized", &error_fa= tal); > + > + pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->id), > + &eq->xscom_regs); > + } > +} So, this function is mostly identical to the P9 variant, except the xscom offset. Unless the refinements envisioned in the changelog bring substantial change, I'd suggest to move this to a common helper and call it from dedica= ted P9 and P10 realize functions. > + > static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) > { > PnvChipClass *pcc =3D PNV_CHIP_GET_CLASS(dev); > @@ -1642,6 +1669,12 @@ static void pnv_chip_power10_realize(DeviceState *= dev, Error **errp) > return; > } > =20 > + pnv_chip_power10_quad_realize(chip10, &local_err); > + if (local_err) { > + error_propagate(errp, local_err); > + return; > + } > + > /* XIVE2 interrupt controller (POWER10) */ > object_property_set_int(OBJECT(&chip10->xive), PNV10_XIVE2_IC_BASE(c= hip), > "ic-bar", &error_fatal);