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Thu, 21 May 2020 13:33:32 +0000 From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Albert Ou , Daniel Lezcano , Thomas Gleixner , Jason Cooper , Marc Zyngier Cc: Atish Patra , Alistair Francis , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v5 0/6] New RISC-V Local Interrupt Controller Driver Date: Thu, 21 May 2020 19:02:55 +0530 Message-Id: <20200521133301.816665-1-anup.patel@wdc.com> X-Mailer: git-send-email 2.25.1 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: MA1PR0101CA0033.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:22::19) To DM6PR04MB6201.namprd04.prod.outlook.com (2603:10b6:5:127::32) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from wdc.com (106.51.30.72) by MA1PR0101CA0033.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:22::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3021.23 via Frontend Transport; Thu, 21 May 2020 13:33:27 +0000 X-Mailer: git-send-email 2.25.1 X-Originating-IP: [106.51.30.72] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: f5b98668-ec46-462e-e18d-08d7fd8b8e03 X-MS-TrafficTypeDiagnostic: DM6PR04MB4442: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: WDCIPOUTBOUND: EOP-TRUE X-MS-Oob-TLC-OOBClassifiers: OLM:8882; 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X-MS-Exchange-AntiSpam-MessageData: iOlfmwc0q652mpNK2wuFX6aIuoY7bX4oUU500hDiOtHz8aLYf4iabAuo0EkeIS5H23mJ2q6LHDBB5sVdPFy22uM821M0x3ZtTqwpgX/R6I2rCHVqNpUQlCwpUbnBci/ZeAainguXM3dUC3s+coCh2two+8vCgx0h/sLTJd5tzyI9VTNfDJ1gZMf1ZdSmuK1PvmLtGULyhNnBTMblJuQSywC8HM7ESzemuEQsbIbkxdAVZ0xEC+bGLcEH1Odc330s0YVaJo/G7w90j11mEU+0/S0sa7CvcNDFM4Ne89fmrivx2ltiImuguBGeQ5nbB88BZyTCKvrJapkW+u+6yEMiFQz1N0M0u/esaMeZNVZy0UusZVpZdnJ+0jItQv2Jjbi1SDJHFKwi7jXAk/jVS+haLDUWMeOF7K2SHlqHohRMXtROYGGIoi8I37KnznWxzzfZEV9DzR4y4tJ7MxP8xe9X/ziIcdepY2s7+EG3W5rnqBY= X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: f5b98668-ec46-462e-e18d-08d7fd8b8e03 X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 May 2020 13:33:32.2793 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: NftLPczDPqDR67R1/punPYitcXJv2+3SSsJqP5ilfGbPSBGFEu950yP3AhTlXxo8QudD1lhCOUS1lE2DjS93gg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR04MB4442 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patchset provides a new RISC-V Local Interrupt Controller Driver for managing per-CPU local interrupts. The overall approach is inspired from the way per-CPU local interrupts are handled by Linux ARM64 and ARM GICv3 driver. Few advantages of this new driver over previous one are: 1. All local interrupts are registered as per-CPU interrupts 2. The RISC-V timer driver can register timer interrupt handler using kernel irq subsystem without relying on arch/riscv to explicitly call it's interrupt handler 3. The KVM RISC-V can use this driver to implement interrupt handler for per-HART guest external interrupt defined by the RISC-V H-Extension 4. In future, we can develop drivers for devices with per-HART interrupts without changing arch code or this driver (example, CLINT timer driver for RISC-V M-mode kernel) With this patchset, output of "cat /proc/interrupts" looks as follows: CPU0 CPU1 CPU2 CPU3 2: 379 0 0 0 SiFive PLIC 10 ttyS0 3: 591 0 0 0 SiFive PLIC 8 virtio0 5: 5079 10821 8435 12984 RISC-V INTC 5 riscv-timer IPI0: 2045 2537 891 870 Rescheduling interrupts IPI1: 9 269 91 168 Function call interrupts IPI2: 0 0 0 0 CPU stop interrupts The patchset is based up Linux-5.7-rc6 and can be found at riscv_intc_v5 branch of: https://github.com/avpatel/linux.git This series is tested on: 1. QEMU RV64 virt machine using Linux RISC-V S-mode 2. QEMU RV32 virt machine using Linux RISC-V S-mode 3. QEMU RV64 virt machine using Linux RISC-V M-mode (i.e. NoMMU) Changes since v4: - Rebased to Linux-5.7-rc6 and multi-PLIC improvement patches - Added separate patch to force select RISCV_INTC for CONFIG_RISCV - Fixed the driver for Linux RISC-V NoMMU Changes since v3: - Rebased to Linux-5.6-rc5 and Atish's PLIC patches - Added separate patch to rename and move plic_find_hart_id() to arch directory - Use riscv_of_parent_hartid() in riscv_intc_init() instead of atomic counter Changes since v2: - Dropped PATCH2 since it was merged long-time back - Rebased series from Linux-4.19-rc2 to Linux-5.6-rc2 Changes since v1: - Removed changes related to puggable IPI triggering - Separate patch for self-contained IPI handling routine - Removed patch for GENERIC_IRQ kconfig options - Added patch to remove do_IRQ() function - Rebased upon Atish's SMP patches Anup Patel (6): RISC-V: self-contained IPI handling routine RISC-V: Rename and move plic_find_hart_id() to arch directory irqchip: RISC-V per-HART local interrupt controller driver clocksource/drivers/timer-riscv: Use per-CPU timer interrupt RISC-V: Remove do_IRQ() function RISC-V: Force select RISCV_INTC for CONFIG_RISCV arch/riscv/Kconfig | 2 + arch/riscv/include/asm/irq.h | 5 - arch/riscv/include/asm/processor.h | 1 + arch/riscv/include/asm/smp.h | 3 + arch/riscv/kernel/cpu.c | 16 +++ arch/riscv/kernel/entry.S | 4 +- arch/riscv/kernel/irq.c | 33 +----- arch/riscv/kernel/smp.c | 11 +- arch/riscv/kernel/traps.c | 2 - drivers/clocksource/timer-riscv.c | 30 ++++- drivers/irqchip/Kconfig | 13 +++ drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-riscv-intc.c | 150 +++++++++++++++++++++++++ drivers/irqchip/irq-sifive-plic.c | 52 +++++---- include/linux/cpuhotplug.h | 1 + include/linux/irqchip/irq-riscv-intc.h | 20 ++++ 16 files changed, 280 insertions(+), 64 deletions(-) create mode 100644 drivers/irqchip/irq-riscv-intc.c create mode 100644 include/linux/irqchip/irq-riscv-intc.h -- 2.25.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,MENTIONS_GIT_HOSTING, MSGID_FROM_MTA_HEADER,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AD58EC433E0 for ; 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Thu, 21 May 2020 13:33:32 +0000 From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Albert Ou , Daniel Lezcano , Thomas Gleixner , Jason Cooper , Marc Zyngier Subject: [PATCH v5 0/6] New RISC-V Local Interrupt Controller Driver Date: Thu, 21 May 2020 19:02:55 +0530 Message-Id: <20200521133301.816665-1-anup.patel@wdc.com> X-Mailer: git-send-email 2.25.1 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: MA1PR0101CA0033.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:22::19) To DM6PR04MB6201.namprd04.prod.outlook.com (2603:10b6:5:127::32) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from wdc.com (106.51.30.72) by MA1PR0101CA0033.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:22::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3021.23 via Frontend Transport; Thu, 21 May 2020 13:33:27 +0000 X-Mailer: git-send-email 2.25.1 X-Originating-IP: [106.51.30.72] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: f5b98668-ec46-462e-e18d-08d7fd8b8e03 X-MS-TrafficTypeDiagnostic: DM6PR04MB4442: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: WDCIPOUTBOUND: EOP-TRUE X-MS-Oob-TLC-OOBClassifiers: OLM:8882; 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DIR:OUT; SFP:1102; X-MS-Exchange-AntiSpam-MessageData: iOlfmwc0q652mpNK2wuFX6aIuoY7bX4oUU500hDiOtHz8aLYf4iabAuo0EkeIS5H23mJ2q6LHDBB5sVdPFy22uM821M0x3ZtTqwpgX/R6I2rCHVqNpUQlCwpUbnBci/ZeAainguXM3dUC3s+coCh2two+8vCgx0h/sLTJd5tzyI9VTNfDJ1gZMf1ZdSmuK1PvmLtGULyhNnBTMblJuQSywC8HM7ESzemuEQsbIbkxdAVZ0xEC+bGLcEH1Odc330s0YVaJo/G7w90j11mEU+0/S0sa7CvcNDFM4Ne89fmrivx2ltiImuguBGeQ5nbB88BZyTCKvrJapkW+u+6yEMiFQz1N0M0u/esaMeZNVZy0UusZVpZdnJ+0jItQv2Jjbi1SDJHFKwi7jXAk/jVS+haLDUWMeOF7K2SHlqHohRMXtROYGGIoi8I37KnznWxzzfZEV9DzR4y4tJ7MxP8xe9X/ziIcdepY2s7+EG3W5rnqBY= X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: f5b98668-ec46-462e-e18d-08d7fd8b8e03 X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 May 2020 13:33:32.2793 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: NftLPczDPqDR67R1/punPYitcXJv2+3SSsJqP5ilfGbPSBGFEu950yP3AhTlXxo8QudD1lhCOUS1lE2DjS93gg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR04MB4442 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200521_063343_905102_D9A7D61E X-CRM114-Status: GOOD ( 17.57 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Anup Patel , Anup Patel , linux-kernel@vger.kernel.org, Atish Patra , Alistair Francis , linux-riscv@lists.infradead.org Sender: "linux-riscv" Errors-To: linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org This patchset provides a new RISC-V Local Interrupt Controller Driver for managing per-CPU local interrupts. The overall approach is inspired from the way per-CPU local interrupts are handled by Linux ARM64 and ARM GICv3 driver. Few advantages of this new driver over previous one are: 1. All local interrupts are registered as per-CPU interrupts 2. The RISC-V timer driver can register timer interrupt handler using kernel irq subsystem without relying on arch/riscv to explicitly call it's interrupt handler 3. The KVM RISC-V can use this driver to implement interrupt handler for per-HART guest external interrupt defined by the RISC-V H-Extension 4. In future, we can develop drivers for devices with per-HART interrupts without changing arch code or this driver (example, CLINT timer driver for RISC-V M-mode kernel) With this patchset, output of "cat /proc/interrupts" looks as follows: CPU0 CPU1 CPU2 CPU3 2: 379 0 0 0 SiFive PLIC 10 ttyS0 3: 591 0 0 0 SiFive PLIC 8 virtio0 5: 5079 10821 8435 12984 RISC-V INTC 5 riscv-timer IPI0: 2045 2537 891 870 Rescheduling interrupts IPI1: 9 269 91 168 Function call interrupts IPI2: 0 0 0 0 CPU stop interrupts The patchset is based up Linux-5.7-rc6 and can be found at riscv_intc_v5 branch of: https://github.com/avpatel/linux.git This series is tested on: 1. QEMU RV64 virt machine using Linux RISC-V S-mode 2. QEMU RV32 virt machine using Linux RISC-V S-mode 3. QEMU RV64 virt machine using Linux RISC-V M-mode (i.e. NoMMU) Changes since v4: - Rebased to Linux-5.7-rc6 and multi-PLIC improvement patches - Added separate patch to force select RISCV_INTC for CONFIG_RISCV - Fixed the driver for Linux RISC-V NoMMU Changes since v3: - Rebased to Linux-5.6-rc5 and Atish's PLIC patches - Added separate patch to rename and move plic_find_hart_id() to arch directory - Use riscv_of_parent_hartid() in riscv_intc_init() instead of atomic counter Changes since v2: - Dropped PATCH2 since it was merged long-time back - Rebased series from Linux-4.19-rc2 to Linux-5.6-rc2 Changes since v1: - Removed changes related to puggable IPI triggering - Separate patch for self-contained IPI handling routine - Removed patch for GENERIC_IRQ kconfig options - Added patch to remove do_IRQ() function - Rebased upon Atish's SMP patches Anup Patel (6): RISC-V: self-contained IPI handling routine RISC-V: Rename and move plic_find_hart_id() to arch directory irqchip: RISC-V per-HART local interrupt controller driver clocksource/drivers/timer-riscv: Use per-CPU timer interrupt RISC-V: Remove do_IRQ() function RISC-V: Force select RISCV_INTC for CONFIG_RISCV arch/riscv/Kconfig | 2 + arch/riscv/include/asm/irq.h | 5 - arch/riscv/include/asm/processor.h | 1 + arch/riscv/include/asm/smp.h | 3 + arch/riscv/kernel/cpu.c | 16 +++ arch/riscv/kernel/entry.S | 4 +- arch/riscv/kernel/irq.c | 33 +----- arch/riscv/kernel/smp.c | 11 +- arch/riscv/kernel/traps.c | 2 - drivers/clocksource/timer-riscv.c | 30 ++++- drivers/irqchip/Kconfig | 13 +++ drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-riscv-intc.c | 150 +++++++++++++++++++++++++ drivers/irqchip/irq-sifive-plic.c | 52 +++++---- include/linux/cpuhotplug.h | 1 + include/linux/irqchip/irq-riscv-intc.h | 20 ++++ 16 files changed, 280 insertions(+), 64 deletions(-) create mode 100644 drivers/irqchip/irq-riscv-intc.c create mode 100644 include/linux/irqchip/irq-riscv-intc.h -- 2.25.1