From: Gavin Wan <Gavin.Wan@amd.com>
To: amd-gfx@lists.freedesktop.org
Cc: Gavin Wan <Gavin.Wan@amd.com>
Subject: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV.
Date: Fri, 22 May 2020 19:39:27 +0000 [thread overview]
Message-ID: <20200522193927.278795-1-Gavin.Wan@amd.com> (raw)
For SRIOV, since the CP_INT_CNTL_RING0 is programed on host side.
The Guest should not program CP_INT_CNTL_RING0 again.
Change-Id: Ic336fab3b23b8371c9e9e192182a3ba14a8db8e1
Signed-off-by: Gavin Wan <Gavin.Wan@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index bd5dd4f64311..4d6928cfc269 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -4558,7 +4558,12 @@ static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
bool enable)
{
- u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
+ u32 tmp;
+
+ if (amdgpu_sriov_vf(adev))
+ return;
+
+ tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
enable ? 1 : 0);
--
2.25.1
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next reply other threads:[~2020-05-22 19:39 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-22 19:39 Gavin Wan [this message]
2020-05-22 19:52 ` [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV Alex Deucher
-- strict thread matches above, loose matches on Subject: below --
2020-05-22 18:19 Gavin Wan
2020-05-22 19:10 ` Alex Deucher
2020-05-22 19:40 ` Wan, Gavin
2020-05-26 4:35 ` Liu, Monk
2020-05-21 19:53 Gavin Wan
2020-05-21 20:25 ` Alex Deucher
2020-05-22 3:40 ` Liu, Monk
2020-05-22 3:46 ` Chen, Guchun
2020-05-22 5:09 ` Zhang, Hawking
2020-05-22 5:51 ` Liu, Monk
2020-05-22 6:12 ` Liu, Monk
2020-05-22 6:16 ` Zhang, Hawking
2020-05-22 6:16 ` Zhang, Hawking
2020-05-22 18:23 ` Wan, Gavin
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