* [PATCH v2 0/3] mmc: sdhci-of-arasan: Add support for Intel Keem Bay
@ 2020-05-26 6:27 Wan Ahmad Zainie
2020-05-26 6:27 ` [PATCH v2 1/3] dt-bindings: mmc: arasan: Add compatible strings " Wan Ahmad Zainie
` (2 more replies)
0 siblings, 3 replies; 9+ messages in thread
From: Wan Ahmad Zainie @ 2020-05-26 6:27 UTC (permalink / raw)
To: ulf.hansson, robh+dt, adrian.hunter, michal.simek
Cc: linux-mmc, devicetree, wan.ahmad.zainie.wan.mohamad
Hi.
The first part is to document the new compatible string required
for eMMC, SD and SDIO support in Intel Keem Bay.
The second part is to add the changes required to support the Host
Controller and its integrated eMMC PHY. The significant change is
to disable 64-bit support.
The patch was tested with Keem Bay evaluation module board.
Thank you.
Best regards,
Zainie
Changes since v1:
- Add patch to convert arasan,sdhci.txt to yaml format.
Wan Ahmad Zainie (3):
dt-bindings: mmc: arasan: Add compatible strings for Intel Keem Bay
mmc: sdhci-of-arasan: Add support for Intel Keem Bay
dt-bindings: mmc: convert arasan sdhci bindings to yaml
.../devicetree/bindings/mmc/arasan,sdhci.txt | 150 ---------
.../devicetree/bindings/mmc/arasan,sdhci.yaml | 293 ++++++++++++++++++
drivers/mmc/host/sdhci-of-arasan.c | 123 ++++++++
3 files changed, 416 insertions(+), 150 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
create mode 100644 Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml
--
2.17.1
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v2 1/3] dt-bindings: mmc: arasan: Add compatible strings for Intel Keem Bay
2020-05-26 6:27 [PATCH v2 0/3] mmc: sdhci-of-arasan: Add support for Intel Keem Bay Wan Ahmad Zainie
@ 2020-05-26 6:27 ` Wan Ahmad Zainie
2020-05-28 10:14 ` Ulf Hansson
2020-05-26 6:27 ` [PATCH v2 2/3] mmc: sdhci-of-arasan: Add support " Wan Ahmad Zainie
2020-05-26 6:27 ` [PATCH v2 3/3] dt-bindings: mmc: convert arasan sdhci bindings to yaml Wan Ahmad Zainie
2 siblings, 1 reply; 9+ messages in thread
From: Wan Ahmad Zainie @ 2020-05-26 6:27 UTC (permalink / raw)
To: ulf.hansson, robh+dt, adrian.hunter, michal.simek
Cc: linux-mmc, devicetree, wan.ahmad.zainie.wan.mohamad
Add new compatible strings in sdhci-of-arasan.c to support Intel Keem Bay
eMMC/SD/SDIO controller, based on Arasan SDHCI 5.1.
Signed-off-by: Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
---
.../devicetree/bindings/mmc/arasan,sdhci.txt | 42 +++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
index 630fe707f5c4..f29bf7dd2ece 100644
--- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
+++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
@@ -27,6 +27,12 @@ Required Properties:
For this device it is strongly suggested to include arasan,soc-ctl-syscon.
- "intel,lgm-sdhci-5.1-sdxc", "arasan,sdhci-5.1": Intel LGM SDXC PHY
For this device it is strongly suggested to include arasan,soc-ctl-syscon.
+ - "intel,keembay-sdhci-5.1-emmc", "arasan,sdhci-5.1": Intel Keem Bay eMMC
+ For this device it is strongly suggested to include arasan,soc-ctl-syscon.
+ - "intel,keembay-sdhci-5.1-sd": Intel Keem Bay SD controller
+ For this device it is strongly suggested to include arasan,soc-ctl-syscon.
+ - "intel,keembay-sdhci-5.1-sdio": Intel Keem Bay SDIO controller
+ For this device it is strongly suggested to include arasan,soc-ctl-syscon.
[5] Documentation/devicetree/bindings/mmc/sdhci-am654.txt
@@ -148,3 +154,39 @@ Example:
phy-names = "phy_arasan";
arasan,soc-ctl-syscon = <&sysconf>;
};
+
+ mmc: mmc@33000000 {
+ compatible = "intel,keembay-sdhci-5.1-emmc", "arasan,sdhci-5.1";
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x0 0x33000000 0x0 0x300>;
+ clock-names = "clk_xin", "clk_ahb";
+ clocks = <&scmi_clk KEEM_BAY_PSS_AUX_EMMC>,
+ <&scmi_clk KEEM_BAY_PSS_EMMC>;
+ phys = <&emmc_phy>;
+ phy-names = "phy_arasan";
+ assigned-clocks = <&scmi_clk KEEM_BAY_PSS_AUX_EMMC>;
+ assigned-clock-rates = <200000000>;
+ clock-output-names = "emmc_cardclock";
+ #clock-cells = <0>;
+ arasan,soc-ctl-syscon = <&mmc_phy_syscon>;
+ };
+
+ sd0: mmc@31000000 {
+ compatible = "intel,keembay-sdhci-5.1-sd";
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x0 0x31000000 0x0 0x300>;
+ clock-names = "clk_xin", "clk_ahb";
+ clocks = <&scmi_clk KEEM_BAY_PSS_AUX_SD0>,
+ <&scmi_clk KEEM_BAY_PSS_SD0>;
+ arasan,soc-ctl-syscon = <&sd0_phy_syscon>;
+ };
+
+ sd1: mmc@32000000 {
+ compatible = "intel,keembay-sdhci-5.1-sdio";
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x0 0x32000000 0x0 0x300>;
+ clock-names = "clk_xin", "clk_ahb";
+ clocks = <&scmi_clk KEEM_BAY_PSS_AUX_SD1>,
+ <&scmi_clk KEEM_BAY_PSS_SD1>;
+ arasan,soc-ctl-syscon = <&sd1_phy_syscon>;
+ };
--
2.17.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v2 2/3] mmc: sdhci-of-arasan: Add support for Intel Keem Bay
2020-05-26 6:27 [PATCH v2 0/3] mmc: sdhci-of-arasan: Add support for Intel Keem Bay Wan Ahmad Zainie
2020-05-26 6:27 ` [PATCH v2 1/3] dt-bindings: mmc: arasan: Add compatible strings " Wan Ahmad Zainie
@ 2020-05-26 6:27 ` Wan Ahmad Zainie
2020-05-28 10:14 ` Ulf Hansson
2020-05-26 6:27 ` [PATCH v2 3/3] dt-bindings: mmc: convert arasan sdhci bindings to yaml Wan Ahmad Zainie
2 siblings, 1 reply; 9+ messages in thread
From: Wan Ahmad Zainie @ 2020-05-26 6:27 UTC (permalink / raw)
To: ulf.hansson, robh+dt, adrian.hunter, michal.simek
Cc: linux-mmc, devicetree, wan.ahmad.zainie.wan.mohamad
Intel Keem Bay SoC eMMC/SD/SDIO controller is based on
Arasan SD 3.0 / eMMC 5.1 host controller IP.
However, it does not support 64-bit access as its AXI interface
has 32-bit address ports.
Signed-off-by: Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
Reviewed-by: Adrian Hunter <adrian.hunter@intel.com>
---
drivers/mmc/host/sdhci-of-arasan.c | 123 +++++++++++++++++++++++++++++
1 file changed, 123 insertions(+)
diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc/host/sdhci-of-arasan.c
index 2fe2c4dcc280..db9b544465cd 100644
--- a/drivers/mmc/host/sdhci-of-arasan.c
+++ b/drivers/mmc/host/sdhci-of-arasan.c
@@ -75,6 +75,7 @@ struct sdhci_arasan_soc_ctl_field {
*
* @baseclkfreq: Where to find corecfg_baseclkfreq
* @clockmultiplier: Where to find corecfg_clockmultiplier
+ * @support64b: Where to find SUPPORT64B bit
* @hiword_update: If true, use HIWORD_UPDATE to access the syscon
*
* It's up to the licensee of the Arsan IP block to make these available
@@ -84,6 +85,7 @@ struct sdhci_arasan_soc_ctl_field {
struct sdhci_arasan_soc_ctl_map {
struct sdhci_arasan_soc_ctl_field baseclkfreq;
struct sdhci_arasan_soc_ctl_field clockmultiplier;
+ struct sdhci_arasan_soc_ctl_field support64b;
bool hiword_update;
};
@@ -180,6 +182,13 @@ static const struct sdhci_arasan_soc_ctl_map intel_lgm_sdxc_soc_ctl_map = {
.hiword_update = false,
};
+static const struct sdhci_arasan_soc_ctl_map intel_keembay_soc_ctl_map = {
+ .baseclkfreq = { .reg = 0x0, .width = 8, .shift = 14 },
+ .clockmultiplier = { .reg = 0x4, .width = 8, .shift = 14 },
+ .support64b = { .reg = 0x4, .width = 1, .shift = 24 },
+ .hiword_update = false,
+};
+
/**
* sdhci_arasan_syscon_write - Write to a field in soc_ctl registers
*
@@ -1095,6 +1104,50 @@ static struct sdhci_arasan_of_data sdhci_arasan_generic_data = {
.clk_ops = &arasan_clk_ops,
};
+static const struct sdhci_pltfm_data sdhci_keembay_emmc_pdata = {
+ .ops = &sdhci_arasan_cqe_ops,
+ .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
+ SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
+ SDHCI_QUIRK_NO_LED |
+ SDHCI_QUIRK_32BIT_DMA_ADDR |
+ SDHCI_QUIRK_32BIT_DMA_SIZE |
+ SDHCI_QUIRK_32BIT_ADMA_SIZE,
+ .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
+ SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
+ SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 |
+ SDHCI_QUIRK2_STOP_WITH_TC |
+ SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
+};
+
+static const struct sdhci_pltfm_data sdhci_keembay_sd_pdata = {
+ .ops = &sdhci_arasan_ops,
+ .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
+ SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
+ SDHCI_QUIRK_NO_LED |
+ SDHCI_QUIRK_32BIT_DMA_ADDR |
+ SDHCI_QUIRK_32BIT_DMA_SIZE |
+ SDHCI_QUIRK_32BIT_ADMA_SIZE,
+ .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
+ SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
+ SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON |
+ SDHCI_QUIRK2_STOP_WITH_TC |
+ SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
+};
+
+static const struct sdhci_pltfm_data sdhci_keembay_sdio_pdata = {
+ .ops = &sdhci_arasan_ops,
+ .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
+ SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
+ SDHCI_QUIRK_NO_LED |
+ SDHCI_QUIRK_32BIT_DMA_ADDR |
+ SDHCI_QUIRK_32BIT_DMA_SIZE |
+ SDHCI_QUIRK_32BIT_ADMA_SIZE,
+ .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
+ SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
+ SDHCI_QUIRK2_HOST_OFF_CARD_ON |
+ SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
+};
+
static struct sdhci_arasan_of_data sdhci_arasan_rk3399_data = {
.soc_ctl_map = &rk3399_soc_ctl_map,
.pdata = &sdhci_arasan_cqe_pdata,
@@ -1140,6 +1193,21 @@ static struct sdhci_arasan_of_data sdhci_arasan_versal_data = {
.clk_ops = &versal_clk_ops,
};
+static struct sdhci_arasan_of_data intel_keembay_emmc_data = {
+ .soc_ctl_map = &intel_keembay_soc_ctl_map,
+ .pdata = &sdhci_keembay_emmc_pdata,
+};
+
+static struct sdhci_arasan_of_data intel_keembay_sd_data = {
+ .soc_ctl_map = &intel_keembay_soc_ctl_map,
+ .pdata = &sdhci_keembay_sd_pdata,
+};
+
+static struct sdhci_arasan_of_data intel_keembay_sdio_data = {
+ .soc_ctl_map = &intel_keembay_soc_ctl_map,
+ .pdata = &sdhci_keembay_sdio_pdata,
+};
+
static const struct of_device_id sdhci_arasan_of_match[] = {
/* SoC-specific compatible strings w/ soc_ctl_map */
{
@@ -1154,6 +1222,18 @@ static const struct of_device_id sdhci_arasan_of_match[] = {
.compatible = "intel,lgm-sdhci-5.1-sdxc",
.data = &intel_lgm_sdxc_data,
},
+ {
+ .compatible = "intel,keembay-sdhci-5.1-emmc",
+ .data = &intel_keembay_emmc_data,
+ },
+ {
+ .compatible = "intel,keembay-sdhci-5.1-sd",
+ .data = &intel_keembay_sd_data,
+ },
+ {
+ .compatible = "intel,keembay-sdhci-5.1-sdio",
+ .data = &intel_keembay_sdio_data,
+ },
/* Generic compatible below here */
{
.compatible = "arasan,sdhci-8.9a",
@@ -1297,6 +1377,40 @@ static void sdhci_arasan_unregister_sdclk(struct device *dev)
of_clk_del_provider(dev->of_node);
}
+/**
+ * sdhci_arasan_update_support64b - Set SUPPORT_64B (64-bit System Bus Support)
+ *
+ * This should be set based on the System Address Bus.
+ * 0: the Core supports only 32-bit System Address Bus.
+ * 1: the Core supports 64-bit System Address Bus.
+ *
+ * NOTES:
+ * - For Keem Bay, it is required to clear this bit. Its default value is 1'b1.
+ * Keem Bay does not support 64-bit access.
+ *
+ * @host The sdhci_host
+ */
+static void sdhci_arasan_update_support64b(struct sdhci_host *host, u32 value)
+{
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
+ const struct sdhci_arasan_soc_ctl_map *soc_ctl_map =
+ sdhci_arasan->soc_ctl_map;
+
+ /* Having a map is optional */
+ if (!soc_ctl_map)
+ return;
+
+ /* If we have a map, we expect to have a syscon */
+ if (!sdhci_arasan->soc_ctl_base) {
+ pr_warn("%s: Have regmap, but no soc-ctl-syscon\n",
+ mmc_hostname(host->mmc));
+ return;
+ }
+
+ sdhci_arasan_syscon_write(host, &soc_ctl_map->support64b, value);
+}
+
/**
* sdhci_arasan_register_sdclk - Register the sdcardclk for a PHY to use
*
@@ -1469,6 +1583,15 @@ static int sdhci_arasan_probe(struct platform_device *pdev)
"rockchip,rk3399-sdhci-5.1"))
sdhci_arasan_update_clockmultiplier(host, 0x0);
+ if (of_device_is_compatible(np, "intel,keembay-sdhci-5.1-emmc") ||
+ of_device_is_compatible(np, "intel,keembay-sdhci-5.1-sd") ||
+ of_device_is_compatible(np, "intel,keembay-sdhci-5.1-sdio")) {
+ sdhci_arasan_update_clockmultiplier(host, 0x0);
+ sdhci_arasan_update_support64b(host, 0x0);
+
+ host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
+ }
+
sdhci_arasan_update_baseclkfreq(host);
ret = sdhci_arasan_register_sdclk(sdhci_arasan, clk_xin, &pdev->dev);
--
2.17.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v2 3/3] dt-bindings: mmc: convert arasan sdhci bindings to yaml
2020-05-26 6:27 [PATCH v2 0/3] mmc: sdhci-of-arasan: Add support for Intel Keem Bay Wan Ahmad Zainie
2020-05-26 6:27 ` [PATCH v2 1/3] dt-bindings: mmc: arasan: Add compatible strings " Wan Ahmad Zainie
2020-05-26 6:27 ` [PATCH v2 2/3] mmc: sdhci-of-arasan: Add support " Wan Ahmad Zainie
@ 2020-05-26 6:27 ` Wan Ahmad Zainie
2020-05-28 10:14 ` Ulf Hansson
2020-05-29 17:25 ` Rob Herring
2 siblings, 2 replies; 9+ messages in thread
From: Wan Ahmad Zainie @ 2020-05-26 6:27 UTC (permalink / raw)
To: ulf.hansson, robh+dt, adrian.hunter, michal.simek
Cc: linux-mmc, devicetree, wan.ahmad.zainie.wan.mohamad
Convert arasan,sdhci.txt file to yaml. The new file arasan,sdhci.yaml
will inherit properties from mmc-controller.yaml. 'sdhci' is no longer
a valid name for node and should be changed to 'mmc'.
Suggested-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
---
.../devicetree/bindings/mmc/arasan,sdhci.txt | 192 ------------
.../devicetree/bindings/mmc/arasan,sdhci.yaml | 293 ++++++++++++++++++
2 files changed, 293 insertions(+), 192 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
create mode 100644 Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml
diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
deleted file mode 100644
index f29bf7dd2ece..000000000000
--- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
+++ /dev/null
@@ -1,192 +0,0 @@
-Device Tree Bindings for the Arasan SDHCI Controller
-
- The bindings follow the mmc[1], clock[2], interrupt[3] and phy[4] bindings.
- Only deviations are documented here.
-
- [1] Documentation/devicetree/bindings/mmc/mmc.txt
- [2] Documentation/devicetree/bindings/clock/clock-bindings.txt
- [3] Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
- [4] Documentation/devicetree/bindings/phy/phy-bindings.txt
-
-Required Properties:
- - compatible: Compatibility string. One of:
- - "arasan,sdhci-8.9a": generic Arasan SDHCI 8.9a PHY
- - "arasan,sdhci-4.9a": generic Arasan SDHCI 4.9a PHY
- - "arasan,sdhci-5.1": generic Arasan SDHCI 5.1 PHY
- - "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1": rk3399 eMMC PHY
- For this device it is strongly suggested to include arasan,soc-ctl-syscon.
- - "xlnx,zynqmp-8.9a": ZynqMP SDHCI 8.9a PHY
- For this device it is strongly suggested to include clock-output-names and
- #clock-cells.
- - "xlnx,versal-8.9a": Versal SDHCI 8.9a PHY
- For this device it is strongly suggested to include clock-output-names and
- #clock-cells.
- - "ti,am654-sdhci-5.1", "arasan,sdhci-5.1": TI AM654 MMC PHY
- Note: This binding has been deprecated and moved to [5].
- - "intel,lgm-sdhci-5.1-emmc", "arasan,sdhci-5.1": Intel LGM eMMC PHY
- For this device it is strongly suggested to include arasan,soc-ctl-syscon.
- - "intel,lgm-sdhci-5.1-sdxc", "arasan,sdhci-5.1": Intel LGM SDXC PHY
- For this device it is strongly suggested to include arasan,soc-ctl-syscon.
- - "intel,keembay-sdhci-5.1-emmc", "arasan,sdhci-5.1": Intel Keem Bay eMMC
- For this device it is strongly suggested to include arasan,soc-ctl-syscon.
- - "intel,keembay-sdhci-5.1-sd": Intel Keem Bay SD controller
- For this device it is strongly suggested to include arasan,soc-ctl-syscon.
- - "intel,keembay-sdhci-5.1-sdio": Intel Keem Bay SDIO controller
- For this device it is strongly suggested to include arasan,soc-ctl-syscon.
-
- [5] Documentation/devicetree/bindings/mmc/sdhci-am654.txt
-
- - reg: From mmc bindings: Register location and length.
- - clocks: From clock bindings: Handles to clock inputs.
- - clock-names: From clock bindings: Tuple including "clk_xin" and "clk_ahb"
- - interrupts: Interrupt specifier
-
-Required Properties for "arasan,sdhci-5.1":
- - phys: From PHY bindings: Phandle for the Generic PHY for arasan.
- - phy-names: MUST be "phy_arasan".
-
-Optional Properties:
- - arasan,soc-ctl-syscon: A phandle to a syscon device (see ../mfd/syscon.txt)
- used to access core corecfg registers. Offsets of registers in this
- syscon are determined based on the main compatible string for the device.
- - clock-output-names: If specified, this will be the name of the card clock
- which will be exposed by this device. Required if #clock-cells is
- specified.
- - #clock-cells: If specified this should be the value <0> or <1>. With this
- property in place we will export one or two clocks representing the Card
- Clock. These clocks are expected to be consumed by our PHY.
- - xlnx,fails-without-test-cd: when present, the controller doesn't work when
- the CD line is not connected properly, and the line is not connected
- properly. Test mode can be used to force the controller to function.
- - xlnx,int-clock-stable-broken: when present, the controller always reports
- that the internal clock is stable even when it is not.
-
- - xlnx,mio-bank: When specified, this will indicate the MIO bank number in
- which the command and data lines are configured. If not specified, driver
- will assume this as 0.
-
-Example:
- sdhci@e0100000 {
- compatible = "arasan,sdhci-8.9a";
- reg = <0xe0100000 0x1000>;
- clock-names = "clk_xin", "clk_ahb";
- clocks = <&clkc 21>, <&clkc 32>;
- interrupt-parent = <&gic>;
- interrupts = <0 24 4>;
- } ;
-
- sdhci@e2800000 {
- compatible = "arasan,sdhci-5.1";
- reg = <0xe2800000 0x1000>;
- clock-names = "clk_xin", "clk_ahb";
- clocks = <&cru 8>, <&cru 18>;
- interrupt-parent = <&gic>;
- interrupts = <0 24 4>;
- phys = <&emmc_phy>;
- phy-names = "phy_arasan";
- } ;
-
- sdhci: sdhci@fe330000 {
- compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
- reg = <0x0 0xfe330000 0x0 0x10000>;
- interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
- clock-names = "clk_xin", "clk_ahb";
- arasan,soc-ctl-syscon = <&grf>;
- assigned-clocks = <&cru SCLK_EMMC>;
- assigned-clock-rates = <200000000>;
- clock-output-names = "emmc_cardclock";
- phys = <&emmc_phy>;
- phy-names = "phy_arasan";
- #clock-cells = <0>;
- };
-
- sdhci: mmc@ff160000 {
- compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
- interrupt-parent = <&gic>;
- interrupts = <0 48 4>;
- reg = <0x0 0xff160000 0x0 0x1000>;
- clocks = <&clk200>, <&clk200>;
- clock-names = "clk_xin", "clk_ahb";
- clock-output-names = "clk_out_sd0", "clk_in_sd0";
- #clock-cells = <1>;
- clk-phase-sd-hs = <63>, <72>;
- };
-
- sdhci: mmc@f1040000 {
- compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a";
- interrupt-parent = <&gic>;
- interrupts = <0 126 4>;
- reg = <0x0 0xf1040000 0x0 0x10000>;
- clocks = <&clk200>, <&clk200>;
- clock-names = "clk_xin", "clk_ahb";
- clock-output-names = "clk_out_sd0", "clk_in_sd0";
- #clock-cells = <1>;
- clk-phase-sd-hs = <132>, <60>;
- };
-
- emmc: sdhci@ec700000 {
- compatible = "intel,lgm-sdhci-5.1-emmc", "arasan,sdhci-5.1";
- reg = <0xec700000 0x300>;
- interrupt-parent = <&ioapic1>;
- interrupts = <44 1>;
- clocks = <&cgu0 LGM_CLK_EMMC5>, <&cgu0 LGM_CLK_NGI>,
- <&cgu0 LGM_GCLK_EMMC>;
- clock-names = "clk_xin", "clk_ahb", "gate";
- clock-output-names = "emmc_cardclock";
- #clock-cells = <0>;
- phys = <&emmc_phy>;
- phy-names = "phy_arasan";
- arasan,soc-ctl-syscon = <&sysconf>;
- };
-
- sdxc: sdhci@ec600000 {
- compatible = "arasan,sdhci-5.1", "intel,lgm-sdhci-5.1-sdxc";
- reg = <0xec600000 0x300>;
- interrupt-parent = <&ioapic1>;
- interrupts = <43 1>;
- clocks = <&cgu0 LGM_CLK_SDIO>, <&cgu0 LGM_CLK_NGI>,
- <&cgu0 LGM_GCLK_SDXC>;
- clock-names = "clk_xin", "clk_ahb", "gate";
- clock-output-names = "sdxc_cardclock";
- #clock-cells = <0>;
- phys = <&sdxc_phy>;
- phy-names = "phy_arasan";
- arasan,soc-ctl-syscon = <&sysconf>;
- };
-
- mmc: mmc@33000000 {
- compatible = "intel,keembay-sdhci-5.1-emmc", "arasan,sdhci-5.1";
- interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0x0 0x33000000 0x0 0x300>;
- clock-names = "clk_xin", "clk_ahb";
- clocks = <&scmi_clk KEEM_BAY_PSS_AUX_EMMC>,
- <&scmi_clk KEEM_BAY_PSS_EMMC>;
- phys = <&emmc_phy>;
- phy-names = "phy_arasan";
- assigned-clocks = <&scmi_clk KEEM_BAY_PSS_AUX_EMMC>;
- assigned-clock-rates = <200000000>;
- clock-output-names = "emmc_cardclock";
- #clock-cells = <0>;
- arasan,soc-ctl-syscon = <&mmc_phy_syscon>;
- };
-
- sd0: mmc@31000000 {
- compatible = "intel,keembay-sdhci-5.1-sd";
- interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0x0 0x31000000 0x0 0x300>;
- clock-names = "clk_xin", "clk_ahb";
- clocks = <&scmi_clk KEEM_BAY_PSS_AUX_SD0>,
- <&scmi_clk KEEM_BAY_PSS_SD0>;
- arasan,soc-ctl-syscon = <&sd0_phy_syscon>;
- };
-
- sd1: mmc@32000000 {
- compatible = "intel,keembay-sdhci-5.1-sdio";
- interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0x0 0x32000000 0x0 0x300>;
- clock-names = "clk_xin", "clk_ahb";
- clocks = <&scmi_clk KEEM_BAY_PSS_AUX_SD1>,
- <&scmi_clk KEEM_BAY_PSS_SD1>;
- arasan,soc-ctl-syscon = <&sd1_phy_syscon>;
- };
diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml b/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml
new file mode 100644
index 000000000000..927e2f13958b
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml
@@ -0,0 +1,293 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/mmc/arasan,sdhci.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Device Tree Bindings for the Arasan SDHCI Controller
+
+allOf:
+ - $ref: "mmc-controller.yaml#"
+
+maintainers:
+ - Adrian Hunter <adrian.hunter@intel.com>
+
+properties:
+ compatible:
+ oneOf:
+ - const: arasan,sdhci-8.9a # generic Arasan SDHCI 8.9a PHY
+ - const: arasan,sdhci-4.9a # generic Arasan SDHCI 4.9a PHY
+ - const: arasan,sdhci-5.1 # generic Arasan SDHCI 5.1 PHY
+ - items:
+ - const: rockchip,rk3399-sdhci-5.1 # rk3399 eMMC PHY
+ - const: arasan,sdhci-5.1
+ description: |
+ For this device it is strongly suggested to include
+ arasan,soc-ctl-syscon.
+ - items:
+ - const: xlnx,zynqmp-8.9a # ZynqMP SDHCI 8.9a PHY
+ - const: arasan,sdhci-8.9a
+ description: |
+ For this device it is strongly suggested to include
+ clock-output-names and '#clock-cells'.
+ - items:
+ - const: xlnx,versal-8.9a # Versal SDHCI 8.9a PHY
+ - const: arasan,sdhci-8.9a
+ description: |
+ For this device it is strongly suggested to include
+ clock-output-names and '#clock-cells'.
+ - items:
+ - const: intel,lgm-sdhci-5.1-emmc # Intel LGM eMMC PHY
+ - const: arasan,sdhci-5.1
+ description: |
+ For this device it is strongly suggested to include
+ arasan,soc-ctl-syscon.
+ - items:
+ - const: intel,lgm-sdhci-5.1-sdxc # Intel LGM SDXC PHY
+ - const: arasan,sdhci-5.1
+ description: |
+ For this device it is strongly suggested to include
+ arasan,soc-ctl-syscon.
+ - items:
+ - const: intel,keembay-sdhci-5.1-emmc # Intel Keem Bay eMMC PHY
+ - const: arasan,sdhci-5.1
+ description: |
+ For this device it is strongly suggested to include
+ arasan,soc-ctl-syscon.
+ - const: intel,keembay-sdhci-5.1-sd # Intel Keem Bay SD controller
+ description: |
+ For this device it is strongly suggested to include
+ arasan,soc-ctl-syscon.
+ - const: intel,keembay-sdhci-5.1-sdio # Intel Keem Bay SDIO controller
+ description: |
+ For this device it is strongly suggested to include
+ arasan,soc-ctl-syscon.
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ minItems: 2
+ maxItems: 3
+
+ clock-names:
+ minItems: 2
+ items:
+ - const: clk_xin
+ - const: clk_ahb
+ - const: gate
+
+ interrupts:
+ maxItems: 1
+
+ phys:
+ maxItems: 1
+
+ phy-names:
+ const: phy_arasan
+
+ arasan,soc-ctl-syscon:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: |
+ A phandle to a syscon device (see ../mfd/syscon.txt) used to access
+ core corecfg registers. Offsets of registers in this syscon are
+ determined based on the main compatible string for the device.
+
+ clock-output-names:
+ description: |
+ If specified, this will be the name of the card clock which will
+ be exposed by this device. Required if '#clock-cells' is specified.
+
+ '#clock-cells':
+ enum: [0, 1]
+ description: |
+ With this property in place we will export one or two clocks
+ representing the Card Clock. These clocks are expected to be
+ consumed by our PHY.
+
+ xlnx,fails-without-test-cd:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description: |
+ When present, the controller doesn't work when the CD line is not
+ connected properly, and the line is not connected properly.
+ Test mode can be used to force the controller to function.
+
+ xlnx,int-clock-stable-broken:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description: |
+ When present, the controller always reports that the internal clock
+ is stable even when it is not.
+
+ xlnx,mio-bank:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ When specified, this will indicate the MIO bank number in which
+ the command and data lines are configured. If not specified, driver
+ will assume this as 0.
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+
+if:
+ properties:
+ compatible:
+ contains:
+ const: arasan,sdhci-5.1
+then:
+ required:
+ - phys
+ - phy-names
+
+examples:
+ - |
+ mmc@e0100000 {
+ compatible = "arasan,sdhci-8.9a";
+ reg = <0xe0100000 0x1000>;
+ clock-names = "clk_xin", "clk_ahb";
+ clocks = <&clkc 21>, <&clkc 32>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 24 4>;
+ };
+
+ - |
+ mmc@e2800000 {
+ compatible = "arasan,sdhci-5.1";
+ reg = <0xe2800000 0x1000>;
+ clock-names = "clk_xin", "clk_ahb";
+ clocks = <&cru 8>, <&cru 18>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 24 4>;
+ phys = <&emmc_phy>;
+ phy-names = "phy_arasan";
+ };
+
+ - |
+ #include <dt-bindings/clock/rk3399-cru.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ mmc@fe330000 {
+ compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
+ reg = <0x0 0xfe330000 0x0 0x10000>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
+ clock-names = "clk_xin", "clk_ahb";
+ arasan,soc-ctl-syscon = <&grf>;
+ assigned-clocks = <&cru SCLK_EMMC>;
+ assigned-clock-rates = <200000000>;
+ clock-output-names = "emmc_cardclock";
+ phys = <&emmc_phy>;
+ phy-names = "phy_arasan";
+ #clock-cells = <0>;
+ };
+
+ - |
+ mmc@ff160000 {
+ compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
+ interrupt-parent = <&gic>;
+ interrupts = <0 48 4>;
+ reg = <0x0 0xff160000 0x0 0x1000>;
+ clocks = <&clk200>, <&clk200>;
+ clock-names = "clk_xin", "clk_ahb";
+ clock-output-names = "clk_out_sd0", "clk_in_sd0";
+ #clock-cells = <1>;
+ clk-phase-sd-hs = <63 72>;
+ };
+
+ - |
+ mmc@f1040000 {
+ compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a";
+ interrupt-parent = <&gic>;
+ interrupts = <0 126 4>;
+ reg = <0x0 0xf1040000 0x0 0x10000>;
+ clocks = <&clk200>, <&clk200>;
+ clock-names = "clk_xin", "clk_ahb";
+ clock-output-names = "clk_out_sd0", "clk_in_sd0";
+ #clock-cells = <1>;
+ clk-phase-sd-hs = <132>, <60>;
+ };
+
+ - |
+ #define LGM_CLK_EMMC5
+ #define LGM_CLK_NGI
+ #define LGM_GCLK_EMMC
+ mmc@ec700000 {
+ compatible = "intel,lgm-sdhci-5.1-emmc", "arasan,sdhci-5.1";
+ reg = <0xec700000 0x300>;
+ interrupt-parent = <&ioapic1>;
+ interrupts = <44 1>;
+ clocks = <&cgu0 LGM_CLK_EMMC5>, <&cgu0 LGM_CLK_NGI>,
+ <&cgu0 LGM_GCLK_EMMC>;
+ clock-names = "clk_xin", "clk_ahb", "gate";
+ clock-output-names = "emmc_cardclock";
+ #clock-cells = <0>;
+ phys = <&emmc_phy>;
+ phy-names = "phy_arasan";
+ arasan,soc-ctl-syscon = <&sysconf>;
+ };
+
+ - |
+ #define LGM_CLK_SDIO
+ #define LGM_GCLK_SDXC
+ mmc@ec600000 {
+ compatible = "intel,lgm-sdhci-5.1-sdxc", "arasan,sdhci-5.1";
+ reg = <0xec600000 0x300>;
+ interrupt-parent = <&ioapic1>;
+ interrupts = <43 1>;
+ clocks = <&cgu0 LGM_CLK_SDIO>, <&cgu0 LGM_CLK_NGI>,
+ <&cgu0 LGM_GCLK_SDXC>;
+ clock-names = "clk_xin", "clk_ahb", "gate";
+ clock-output-names = "sdxc_cardclock";
+ #clock-cells = <0>;
+ phys = <&sdxc_phy>;
+ phy-names = "phy_arasan";
+ arasan,soc-ctl-syscon = <&sysconf>;
+ };
+
+ - |
+ #define KEEM_BAY_PSS_AUX_EMMC
+ #define KEEM_BAY_PSS_EMMC
+ mmc@33000000 {
+ compatible = "intel,keembay-sdhci-5.1-emmc", "arasan,sdhci-5.1";
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x0 0x33000000 0x0 0x300>;
+ clock-names = "clk_xin", "clk_ahb";
+ clocks = <&scmi_clk KEEM_BAY_PSS_AUX_EMMC>,
+ <&scmi_clk KEEM_BAY_PSS_EMMC>;
+ phys = <&emmc_phy>;
+ phy-names = "phy_arasan";
+ assigned-clocks = <&scmi_clk KEEM_BAY_PSS_AUX_EMMC>;
+ assigned-clock-rates = <200000000>;
+ clock-output-names = "emmc_cardclock";
+ #clock-cells = <0>;
+ arasan,soc-ctl-syscon = <&mmc_phy_syscon>;
+ };
+
+ - |
+ #define KEEM_BAY_PSS_AUX_SD0
+ #define KEEM_BAY_PSS_SD0
+ mmc@31000000 {
+ compatible = "intel,keembay-sdhci-5.1-sd";
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x0 0x31000000 0x0 0x300>;
+ clock-names = "clk_xin", "clk_ahb";
+ clocks = <&scmi_clk KEEM_BAY_PSS_AUX_SD0>,
+ <&scmi_clk KEEM_BAY_PSS_SD0>;
+ arasan,soc-ctl-syscon = <&sd0_phy_syscon>;
+ };
+
+ - |
+ #define KEEM_BAY_PSS_AUX_SD1
+ #define KEEM_BAY_PSS_SD1
+ mmc@32000000 {
+ compatible = "intel,keembay-sdhci-5.1-sdio";
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x0 0x32000000 0x0 0x300>;
+ clock-names = "clk_xin", "clk_ahb";
+ clocks = <&scmi_clk KEEM_BAY_PSS_AUX_SD1>,
+ <&scmi_clk KEEM_BAY_PSS_SD1>;
+ arasan,soc-ctl-syscon = <&sd1_phy_syscon>;
+ };
--
2.17.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH v2 1/3] dt-bindings: mmc: arasan: Add compatible strings for Intel Keem Bay
2020-05-26 6:27 ` [PATCH v2 1/3] dt-bindings: mmc: arasan: Add compatible strings " Wan Ahmad Zainie
@ 2020-05-28 10:14 ` Ulf Hansson
0 siblings, 0 replies; 9+ messages in thread
From: Ulf Hansson @ 2020-05-28 10:14 UTC (permalink / raw)
To: Wan Ahmad Zainie
Cc: Rob Herring, Adrian Hunter, Michal Simek, linux-mmc, DTML
On Tue, 26 May 2020 at 08:29, Wan Ahmad Zainie
<wan.ahmad.zainie.wan.mohamad@intel.com> wrote:
>
> Add new compatible strings in sdhci-of-arasan.c to support Intel Keem Bay
> eMMC/SD/SDIO controller, based on Arasan SDHCI 5.1.
>
> Signed-off-by: Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
Applied for next, thanks!
Kind regards
Uffe
> ---
> .../devicetree/bindings/mmc/arasan,sdhci.txt | 42 +++++++++++++++++++
> 1 file changed, 42 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
> index 630fe707f5c4..f29bf7dd2ece 100644
> --- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
> +++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
> @@ -27,6 +27,12 @@ Required Properties:
> For this device it is strongly suggested to include arasan,soc-ctl-syscon.
> - "intel,lgm-sdhci-5.1-sdxc", "arasan,sdhci-5.1": Intel LGM SDXC PHY
> For this device it is strongly suggested to include arasan,soc-ctl-syscon.
> + - "intel,keembay-sdhci-5.1-emmc", "arasan,sdhci-5.1": Intel Keem Bay eMMC
> + For this device it is strongly suggested to include arasan,soc-ctl-syscon.
> + - "intel,keembay-sdhci-5.1-sd": Intel Keem Bay SD controller
> + For this device it is strongly suggested to include arasan,soc-ctl-syscon.
> + - "intel,keembay-sdhci-5.1-sdio": Intel Keem Bay SDIO controller
> + For this device it is strongly suggested to include arasan,soc-ctl-syscon.
>
> [5] Documentation/devicetree/bindings/mmc/sdhci-am654.txt
>
> @@ -148,3 +154,39 @@ Example:
> phy-names = "phy_arasan";
> arasan,soc-ctl-syscon = <&sysconf>;
> };
> +
> + mmc: mmc@33000000 {
> + compatible = "intel,keembay-sdhci-5.1-emmc", "arasan,sdhci-5.1";
> + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x0 0x33000000 0x0 0x300>;
> + clock-names = "clk_xin", "clk_ahb";
> + clocks = <&scmi_clk KEEM_BAY_PSS_AUX_EMMC>,
> + <&scmi_clk KEEM_BAY_PSS_EMMC>;
> + phys = <&emmc_phy>;
> + phy-names = "phy_arasan";
> + assigned-clocks = <&scmi_clk KEEM_BAY_PSS_AUX_EMMC>;
> + assigned-clock-rates = <200000000>;
> + clock-output-names = "emmc_cardclock";
> + #clock-cells = <0>;
> + arasan,soc-ctl-syscon = <&mmc_phy_syscon>;
> + };
> +
> + sd0: mmc@31000000 {
> + compatible = "intel,keembay-sdhci-5.1-sd";
> + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x0 0x31000000 0x0 0x300>;
> + clock-names = "clk_xin", "clk_ahb";
> + clocks = <&scmi_clk KEEM_BAY_PSS_AUX_SD0>,
> + <&scmi_clk KEEM_BAY_PSS_SD0>;
> + arasan,soc-ctl-syscon = <&sd0_phy_syscon>;
> + };
> +
> + sd1: mmc@32000000 {
> + compatible = "intel,keembay-sdhci-5.1-sdio";
> + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x0 0x32000000 0x0 0x300>;
> + clock-names = "clk_xin", "clk_ahb";
> + clocks = <&scmi_clk KEEM_BAY_PSS_AUX_SD1>,
> + <&scmi_clk KEEM_BAY_PSS_SD1>;
> + arasan,soc-ctl-syscon = <&sd1_phy_syscon>;
> + };
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2 2/3] mmc: sdhci-of-arasan: Add support for Intel Keem Bay
2020-05-26 6:27 ` [PATCH v2 2/3] mmc: sdhci-of-arasan: Add support " Wan Ahmad Zainie
@ 2020-05-28 10:14 ` Ulf Hansson
0 siblings, 0 replies; 9+ messages in thread
From: Ulf Hansson @ 2020-05-28 10:14 UTC (permalink / raw)
To: Wan Ahmad Zainie
Cc: Rob Herring, Adrian Hunter, Michal Simek, linux-mmc, DTML
On Tue, 26 May 2020 at 08:29, Wan Ahmad Zainie
<wan.ahmad.zainie.wan.mohamad@intel.com> wrote:
>
> Intel Keem Bay SoC eMMC/SD/SDIO controller is based on
> Arasan SD 3.0 / eMMC 5.1 host controller IP.
>
> However, it does not support 64-bit access as its AXI interface
> has 32-bit address ports.
>
> Signed-off-by: Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
> Reviewed-by: Adrian Hunter <adrian.hunter@intel.com>
Applied for next, thanks!
Kind regards
Uffe
> ---
> drivers/mmc/host/sdhci-of-arasan.c | 123 +++++++++++++++++++++++++++++
> 1 file changed, 123 insertions(+)
>
> diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc/host/sdhci-of-arasan.c
> index 2fe2c4dcc280..db9b544465cd 100644
> --- a/drivers/mmc/host/sdhci-of-arasan.c
> +++ b/drivers/mmc/host/sdhci-of-arasan.c
> @@ -75,6 +75,7 @@ struct sdhci_arasan_soc_ctl_field {
> *
> * @baseclkfreq: Where to find corecfg_baseclkfreq
> * @clockmultiplier: Where to find corecfg_clockmultiplier
> + * @support64b: Where to find SUPPORT64B bit
> * @hiword_update: If true, use HIWORD_UPDATE to access the syscon
> *
> * It's up to the licensee of the Arsan IP block to make these available
> @@ -84,6 +85,7 @@ struct sdhci_arasan_soc_ctl_field {
> struct sdhci_arasan_soc_ctl_map {
> struct sdhci_arasan_soc_ctl_field baseclkfreq;
> struct sdhci_arasan_soc_ctl_field clockmultiplier;
> + struct sdhci_arasan_soc_ctl_field support64b;
> bool hiword_update;
> };
>
> @@ -180,6 +182,13 @@ static const struct sdhci_arasan_soc_ctl_map intel_lgm_sdxc_soc_ctl_map = {
> .hiword_update = false,
> };
>
> +static const struct sdhci_arasan_soc_ctl_map intel_keembay_soc_ctl_map = {
> + .baseclkfreq = { .reg = 0x0, .width = 8, .shift = 14 },
> + .clockmultiplier = { .reg = 0x4, .width = 8, .shift = 14 },
> + .support64b = { .reg = 0x4, .width = 1, .shift = 24 },
> + .hiword_update = false,
> +};
> +
> /**
> * sdhci_arasan_syscon_write - Write to a field in soc_ctl registers
> *
> @@ -1095,6 +1104,50 @@ static struct sdhci_arasan_of_data sdhci_arasan_generic_data = {
> .clk_ops = &arasan_clk_ops,
> };
>
> +static const struct sdhci_pltfm_data sdhci_keembay_emmc_pdata = {
> + .ops = &sdhci_arasan_cqe_ops,
> + .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
> + SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
> + SDHCI_QUIRK_NO_LED |
> + SDHCI_QUIRK_32BIT_DMA_ADDR |
> + SDHCI_QUIRK_32BIT_DMA_SIZE |
> + SDHCI_QUIRK_32BIT_ADMA_SIZE,
> + .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
> + SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
> + SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 |
> + SDHCI_QUIRK2_STOP_WITH_TC |
> + SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
> +};
> +
> +static const struct sdhci_pltfm_data sdhci_keembay_sd_pdata = {
> + .ops = &sdhci_arasan_ops,
> + .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
> + SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
> + SDHCI_QUIRK_NO_LED |
> + SDHCI_QUIRK_32BIT_DMA_ADDR |
> + SDHCI_QUIRK_32BIT_DMA_SIZE |
> + SDHCI_QUIRK_32BIT_ADMA_SIZE,
> + .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
> + SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
> + SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON |
> + SDHCI_QUIRK2_STOP_WITH_TC |
> + SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
> +};
> +
> +static const struct sdhci_pltfm_data sdhci_keembay_sdio_pdata = {
> + .ops = &sdhci_arasan_ops,
> + .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
> + SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
> + SDHCI_QUIRK_NO_LED |
> + SDHCI_QUIRK_32BIT_DMA_ADDR |
> + SDHCI_QUIRK_32BIT_DMA_SIZE |
> + SDHCI_QUIRK_32BIT_ADMA_SIZE,
> + .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
> + SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
> + SDHCI_QUIRK2_HOST_OFF_CARD_ON |
> + SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
> +};
> +
> static struct sdhci_arasan_of_data sdhci_arasan_rk3399_data = {
> .soc_ctl_map = &rk3399_soc_ctl_map,
> .pdata = &sdhci_arasan_cqe_pdata,
> @@ -1140,6 +1193,21 @@ static struct sdhci_arasan_of_data sdhci_arasan_versal_data = {
> .clk_ops = &versal_clk_ops,
> };
>
> +static struct sdhci_arasan_of_data intel_keembay_emmc_data = {
> + .soc_ctl_map = &intel_keembay_soc_ctl_map,
> + .pdata = &sdhci_keembay_emmc_pdata,
> +};
> +
> +static struct sdhci_arasan_of_data intel_keembay_sd_data = {
> + .soc_ctl_map = &intel_keembay_soc_ctl_map,
> + .pdata = &sdhci_keembay_sd_pdata,
> +};
> +
> +static struct sdhci_arasan_of_data intel_keembay_sdio_data = {
> + .soc_ctl_map = &intel_keembay_soc_ctl_map,
> + .pdata = &sdhci_keembay_sdio_pdata,
> +};
> +
> static const struct of_device_id sdhci_arasan_of_match[] = {
> /* SoC-specific compatible strings w/ soc_ctl_map */
> {
> @@ -1154,6 +1222,18 @@ static const struct of_device_id sdhci_arasan_of_match[] = {
> .compatible = "intel,lgm-sdhci-5.1-sdxc",
> .data = &intel_lgm_sdxc_data,
> },
> + {
> + .compatible = "intel,keembay-sdhci-5.1-emmc",
> + .data = &intel_keembay_emmc_data,
> + },
> + {
> + .compatible = "intel,keembay-sdhci-5.1-sd",
> + .data = &intel_keembay_sd_data,
> + },
> + {
> + .compatible = "intel,keembay-sdhci-5.1-sdio",
> + .data = &intel_keembay_sdio_data,
> + },
> /* Generic compatible below here */
> {
> .compatible = "arasan,sdhci-8.9a",
> @@ -1297,6 +1377,40 @@ static void sdhci_arasan_unregister_sdclk(struct device *dev)
> of_clk_del_provider(dev->of_node);
> }
>
> +/**
> + * sdhci_arasan_update_support64b - Set SUPPORT_64B (64-bit System Bus Support)
> + *
> + * This should be set based on the System Address Bus.
> + * 0: the Core supports only 32-bit System Address Bus.
> + * 1: the Core supports 64-bit System Address Bus.
> + *
> + * NOTES:
> + * - For Keem Bay, it is required to clear this bit. Its default value is 1'b1.
> + * Keem Bay does not support 64-bit access.
> + *
> + * @host The sdhci_host
> + */
> +static void sdhci_arasan_update_support64b(struct sdhci_host *host, u32 value)
> +{
> + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> + struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
> + const struct sdhci_arasan_soc_ctl_map *soc_ctl_map =
> + sdhci_arasan->soc_ctl_map;
> +
> + /* Having a map is optional */
> + if (!soc_ctl_map)
> + return;
> +
> + /* If we have a map, we expect to have a syscon */
> + if (!sdhci_arasan->soc_ctl_base) {
> + pr_warn("%s: Have regmap, but no soc-ctl-syscon\n",
> + mmc_hostname(host->mmc));
> + return;
> + }
> +
> + sdhci_arasan_syscon_write(host, &soc_ctl_map->support64b, value);
> +}
> +
> /**
> * sdhci_arasan_register_sdclk - Register the sdcardclk for a PHY to use
> *
> @@ -1469,6 +1583,15 @@ static int sdhci_arasan_probe(struct platform_device *pdev)
> "rockchip,rk3399-sdhci-5.1"))
> sdhci_arasan_update_clockmultiplier(host, 0x0);
>
> + if (of_device_is_compatible(np, "intel,keembay-sdhci-5.1-emmc") ||
> + of_device_is_compatible(np, "intel,keembay-sdhci-5.1-sd") ||
> + of_device_is_compatible(np, "intel,keembay-sdhci-5.1-sdio")) {
> + sdhci_arasan_update_clockmultiplier(host, 0x0);
> + sdhci_arasan_update_support64b(host, 0x0);
> +
> + host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
> + }
> +
> sdhci_arasan_update_baseclkfreq(host);
>
> ret = sdhci_arasan_register_sdclk(sdhci_arasan, clk_xin, &pdev->dev);
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2 3/3] dt-bindings: mmc: convert arasan sdhci bindings to yaml
2020-05-26 6:27 ` [PATCH v2 3/3] dt-bindings: mmc: convert arasan sdhci bindings to yaml Wan Ahmad Zainie
@ 2020-05-28 10:14 ` Ulf Hansson
2020-05-29 17:25 ` Rob Herring
1 sibling, 0 replies; 9+ messages in thread
From: Ulf Hansson @ 2020-05-28 10:14 UTC (permalink / raw)
To: Wan Ahmad Zainie, Rob Herring
Cc: Adrian Hunter, Michal Simek, linux-mmc, DTML
On Tue, 26 May 2020 at 08:29, Wan Ahmad Zainie
<wan.ahmad.zainie.wan.mohamad@intel.com> wrote:
>
> Convert arasan,sdhci.txt file to yaml. The new file arasan,sdhci.yaml
> will inherit properties from mmc-controller.yaml. 'sdhci' is no longer
> a valid name for node and should be changed to 'mmc'.
>
> Suggested-by: Ulf Hansson <ulf.hansson@linaro.org>
> Signed-off-by: Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
I didn't queue this one yet, as I am would appreciate some feedback
from Rob first.
Kind regards
Uffe
> ---
> .../devicetree/bindings/mmc/arasan,sdhci.txt | 192 ------------
> .../devicetree/bindings/mmc/arasan,sdhci.yaml | 293 ++++++++++++++++++
> 2 files changed, 293 insertions(+), 192 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
> create mode 100644 Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml
>
> diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
> deleted file mode 100644
> index f29bf7dd2ece..000000000000
> --- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
> +++ /dev/null
> @@ -1,192 +0,0 @@
> -Device Tree Bindings for the Arasan SDHCI Controller
> -
> - The bindings follow the mmc[1], clock[2], interrupt[3] and phy[4] bindings.
> - Only deviations are documented here.
> -
> - [1] Documentation/devicetree/bindings/mmc/mmc.txt
> - [2] Documentation/devicetree/bindings/clock/clock-bindings.txt
> - [3] Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
> - [4] Documentation/devicetree/bindings/phy/phy-bindings.txt
> -
> -Required Properties:
> - - compatible: Compatibility string. One of:
> - - "arasan,sdhci-8.9a": generic Arasan SDHCI 8.9a PHY
> - - "arasan,sdhci-4.9a": generic Arasan SDHCI 4.9a PHY
> - - "arasan,sdhci-5.1": generic Arasan SDHCI 5.1 PHY
> - - "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1": rk3399 eMMC PHY
> - For this device it is strongly suggested to include arasan,soc-ctl-syscon.
> - - "xlnx,zynqmp-8.9a": ZynqMP SDHCI 8.9a PHY
> - For this device it is strongly suggested to include clock-output-names and
> - #clock-cells.
> - - "xlnx,versal-8.9a": Versal SDHCI 8.9a PHY
> - For this device it is strongly suggested to include clock-output-names and
> - #clock-cells.
> - - "ti,am654-sdhci-5.1", "arasan,sdhci-5.1": TI AM654 MMC PHY
> - Note: This binding has been deprecated and moved to [5].
> - - "intel,lgm-sdhci-5.1-emmc", "arasan,sdhci-5.1": Intel LGM eMMC PHY
> - For this device it is strongly suggested to include arasan,soc-ctl-syscon.
> - - "intel,lgm-sdhci-5.1-sdxc", "arasan,sdhci-5.1": Intel LGM SDXC PHY
> - For this device it is strongly suggested to include arasan,soc-ctl-syscon.
> - - "intel,keembay-sdhci-5.1-emmc", "arasan,sdhci-5.1": Intel Keem Bay eMMC
> - For this device it is strongly suggested to include arasan,soc-ctl-syscon.
> - - "intel,keembay-sdhci-5.1-sd": Intel Keem Bay SD controller
> - For this device it is strongly suggested to include arasan,soc-ctl-syscon.
> - - "intel,keembay-sdhci-5.1-sdio": Intel Keem Bay SDIO controller
> - For this device it is strongly suggested to include arasan,soc-ctl-syscon.
> -
> - [5] Documentation/devicetree/bindings/mmc/sdhci-am654.txt
> -
> - - reg: From mmc bindings: Register location and length.
> - - clocks: From clock bindings: Handles to clock inputs.
> - - clock-names: From clock bindings: Tuple including "clk_xin" and "clk_ahb"
> - - interrupts: Interrupt specifier
> -
> -Required Properties for "arasan,sdhci-5.1":
> - - phys: From PHY bindings: Phandle for the Generic PHY for arasan.
> - - phy-names: MUST be "phy_arasan".
> -
> -Optional Properties:
> - - arasan,soc-ctl-syscon: A phandle to a syscon device (see ../mfd/syscon.txt)
> - used to access core corecfg registers. Offsets of registers in this
> - syscon are determined based on the main compatible string for the device.
> - - clock-output-names: If specified, this will be the name of the card clock
> - which will be exposed by this device. Required if #clock-cells is
> - specified.
> - - #clock-cells: If specified this should be the value <0> or <1>. With this
> - property in place we will export one or two clocks representing the Card
> - Clock. These clocks are expected to be consumed by our PHY.
> - - xlnx,fails-without-test-cd: when present, the controller doesn't work when
> - the CD line is not connected properly, and the line is not connected
> - properly. Test mode can be used to force the controller to function.
> - - xlnx,int-clock-stable-broken: when present, the controller always reports
> - that the internal clock is stable even when it is not.
> -
> - - xlnx,mio-bank: When specified, this will indicate the MIO bank number in
> - which the command and data lines are configured. If not specified, driver
> - will assume this as 0.
> -
> -Example:
> - sdhci@e0100000 {
> - compatible = "arasan,sdhci-8.9a";
> - reg = <0xe0100000 0x1000>;
> - clock-names = "clk_xin", "clk_ahb";
> - clocks = <&clkc 21>, <&clkc 32>;
> - interrupt-parent = <&gic>;
> - interrupts = <0 24 4>;
> - } ;
> -
> - sdhci@e2800000 {
> - compatible = "arasan,sdhci-5.1";
> - reg = <0xe2800000 0x1000>;
> - clock-names = "clk_xin", "clk_ahb";
> - clocks = <&cru 8>, <&cru 18>;
> - interrupt-parent = <&gic>;
> - interrupts = <0 24 4>;
> - phys = <&emmc_phy>;
> - phy-names = "phy_arasan";
> - } ;
> -
> - sdhci: sdhci@fe330000 {
> - compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
> - reg = <0x0 0xfe330000 0x0 0x10000>;
> - interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
> - clock-names = "clk_xin", "clk_ahb";
> - arasan,soc-ctl-syscon = <&grf>;
> - assigned-clocks = <&cru SCLK_EMMC>;
> - assigned-clock-rates = <200000000>;
> - clock-output-names = "emmc_cardclock";
> - phys = <&emmc_phy>;
> - phy-names = "phy_arasan";
> - #clock-cells = <0>;
> - };
> -
> - sdhci: mmc@ff160000 {
> - compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
> - interrupt-parent = <&gic>;
> - interrupts = <0 48 4>;
> - reg = <0x0 0xff160000 0x0 0x1000>;
> - clocks = <&clk200>, <&clk200>;
> - clock-names = "clk_xin", "clk_ahb";
> - clock-output-names = "clk_out_sd0", "clk_in_sd0";
> - #clock-cells = <1>;
> - clk-phase-sd-hs = <63>, <72>;
> - };
> -
> - sdhci: mmc@f1040000 {
> - compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a";
> - interrupt-parent = <&gic>;
> - interrupts = <0 126 4>;
> - reg = <0x0 0xf1040000 0x0 0x10000>;
> - clocks = <&clk200>, <&clk200>;
> - clock-names = "clk_xin", "clk_ahb";
> - clock-output-names = "clk_out_sd0", "clk_in_sd0";
> - #clock-cells = <1>;
> - clk-phase-sd-hs = <132>, <60>;
> - };
> -
> - emmc: sdhci@ec700000 {
> - compatible = "intel,lgm-sdhci-5.1-emmc", "arasan,sdhci-5.1";
> - reg = <0xec700000 0x300>;
> - interrupt-parent = <&ioapic1>;
> - interrupts = <44 1>;
> - clocks = <&cgu0 LGM_CLK_EMMC5>, <&cgu0 LGM_CLK_NGI>,
> - <&cgu0 LGM_GCLK_EMMC>;
> - clock-names = "clk_xin", "clk_ahb", "gate";
> - clock-output-names = "emmc_cardclock";
> - #clock-cells = <0>;
> - phys = <&emmc_phy>;
> - phy-names = "phy_arasan";
> - arasan,soc-ctl-syscon = <&sysconf>;
> - };
> -
> - sdxc: sdhci@ec600000 {
> - compatible = "arasan,sdhci-5.1", "intel,lgm-sdhci-5.1-sdxc";
> - reg = <0xec600000 0x300>;
> - interrupt-parent = <&ioapic1>;
> - interrupts = <43 1>;
> - clocks = <&cgu0 LGM_CLK_SDIO>, <&cgu0 LGM_CLK_NGI>,
> - <&cgu0 LGM_GCLK_SDXC>;
> - clock-names = "clk_xin", "clk_ahb", "gate";
> - clock-output-names = "sdxc_cardclock";
> - #clock-cells = <0>;
> - phys = <&sdxc_phy>;
> - phy-names = "phy_arasan";
> - arasan,soc-ctl-syscon = <&sysconf>;
> - };
> -
> - mmc: mmc@33000000 {
> - compatible = "intel,keembay-sdhci-5.1-emmc", "arasan,sdhci-5.1";
> - interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
> - reg = <0x0 0x33000000 0x0 0x300>;
> - clock-names = "clk_xin", "clk_ahb";
> - clocks = <&scmi_clk KEEM_BAY_PSS_AUX_EMMC>,
> - <&scmi_clk KEEM_BAY_PSS_EMMC>;
> - phys = <&emmc_phy>;
> - phy-names = "phy_arasan";
> - assigned-clocks = <&scmi_clk KEEM_BAY_PSS_AUX_EMMC>;
> - assigned-clock-rates = <200000000>;
> - clock-output-names = "emmc_cardclock";
> - #clock-cells = <0>;
> - arasan,soc-ctl-syscon = <&mmc_phy_syscon>;
> - };
> -
> - sd0: mmc@31000000 {
> - compatible = "intel,keembay-sdhci-5.1-sd";
> - interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
> - reg = <0x0 0x31000000 0x0 0x300>;
> - clock-names = "clk_xin", "clk_ahb";
> - clocks = <&scmi_clk KEEM_BAY_PSS_AUX_SD0>,
> - <&scmi_clk KEEM_BAY_PSS_SD0>;
> - arasan,soc-ctl-syscon = <&sd0_phy_syscon>;
> - };
> -
> - sd1: mmc@32000000 {
> - compatible = "intel,keembay-sdhci-5.1-sdio";
> - interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
> - reg = <0x0 0x32000000 0x0 0x300>;
> - clock-names = "clk_xin", "clk_ahb";
> - clocks = <&scmi_clk KEEM_BAY_PSS_AUX_SD1>,
> - <&scmi_clk KEEM_BAY_PSS_SD1>;
> - arasan,soc-ctl-syscon = <&sd1_phy_syscon>;
> - };
> diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml b/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml
> new file mode 100644
> index 000000000000..927e2f13958b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml
> @@ -0,0 +1,293 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/mmc/arasan,sdhci.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: Device Tree Bindings for the Arasan SDHCI Controller
> +
> +allOf:
> + - $ref: "mmc-controller.yaml#"
> +
> +maintainers:
> + - Adrian Hunter <adrian.hunter@intel.com>
> +
> +properties:
> + compatible:
> + oneOf:
> + - const: arasan,sdhci-8.9a # generic Arasan SDHCI 8.9a PHY
> + - const: arasan,sdhci-4.9a # generic Arasan SDHCI 4.9a PHY
> + - const: arasan,sdhci-5.1 # generic Arasan SDHCI 5.1 PHY
> + - items:
> + - const: rockchip,rk3399-sdhci-5.1 # rk3399 eMMC PHY
> + - const: arasan,sdhci-5.1
> + description: |
> + For this device it is strongly suggested to include
> + arasan,soc-ctl-syscon.
> + - items:
> + - const: xlnx,zynqmp-8.9a # ZynqMP SDHCI 8.9a PHY
> + - const: arasan,sdhci-8.9a
> + description: |
> + For this device it is strongly suggested to include
> + clock-output-names and '#clock-cells'.
> + - items:
> + - const: xlnx,versal-8.9a # Versal SDHCI 8.9a PHY
> + - const: arasan,sdhci-8.9a
> + description: |
> + For this device it is strongly suggested to include
> + clock-output-names and '#clock-cells'.
> + - items:
> + - const: intel,lgm-sdhci-5.1-emmc # Intel LGM eMMC PHY
> + - const: arasan,sdhci-5.1
> + description: |
> + For this device it is strongly suggested to include
> + arasan,soc-ctl-syscon.
> + - items:
> + - const: intel,lgm-sdhci-5.1-sdxc # Intel LGM SDXC PHY
> + - const: arasan,sdhci-5.1
> + description: |
> + For this device it is strongly suggested to include
> + arasan,soc-ctl-syscon.
> + - items:
> + - const: intel,keembay-sdhci-5.1-emmc # Intel Keem Bay eMMC PHY
> + - const: arasan,sdhci-5.1
> + description: |
> + For this device it is strongly suggested to include
> + arasan,soc-ctl-syscon.
> + - const: intel,keembay-sdhci-5.1-sd # Intel Keem Bay SD controller
> + description: |
> + For this device it is strongly suggested to include
> + arasan,soc-ctl-syscon.
> + - const: intel,keembay-sdhci-5.1-sdio # Intel Keem Bay SDIO controller
> + description: |
> + For this device it is strongly suggested to include
> + arasan,soc-ctl-syscon.
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + minItems: 2
> + maxItems: 3
> +
> + clock-names:
> + minItems: 2
> + items:
> + - const: clk_xin
> + - const: clk_ahb
> + - const: gate
> +
> + interrupts:
> + maxItems: 1
> +
> + phys:
> + maxItems: 1
> +
> + phy-names:
> + const: phy_arasan
> +
> + arasan,soc-ctl-syscon:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description: |
> + A phandle to a syscon device (see ../mfd/syscon.txt) used to access
> + core corecfg registers. Offsets of registers in this syscon are
> + determined based on the main compatible string for the device.
> +
> + clock-output-names:
> + description: |
> + If specified, this will be the name of the card clock which will
> + be exposed by this device. Required if '#clock-cells' is specified.
> +
> + '#clock-cells':
> + enum: [0, 1]
> + description: |
> + With this property in place we will export one or two clocks
> + representing the Card Clock. These clocks are expected to be
> + consumed by our PHY.
> +
> + xlnx,fails-without-test-cd:
> + $ref: /schemas/types.yaml#/definitions/flag
> + description: |
> + When present, the controller doesn't work when the CD line is not
> + connected properly, and the line is not connected properly.
> + Test mode can be used to force the controller to function.
> +
> + xlnx,int-clock-stable-broken:
> + $ref: /schemas/types.yaml#/definitions/flag
> + description: |
> + When present, the controller always reports that the internal clock
> + is stable even when it is not.
> +
> + xlnx,mio-bank:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: |
> + When specified, this will indicate the MIO bank number in which
> + the command and data lines are configured. If not specified, driver
> + will assume this as 0.
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - clocks
> + - clock-names
> +
> +if:
> + properties:
> + compatible:
> + contains:
> + const: arasan,sdhci-5.1
> +then:
> + required:
> + - phys
> + - phy-names
> +
> +examples:
> + - |
> + mmc@e0100000 {
> + compatible = "arasan,sdhci-8.9a";
> + reg = <0xe0100000 0x1000>;
> + clock-names = "clk_xin", "clk_ahb";
> + clocks = <&clkc 21>, <&clkc 32>;
> + interrupt-parent = <&gic>;
> + interrupts = <0 24 4>;
> + };
> +
> + - |
> + mmc@e2800000 {
> + compatible = "arasan,sdhci-5.1";
> + reg = <0xe2800000 0x1000>;
> + clock-names = "clk_xin", "clk_ahb";
> + clocks = <&cru 8>, <&cru 18>;
> + interrupt-parent = <&gic>;
> + interrupts = <0 24 4>;
> + phys = <&emmc_phy>;
> + phy-names = "phy_arasan";
> + };
> +
> + - |
> + #include <dt-bindings/clock/rk3399-cru.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/interrupt-controller/irq.h>
> + mmc@fe330000 {
> + compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
> + reg = <0x0 0xfe330000 0x0 0x10000>;
> + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
> + clock-names = "clk_xin", "clk_ahb";
> + arasan,soc-ctl-syscon = <&grf>;
> + assigned-clocks = <&cru SCLK_EMMC>;
> + assigned-clock-rates = <200000000>;
> + clock-output-names = "emmc_cardclock";
> + phys = <&emmc_phy>;
> + phy-names = "phy_arasan";
> + #clock-cells = <0>;
> + };
> +
> + - |
> + mmc@ff160000 {
> + compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
> + interrupt-parent = <&gic>;
> + interrupts = <0 48 4>;
> + reg = <0x0 0xff160000 0x0 0x1000>;
> + clocks = <&clk200>, <&clk200>;
> + clock-names = "clk_xin", "clk_ahb";
> + clock-output-names = "clk_out_sd0", "clk_in_sd0";
> + #clock-cells = <1>;
> + clk-phase-sd-hs = <63 72>;
> + };
> +
> + - |
> + mmc@f1040000 {
> + compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a";
> + interrupt-parent = <&gic>;
> + interrupts = <0 126 4>;
> + reg = <0x0 0xf1040000 0x0 0x10000>;
> + clocks = <&clk200>, <&clk200>;
> + clock-names = "clk_xin", "clk_ahb";
> + clock-output-names = "clk_out_sd0", "clk_in_sd0";
> + #clock-cells = <1>;
> + clk-phase-sd-hs = <132>, <60>;
> + };
> +
> + - |
> + #define LGM_CLK_EMMC5
> + #define LGM_CLK_NGI
> + #define LGM_GCLK_EMMC
> + mmc@ec700000 {
> + compatible = "intel,lgm-sdhci-5.1-emmc", "arasan,sdhci-5.1";
> + reg = <0xec700000 0x300>;
> + interrupt-parent = <&ioapic1>;
> + interrupts = <44 1>;
> + clocks = <&cgu0 LGM_CLK_EMMC5>, <&cgu0 LGM_CLK_NGI>,
> + <&cgu0 LGM_GCLK_EMMC>;
> + clock-names = "clk_xin", "clk_ahb", "gate";
> + clock-output-names = "emmc_cardclock";
> + #clock-cells = <0>;
> + phys = <&emmc_phy>;
> + phy-names = "phy_arasan";
> + arasan,soc-ctl-syscon = <&sysconf>;
> + };
> +
> + - |
> + #define LGM_CLK_SDIO
> + #define LGM_GCLK_SDXC
> + mmc@ec600000 {
> + compatible = "intel,lgm-sdhci-5.1-sdxc", "arasan,sdhci-5.1";
> + reg = <0xec600000 0x300>;
> + interrupt-parent = <&ioapic1>;
> + interrupts = <43 1>;
> + clocks = <&cgu0 LGM_CLK_SDIO>, <&cgu0 LGM_CLK_NGI>,
> + <&cgu0 LGM_GCLK_SDXC>;
> + clock-names = "clk_xin", "clk_ahb", "gate";
> + clock-output-names = "sdxc_cardclock";
> + #clock-cells = <0>;
> + phys = <&sdxc_phy>;
> + phy-names = "phy_arasan";
> + arasan,soc-ctl-syscon = <&sysconf>;
> + };
> +
> + - |
> + #define KEEM_BAY_PSS_AUX_EMMC
> + #define KEEM_BAY_PSS_EMMC
> + mmc@33000000 {
> + compatible = "intel,keembay-sdhci-5.1-emmc", "arasan,sdhci-5.1";
> + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x0 0x33000000 0x0 0x300>;
> + clock-names = "clk_xin", "clk_ahb";
> + clocks = <&scmi_clk KEEM_BAY_PSS_AUX_EMMC>,
> + <&scmi_clk KEEM_BAY_PSS_EMMC>;
> + phys = <&emmc_phy>;
> + phy-names = "phy_arasan";
> + assigned-clocks = <&scmi_clk KEEM_BAY_PSS_AUX_EMMC>;
> + assigned-clock-rates = <200000000>;
> + clock-output-names = "emmc_cardclock";
> + #clock-cells = <0>;
> + arasan,soc-ctl-syscon = <&mmc_phy_syscon>;
> + };
> +
> + - |
> + #define KEEM_BAY_PSS_AUX_SD0
> + #define KEEM_BAY_PSS_SD0
> + mmc@31000000 {
> + compatible = "intel,keembay-sdhci-5.1-sd";
> + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x0 0x31000000 0x0 0x300>;
> + clock-names = "clk_xin", "clk_ahb";
> + clocks = <&scmi_clk KEEM_BAY_PSS_AUX_SD0>,
> + <&scmi_clk KEEM_BAY_PSS_SD0>;
> + arasan,soc-ctl-syscon = <&sd0_phy_syscon>;
> + };
> +
> + - |
> + #define KEEM_BAY_PSS_AUX_SD1
> + #define KEEM_BAY_PSS_SD1
> + mmc@32000000 {
> + compatible = "intel,keembay-sdhci-5.1-sdio";
> + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x0 0x32000000 0x0 0x300>;
> + clock-names = "clk_xin", "clk_ahb";
> + clocks = <&scmi_clk KEEM_BAY_PSS_AUX_SD1>,
> + <&scmi_clk KEEM_BAY_PSS_SD1>;
> + arasan,soc-ctl-syscon = <&sd1_phy_syscon>;
> + };
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2 3/3] dt-bindings: mmc: convert arasan sdhci bindings to yaml
2020-05-26 6:27 ` [PATCH v2 3/3] dt-bindings: mmc: convert arasan sdhci bindings to yaml Wan Ahmad Zainie
2020-05-28 10:14 ` Ulf Hansson
@ 2020-05-29 17:25 ` Rob Herring
2020-06-08 8:58 ` Wan Mohamad, Wan Ahmad Zainie
1 sibling, 1 reply; 9+ messages in thread
From: Rob Herring @ 2020-05-29 17:25 UTC (permalink / raw)
To: Wan Ahmad Zainie
Cc: ulf.hansson, adrian.hunter, michal.simek, linux-mmc, devicetree
On Tue, May 26, 2020 at 02:27:58PM +0800, Wan Ahmad Zainie wrote:
> Convert arasan,sdhci.txt file to yaml. The new file arasan,sdhci.yaml
> will inherit properties from mmc-controller.yaml. 'sdhci' is no longer
> a valid name for node and should be changed to 'mmc'.
>
> Suggested-by: Ulf Hansson <ulf.hansson@linaro.org>
> Signed-off-by: Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
> ---
> .../devicetree/bindings/mmc/arasan,sdhci.txt | 192 ------------
> .../devicetree/bindings/mmc/arasan,sdhci.yaml | 293 ++++++++++++++++++
> 2 files changed, 293 insertions(+), 192 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
> create mode 100644 Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml
> diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml b/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml
> new file mode 100644
> index 000000000000..927e2f13958b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml
> @@ -0,0 +1,293 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/mmc/arasan,sdhci.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: Device Tree Bindings for the Arasan SDHCI Controller
> +
> +allOf:
> + - $ref: "mmc-controller.yaml#"
> +
> +maintainers:
> + - Adrian Hunter <adrian.hunter@intel.com>
> +
> +properties:
> + compatible:
> + oneOf:
> + - const: arasan,sdhci-8.9a # generic Arasan SDHCI 8.9a PHY
> + - const: arasan,sdhci-4.9a # generic Arasan SDHCI 4.9a PHY
> + - const: arasan,sdhci-5.1 # generic Arasan SDHCI 5.1 PHY
> + - items:
> + - const: rockchip,rk3399-sdhci-5.1 # rk3399 eMMC PHY
> + - const: arasan,sdhci-5.1
> + description: |
Can drop '|' as formatting isn't important.
> + For this device it is strongly suggested to include
> + arasan,soc-ctl-syscon.
> + - items:
> + - const: xlnx,zynqmp-8.9a # ZynqMP SDHCI 8.9a PHY
> + - const: arasan,sdhci-8.9a
> + description: |
> + For this device it is strongly suggested to include
> + clock-output-names and '#clock-cells'.
Sounds like a constraint. It's either optional or required though. There
is no suggested.
> + - items:
> + - const: xlnx,versal-8.9a # Versal SDHCI 8.9a PHY
> + - const: arasan,sdhci-8.9a
> + description: |
> + For this device it is strongly suggested to include
> + clock-output-names and '#clock-cells'.
> + - items:
> + - const: intel,lgm-sdhci-5.1-emmc # Intel LGM eMMC PHY
> + - const: arasan,sdhci-5.1
> + description: |
> + For this device it is strongly suggested to include
> + arasan,soc-ctl-syscon.
> + - items:
> + - const: intel,lgm-sdhci-5.1-sdxc # Intel LGM SDXC PHY
> + - const: arasan,sdhci-5.1
> + description: |
> + For this device it is strongly suggested to include
> + arasan,soc-ctl-syscon.
> + - items:
> + - const: intel,keembay-sdhci-5.1-emmc # Intel Keem Bay eMMC PHY
> + - const: arasan,sdhci-5.1
> + description: |
> + For this device it is strongly suggested to include
> + arasan,soc-ctl-syscon.
> + - const: intel,keembay-sdhci-5.1-sd # Intel Keem Bay SD controller
> + description: |
> + For this device it is strongly suggested to include
> + arasan,soc-ctl-syscon.
> + - const: intel,keembay-sdhci-5.1-sdio # Intel Keem Bay SDIO controller
> + description: |
> + For this device it is strongly suggested to include
> + arasan,soc-ctl-syscon.
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + minItems: 2
> + maxItems: 3
> +
> + clock-names:
> + minItems: 2
> + items:
> + - const: clk_xin
> + - const: clk_ahb
> + - const: gate
> +
> + interrupts:
> + maxItems: 1
> +
> + phys:
> + maxItems: 1
> +
> + phy-names:
> + const: phy_arasan
> +
> + arasan,soc-ctl-syscon:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description: |
> + A phandle to a syscon device (see ../mfd/syscon.txt) used to access
> + core corecfg registers. Offsets of registers in this syscon are
> + determined based on the main compatible string for the device.
> +
> + clock-output-names:
> + description: |
> + If specified, this will be the name of the card clock which will
> + be exposed by this device. Required if '#clock-cells' is specified.
The last sentence can be a 'dependencies' schema.
Are there defined names for this?
> +
> + '#clock-cells':
> + enum: [0, 1]
> + description: |
> + With this property in place we will export one or two clocks
> + representing the Card Clock. These clocks are expected to be
> + consumed by our PHY.
> +
> + xlnx,fails-without-test-cd:
> + $ref: /schemas/types.yaml#/definitions/flag
> + description: |
> + When present, the controller doesn't work when the CD line is not
> + connected properly, and the line is not connected properly.
> + Test mode can be used to force the controller to function.
> +
> + xlnx,int-clock-stable-broken:
> + $ref: /schemas/types.yaml#/definitions/flag
> + description: |
> + When present, the controller always reports that the internal clock
> + is stable even when it is not.
> +
> + xlnx,mio-bank:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: |
> + When specified, this will indicate the MIO bank number in which
> + the command and data lines are configured. If not specified, driver
> + will assume this as 0.
default: 0
Is there a range of valid values?
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - clocks
> + - clock-names
> +
> +if:
> + properties:
> + compatible:
> + contains:
> + const: arasan,sdhci-5.1
> +then:
> + required:
> + - phys
> + - phy-names
Add: unevaluatedProperties: false
> +
> +examples:
> + - |
> + mmc@e0100000 {
> + compatible = "arasan,sdhci-8.9a";
> + reg = <0xe0100000 0x1000>;
> + clock-names = "clk_xin", "clk_ahb";
> + clocks = <&clkc 21>, <&clkc 32>;
> + interrupt-parent = <&gic>;
> + interrupts = <0 24 4>;
> + };
> +
> + - |
> + mmc@e2800000 {
> + compatible = "arasan,sdhci-5.1";
> + reg = <0xe2800000 0x1000>;
> + clock-names = "clk_xin", "clk_ahb";
> + clocks = <&cru 8>, <&cru 18>;
> + interrupt-parent = <&gic>;
> + interrupts = <0 24 4>;
> + phys = <&emmc_phy>;
> + phy-names = "phy_arasan";
> + };
> +
> + - |
> + #include <dt-bindings/clock/rk3399-cru.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/interrupt-controller/irq.h>
> + mmc@fe330000 {
> + compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
> + reg = <0x0 0xfe330000 0x0 0x10000>;
Examples default to a single cell each for size and address.
> + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
> + clock-names = "clk_xin", "clk_ahb";
> + arasan,soc-ctl-syscon = <&grf>;
> + assigned-clocks = <&cru SCLK_EMMC>;
> + assigned-clock-rates = <200000000>;
> + clock-output-names = "emmc_cardclock";
> + phys = <&emmc_phy>;
> + phy-names = "phy_arasan";
> + #clock-cells = <0>;
> + };
> +
> + - |
> + mmc@ff160000 {
> + compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
> + interrupt-parent = <&gic>;
> + interrupts = <0 48 4>;
> + reg = <0x0 0xff160000 0x0 0x1000>;
Same here.
> + clocks = <&clk200>, <&clk200>;
> + clock-names = "clk_xin", "clk_ahb";
> + clock-output-names = "clk_out_sd0", "clk_in_sd0";
> + #clock-cells = <1>;
> + clk-phase-sd-hs = <63 72>;
> + };
> +
> + - |
> + mmc@f1040000 {
> + compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a";
> + interrupt-parent = <&gic>;
> + interrupts = <0 126 4>;
> + reg = <0x0 0xf1040000 0x0 0x10000>;
> + clocks = <&clk200>, <&clk200>;
> + clock-names = "clk_xin", "clk_ahb";
> + clock-output-names = "clk_out_sd0", "clk_in_sd0";
> + #clock-cells = <1>;
> + clk-phase-sd-hs = <132>, <60>;
> + };
> +
> + - |
> + #define LGM_CLK_EMMC5
> + #define LGM_CLK_NGI
> + #define LGM_GCLK_EMMC
> + mmc@ec700000 {
> + compatible = "intel,lgm-sdhci-5.1-emmc", "arasan,sdhci-5.1";
> + reg = <0xec700000 0x300>;
> + interrupt-parent = <&ioapic1>;
> + interrupts = <44 1>;
> + clocks = <&cgu0 LGM_CLK_EMMC5>, <&cgu0 LGM_CLK_NGI>,
> + <&cgu0 LGM_GCLK_EMMC>;
> + clock-names = "clk_xin", "clk_ahb", "gate";
> + clock-output-names = "emmc_cardclock";
> + #clock-cells = <0>;
> + phys = <&emmc_phy>;
> + phy-names = "phy_arasan";
> + arasan,soc-ctl-syscon = <&sysconf>;
> + };
> +
> + - |
> + #define LGM_CLK_SDIO
> + #define LGM_GCLK_SDXC
> + mmc@ec600000 {
> + compatible = "intel,lgm-sdhci-5.1-sdxc", "arasan,sdhci-5.1";
> + reg = <0xec600000 0x300>;
> + interrupt-parent = <&ioapic1>;
> + interrupts = <43 1>;
> + clocks = <&cgu0 LGM_CLK_SDIO>, <&cgu0 LGM_CLK_NGI>,
> + <&cgu0 LGM_GCLK_SDXC>;
> + clock-names = "clk_xin", "clk_ahb", "gate";
> + clock-output-names = "sdxc_cardclock";
> + #clock-cells = <0>;
> + phys = <&sdxc_phy>;
> + phy-names = "phy_arasan";
> + arasan,soc-ctl-syscon = <&sysconf>;
> + };
> +
> + - |
> + #define KEEM_BAY_PSS_AUX_EMMC
> + #define KEEM_BAY_PSS_EMMC
> + mmc@33000000 {
> + compatible = "intel,keembay-sdhci-5.1-emmc", "arasan,sdhci-5.1";
> + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x0 0x33000000 0x0 0x300>;
> + clock-names = "clk_xin", "clk_ahb";
> + clocks = <&scmi_clk KEEM_BAY_PSS_AUX_EMMC>,
> + <&scmi_clk KEEM_BAY_PSS_EMMC>;
> + phys = <&emmc_phy>;
> + phy-names = "phy_arasan";
> + assigned-clocks = <&scmi_clk KEEM_BAY_PSS_AUX_EMMC>;
> + assigned-clock-rates = <200000000>;
> + clock-output-names = "emmc_cardclock";
> + #clock-cells = <0>;
> + arasan,soc-ctl-syscon = <&mmc_phy_syscon>;
> + };
> +
> + - |
> + #define KEEM_BAY_PSS_AUX_SD0
> + #define KEEM_BAY_PSS_SD0
> + mmc@31000000 {
> + compatible = "intel,keembay-sdhci-5.1-sd";
> + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x0 0x31000000 0x0 0x300>;
> + clock-names = "clk_xin", "clk_ahb";
> + clocks = <&scmi_clk KEEM_BAY_PSS_AUX_SD0>,
> + <&scmi_clk KEEM_BAY_PSS_SD0>;
> + arasan,soc-ctl-syscon = <&sd0_phy_syscon>;
> + };
> +
> + - |
> + #define KEEM_BAY_PSS_AUX_SD1
> + #define KEEM_BAY_PSS_SD1
> + mmc@32000000 {
> + compatible = "intel,keembay-sdhci-5.1-sdio";
> + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x0 0x32000000 0x0 0x300>;
> + clock-names = "clk_xin", "clk_ahb";
> + clocks = <&scmi_clk KEEM_BAY_PSS_AUX_SD1>,
> + <&scmi_clk KEEM_BAY_PSS_SD1>;
> + arasan,soc-ctl-syscon = <&sd1_phy_syscon>;
> + };
Really need 3 Keem Bay examples?
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 9+ messages in thread
* RE: [PATCH v2 3/3] dt-bindings: mmc: convert arasan sdhci bindings to yaml
2020-05-29 17:25 ` Rob Herring
@ 2020-06-08 8:58 ` Wan Mohamad, Wan Ahmad Zainie
0 siblings, 0 replies; 9+ messages in thread
From: Wan Mohamad, Wan Ahmad Zainie @ 2020-06-08 8:58 UTC (permalink / raw)
To: Rob Herring
Cc: ulf.hansson, Hunter, Adrian, michal.simek, linux-mmc, devicetree
> -----Original Message-----
> From: Rob Herring <robh@kernel.org>
> Sent: Saturday, May 30, 2020 1:26 AM
> To: Wan Mohamad, Wan Ahmad Zainie
> <wan.ahmad.zainie.wan.mohamad@intel.com>
> Cc: ulf.hansson@linaro.org; Hunter, Adrian <adrian.hunter@intel.com>;
> michal.simek@xilinx.com; linux-mmc@vger.kernel.org;
> devicetree@vger.kernel.org
> Subject: Re: [PATCH v2 3/3] dt-bindings: mmc: convert arasan sdhci bindings
> to yaml
>
> On Tue, May 26, 2020 at 02:27:58PM +0800, Wan Ahmad Zainie wrote:
> > Convert arasan,sdhci.txt file to yaml. The new file arasan,sdhci.yaml
> > will inherit properties from mmc-controller.yaml. 'sdhci' is no longer
> > a valid name for node and should be changed to 'mmc'.
> >
> > Suggested-by: Ulf Hansson <ulf.hansson@linaro.org>
> > Signed-off-by: Wan Ahmad Zainie
> <wan.ahmad.zainie.wan.mohamad@intel.com>
> > ---
> > .../devicetree/bindings/mmc/arasan,sdhci.txt | 192 ------------
> > .../devicetree/bindings/mmc/arasan,sdhci.yaml | 293
> ++++++++++++++++++
> > 2 files changed, 293 insertions(+), 192 deletions(-)
> > delete mode 100644
> Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
> > create mode 100644
> Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml
>
>
> > diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml
> b/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml
> > new file mode 100644
> > index 000000000000..927e2f13958b
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml
> > @@ -0,0 +1,293 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: "http://devicetree.org/schemas/mmc/arasan,sdhci.yaml#"
> > +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> > +
> > +title: Device Tree Bindings for the Arasan SDHCI Controller
> > +
> > +allOf:
> > + - $ref: "mmc-controller.yaml#"
> > +
> > +maintainers:
> > + - Adrian Hunter <adrian.hunter@intel.com>
> > +
> > +properties:
> > + compatible:
> > + oneOf:
> > + - const: arasan,sdhci-8.9a # generic Arasan SDHCI 8.9a PHY
> > + - const: arasan,sdhci-4.9a # generic Arasan SDHCI 4.9a PHY
> > + - const: arasan,sdhci-5.1 # generic Arasan SDHCI 5.1 PHY
> > + - items:
> > + - const: rockchip,rk3399-sdhci-5.1 # rk3399 eMMC PHY
> > + - const: arasan,sdhci-5.1
> > + description: |
>
> Can drop '|' as formatting isn't important.
I will drop in v3.
>
> > + For this device it is strongly suggested to include
> > + arasan,soc-ctl-syscon.
> > + - items:
> > + - const: xlnx,zynqmp-8.9a # ZynqMP SDHCI 8.9a PHY
> > + - const: arasan,sdhci-8.9a
> > + description: |
> > + For this device it is strongly suggested to include
> > + clock-output-names and '#clock-cells'.
>
> Sounds like a constraint. It's either optional or required though. There
> is no suggested.
>
> > + - items:
> > + - const: xlnx,versal-8.9a # Versal SDHCI 8.9a PHY
> > + - const: arasan,sdhci-8.9a
> > + description: |
> > + For this device it is strongly suggested to include
> > + clock-output-names and '#clock-cells'.
> > + - items:
> > + - const: intel,lgm-sdhci-5.1-emmc # Intel LGM eMMC PHY
> > + - const: arasan,sdhci-5.1
> > + description: |
> > + For this device it is strongly suggested to include
> > + arasan,soc-ctl-syscon.
> > + - items:
> > + - const: intel,lgm-sdhci-5.1-sdxc # Intel LGM SDXC PHY
> > + - const: arasan,sdhci-5.1
> > + description: |
> > + For this device it is strongly suggested to include
> > + arasan,soc-ctl-syscon.
> > + - items:
> > + - const: intel,keembay-sdhci-5.1-emmc # Intel Keem Bay eMMC PHY
> > + - const: arasan,sdhci-5.1
> > + description: |
> > + For this device it is strongly suggested to include
> > + arasan,soc-ctl-syscon.
> > + - const: intel,keembay-sdhci-5.1-sd # Intel Keem Bay SD controller
> > + description: |
> > + For this device it is strongly suggested to include
> > + arasan,soc-ctl-syscon.
> > + - const: intel,keembay-sdhci-5.1-sdio # Intel Keem Bay SDIO
> controller
> > + description: |
> > + For this device it is strongly suggested to include
> > + arasan,soc-ctl-syscon.
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + clocks:
> > + minItems: 2
> > + maxItems: 3
> > +
> > + clock-names:
> > + minItems: 2
> > + items:
> > + - const: clk_xin
> > + - const: clk_ahb
> > + - const: gate
> > +
> > + interrupts:
> > + maxItems: 1
> > +
> > + phys:
> > + maxItems: 1
> > +
> > + phy-names:
> > + const: phy_arasan
> > +
> > + arasan,soc-ctl-syscon:
> > + $ref: /schemas/types.yaml#/definitions/phandle
> > + description: |
> > + A phandle to a syscon device (see ../mfd/syscon.txt) used to access
> > + core corecfg registers. Offsets of registers in this syscon are
> > + determined based on the main compatible string for the device.
> > +
> > + clock-output-names:
> > + description: |
> > + If specified, this will be the name of the card clock which will
> > + be exposed by this device. Required if '#clock-cells' is specified.
>
> The last sentence can be a 'dependencies' schema.
I will add this in dependencies schema in v3.
>
> Are there defined names for this?
From the source code, only xlnx,... uses constant names i.e. clk_in_sd0 and
clk_in_sd1. For the rest, any name can be used.
>
> > +
> > + '#clock-cells':
> > + enum: [0, 1]
> > + description: |
> > + With this property in place we will export one or two clocks
> > + representing the Card Clock. These clocks are expected to be
> > + consumed by our PHY.
> > +
> > + xlnx,fails-without-test-cd:
> > + $ref: /schemas/types.yaml#/definitions/flag
> > + description: |
> > + When present, the controller doesn't work when the CD line is not
> > + connected properly, and the line is not connected properly.
> > + Test mode can be used to force the controller to function.
> > +
> > + xlnx,int-clock-stable-broken:
> > + $ref: /schemas/types.yaml#/definitions/flag
> > + description: |
> > + When present, the controller always reports that the internal clock
> > + is stable even when it is not.
> > +
> > + xlnx,mio-bank:
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + description: |
> > + When specified, this will indicate the MIO bank number in which
> > + the command and data lines are configured. If not specified, driver
> > + will assume this as 0.
>
> default: 0
I will add in v3.
>
> Is there a range of valid values?
From the source code, the valid value is 0 and 2.
I will add enum: [0, 2] in v3.
>
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - interrupts
> > + - clocks
> > + - clock-names
> > +
> > +if:
> > + properties:
> > + compatible:
> > + contains:
> > + const: arasan,sdhci-5.1
> > +then:
> > + required:
> > + - phys
> > + - phy-names
>
> Add: unevaluatedProperties: false
I will add in v3.
>
> > +
> > +examples:
> > + - |
> > + mmc@e0100000 {
> > + compatible = "arasan,sdhci-8.9a";
> > + reg = <0xe0100000 0x1000>;
> > + clock-names = "clk_xin", "clk_ahb";
> > + clocks = <&clkc 21>, <&clkc 32>;
> > + interrupt-parent = <&gic>;
> > + interrupts = <0 24 4>;
> > + };
> > +
> > + - |
> > + mmc@e2800000 {
> > + compatible = "arasan,sdhci-5.1";
> > + reg = <0xe2800000 0x1000>;
> > + clock-names = "clk_xin", "clk_ahb";
> > + clocks = <&cru 8>, <&cru 18>;
> > + interrupt-parent = <&gic>;
> > + interrupts = <0 24 4>;
> > + phys = <&emmc_phy>;
> > + phy-names = "phy_arasan";
> > + };
> > +
> > + - |
> > + #include <dt-bindings/clock/rk3399-cru.h>
> > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > + #include <dt-bindings/interrupt-controller/irq.h>
> > + mmc@fe330000 {
> > + compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
> > + reg = <0x0 0xfe330000 0x0 0x10000>;
>
> Examples default to a single cell each for size and address.
I will modify in v3.
>
> > + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
> > + clock-names = "clk_xin", "clk_ahb";
> > + arasan,soc-ctl-syscon = <&grf>;
> > + assigned-clocks = <&cru SCLK_EMMC>;
> > + assigned-clock-rates = <200000000>;
> > + clock-output-names = "emmc_cardclock";
> > + phys = <&emmc_phy>;
> > + phy-names = "phy_arasan";
> > + #clock-cells = <0>;
> > + };
> > +
> > + - |
> > + mmc@ff160000 {
> > + compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
> > + interrupt-parent = <&gic>;
> > + interrupts = <0 48 4>;
> > + reg = <0x0 0xff160000 0x0 0x1000>;
>
> Same here.
>
> > + clocks = <&clk200>, <&clk200>;
> > + clock-names = "clk_xin", "clk_ahb";
> > + clock-output-names = "clk_out_sd0", "clk_in_sd0";
> > + #clock-cells = <1>;
> > + clk-phase-sd-hs = <63 72>;
> > + };
> > +
> > + - |
> > + mmc@f1040000 {
> > + compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a";
> > + interrupt-parent = <&gic>;
> > + interrupts = <0 126 4>;
> > + reg = <0x0 0xf1040000 0x0 0x10000>;
> > + clocks = <&clk200>, <&clk200>;
> > + clock-names = "clk_xin", "clk_ahb";
> > + clock-output-names = "clk_out_sd0", "clk_in_sd0";
> > + #clock-cells = <1>;
> > + clk-phase-sd-hs = <132>, <60>;
> > + };
> > +
> > + - |
> > + #define LGM_CLK_EMMC5
> > + #define LGM_CLK_NGI
> > + #define LGM_GCLK_EMMC
> > + mmc@ec700000 {
> > + compatible = "intel,lgm-sdhci-5.1-emmc", "arasan,sdhci-5.1";
> > + reg = <0xec700000 0x300>;
> > + interrupt-parent = <&ioapic1>;
> > + interrupts = <44 1>;
> > + clocks = <&cgu0 LGM_CLK_EMMC5>, <&cgu0 LGM_CLK_NGI>,
> > + <&cgu0 LGM_GCLK_EMMC>;
> > + clock-names = "clk_xin", "clk_ahb", "gate";
> > + clock-output-names = "emmc_cardclock";
> > + #clock-cells = <0>;
> > + phys = <&emmc_phy>;
> > + phy-names = "phy_arasan";
> > + arasan,soc-ctl-syscon = <&sysconf>;
> > + };
> > +
> > + - |
> > + #define LGM_CLK_SDIO
> > + #define LGM_GCLK_SDXC
> > + mmc@ec600000 {
> > + compatible = "intel,lgm-sdhci-5.1-sdxc", "arasan,sdhci-5.1";
> > + reg = <0xec600000 0x300>;
> > + interrupt-parent = <&ioapic1>;
> > + interrupts = <43 1>;
> > + clocks = <&cgu0 LGM_CLK_SDIO>, <&cgu0 LGM_CLK_NGI>,
> > + <&cgu0 LGM_GCLK_SDXC>;
> > + clock-names = "clk_xin", "clk_ahb", "gate";
> > + clock-output-names = "sdxc_cardclock";
> > + #clock-cells = <0>;
> > + phys = <&sdxc_phy>;
> > + phy-names = "phy_arasan";
> > + arasan,soc-ctl-syscon = <&sysconf>;
> > + };
> > +
> > + - |
> > + #define KEEM_BAY_PSS_AUX_EMMC
> > + #define KEEM_BAY_PSS_EMMC
> > + mmc@33000000 {
> > + compatible = "intel,keembay-sdhci-5.1-emmc", "arasan,sdhci-5.1";
> > + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
> > + reg = <0x0 0x33000000 0x0 0x300>;
> > + clock-names = "clk_xin", "clk_ahb";
> > + clocks = <&scmi_clk KEEM_BAY_PSS_AUX_EMMC>,
> > + <&scmi_clk KEEM_BAY_PSS_EMMC>;
> > + phys = <&emmc_phy>;
> > + phy-names = "phy_arasan";
> > + assigned-clocks = <&scmi_clk KEEM_BAY_PSS_AUX_EMMC>;
> > + assigned-clock-rates = <200000000>;
> > + clock-output-names = "emmc_cardclock";
> > + #clock-cells = <0>;
> > + arasan,soc-ctl-syscon = <&mmc_phy_syscon>;
> > + };
> > +
> > + - |
> > + #define KEEM_BAY_PSS_AUX_SD0
> > + #define KEEM_BAY_PSS_SD0
> > + mmc@31000000 {
> > + compatible = "intel,keembay-sdhci-5.1-sd";
> > + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
> > + reg = <0x0 0x31000000 0x0 0x300>;
> > + clock-names = "clk_xin", "clk_ahb";
> > + clocks = <&scmi_clk KEEM_BAY_PSS_AUX_SD0>,
> > + <&scmi_clk KEEM_BAY_PSS_SD0>;
> > + arasan,soc-ctl-syscon = <&sd0_phy_syscon>;
> > + };
> > +
> > + - |
> > + #define KEEM_BAY_PSS_AUX_SD1
> > + #define KEEM_BAY_PSS_SD1
> > + mmc@32000000 {
> > + compatible = "intel,keembay-sdhci-5.1-sdio";
> > + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
> > + reg = <0x0 0x32000000 0x0 0x300>;
> > + clock-names = "clk_xin", "clk_ahb";
> > + clocks = <&scmi_clk KEEM_BAY_PSS_AUX_SD1>,
> > + <&scmi_clk KEEM_BAY_PSS_SD1>;
> > + arasan,soc-ctl-syscon = <&sd1_phy_syscon>;
> > + };
>
> Really need 3 Keem Bay examples?
I believe 2 examples is sufficient for Keem Bay.
I will drop one in v3.
>
> > --
> > 2.17.1
> >
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2020-06-08 8:58 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-05-26 6:27 [PATCH v2 0/3] mmc: sdhci-of-arasan: Add support for Intel Keem Bay Wan Ahmad Zainie
2020-05-26 6:27 ` [PATCH v2 1/3] dt-bindings: mmc: arasan: Add compatible strings " Wan Ahmad Zainie
2020-05-28 10:14 ` Ulf Hansson
2020-05-26 6:27 ` [PATCH v2 2/3] mmc: sdhci-of-arasan: Add support " Wan Ahmad Zainie
2020-05-28 10:14 ` Ulf Hansson
2020-05-26 6:27 ` [PATCH v2 3/3] dt-bindings: mmc: convert arasan sdhci bindings to yaml Wan Ahmad Zainie
2020-05-28 10:14 ` Ulf Hansson
2020-05-29 17:25 ` Rob Herring
2020-06-08 8:58 ` Wan Mohamad, Wan Ahmad Zainie
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