* [PATCH 00/24] spi: dm-conversion (part2)
@ 2020-05-27 16:46 Jagan Teki
2020-05-27 16:46 ` [PATCH 01/24] arm: Remove configs/B4420QDS_NAND_defconfig board Jagan Teki
` (22 more replies)
0 siblings, 23 replies; 59+ messages in thread
From: Jagan Teki @ 2020-05-27 16:46 UTC (permalink / raw)
To: u-boot
I believe some boards can directly enable DM_SPI if it has
OF_CONTROL enabled already, so now it's the last call for
board maintainers to take care of this.
Now all boards which are using fsl_espi are removed due to
no action on dm conversion from years.
These will merge as soon as possible, based on the response.
Travis-CI:
https://travis-ci.org/github/openedev/u-boot-amarula/builds/691819005
Any inputs?
Jagan.
Jagan Teki (24):
arm: Remove configs/B4420QDS_NAND_defconfig board
arm: Remove configs/BSC9131RDB_NAND_SYSCLK100_defconfig board
arm: Remove configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig board
arm: Remove configs/C29XPCIE_NAND_defconfig board
arm: Remove configs/Cyrus_P5020_defconfig board
arm: Remove configs/MPC8536DS_36BIT_defconfig board
arm: Remove configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig board
arm: Remove configs/P1020MBG-PC_36BIT_SDCARD_defconfig board
arm: Remove configs/P1022DS_36BIT_NAND_defconfig board
arm: Remove configs/P2041RDB_NAND_defconfig board
arm: Remove configs/P3041DS_NAND_SECURE_BOOT_defconfig board
arm: Remove configs/T1023RDB_NAND_defconfig board
arm: Remove configs/T1024QDS_DDR4_SECURE_BOOT_defconfig board
arm: Remove configs/T1040D4RDB_NAND_defconfig board
arm: Remove configs/T1040QDS_DDR4_defconfig board
arm: Remove configs/T2080QDS_NAND_defconfig board
arm: Remove configs/T2080RDB_NAND_defconfig board
arm: Remove configs/T4160QDS_NAND_defconfig board
arm: Remove configs/T4160RDB_defconfig board
arm: Remove configs/TWR-P1025_defconfig board
arm: Remove configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig
board
arm: Remove configs/kmcoge4_defconfig board
spi: Zap fsl_espi
mtd: spi: Drop fsl_espi_spl
arch/powerpc/cpu/mpc85xx/Kconfig | 21 -
arch/powerpc/cpu/mpc85xx/fdt.c | 7 -
arch/powerpc/include/asm/immap_85xx.h | 2 -
board/Arcturus/ucp1020/spl.c | 6 -
board/freescale/b4860qds/Kconfig | 14 -
board/freescale/b4860qds/MAINTAINERS | 17 -
board/freescale/b4860qds/Makefile | 16 -
board/freescale/b4860qds/b4860qds.c | 1274 -----------------
board/freescale/b4860qds/b4860qds.h | 12 -
.../b4860qds/b4860qds_crossbar_con.h | 72 -
board/freescale/b4860qds/b4860qds_qixis.h | 28 -
board/freescale/b4860qds/b4_pbi.cfg | 30 -
board/freescale/b4860qds/b4_rcw.cfg | 7 -
board/freescale/b4860qds/ddr.c | 267 ----
board/freescale/b4860qds/eth_b4860qds.c | 454 ------
board/freescale/b4860qds/law.c | 28 -
board/freescale/b4860qds/pci.c | 23 -
board/freescale/b4860qds/spl.c | 119 --
board/freescale/b4860qds/tlb.c | 154 --
board/freescale/bsc9131rdb/Kconfig | 12 -
board/freescale/bsc9131rdb/MAINTAINERS | 9 -
board/freescale/bsc9131rdb/Makefile | 21 -
board/freescale/bsc9131rdb/README | 151 --
board/freescale/bsc9131rdb/bsc9131rdb.c | 82 --
board/freescale/bsc9131rdb/ddr.c | 170 ---
board/freescale/bsc9131rdb/law.c | 18 -
board/freescale/bsc9131rdb/spl_minimal.c | 105 --
board/freescale/bsc9131rdb/tlb.c | 61 -
board/freescale/bsc9132qds/Kconfig | 14 -
board/freescale/bsc9132qds/MAINTAINERS | 25 -
board/freescale/bsc9132qds/Makefile | 21 -
board/freescale/bsc9132qds/README | 150 --
board/freescale/bsc9132qds/bsc9132qds.c | 432 ------
board/freescale/bsc9132qds/ddr.c | 191 ---
board/freescale/bsc9132qds/law.c | 28 -
board/freescale/bsc9132qds/spl_minimal.c | 117 --
board/freescale/bsc9132qds/tlb.c | 91 --
board/freescale/c29xpcie/Kconfig | 14 -
board/freescale/c29xpcie/MAINTAINERS | 10 -
board/freescale/c29xpcie/Makefile | 25 -
board/freescale/c29xpcie/README | 100 --
board/freescale/c29xpcie/c29xpcie.c | 159 --
board/freescale/c29xpcie/cpld.c | 133 --
board/freescale/c29xpcie/cpld.h | 39 -
board/freescale/c29xpcie/ddr.c | 106 --
board/freescale/c29xpcie/law.c | 18 -
board/freescale/c29xpcie/spl.c | 81 --
board/freescale/c29xpcie/spl_minimal.c | 63 -
board/freescale/c29xpcie/tlb.c | 84 --
board/freescale/corenet_ds/Kconfig | 59 -
board/freescale/corenet_ds/MAINTAINERS | 37 -
board/freescale/corenet_ds/Makefile | 16 -
board/freescale/corenet_ds/corenet_ds.c | 215 ---
board/freescale/corenet_ds/corenet_ds.h | 12 -
board/freescale/corenet_ds/ddr.c | 286 ----
board/freescale/corenet_ds/eth_hydra.c | 520 -------
board/freescale/corenet_ds/eth_p4080.c | 483 -------
board/freescale/corenet_ds/eth_superhydra.c | 771 ----------
board/freescale/corenet_ds/p3041ds_ddr.c | 11 -
board/freescale/corenet_ds/p4080ds_ddr.c | 347 -----
board/freescale/corenet_ds/p5020ds_ddr.c | 15 -
board/freescale/corenet_ds/p5040ds_ddr.c | 15 -
board/freescale/corenet_ds/pbi.cfg | 33 -
board/freescale/corenet_ds/rcw_p2041rdb.cfg | 11 -
board/freescale/corenet_ds/rcw_p3041ds.cfg | 11 -
board/freescale/corenet_ds/rcw_p4080ds.cfg | 11 -
board/freescale/corenet_ds/rcw_p5020ds.cfg | 11 -
board/freescale/corenet_ds/rcw_p5040ds.cfg | 11 -
board/freescale/mpc8536ds/Kconfig | 12 -
board/freescale/mpc8536ds/MAINTAINERS | 9 -
board/freescale/mpc8536ds/Makefile | 10 -
board/freescale/mpc8536ds/README | 127 --
board/freescale/mpc8536ds/ddr.c | 59 -
board/freescale/mpc8536ds/law.c | 19 -
board/freescale/mpc8536ds/mpc8536ds.c | 293 ----
board/freescale/mpc8536ds/tlb.c | 70 -
board/freescale/p1010rdb/Kconfig | 14 -
board/freescale/p1010rdb/MAINTAINERS | 33 -
board/freescale/p1010rdb/Makefile | 24 -
board/freescale/p1010rdb/README.P1010RDB-PA | 208 ---
board/freescale/p1010rdb/README.P1010RDB-PB | 188 ---
board/freescale/p1010rdb/ddr.c | 235 ---
board/freescale/p1010rdb/law.c | 16 -
board/freescale/p1010rdb/p1010rdb.c | 731 ----------
board/freescale/p1010rdb/spl.c | 114 --
board/freescale/p1010rdb/spl_minimal.c | 65 -
board/freescale/p1010rdb/tlb.c | 90 --
board/freescale/p1022ds/Kconfig | 12 -
board/freescale/p1022ds/MAINTAINERS | 13 -
board/freescale/p1022ds/Makefile | 25 -
board/freescale/p1022ds/README | 23 -
board/freescale/p1022ds/ddr.c | 106 --
board/freescale/p1022ds/diu.c | 478 -------
board/freescale/p1022ds/law.c | 18 -
board/freescale/p1022ds/p1022ds.c | 364 -----
board/freescale/p1022ds/spl.c | 131 --
board/freescale/p1022ds/spl_minimal.c | 71 -
board/freescale/p1022ds/tlb.c | 101 --
board/freescale/p1_p2_rdb_pc/Kconfig | 19 -
board/freescale/p1_p2_rdb_pc/MAINTAINERS | 51 -
board/freescale/p1_p2_rdb_pc/Makefile | 24 -
board/freescale/p1_p2_rdb_pc/README | 66 -
board/freescale/p1_p2_rdb_pc/ddr.c | 292 ----
board/freescale/p1_p2_rdb_pc/law.c | 22 -
board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 536 -------
board/freescale/p1_p2_rdb_pc/spl.c | 123 --
board/freescale/p1_p2_rdb_pc/spl_minimal.c | 63 -
board/freescale/p1_p2_rdb_pc/tlb.c | 110 --
board/freescale/p1_twr/Kconfig | 12 -
board/freescale/p1_twr/MAINTAINERS | 6 -
board/freescale/p1_twr/Makefile | 9 -
board/freescale/p1_twr/ddr.c | 69 -
board/freescale/p1_twr/law.c | 15 -
board/freescale/p1_twr/p1_twr.c | 292 ----
board/freescale/p1_twr/tlb.c | 75 -
board/freescale/p2041rdb/Kconfig | 14 -
board/freescale/p2041rdb/MAINTAINERS | 11 -
board/freescale/p2041rdb/Makefile | 10 -
board/freescale/p2041rdb/README | 141 --
board/freescale/p2041rdb/cpld.c | 157 --
board/freescale/p2041rdb/cpld.h | 54 -
board/freescale/p2041rdb/ddr.c | 143 --
board/freescale/p2041rdb/eth.c | 201 ---
board/freescale/p2041rdb/p2041rdb.c | 244 ----
board/freescale/t102xqds/Kconfig | 14 -
board/freescale/t102xqds/MAINTAINERS | 12 -
board/freescale/t102xqds/Makefile | 15 -
board/freescale/t102xqds/README | 328 -----
board/freescale/t102xqds/ddr.c | 195 ---
board/freescale/t102xqds/eth_t102xqds.c | 445 ------
board/freescale/t102xqds/law.c | 31 -
board/freescale/t102xqds/pci.c | 23 -
board/freescale/t102xqds/spl.c | 156 --
board/freescale/t102xqds/t1024_nand_rcw.cfg | 10 -
board/freescale/t102xqds/t1024_pbi.cfg | 26 -
board/freescale/t102xqds/t1024_sd_rcw.cfg | 10 -
board/freescale/t102xqds/t1024_spi_rcw.cfg | 10 -
board/freescale/t102xqds/t102xqds.c | 497 -------
board/freescale/t102xqds/t102xqds.h | 14 -
board/freescale/t102xqds/t102xqds_qixis.h | 63 -
board/freescale/t102xqds/tlb.c | 116 --
board/freescale/t102xrdb/Kconfig | 14 -
board/freescale/t102xrdb/MAINTAINERS | 15 -
board/freescale/t102xrdb/Makefile | 17 -
board/freescale/t102xrdb/README | 340 -----
board/freescale/t102xrdb/cpld.c | 102 --
board/freescale/t102xrdb/cpld.h | 48 -
board/freescale/t102xrdb/ddr.c | 257 ----
board/freescale/t102xrdb/eth_t102xrdb.c | 146 --
board/freescale/t102xrdb/law.c | 31 -
board/freescale/t102xrdb/pci.c | 25 -
board/freescale/t102xrdb/spl.c | 143 --
board/freescale/t102xrdb/t1023_nand_rcw.cfg | 8 -
board/freescale/t102xrdb/t1023_sd_rcw.cfg | 8 -
board/freescale/t102xrdb/t1023_spi_rcw.cfg | 8 -
board/freescale/t102xrdb/t1024_nand_rcw.cfg | 8 -
board/freescale/t102xrdb/t1024_pbi.cfg | 26 -
board/freescale/t102xrdb/t1024_sd_rcw.cfg | 8 -
board/freescale/t102xrdb/t1024_spi_rcw.cfg | 8 -
board/freescale/t102xrdb/t102xrdb.c | 394 -----
board/freescale/t102xrdb/t102xrdb.h | 15 -
board/freescale/t102xrdb/tlb.c | 116 --
board/freescale/t1040qds/Kconfig | 14 -
board/freescale/t1040qds/MAINTAINERS | 12 -
board/freescale/t1040qds/Makefile | 11 -
board/freescale/t1040qds/README | 169 ---
board/freescale/t1040qds/ddr.c | 142 --
board/freescale/t1040qds/ddr.h | 52 -
board/freescale/t1040qds/diu.c | 98 --
board/freescale/t1040qds/eth.c | 592 --------
board/freescale/t1040qds/law.c | 31 -
board/freescale/t1040qds/pci.c | 23 -
board/freescale/t1040qds/t1040_pbi.cfg | 27 -
board/freescale/t1040qds/t1040_rcw.cfg | 7 -
board/freescale/t1040qds/t1040qds.c | 305 ----
board/freescale/t1040qds/t1040qds.h | 14 -
board/freescale/t1040qds/t1040qds_qixis.h | 51 -
board/freescale/t1040qds/tlb.c | 107 --
board/freescale/t104xrdb/Kconfig | 16 -
board/freescale/t104xrdb/MAINTAINERS | 38 -
board/freescale/t104xrdb/Makefile | 16 -
board/freescale/t104xrdb/README | 386 -----
board/freescale/t104xrdb/cpld.c | 115 --
board/freescale/t104xrdb/cpld.h | 46 -
board/freescale/t104xrdb/ddr.c | 145 --
board/freescale/t104xrdb/ddr.h | 56 -
board/freescale/t104xrdb/diu.c | 84 --
board/freescale/t104xrdb/eth.c | 154 --
board/freescale/t104xrdb/law.c | 31 -
board/freescale/t104xrdb/pci.c | 25 -
board/freescale/t104xrdb/spl.c | 142 --
board/freescale/t104xrdb/t1040_nand_rcw.cfg | 7 -
board/freescale/t104xrdb/t1040_sd_rcw.cfg | 7 -
board/freescale/t104xrdb/t1040_spi_rcw.cfg | 7 -
board/freescale/t104xrdb/t1040d4_nand_rcw.cfg | 7 -
board/freescale/t104xrdb/t1040d4_sd_rcw.cfg | 7 -
board/freescale/t104xrdb/t1040d4_spi_rcw.cfg | 7 -
board/freescale/t104xrdb/t1042_nand_rcw.cfg | 7 -
.../freescale/t104xrdb/t1042_pi_nand_rcw.cfg | 7 -
board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg | 7 -
board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg | 7 -
board/freescale/t104xrdb/t1042_sd_rcw.cfg | 7 -
board/freescale/t104xrdb/t1042_spi_rcw.cfg | 7 -
board/freescale/t104xrdb/t1042d4_nand_rcw.cfg | 7 -
board/freescale/t104xrdb/t1042d4_sd_rcw.cfg | 7 -
board/freescale/t104xrdb/t1042d4_spi_rcw.cfg | 7 -
board/freescale/t104xrdb/t104x_pbi.cfg | 36 -
board/freescale/t104xrdb/t104x_pbi_sb.cfg | 38 -
board/freescale/t104xrdb/t104xrdb.c | 161 ---
board/freescale/t104xrdb/t104xrdb.h | 12 -
board/freescale/t104xrdb/tlb.c | 131 --
board/freescale/t208xqds/Kconfig | 14 -
board/freescale/t208xqds/MAINTAINERS | 20 -
board/freescale/t208xqds/Makefile | 17 -
board/freescale/t208xqds/README | 293 ----
board/freescale/t208xqds/ddr.c | 125 --
board/freescale/t208xqds/ddr.h | 70 -
board/freescale/t208xqds/eth_t208xqds.c | 826 -----------
board/freescale/t208xqds/law.c | 33 -
board/freescale/t208xqds/pci.c | 25 -
board/freescale/t208xqds/spl.c | 142 --
board/freescale/t208xqds/t2080_nand_rcw.cfg | 16 -
board/freescale/t208xqds/t2080_sd_rcw.cfg | 16 -
board/freescale/t208xqds/t2080_spi_rcw.cfg | 16 -
board/freescale/t208xqds/t2081_nand_rcw.cfg | 8 -
board/freescale/t208xqds/t2081_sd_rcw.cfg | 8 -
board/freescale/t208xqds/t2081_spi_rcw.cfg | 8 -
board/freescale/t208xqds/t208x_pbi.cfg | 40 -
board/freescale/t208xqds/t208xqds.c | 489 -------
board/freescale/t208xqds/t208xqds.h | 12 -
board/freescale/t208xqds/t208xqds_qixis.h | 48 -
board/freescale/t208xqds/tlb.c | 152 --
board/freescale/t208xrdb/Kconfig | 14 -
board/freescale/t208xrdb/MAINTAINERS | 15 -
board/freescale/t208xrdb/Makefile | 16 -
board/freescale/t208xrdb/README | 283 ----
board/freescale/t208xrdb/cpld.c | 70 -
board/freescale/t208xrdb/cpld.h | 44 -
board/freescale/t208xrdb/ddr.c | 118 --
board/freescale/t208xrdb/ddr.h | 46 -
board/freescale/t208xrdb/eth_t208xrdb.c | 107 --
board/freescale/t208xrdb/law.c | 33 -
board/freescale/t208xrdb/pci.c | 25 -
board/freescale/t208xrdb/spl.c | 112 --
board/freescale/t208xrdb/t2080_nand_rcw.cfg | 19 -
board/freescale/t208xrdb/t2080_pbi.cfg | 40 -
board/freescale/t208xrdb/t2080_sd_rcw.cfg | 19 -
board/freescale/t208xrdb/t2080_spi_rcw.cfg | 19 -
board/freescale/t208xrdb/t208xrdb.c | 142 --
board/freescale/t208xrdb/t208xrdb.h | 12 -
board/freescale/t208xrdb/tlb.c | 152 --
board/freescale/t4qds/Kconfig | 14 -
board/freescale/t4qds/MAINTAINERS | 18 -
board/freescale/t4qds/Makefile | 15 -
board/freescale/t4qds/README | 194 ---
board/freescale/t4qds/ddr.c | 134 --
board/freescale/t4qds/ddr.h | 81 --
board/freescale/t4qds/eth.c | 869 -----------
board/freescale/t4qds/law.c | 33 -
board/freescale/t4qds/pci.c | 23 -
board/freescale/t4qds/spl.c | 145 --
board/freescale/t4qds/t4240emu.c | 85 --
board/freescale/t4qds/t4240qds.c | 927 ------------
board/freescale/t4qds/t4240qds_qixis.h | 42 -
board/freescale/t4qds/t4_nand_rcw.cfg | 7 -
board/freescale/t4qds/t4_pbi.cfg | 21 -
board/freescale/t4qds/t4_sd_rcw.cfg | 7 -
board/freescale/t4qds/t4qds.h | 12 -
board/freescale/t4qds/tlb.c | 146 --
board/freescale/t4rdb/Kconfig | 14 -
board/freescale/t4rdb/MAINTAINERS | 8 -
board/freescale/t4rdb/Makefile | 19 -
board/freescale/t4rdb/cpld.c | 129 --
board/freescale/t4rdb/cpld.h | 48 -
board/freescale/t4rdb/ddr.c | 127 --
board/freescale/t4rdb/ddr.h | 77 -
board/freescale/t4rdb/eth.c | 152 --
board/freescale/t4rdb/law.c | 30 -
board/freescale/t4rdb/pci.c | 25 -
board/freescale/t4rdb/spl.c | 99 --
board/freescale/t4rdb/t4240rdb.c | 150 --
board/freescale/t4rdb/t4_pbi.cfg | 27 -
board/freescale/t4rdb/t4_sd_rcw.cfg | 7 -
board/freescale/t4rdb/t4rdb.h | 17 -
board/freescale/t4rdb/tlb.c | 123 --
board/gdsys/p1022/Kconfig | 22 -
board/gdsys/p1022/MAINTAINERS | 9 -
board/gdsys/p1022/Makefile | 10 -
board/gdsys/p1022/controlcenterd-id.c | 1244 ----------------
board/gdsys/p1022/controlcenterd-id.h | 15 -
board/gdsys/p1022/controlcenterd.c | 431 ------
board/gdsys/p1022/ddr.c | 68 -
board/gdsys/p1022/diu.c | 85 --
board/gdsys/p1022/law.c | 16 -
board/gdsys/p1022/sdhc_boot.c | 63 -
board/gdsys/p1022/tlb.c | 73 -
board/keymile/Kconfig | 1 -
board/keymile/kmp204x/Kconfig | 20 -
board/keymile/kmp204x/MAINTAINERS | 6 -
board/keymile/kmp204x/Makefile | 10 -
board/keymile/kmp204x/ddr.c | 69 -
board/keymile/kmp204x/eth.c | 71 -
board/keymile/kmp204x/kmp204x.c | 265 ----
board/keymile/kmp204x/kmp204x.h | 8 -
board/keymile/kmp204x/law.c | 39 -
board/keymile/kmp204x/pbi.cfg | 74 -
board/keymile/kmp204x/pci.c | 125 --
board/keymile/kmp204x/rcw_kmp204x.cfg | 11 -
board/keymile/kmp204x/tlb.c | 109 --
board/varisys/cyrus/Kconfig | 14 -
board/varisys/cyrus/MAINTAINERS | 7 -
board/varisys/cyrus/Makefile | 8 -
board/varisys/cyrus/README | 19 -
board/varisys/cyrus/cyrus.c | 117 --
board/varisys/cyrus/cyrus.h | 9 -
board/varisys/cyrus/ddr.c | 191 ---
board/varisys/cyrus/eth.c | 100 --
board/varisys/cyrus/law.c | 26 -
board/varisys/cyrus/pbi.cfg | 35 -
board/varisys/cyrus/pci.c | 23 -
board/varisys/cyrus/rcw_p5020_v2.cfg | 11 -
board/varisys/cyrus/rcw_p5040.cfg | 11 -
board/varisys/cyrus/tlb.c | 105 --
common/spl/Kconfig | 4 -
configs/B4420QDS_NAND_defconfig | 69 -
configs/B4420QDS_SPIFLASH_defconfig | 55 -
configs/B4420QDS_defconfig | 53 -
configs/B4860QDS_NAND_defconfig | 69 -
configs/B4860QDS_SECURE_BOOT_defconfig | 56 -
configs/B4860QDS_SPIFLASH_defconfig | 55 -
configs/B4860QDS_SRIO_PCIE_BOOT_defconfig | 49 -
configs/B4860QDS_defconfig | 53 -
configs/BSC9131RDB_NAND_SYSCLK100_defconfig | 64 -
configs/BSC9131RDB_NAND_defconfig | 63 -
.../BSC9131RDB_SPIFLASH_SYSCLK100_defconfig | 56 -
configs/BSC9131RDB_SPIFLASH_defconfig | 56 -
...BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig | 66 -
configs/BSC9132QDS_NAND_DDRCLK100_defconfig | 72 -
...BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig | 66 -
configs/BSC9132QDS_NAND_DDRCLK133_defconfig | 72 -
.../BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig | 65 -
configs/BSC9132QDS_NOR_DDRCLK100_defconfig | 63 -
.../BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig | 65 -
configs/BSC9132QDS_NOR_DDRCLK133_defconfig | 63 -
...C9132QDS_SDCARD_DDRCLK100_SECURE_defconfig | 66 -
configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig | 63 -
...C9132QDS_SDCARD_DDRCLK133_SECURE_defconfig | 66 -
configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig | 63 -
...132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig | 66 -
.../BSC9132QDS_SPIFLASH_DDRCLK100_defconfig | 64 -
...132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig | 66 -
.../BSC9132QDS_SPIFLASH_DDRCLK133_defconfig | 64 -
configs/C29XPCIE_NAND_defconfig | 70 -
configs/C29XPCIE_NOR_SECBOOT_defconfig | 55 -
configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig | 57 -
configs/C29XPCIE_SPIFLASH_defconfig | 55 -
configs/C29XPCIE_defconfig | 53 -
configs/Cyrus_P5020_defconfig | 45 -
configs/Cyrus_P5040_defconfig | 45 -
configs/MPC8536DS_36BIT_defconfig | 61 -
configs/MPC8536DS_SDCARD_defconfig | 60 -
configs/MPC8536DS_SPIFLASH_defconfig | 61 -
configs/MPC8536DS_defconfig | 60 -
.../P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig | 63 -
configs/P1010RDB-PA_36BIT_NAND_defconfig | 85 --
.../P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig | 62 -
configs/P1010RDB-PA_36BIT_NOR_defconfig | 67 -
configs/P1010RDB-PA_36BIT_SDCARD_defconfig | 79 -
...010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig | 64 -
configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig | 81 --
configs/P1010RDB-PA_NAND_SECBOOT_defconfig | 62 -
configs/P1010RDB-PA_NAND_defconfig | 84 --
configs/P1010RDB-PA_NOR_SECBOOT_defconfig | 60 -
configs/P1010RDB-PA_NOR_defconfig | 66 -
configs/P1010RDB-PA_SDCARD_defconfig | 78 -
.../P1010RDB-PA_SPIFLASH_SECBOOT_defconfig | 63 -
configs/P1010RDB-PA_SPIFLASH_defconfig | 80 --
.../P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig | 63 -
configs/P1010RDB-PB_36BIT_NAND_defconfig | 85 --
.../P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig | 62 -
configs/P1010RDB-PB_36BIT_NOR_defconfig | 67 -
configs/P1010RDB-PB_36BIT_SDCARD_defconfig | 79 -
...010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig | 64 -
configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig | 81 --
configs/P1010RDB-PB_NAND_SECBOOT_defconfig | 62 -
configs/P1010RDB-PB_NAND_defconfig | 84 --
configs/P1010RDB-PB_NOR_SECBOOT_defconfig | 61 -
configs/P1010RDB-PB_NOR_defconfig | 66 -
configs/P1010RDB-PB_SDCARD_defconfig | 78 -
.../P1010RDB-PB_SPIFLASH_SECBOOT_defconfig | 63 -
configs/P1010RDB-PB_SPIFLASH_defconfig | 80 --
configs/P1020MBG-PC_36BIT_SDCARD_defconfig | 67 -
configs/P1020MBG-PC_36BIT_defconfig | 55 -
configs/P1020MBG-PC_SDCARD_defconfig | 66 -
configs/P1020MBG-PC_defconfig | 54 -
configs/P1020RDB-PC_36BIT_NAND_defconfig | 85 --
configs/P1020RDB-PC_36BIT_SDCARD_defconfig | 80 --
configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 82 --
configs/P1020RDB-PC_36BIT_defconfig | 69 -
configs/P1020RDB-PC_NAND_defconfig | 84 --
configs/P1020RDB-PC_SDCARD_defconfig | 79 -
configs/P1020RDB-PC_SPIFLASH_defconfig | 81 --
configs/P1020RDB-PC_defconfig | 68 -
configs/P1020RDB-PD_NAND_defconfig | 88 --
configs/P1020RDB-PD_SDCARD_defconfig | 83 --
configs/P1020RDB-PD_SPIFLASH_defconfig | 85 --
configs/P1020RDB-PD_defconfig | 72 -
configs/P1020UTM-PC_36BIT_SDCARD_defconfig | 67 -
configs/P1020UTM-PC_36BIT_defconfig | 55 -
configs/P1020UTM-PC_SDCARD_defconfig | 66 -
configs/P1020UTM-PC_defconfig | 54 -
configs/P1021RDB-PC_36BIT_NAND_defconfig | 84 --
configs/P1021RDB-PC_36BIT_SDCARD_defconfig | 79 -
configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig | 81 --
configs/P1021RDB-PC_36BIT_defconfig | 67 -
configs/P1021RDB-PC_NAND_defconfig | 83 --
configs/P1021RDB-PC_SDCARD_defconfig | 78 -
configs/P1021RDB-PC_SPIFLASH_defconfig | 80 --
configs/P1021RDB-PC_defconfig | 66 -
configs/P1022DS_36BIT_NAND_defconfig | 80 --
configs/P1022DS_36BIT_SDCARD_defconfig | 74 -
configs/P1022DS_36BIT_SPIFLASH_defconfig | 76 -
configs/P1022DS_36BIT_defconfig | 62 -
configs/P1022DS_NAND_defconfig | 79 -
configs/P1022DS_SDCARD_defconfig | 73 -
configs/P1022DS_SPIFLASH_defconfig | 75 -
configs/P1022DS_defconfig | 61 -
configs/P1024RDB_36BIT_defconfig | 61 -
configs/P1024RDB_NAND_defconfig | 77 -
configs/P1024RDB_SDCARD_defconfig | 71 -
configs/P1024RDB_SPIFLASH_defconfig | 73 -
configs/P1024RDB_defconfig | 60 -
configs/P1025RDB_36BIT_defconfig | 63 -
configs/P1025RDB_NAND_defconfig | 80 --
configs/P1025RDB_SDCARD_defconfig | 73 -
configs/P1025RDB_SPIFLASH_defconfig | 76 -
configs/P1025RDB_defconfig | 62 -
configs/P2020RDB-PC_36BIT_NAND_defconfig | 90 --
configs/P2020RDB-PC_36BIT_SDCARD_defconfig | 85 --
configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 87 --
configs/P2020RDB-PC_36BIT_defconfig | 74 -
configs/P2020RDB-PC_NAND_defconfig | 89 --
configs/P2020RDB-PC_SDCARD_defconfig | 84 --
configs/P2020RDB-PC_SPIFLASH_defconfig | 86 --
configs/P2020RDB-PC_defconfig | 73 -
configs/P2041RDB_NAND_defconfig | 64 -
configs/P2041RDB_SDCARD_defconfig | 63 -
configs/P2041RDB_SECURE_BOOT_defconfig | 57 -
configs/P2041RDB_SPIFLASH_defconfig | 64 -
configs/P2041RDB_SRIO_PCIE_BOOT_defconfig | 50 -
configs/P2041RDB_defconfig | 62 -
configs/P3041DS_NAND_SECURE_BOOT_defconfig | 59 -
configs/P3041DS_NAND_defconfig | 64 -
configs/P3041DS_SDCARD_defconfig | 63 -
configs/P3041DS_SECURE_BOOT_defconfig | 57 -
configs/P3041DS_SPIFLASH_defconfig | 64 -
configs/P3041DS_SRIO_PCIE_BOOT_defconfig | 50 -
configs/P3041DS_defconfig | 62 -
configs/P4080DS_SDCARD_defconfig | 62 -
configs/P4080DS_SECURE_BOOT_defconfig | 56 -
configs/P4080DS_SPIFLASH_defconfig | 63 -
configs/P4080DS_SRIO_PCIE_BOOT_defconfig | 48 -
configs/P4080DS_defconfig | 61 -
configs/P5020DS_NAND_SECURE_BOOT_defconfig | 60 -
configs/P5020DS_NAND_defconfig | 57 -
configs/P5020DS_SDCARD_defconfig | 55 -
configs/P5020DS_SECURE_BOOT_defconfig | 57 -
configs/P5020DS_SPIFLASH_defconfig | 56 -
configs/P5020DS_SRIO_PCIE_BOOT_defconfig | 50 -
configs/P5020DS_defconfig | 54 -
configs/P5040DS_NAND_SECURE_BOOT_defconfig | 60 -
configs/P5040DS_NAND_defconfig | 65 -
configs/P5040DS_SDCARD_defconfig | 63 -
configs/P5040DS_SECURE_BOOT_defconfig | 57 -
configs/P5040DS_SPIFLASH_defconfig | 64 -
configs/P5040DS_defconfig | 62 -
configs/T1023RDB_NAND_defconfig | 77 -
configs/T1023RDB_SDCARD_defconfig | 74 -
configs/T1023RDB_SECURE_BOOT_defconfig | 64 -
configs/T1023RDB_SPIFLASH_defconfig | 77 -
configs/T1023RDB_defconfig | 61 -
configs/T1024QDS_DDR4_SECURE_BOOT_defconfig | 69 -
configs/T1024QDS_DDR4_defconfig | 64 -
configs/T1024QDS_NAND_defconfig | 83 --
configs/T1024QDS_SDCARD_defconfig | 80 --
configs/T1024QDS_SECURE_BOOT_defconfig | 70 -
configs/T1024QDS_SPIFLASH_defconfig | 83 --
configs/T1024QDS_defconfig | 67 -
configs/T1024RDB_NAND_defconfig | 86 --
configs/T1024RDB_SDCARD_defconfig | 83 --
configs/T1024RDB_SECURE_BOOT_defconfig | 66 -
configs/T1024RDB_SPIFLASH_defconfig | 86 --
configs/T1024RDB_defconfig | 71 -
configs/T1040D4RDB_NAND_defconfig | 75 -
configs/T1040D4RDB_SDCARD_defconfig | 72 -
configs/T1040D4RDB_SECURE_BOOT_defconfig | 61 -
configs/T1040D4RDB_SPIFLASH_defconfig | 75 -
configs/T1040D4RDB_defconfig | 59 -
configs/T1040QDS_DDR4_defconfig | 67 -
configs/T1040QDS_SECURE_BOOT_defconfig | 70 -
configs/T1040QDS_defconfig | 68 -
configs/T1040RDB_NAND_defconfig | 76 -
configs/T1040RDB_SDCARD_defconfig | 73 -
configs/T1040RDB_SECURE_BOOT_defconfig | 62 -
configs/T1040RDB_SPIFLASH_defconfig | 76 -
configs/T1040RDB_defconfig | 60 -
configs/T1042D4RDB_NAND_defconfig | 86 --
configs/T1042D4RDB_SDCARD_defconfig | 83 --
configs/T1042D4RDB_SECURE_BOOT_defconfig | 64 -
configs/T1042D4RDB_SPIFLASH_defconfig | 86 --
configs/T1042D4RDB_defconfig | 71 -
.../T1042RDB_PI_NAND_SECURE_BOOT_defconfig | 85 --
configs/T1042RDB_PI_NAND_defconfig | 80 --
configs/T1042RDB_PI_SDCARD_defconfig | 77 -
configs/T1042RDB_PI_SPIFLASH_defconfig | 80 --
configs/T1042RDB_PI_defconfig | 64 -
configs/T1042RDB_SECURE_BOOT_defconfig | 61 -
configs/T1042RDB_defconfig | 59 -
configs/T2080QDS_NAND_defconfig | 83 --
configs/T2080QDS_SDCARD_defconfig | 80 --
configs/T2080QDS_SECURE_BOOT_defconfig | 70 -
configs/T2080QDS_SPIFLASH_defconfig | 83 --
configs/T2080QDS_SRIO_PCIE_BOOT_defconfig | 60 -
configs/T2080QDS_defconfig | 68 -
configs/T2080RDB_NAND_defconfig | 84 --
configs/T2080RDB_SDCARD_defconfig | 81 --
configs/T2080RDB_SECURE_BOOT_defconfig | 63 -
configs/T2080RDB_SPIFLASH_defconfig | 84 --
configs/T2080RDB_SRIO_PCIE_BOOT_defconfig | 53 -
configs/T2080RDB_defconfig | 68 -
configs/T2081QDS_NAND_defconfig | 75 -
configs/T2081QDS_SDCARD_defconfig | 72 -
configs/T2081QDS_SPIFLASH_defconfig | 75 -
configs/T2081QDS_SRIO_PCIE_BOOT_defconfig | 51 -
configs/T2081QDS_defconfig | 59 -
configs/T4160QDS_NAND_defconfig | 69 -
configs/T4160QDS_SDCARD_defconfig | 66 -
configs/T4160QDS_SECURE_BOOT_defconfig | 56 -
configs/T4160QDS_defconfig | 53 -
configs/T4160RDB_defconfig | 54 -
configs/T4240QDS_NAND_defconfig | 69 -
configs/T4240QDS_SDCARD_defconfig | 66 -
configs/T4240QDS_SECURE_BOOT_defconfig | 56 -
configs/T4240QDS_SRIO_PCIE_BOOT_defconfig | 49 -
configs/T4240QDS_defconfig | 53 -
configs/T4240RDB_SDCARD_defconfig | 74 -
configs/T4240RDB_defconfig | 62 -
configs/TWR-P1025_defconfig | 64 -
...trolcenterd_36BIT_SDCARD_DEVELOP_defconfig | 68 -
configs/controlcenterd_36BIT_SDCARD_defconfig | 68 -
...ntrolcenterd_TRAILBLAZER_DEVELOP_defconfig | 36 -
configs/controlcenterd_TRAILBLAZER_defconfig | 36 -
configs/kmcoge4_defconfig | 68 -
drivers/mtd/spi/Makefile | 1 -
drivers/mtd/spi/fsl_espi_spl.c | 91 --
drivers/spi/Kconfig | 8 -
drivers/spi/Makefile | 1 -
drivers/spi/fsl_espi.c | 386 -----
include/configs/B4860QDS.h | 759 ----------
include/configs/BSC9131RDB.h | 337 -----
include/configs/BSC9132QDS.h | 548 -------
include/configs/C29XPCIE.h | 443 ------
include/configs/MPC8536DS.h | 642 ---------
include/configs/P1010RDB.h | 766 ----------
include/configs/P1022DS.h | 593 --------
include/configs/P2041RDB.h | 585 --------
include/configs/P3041DS.h | 24 -
include/configs/P4080DS.h | 23 -
include/configs/P5020DS.h | 25 -
include/configs/P5040DS.h | 19 -
include/configs/T102xQDS.h | 756 ----------
include/configs/T102xRDB.h | 721 ----------
include/configs/T1040QDS.h | 667 ---------
include/configs/T104xRDB.h | 813 -----------
include/configs/T208xQDS.h | 771 ----------
include/configs/T208xRDB.h | 717 ----------
include/configs/T4240QDS.h | 555 -------
include/configs/T4240RDB.h | 681 ---------
include/configs/controlcenterd.h | 362 -----
include/configs/cyrus.h | 466 ------
include/configs/kmp204x.h | 435 ------
include/configs/p1_p2_rdb_pc.h | 881 ------------
include/configs/p1_twr.h | 480 -------
scripts/config_whitelist.txt | 1 -
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delete mode 100644 configs/T1040D4RDB_SPIFLASH_defconfig
delete mode 100644 configs/T1040D4RDB_defconfig
delete mode 100644 configs/T1040QDS_DDR4_defconfig
delete mode 100644 configs/T1040QDS_SECURE_BOOT_defconfig
delete mode 100644 configs/T1040QDS_defconfig
delete mode 100644 configs/T1040RDB_NAND_defconfig
delete mode 100644 configs/T1040RDB_SDCARD_defconfig
delete mode 100644 configs/T1040RDB_SECURE_BOOT_defconfig
delete mode 100644 configs/T1040RDB_SPIFLASH_defconfig
delete mode 100644 configs/T1040RDB_defconfig
delete mode 100644 configs/T1042D4RDB_NAND_defconfig
delete mode 100644 configs/T1042D4RDB_SDCARD_defconfig
delete mode 100644 configs/T1042D4RDB_SECURE_BOOT_defconfig
delete mode 100644 configs/T1042D4RDB_SPIFLASH_defconfig
delete mode 100644 configs/T1042D4RDB_defconfig
delete mode 100644 configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig
delete mode 100644 configs/T1042RDB_PI_NAND_defconfig
delete mode 100644 configs/T1042RDB_PI_SDCARD_defconfig
delete mode 100644 configs/T1042RDB_PI_SPIFLASH_defconfig
delete mode 100644 configs/T1042RDB_PI_defconfig
delete mode 100644 configs/T1042RDB_SECURE_BOOT_defconfig
delete mode 100644 configs/T1042RDB_defconfig
delete mode 100644 configs/T2080QDS_NAND_defconfig
delete mode 100644 configs/T2080QDS_SDCARD_defconfig
delete mode 100644 configs/T2080QDS_SECURE_BOOT_defconfig
delete mode 100644 configs/T2080QDS_SPIFLASH_defconfig
delete mode 100644 configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
delete mode 100644 configs/T2080QDS_defconfig
delete mode 100644 configs/T2080RDB_NAND_defconfig
delete mode 100644 configs/T2080RDB_SDCARD_defconfig
delete mode 100644 configs/T2080RDB_SECURE_BOOT_defconfig
delete mode 100644 configs/T2080RDB_SPIFLASH_defconfig
delete mode 100644 configs/T2080RDB_SRIO_PCIE_BOOT_defconfig
delete mode 100644 configs/T2080RDB_defconfig
delete mode 100644 configs/T2081QDS_NAND_defconfig
delete mode 100644 configs/T2081QDS_SDCARD_defconfig
delete mode 100644 configs/T2081QDS_SPIFLASH_defconfig
delete mode 100644 configs/T2081QDS_SRIO_PCIE_BOOT_defconfig
delete mode 100644 configs/T2081QDS_defconfig
delete mode 100644 configs/T4160QDS_NAND_defconfig
delete mode 100644 configs/T4160QDS_SDCARD_defconfig
delete mode 100644 configs/T4160QDS_SECURE_BOOT_defconfig
delete mode 100644 configs/T4160QDS_defconfig
delete mode 100644 configs/T4160RDB_defconfig
delete mode 100644 configs/T4240QDS_NAND_defconfig
delete mode 100644 configs/T4240QDS_SDCARD_defconfig
delete mode 100644 configs/T4240QDS_SECURE_BOOT_defconfig
delete mode 100644 configs/T4240QDS_SRIO_PCIE_BOOT_defconfig
delete mode 100644 configs/T4240QDS_defconfig
delete mode 100644 configs/T4240RDB_SDCARD_defconfig
delete mode 100644 configs/T4240RDB_defconfig
delete mode 100644 configs/TWR-P1025_defconfig
delete mode 100644 configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig
delete mode 100644 configs/controlcenterd_36BIT_SDCARD_defconfig
delete mode 100644 configs/controlcenterd_TRAILBLAZER_DEVELOP_defconfig
delete mode 100644 configs/controlcenterd_TRAILBLAZER_defconfig
delete mode 100644 configs/kmcoge4_defconfig
delete mode 100644 drivers/mtd/spi/fsl_espi_spl.c
delete mode 100644 drivers/spi/fsl_espi.c
delete mode 100644 include/configs/B4860QDS.h
delete mode 100644 include/configs/BSC9131RDB.h
delete mode 100644 include/configs/BSC9132QDS.h
delete mode 100644 include/configs/C29XPCIE.h
delete mode 100644 include/configs/MPC8536DS.h
delete mode 100644 include/configs/P1010RDB.h
delete mode 100644 include/configs/P1022DS.h
delete mode 100644 include/configs/P2041RDB.h
delete mode 100644 include/configs/P3041DS.h
delete mode 100644 include/configs/P4080DS.h
delete mode 100644 include/configs/P5020DS.h
delete mode 100644 include/configs/P5040DS.h
delete mode 100644 include/configs/T102xQDS.h
delete mode 100644 include/configs/T102xRDB.h
delete mode 100644 include/configs/T1040QDS.h
delete mode 100644 include/configs/T104xRDB.h
delete mode 100644 include/configs/T208xQDS.h
delete mode 100644 include/configs/T208xRDB.h
delete mode 100644 include/configs/T4240QDS.h
delete mode 100644 include/configs/T4240RDB.h
delete mode 100644 include/configs/controlcenterd.h
delete mode 100644 include/configs/cyrus.h
delete mode 100644 include/configs/kmp204x.h
delete mode 100644 include/configs/p1_p2_rdb_pc.h
delete mode 100644 include/configs/p1_twr.h
--
2.25.1
^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH 01/24] arm: Remove configs/B4420QDS_NAND_defconfig board
2020-05-27 16:46 [PATCH 00/24] spi: dm-conversion (part2) Jagan Teki
@ 2020-05-27 16:46 ` Jagan Teki
2020-05-28 7:00 ` Priyanka Jain
2020-05-27 16:46 ` [PATCH 02/24] arm: Remove configs/BSC9131RDB_NAND_SYSCLK100_defconfig board Jagan Teki
` (21 subsequent siblings)
22 siblings, 1 reply; 59+ messages in thread
From: Jagan Teki @ 2020-05-27 16:46 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_SPI by the deadline.
Remove it.
Patch-cc: Ashish Kumar <ashish.kumar@nxp.com>
Patch-cc: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
arch/powerpc/cpu/mpc85xx/Kconfig | 1 -
board/freescale/b4860qds/Kconfig | 14 -
board/freescale/b4860qds/MAINTAINERS | 17 -
board/freescale/b4860qds/Makefile | 16 -
board/freescale/b4860qds/b4860qds.c | 1274 -----------------
board/freescale/b4860qds/b4860qds.h | 12 -
.../b4860qds/b4860qds_crossbar_con.h | 72 -
board/freescale/b4860qds/b4860qds_qixis.h | 28 -
board/freescale/b4860qds/b4_pbi.cfg | 30 -
board/freescale/b4860qds/b4_rcw.cfg | 7 -
board/freescale/b4860qds/ddr.c | 267 ----
board/freescale/b4860qds/eth_b4860qds.c | 454 ------
board/freescale/b4860qds/law.c | 28 -
board/freescale/b4860qds/pci.c | 23 -
board/freescale/b4860qds/spl.c | 119 --
board/freescale/b4860qds/tlb.c | 154 --
configs/B4420QDS_NAND_defconfig | 69 -
configs/B4420QDS_SPIFLASH_defconfig | 55 -
configs/B4420QDS_defconfig | 53 -
configs/B4860QDS_NAND_defconfig | 69 -
configs/B4860QDS_SECURE_BOOT_defconfig | 56 -
configs/B4860QDS_SPIFLASH_defconfig | 55 -
configs/B4860QDS_SRIO_PCIE_BOOT_defconfig | 49 -
configs/B4860QDS_defconfig | 53 -
include/configs/B4860QDS.h | 759 ----------
25 files changed, 3734 deletions(-)
delete mode 100644 board/freescale/b4860qds/Kconfig
delete mode 100644 board/freescale/b4860qds/MAINTAINERS
delete mode 100644 board/freescale/b4860qds/Makefile
delete mode 100644 board/freescale/b4860qds/b4860qds.c
delete mode 100644 board/freescale/b4860qds/b4860qds.h
delete mode 100644 board/freescale/b4860qds/b4860qds_crossbar_con.h
delete mode 100644 board/freescale/b4860qds/b4860qds_qixis.h
delete mode 100644 board/freescale/b4860qds/b4_pbi.cfg
delete mode 100644 board/freescale/b4860qds/b4_rcw.cfg
delete mode 100644 board/freescale/b4860qds/ddr.c
delete mode 100644 board/freescale/b4860qds/eth_b4860qds.c
delete mode 100644 board/freescale/b4860qds/law.c
delete mode 100644 board/freescale/b4860qds/pci.c
delete mode 100644 board/freescale/b4860qds/spl.c
delete mode 100644 board/freescale/b4860qds/tlb.c
delete mode 100644 configs/B4420QDS_NAND_defconfig
delete mode 100644 configs/B4420QDS_SPIFLASH_defconfig
delete mode 100644 configs/B4420QDS_defconfig
delete mode 100644 configs/B4860QDS_NAND_defconfig
delete mode 100644 configs/B4860QDS_SECURE_BOOT_defconfig
delete mode 100644 configs/B4860QDS_SPIFLASH_defconfig
delete mode 100644 configs/B4860QDS_SRIO_PCIE_BOOT_defconfig
delete mode 100644 configs/B4860QDS_defconfig
delete mode 100644 include/configs/B4860QDS.h
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 6fc6ea8fef..dca83f4408 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -1589,7 +1589,6 @@ config SYS_FSL_LBC_CLK_DIV
Defines divider of platform clock(clock input to
eLBC controller).
-source "board/freescale/b4860qds/Kconfig"
source "board/freescale/bsc9131rdb/Kconfig"
source "board/freescale/bsc9132qds/Kconfig"
source "board/freescale/c29xpcie/Kconfig"
diff --git a/board/freescale/b4860qds/Kconfig b/board/freescale/b4860qds/Kconfig
deleted file mode 100644
index 9bb667ab4f..0000000000
--- a/board/freescale/b4860qds/Kconfig
+++ /dev/null
@@ -1,14 +0,0 @@
-if TARGET_B4860QDS || TARGET_B4420QDS
-
-config SYS_BOARD
- default "b4860qds"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "B4860QDS"
-
-source "board/freescale/common/Kconfig"
-
-endif
diff --git a/board/freescale/b4860qds/MAINTAINERS b/board/freescale/b4860qds/MAINTAINERS
deleted file mode 100644
index 34ac099e44..0000000000
--- a/board/freescale/b4860qds/MAINTAINERS
+++ /dev/null
@@ -1,17 +0,0 @@
-B4860QDS BOARD
-M: Ashish Kumar <ashish.kumar@nxp.com>
-S: Maintained
-F: board/freescale/b4860qds/
-F: include/configs/B4860QDS.h
-F: configs/B4420QDS_defconfig
-F: configs/B4420QDS_NAND_defconfig
-F: configs/B4420QDS_SPIFLASH_defconfig
-F: configs/B4860QDS_defconfig
-F: configs/B4860QDS_NAND_defconfig
-F: configs/B4860QDS_SPIFLASH_defconfig
-F: configs/B4860QDS_SRIO_PCIE_BOOT_defconfig
-
-B4860QDS_SECURE_BOOT BOARD
-M: Ruchika Gupta <ruchika.gupta@nxp.com>
-S: Maintained
-F: configs/B4860QDS_SECURE_BOOT_defconfig
diff --git a/board/freescale/b4860qds/Makefile b/board/freescale/b4860qds/Makefile
deleted file mode 100644
index c0ba2c0168..0000000000
--- a/board/freescale/b4860qds/Makefile
+++ /dev/null
@@ -1,16 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2012 Freescale Semiconductor, Inc.
-
-ifdef CONFIG_SPL_BUILD
-obj-y += spl.o
-else
-obj-y += b4860qds.o
-obj-$(CONFIG_TARGET_B4860QDS) += eth_b4860qds.o
-obj-$(CONFIG_TARGET_B4420QDS) += eth_b4860qds.o
-obj-$(CONFIG_PCI) += pci.o
-endif
-
-obj-y += ddr.o
-obj-y += law.o
-obj-y += tlb.o
diff --git a/board/freescale/b4860qds/b4860qds.c b/board/freescale/b4860qds/b4860qds.c
deleted file mode 100644
index e10f948ae5..0000000000
--- a/board/freescale/b4860qds/b4860qds.c
+++ /dev/null
@@ -1,1274 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2011-2012 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <env.h>
-#include <fdt_support.h>
-#include <i2c.h>
-#include <image.h>
-#include <init.h>
-#include <irq_func.h>
-#include <log.h>
-#include <netdev.h>
-#include <linux/compiler.h>
-#include <asm/mmu.h>
-#include <asm/processor.h>
-#include <linux/delay.h>
-#include <linux/errno.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_law.h>
-#include <asm/fsl_serdes.h>
-#include <asm/fsl_liodn.h>
-#include <fm_eth.h>
-#include <hwconfig.h>
-
-#include "../common/qixis.h"
-#include "../common/vsc3316_3308.h"
-#include "../common/idt8t49n222a_serdes_clk.h"
-#include "../common/zm7300.h"
-#include "b4860qds.h"
-#include "b4860qds_qixis.h"
-#include "b4860qds_crossbar_con.h"
-
-#define CLK_MUX_SEL_MASK 0x4
-#define ETH_PHY_CLK_OUT 0x4
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
- char buf[64];
- u8 sw;
- struct cpu_type *cpu = gd->arch.cpu;
- static const char *const freq[] = {"100", "125", "156.25", "161.13",
- "122.88", "122.88", "122.88"};
- int clock;
-
- printf("Board: %sQDS, ", cpu->name);
- printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ",
- QIXIS_READ(id), QIXIS_READ(arch));
-
- sw = QIXIS_READ(brdcfg[0]);
- sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
-
- if (sw < 0x8)
- printf("vBank: %d\n", sw);
- else if (sw >= 0x8 && sw <= 0xE)
- puts("NAND\n");
- else
- printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
-
- printf("FPGA: v%d (%s), build %d",
- (int)QIXIS_READ(scver), qixis_read_tag(buf),
- (int)qixis_read_minor());
- /* the timestamp string contains "\n"@the end */
- printf(" on %s", qixis_read_time(buf));
-
- /*
- * Display the actual SERDES reference clocks as configured by the
- * dip switches on the board. Note that the SWx registers could
- * technically be set to force the reference clocks to match the
- * values that the SERDES expects (or vice versa). For now, however,
- * we just display both values and hope the user notices when they
- * don't match.
- */
- puts("SERDES Reference Clocks: ");
- sw = QIXIS_READ(brdcfg[2]);
- clock = (sw >> 5) & 7;
- printf("Bank1=%sMHz ", freq[clock]);
- sw = QIXIS_READ(brdcfg[4]);
- clock = (sw >> 6) & 3;
- printf("Bank2=%sMHz\n", freq[clock]);
-
- return 0;
-}
-
-int select_i2c_ch_pca(u8 ch)
-{
- int ret;
-
- /* Selecting proper channel via PCA*/
- ret = i2c_write(I2C_MUX_PCA_ADDR, 0x0, 1, &ch, 1);
- if (ret) {
- printf("PCA: failed to select proper channel.\n");
- return ret;
- }
-
- return 0;
-}
-
-/*
- * read_voltage from sensor on I2C bus
- * We use average of 4 readings, waiting for 532us befor another reading
- */
-#define WAIT_FOR_ADC 532 /* wait for 532 microseconds for ADC */
-#define NUM_READINGS 4 /* prefer to be power of 2 for efficiency */
-
-static inline int read_voltage(void)
-{
- int i, ret, voltage_read = 0;
- u16 vol_mon;
-
- for (i = 0; i < NUM_READINGS; i++) {
- ret = i2c_read(I2C_VOL_MONITOR_ADDR,
- I2C_VOL_MONITOR_BUS_V_OFFSET, 1, (void *)&vol_mon, 2);
- if (ret) {
- printf("VID: failed to read core voltage\n");
- return ret;
- }
- if (vol_mon & I2C_VOL_MONITOR_BUS_V_OVF) {
- printf("VID: Core voltage sensor error\n");
- return -1;
- }
- debug("VID: bus voltage reads 0x%04x\n", vol_mon);
- /* LSB = 4mv */
- voltage_read += (vol_mon >> I2C_VOL_MONITOR_BUS_V_SHIFT) * 4;
- udelay(WAIT_FOR_ADC);
- }
- /* calculate the average */
- voltage_read /= NUM_READINGS;
-
- return voltage_read;
-}
-
-static int adjust_vdd(ulong vdd_override)
-{
- int re_enable = disable_interrupts();
- ccsr_gur_t __iomem *gur =
- (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- u32 fusesr;
- u8 vid;
- int vdd_target, vdd_last;
- int existing_voltage, temp_voltage, voltage; /* all in 1/10 mV */
- int ret;
- unsigned int orig_i2c_speed;
- unsigned long vdd_string_override;
- char *vdd_string;
- static const uint16_t vdd[32] = {
- 0, /* unused */
- 9875, /* 0.9875V */
- 9750,
- 9625,
- 9500,
- 9375,
- 9250,
- 9125,
- 9000,
- 8875,
- 8750,
- 8625,
- 8500,
- 8375,
- 8250,
- 8125,
- 10000, /* 1.0000V */
- 10125,
- 10250,
- 10375,
- 10500,
- 10625,
- 10750,
- 10875,
- 11000,
- 0, /* reserved */
- };
- struct vdd_drive {
- u8 vid;
- unsigned voltage;
- };
-
- ret = select_i2c_ch_pca(I2C_MUX_CH_VOL_MONITOR);
- if (ret) {
- printf("VID: I2c failed to switch channel\n");
- ret = -1;
- goto exit;
- }
-
- /* get the voltage ID from fuse status register */
- fusesr = in_be32(&gur->dcfg_fusesr);
- vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_VID_SHIFT) &
- FSL_CORENET_DCFG_FUSESR_VID_MASK;
- if (vid == FSL_CORENET_DCFG_FUSESR_VID_MASK) {
- vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) &
- FSL_CORENET_DCFG_FUSESR_ALTVID_MASK;
- }
- vdd_target = vdd[vid];
- debug("VID:Reading from from fuse,vid=%x vdd is %dmV\n",
- vid, vdd_target/10);
-
- /* check override variable for overriding VDD */
- vdd_string = env_get("b4qds_vdd_mv");
- if (vdd_override == 0 && vdd_string &&
- !strict_strtoul(vdd_string, 10, &vdd_string_override))
- vdd_override = vdd_string_override;
- if (vdd_override >= 819 && vdd_override <= 1212) {
- vdd_target = vdd_override * 10; /* convert to 1/10 mV */
- debug("VDD override is %lu\n", vdd_override);
- } else if (vdd_override != 0) {
- printf("Invalid value.\n");
- }
-
- if (vdd_target == 0) {
- printf("VID: VID not used\n");
- ret = 0;
- goto exit;
- }
-
- /*
- * Read voltage monitor to check real voltage.
- * Voltage monitor LSB is 4mv.
- */
- vdd_last = read_voltage();
- if (vdd_last < 0) {
- printf("VID: abort VID adjustment\n");
- ret = -1;
- goto exit;
- }
-
- debug("VID: Core voltage is@%d mV\n", vdd_last);
- ret = select_i2c_ch_pca(I2C_MUX_CH_DPM);
- if (ret) {
- printf("VID: I2c failed to switch channel to DPM\n");
- ret = -1;
- goto exit;
- }
-
- /* Round up to the value of step of Voltage regulator */
- voltage = roundup(vdd_target, ZM_STEP);
- debug("VID: rounded up voltage = %d\n", voltage);
-
- /* lower the speed to 100kHz to access ZM7300 device */
- debug("VID: Setting bus speed to 100KHz if not already set\n");
- orig_i2c_speed = i2c_get_bus_speed();
- if (orig_i2c_speed != 100000)
- i2c_set_bus_speed(100000);
-
- /* Read the existing level on board, if equal to requsted one,
- no need to re-set */
- existing_voltage = zm_read_voltage();
-
- /* allowing the voltage difference of one step 0.0125V acceptable */
- if ((existing_voltage >= voltage) &&
- (existing_voltage < (voltage + ZM_STEP))) {
- debug("VID: voltage already set as requested,returning\n");
- ret = existing_voltage;
- goto out;
- }
- debug("VID: Changing voltage for board from %dmV to %dmV\n",
- existing_voltage/10, voltage/10);
-
- if (zm_disable_wp() < 0) {
- ret = -1;
- goto out;
- }
- /* Change Voltage: the change is done through all the steps in the
- way, to avoid reset to the board due to power good signal fail
- in big voltage change gap jump.
- */
- if (existing_voltage > voltage) {
- temp_voltage = existing_voltage - ZM_STEP;
- while (temp_voltage >= voltage) {
- ret = zm_write_voltage(temp_voltage);
- if (ret == temp_voltage) {
- temp_voltage -= ZM_STEP;
- } else {
- /* ZM7300 device failed to set
- * the voltage */
- printf
- ("VID:Stepping down vol failed:%dmV\n",
- temp_voltage/10);
- ret = -1;
- goto out;
- }
- }
- } else {
- temp_voltage = existing_voltage + ZM_STEP;
- while (temp_voltage < (voltage + ZM_STEP)) {
- ret = zm_write_voltage(temp_voltage);
- if (ret == temp_voltage) {
- temp_voltage += ZM_STEP;
- } else {
- /* ZM7300 device failed to set
- * the voltage */
- printf
- ("VID:Stepping up vol failed:%dmV\n",
- temp_voltage/10);
- ret = -1;
- goto out;
- }
- }
- }
-
- if (zm_enable_wp() < 0)
- ret = -1;
-
- /* restore the speed to 400kHz */
-out: debug("VID: Restore the I2C bus speed to %dKHz\n",
- orig_i2c_speed/1000);
- i2c_set_bus_speed(orig_i2c_speed);
- if (ret < 0)
- goto exit;
-
- ret = select_i2c_ch_pca(I2C_MUX_CH_VOL_MONITOR);
- if (ret) {
- printf("VID: I2c failed to switch channel\n");
- ret = -1;
- goto exit;
- }
- vdd_last = read_voltage();
- select_i2c_ch_pca(I2C_CH_DEFAULT);
-
- if (vdd_last > 0)
- printf("VID: Core voltage %d mV\n", vdd_last);
- else
- ret = -1;
-
-exit:
- if (re_enable)
- enable_interrupts();
- return ret;
-}
-
-int configure_vsc3316_3308(void)
-{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- unsigned int num_vsc16_con, num_vsc08_con;
- u32 serdes1_prtcl, serdes2_prtcl;
- int ret;
- char buffer[HWCONFIG_BUFFER_SIZE];
- char *buf = NULL;
-
- serdes1_prtcl = in_be32(&gur->rcwsr[4]) &
- FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
- if (!serdes1_prtcl) {
- printf("SERDES1 is not enabled\n");
- return 0;
- }
- serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
- debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl);
-
- serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
- FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
- if (!serdes2_prtcl) {
- printf("SERDES2 is not enabled\n");
- return 0;
- }
- serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
- debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl);
-
- switch (serdes1_prtcl) {
- case 0x29:
- case 0x2a:
- case 0x2C:
- case 0x2D:
- case 0x2E:
- /*
- * Configuration:
- * SERDES: 1
- * Lanes: A,B: SGMII
- * Lanes: C,D,E,F,G,H: CPRI
- */
- debug("Configuring crossbar to use onboard SGMII PHYs:"
- "srds_prctl:%x\n", serdes1_prtcl);
- num_vsc16_con = NUM_CON_VSC3316;
- /* Configure VSC3316 crossbar switch */
- ret = select_i2c_ch_pca(I2C_CH_VSC3316);
- if (!ret) {
- ret = vsc3316_config(VSC3316_TX_ADDRESS,
- vsc16_tx_4sfp_sgmii_12_56,
- num_vsc16_con);
- if (ret)
- return ret;
- ret = vsc3316_config(VSC3316_RX_ADDRESS,
- vsc16_rx_4sfp_sgmii_12_56,
- num_vsc16_con);
- if (ret)
- return ret;
- } else {
- return ret;
- }
- break;
-
- case 0x01:
- case 0x02:
- case 0x04:
- case 0x05:
- case 0x06:
- case 0x07:
- case 0x08:
- case 0x09:
- case 0x0A:
- case 0x0B:
- case 0x0C:
- case 0x2F:
- case 0x30:
- case 0x32:
- case 0x33:
- case 0x34:
- case 0x39:
- case 0x3A:
- case 0x3C:
- case 0x3D:
- case 0x5C:
- case 0x5D:
- /*
- * Configuration:
- * SERDES: 1
- * Lanes: A,B: AURORA
- * Lanes: C,d: SGMII
- * Lanes: E,F,G,H: CPRI
- */
- debug("Configuring crossbar for Aurora, SGMII 3 and 4,"
- " and CPRI. srds_prctl:%x\n", serdes1_prtcl);
- num_vsc16_con = NUM_CON_VSC3316;
- /* Configure VSC3316 crossbar switch */
- ret = select_i2c_ch_pca(I2C_CH_VSC3316);
- if (!ret) {
- ret = vsc3316_config(VSC3316_TX_ADDRESS,
- vsc16_tx_sfp_sgmii_aurora,
- num_vsc16_con);
- if (ret)
- return ret;
- ret = vsc3316_config(VSC3316_RX_ADDRESS,
- vsc16_rx_sfp_sgmii_aurora,
- num_vsc16_con);
- if (ret)
- return ret;
- } else {
- return ret;
- }
- break;
-
-#ifdef CONFIG_ARCH_B4420
- case 0x17:
- case 0x18:
- /*
- * Configuration:
- * SERDES: 1
- * Lanes: A,B,C,D: SGMII
- * Lanes: E,F,G,H: CPRI
- */
- debug("Configuring crossbar to use onboard SGMII PHYs:"
- "srds_prctl:%x\n", serdes1_prtcl);
- num_vsc16_con = NUM_CON_VSC3316;
- /* Configure VSC3316 crossbar switch */
- ret = select_i2c_ch_pca(I2C_CH_VSC3316);
- if (!ret) {
- ret = vsc3316_config(VSC3316_TX_ADDRESS,
- vsc16_tx_sgmii_lane_cd, num_vsc16_con);
- if (ret)
- return ret;
- ret = vsc3316_config(VSC3316_RX_ADDRESS,
- vsc16_rx_sgmii_lane_cd, num_vsc16_con);
- if (ret)
- return ret;
- } else {
- return ret;
- }
- break;
-#endif
-
- case 0x3E:
- case 0x0D:
- case 0x0E:
- case 0x12:
- num_vsc16_con = NUM_CON_VSC3316;
- /* Configure VSC3316 crossbar switch */
- ret = select_i2c_ch_pca(I2C_CH_VSC3316);
- if (!ret) {
- ret = vsc3316_config(VSC3316_TX_ADDRESS,
- vsc16_tx_sfp, num_vsc16_con);
- if (ret)
- return ret;
- ret = vsc3316_config(VSC3316_RX_ADDRESS,
- vsc16_rx_sfp, num_vsc16_con);
- if (ret)
- return ret;
- } else {
- return ret;
- }
- break;
- default:
- printf("WARNING:VSC crossbars programming not supported for:%x"
- " SerDes1 Protocol.\n", serdes1_prtcl);
- return -1;
- }
-
- num_vsc08_con = NUM_CON_VSC3308;
- /* Configure VSC3308 crossbar switch */
- ret = select_i2c_ch_pca(I2C_CH_VSC3308);
- switch (serdes2_prtcl) {
-#ifdef CONFIG_ARCH_B4420
- case 0x9d:
-#endif
- case 0x9E:
- case 0x9A:
- case 0x98:
- case 0x48:
- case 0x49:
- case 0x4E:
- case 0x79:
- case 0x7A:
- if (!ret) {
- ret = vsc3308_config(VSC3308_TX_ADDRESS,
- vsc08_tx_amc, num_vsc08_con);
- if (ret)
- return ret;
- ret = vsc3308_config(VSC3308_RX_ADDRESS,
- vsc08_rx_amc, num_vsc08_con);
- if (ret)
- return ret;
- } else {
- return ret;
- }
- break;
- case 0x80:
- case 0x81:
- case 0x82:
- case 0x83:
- case 0x84:
- case 0x85:
- case 0x86:
- case 0x87:
- case 0x88:
- case 0x89:
- case 0x8a:
- case 0x8b:
- case 0x8c:
- case 0x8d:
- case 0x8e:
- case 0xb1:
- case 0xb2:
- if (!ret) {
- /*
- * Extract hwconfig from environment since environment
- * is not setup properly yet
- */
- env_get_f("hwconfig", buffer, sizeof(buffer));
- buf = buffer;
-
- if (hwconfig_subarg_cmp_f("fsl_b4860_serdes2",
- "sfp_amc", "sfp", buf)) {
-#ifdef CONFIG_SYS_FSL_B4860QDS_XFI_ERR
- /* change default VSC3308 for XFI erratum */
- ret = vsc3308_config_adjust(VSC3308_TX_ADDRESS,
- vsc08_tx_sfp, num_vsc08_con);
- if (ret)
- return ret;
-
- ret = vsc3308_config_adjust(VSC3308_RX_ADDRESS,
- vsc08_rx_sfp, num_vsc08_con);
- if (ret)
- return ret;
-#else
- ret = vsc3308_config(VSC3308_TX_ADDRESS,
- vsc08_tx_sfp, num_vsc08_con);
- if (ret)
- return ret;
-
- ret = vsc3308_config(VSC3308_RX_ADDRESS,
- vsc08_rx_sfp, num_vsc08_con);
- if (ret)
- return ret;
-#endif
- } else {
- ret = vsc3308_config(VSC3308_TX_ADDRESS,
- vsc08_tx_amc, num_vsc08_con);
- if (ret)
- return ret;
-
- ret = vsc3308_config(VSC3308_RX_ADDRESS,
- vsc08_rx_amc, num_vsc08_con);
- if (ret)
- return ret;
- }
-
- } else {
- return ret;
- }
- break;
- default:
- printf("WARNING:VSC crossbars programming not supported for: %x"
- " SerDes2 Protocol.\n", serdes2_prtcl);
- return -1;
- }
-
- return 0;
-}
-
-static int calibrate_pll(serdes_corenet_t *srds_regs, int pll_num)
-{
- u32 rst_err;
-
- /* Steps For SerDes PLLs reset and reconfiguration
- * or PLL power-up procedure
- */
- debug("CALIBRATE PLL:%d\n", pll_num);
- clrbits_be32(&srds_regs->bank[pll_num].rstctl,
- SRDS_RSTCTL_SDRST_B);
- udelay(10);
- clrbits_be32(&srds_regs->bank[pll_num].rstctl,
- (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B));
- udelay(10);
- setbits_be32(&srds_regs->bank[pll_num].rstctl,
- SRDS_RSTCTL_RST);
- setbits_be32(&srds_regs->bank[pll_num].rstctl,
- (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
- | SRDS_RSTCTL_SDRST_B));
-
- udelay(20);
-
- /* Check whether PLL has been locked or not */
- rst_err = in_be32(&srds_regs->bank[pll_num].rstctl) &
- SRDS_RSTCTL_RSTERR;
- rst_err >>= SRDS_RSTCTL_RSTERR_SHIFT;
- debug("RST_ERR value for PLL %d is: 0x%x:\n", pll_num, rst_err);
- if (rst_err)
- return rst_err;
-
- return rst_err;
-}
-
-static int check_pll_locks(serdes_corenet_t *srds_regs, int pll_num)
-{
- int ret = 0;
- u32 fcap, dcbias, bcap, pllcr1, pllcr0;
-
- if (calibrate_pll(srds_regs, pll_num)) {
- /* STEP 1 */
- /* Read fcap, dcbias and bcap value */
- clrbits_be32(&srds_regs->bank[pll_num].pllcr0,
- SRDS_PLLCR0_DCBIAS_OUT_EN);
- fcap = in_be32(&srds_regs->bank[pll_num].pllsr2) &
- SRDS_PLLSR2_FCAP;
- fcap >>= SRDS_PLLSR2_FCAP_SHIFT;
- bcap = in_be32(&srds_regs->bank[pll_num].pllsr2) &
- SRDS_PLLSR2_BCAP_EN;
- bcap >>= SRDS_PLLSR2_BCAP_EN_SHIFT;
- setbits_be32(&srds_regs->bank[pll_num].pllcr0,
- SRDS_PLLCR0_DCBIAS_OUT_EN);
- dcbias = in_be32(&srds_regs->bank[pll_num].pllsr2) &
- SRDS_PLLSR2_DCBIAS;
- dcbias >>= SRDS_PLLSR2_DCBIAS_SHIFT;
- debug("values of bcap:%x, fcap:%x and dcbias:%x\n",
- bcap, fcap, dcbias);
- if (fcap == 0 && bcap == 1) {
- /* Step 3 */
- clrbits_be32(&srds_regs->bank[pll_num].rstctl,
- (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
- | SRDS_RSTCTL_SDRST_B));
- clrbits_be32(&srds_regs->bank[pll_num].pllcr1,
- SRDS_PLLCR1_BCAP_EN);
- setbits_be32(&srds_regs->bank[pll_num].pllcr1,
- SRDS_PLLCR1_BCAP_OVD);
- if (calibrate_pll(srds_regs, pll_num)) {
- /*save the fcap, dcbias and bcap values*/
- clrbits_be32(&srds_regs->bank[pll_num].pllcr0,
- SRDS_PLLCR0_DCBIAS_OUT_EN);
- fcap = in_be32(&srds_regs->bank[pll_num].pllsr2)
- & SRDS_PLLSR2_FCAP;
- fcap >>= SRDS_PLLSR2_FCAP_SHIFT;
- bcap = in_be32(&srds_regs->bank[pll_num].pllsr2)
- & SRDS_PLLSR2_BCAP_EN;
- bcap >>= SRDS_PLLSR2_BCAP_EN_SHIFT;
- setbits_be32(&srds_regs->bank[pll_num].pllcr0,
- SRDS_PLLCR0_DCBIAS_OUT_EN);
- dcbias = in_be32
- (&srds_regs->bank[pll_num].pllsr2) &
- SRDS_PLLSR2_DCBIAS;
- dcbias >>= SRDS_PLLSR2_DCBIAS_SHIFT;
-
- /* Step 4*/
- clrbits_be32(&srds_regs->bank[pll_num].rstctl,
- (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
- | SRDS_RSTCTL_SDRST_B));
- setbits_be32(&srds_regs->bank[pll_num].pllcr1,
- SRDS_PLLCR1_BYP_CAL);
- clrbits_be32(&srds_regs->bank[pll_num].pllcr1,
- SRDS_PLLCR1_BCAP_EN);
- setbits_be32(&srds_regs->bank[pll_num].pllcr1,
- SRDS_PLLCR1_BCAP_OVD);
- /* change the fcap and dcbias to the saved
- * values from Step 3 */
- clrbits_be32(&srds_regs->bank[pll_num].pllcr1,
- SRDS_PLLCR1_PLL_FCAP);
- pllcr1 = (in_be32
- (&srds_regs->bank[pll_num].pllcr1)|
- (fcap << SRDS_PLLCR1_PLL_FCAP_SHIFT));
- out_be32(&srds_regs->bank[pll_num].pllcr1,
- pllcr1);
- clrbits_be32(&srds_regs->bank[pll_num].pllcr0,
- SRDS_PLLCR0_DCBIAS_OVRD);
- pllcr0 = (in_be32
- (&srds_regs->bank[pll_num].pllcr0)|
- (dcbias << SRDS_PLLCR0_DCBIAS_OVRD_SHIFT));
- out_be32(&srds_regs->bank[pll_num].pllcr0,
- pllcr0);
- ret = calibrate_pll(srds_regs, pll_num);
- if (ret)
- return ret;
- } else {
- goto out;
- }
- } else { /* Step 5 */
- clrbits_be32(&srds_regs->bank[pll_num].rstctl,
- (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
- | SRDS_RSTCTL_SDRST_B));
- udelay(10);
- /* Change the fcap, dcbias, and bcap to the
- * values from Step 1 */
- setbits_be32(&srds_regs->bank[pll_num].pllcr1,
- SRDS_PLLCR1_BYP_CAL);
- clrbits_be32(&srds_regs->bank[pll_num].pllcr1,
- SRDS_PLLCR1_PLL_FCAP);
- pllcr1 = (in_be32(&srds_regs->bank[pll_num].pllcr1)|
- (fcap << SRDS_PLLCR1_PLL_FCAP_SHIFT));
- out_be32(&srds_regs->bank[pll_num].pllcr1,
- pllcr1);
- clrbits_be32(&srds_regs->bank[pll_num].pllcr0,
- SRDS_PLLCR0_DCBIAS_OVRD);
- pllcr0 = (in_be32(&srds_regs->bank[pll_num].pllcr0)|
- (dcbias << SRDS_PLLCR0_DCBIAS_OVRD_SHIFT));
- out_be32(&srds_regs->bank[pll_num].pllcr0,
- pllcr0);
- clrbits_be32(&srds_regs->bank[pll_num].pllcr1,
- SRDS_PLLCR1_BCAP_EN);
- setbits_be32(&srds_regs->bank[pll_num].pllcr1,
- SRDS_PLLCR1_BCAP_OVD);
- ret = calibrate_pll(srds_regs, pll_num);
- if (ret)
- return ret;
- }
- }
-out:
- return 0;
-}
-
-static int check_serdes_pll_locks(void)
-{
- serdes_corenet_t *srds1_regs =
- (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
- serdes_corenet_t *srds2_regs =
- (void *)CONFIG_SYS_FSL_CORENET_SERDES2_ADDR;
- int i, ret1, ret2;
-
- debug("\nSerDes1 Lock check\n");
- for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) {
- ret1 = check_pll_locks(srds1_regs, i);
- if (ret1) {
- printf("SerDes1, PLL:%d didnt lock\n", i);
- return ret1;
- }
- }
- debug("\nSerDes2 Lock check\n");
- for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) {
- ret2 = check_pll_locks(srds2_regs, i);
- if (ret2) {
- printf("SerDes2, PLL:%d didnt lock\n", i);
- return ret2;
- }
- }
-
- return 0;
-}
-
-int config_serdes1_refclks(void)
-{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- serdes_corenet_t *srds_regs =
- (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
- u32 serdes1_prtcl, lane;
- unsigned int flag_sgmii_aurora_prtcl = 0;
- int i;
- int ret = 0;
-
- serdes1_prtcl = in_be32(&gur->rcwsr[4]) &
- FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
- if (!serdes1_prtcl) {
- printf("SERDES1 is not enabled\n");
- return -1;
- }
- serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
- debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl);
-
- /* To prevent generation of reset request from SerDes
- * while changing the refclks, By setting SRDS_RST_MSK bit,
- * SerDes reset event cannot cause a reset request
- */
- setbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK);
-
- /* Reconfigure IDT idt8t49n222a device for CPRI to work
- * For this SerDes1's Refclk1 and refclk2 need to be set
- * to 122.88MHz
- */
- switch (serdes1_prtcl) {
- case 0x29:
- case 0x2A:
- case 0x2C:
- case 0x2D:
- case 0x2E:
- case 0x01:
- case 0x02:
- case 0x04:
- case 0x05:
- case 0x06:
- case 0x07:
- case 0x08:
- case 0x09:
- case 0x0A:
- case 0x0B:
- case 0x0C:
- case 0x2F:
- case 0x30:
- case 0x32:
- case 0x33:
- case 0x34:
- case 0x39:
- case 0x3A:
- case 0x3C:
- case 0x3D:
- case 0x5C:
- case 0x5D:
- debug("Configuring idt8t49n222a for CPRI SerDes clks:"
- " for srds_prctl:%x\n", serdes1_prtcl);
- ret = select_i2c_ch_pca(I2C_CH_IDT);
- if (!ret) {
- ret = set_serdes_refclk(IDT_SERDES1_ADDRESS, 1,
- SERDES_REFCLK_122_88,
- SERDES_REFCLK_122_88, 0);
- if (ret) {
- printf("IDT8T49N222A configuration failed.\n");
- goto out;
- } else
- debug("IDT8T49N222A configured.\n");
- } else {
- goto out;
- }
- select_i2c_ch_pca(I2C_CH_DEFAULT);
-
- /* Change SerDes1's Refclk1 to 125MHz for on board
- * SGMIIs or Aurora to work
- */
- for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
- enum srds_prtcl lane_prtcl = serdes_get_prtcl
- (0, serdes1_prtcl, lane);
- switch (lane_prtcl) {
- case SGMII_FM1_DTSEC1:
- case SGMII_FM1_DTSEC2:
- case SGMII_FM1_DTSEC3:
- case SGMII_FM1_DTSEC4:
- case SGMII_FM1_DTSEC5:
- case SGMII_FM1_DTSEC6:
- case AURORA:
- flag_sgmii_aurora_prtcl++;
- break;
- default:
- break;
- }
- }
-
- if (flag_sgmii_aurora_prtcl)
- QIXIS_WRITE(brdcfg[4], QIXIS_SRDS1CLK_125);
-
- /* Steps For SerDes PLLs reset and reconfiguration after
- * changing SerDes's refclks
- */
- for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) {
- debug("For PLL%d reset and reconfiguration after"
- " changing refclks\n", i+1);
- clrbits_be32(&srds_regs->bank[i].rstctl,
- SRDS_RSTCTL_SDRST_B);
- udelay(10);
- clrbits_be32(&srds_regs->bank[i].rstctl,
- (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B));
- udelay(10);
- setbits_be32(&srds_regs->bank[i].rstctl,
- SRDS_RSTCTL_RST);
- setbits_be32(&srds_regs->bank[i].rstctl,
- (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
- | SRDS_RSTCTL_SDRST_B));
- }
- break;
- default:
- printf("WARNING:IDT8T49N222A configuration not"
- " supported for:%x SerDes1 Protocol.\n",
- serdes1_prtcl);
- }
-
-out:
- /* Clearing SRDS_RST_MSK bit as now
- * SerDes reset event can cause a reset request
- */
- clrbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK);
- return ret;
-}
-
-int config_serdes2_refclks(void)
-{
- ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- serdes_corenet_t *srds2_regs =
- (void *)CONFIG_SYS_FSL_CORENET_SERDES2_ADDR;
- u32 serdes2_prtcl;
- int ret = 0;
- int i;
-
- serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
- FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
- if (!serdes2_prtcl) {
- debug("SERDES2 is not enabled\n");
- return -ENODEV;
- }
- serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
- debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl);
-
- /* To prevent generation of reset request from SerDes
- * while changing the refclks, By setting SRDS_RST_MSK bit,
- * SerDes reset event cannot cause a reset request
- */
- setbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK);
-
- /* Reconfigure IDT idt8t49n222a device for PCIe SATA to work
- * For this SerDes2's Refclk1 need to be set to 100MHz
- */
- switch (serdes2_prtcl) {
-#ifdef CONFIG_ARCH_B4420
- case 0x9d:
-#endif
- case 0x9E:
- case 0x9A:
- /* fallthrough */
- case 0xb1:
- case 0xb2:
- debug("Configuring IDT for PCIe SATA for srds_prctl:%x\n",
- serdes2_prtcl);
- ret = select_i2c_ch_pca(I2C_CH_IDT);
- if (!ret) {
- ret = set_serdes_refclk(IDT_SERDES2_ADDRESS, 2,
- SERDES_REFCLK_100,
- SERDES_REFCLK_156_25, 0);
- if (ret) {
- printf("IDT8T49N222A configuration failed.\n");
- goto out;
- } else
- debug("IDT8T49N222A configured.\n");
- } else {
- goto out;
- }
- select_i2c_ch_pca(I2C_CH_DEFAULT);
-
- /* Steps For SerDes PLLs reset and reconfiguration after
- * changing SerDes's refclks
- */
- for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) {
- clrbits_be32(&srds2_regs->bank[i].rstctl,
- SRDS_RSTCTL_SDRST_B);
- udelay(10);
- clrbits_be32(&srds2_regs->bank[i].rstctl,
- (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B));
- udelay(10);
- setbits_be32(&srds2_regs->bank[i].rstctl,
- SRDS_RSTCTL_RST);
- setbits_be32(&srds2_regs->bank[i].rstctl,
- (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
- | SRDS_RSTCTL_SDRST_B));
-
- udelay(10);
- }
- break;
- default:
- printf("IDT configuration not supported for:%x S2 Protocol.\n",
- serdes2_prtcl);
- }
-
-out:
- /* Clearing SRDS_RST_MSK bit as now
- * SerDes reset event can cause a reset request
- */
- clrbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK);
- return ret;
-}
-
-int board_early_init_r(void)
-{
- const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
- int flash_esel = find_tlb_idx((void *)flashbase, 1);
- int ret;
- u32 svr = SVR_SOC_VER(get_svr());
-
- /* Create law for MAPLE only for personalities having MAPLE */
- if ((svr == SVR_B4860) || (svr == SVR_B4440) ||
- (svr == SVR_B4420) || (svr == SVR_B4220)) {
- set_next_law(CONFIG_SYS_MAPLE_MEM_PHYS, LAW_SIZE_16M,
- LAW_TRGT_IF_MAPLE);
- }
-
- /*
- * Remap Boot flash + PROMJET region to caching-inhibited
- * so that flash can be erased properly.
- */
-
- /* Flush d-cache and invalidate i-cache of any FLASH data */
- flush_dcache();
- invalidate_icache();
-
- if (flash_esel == -1) {
- /* very unlikely unless something is messed up */
- puts("Error: Could not find TLB for FLASH BASE\n");
- flash_esel = 2; /* give our best effort to continue */
- } else {
- /* invalidate existing TLB entry for flash + promjet */
- disable_tlb(flash_esel);
- }
-
- set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, flash_esel, BOOKE_PAGESZ_256M, 1);
-
- /*
- * Adjust core voltage according to voltage ID
- * This function changes I2C mux to channel 2.
- */
- if (adjust_vdd(0) < 0)
- printf("Warning: Adjusting core voltage failed\n");
-
- /* SerDes1 refclks need to be set again, as default clks
- * are not suitable for CPRI and onboard SGMIIs to work
- * simultaneously.
- * This function will set SerDes1's Refclk1 and refclk2
- * as per SerDes1 protocols
- */
- if (config_serdes1_refclks())
- printf("SerDes1 Refclks couldn't set properly.\n");
- else
- printf("SerDes1 Refclks have been set.\n");
-
- /* SerDes2 refclks need to be set again, as default clks
- * are not suitable for PCIe SATA to work
- * This function will set SerDes2's Refclk1 and refclk2
- * for SerDes2 protocols having PCIe in them
- * for PCIe SATA to work
- */
- ret = config_serdes2_refclks();
- if (!ret)
- printf("SerDes2 Refclks have been set.\n");
- else if (ret == -ENODEV)
- printf("SerDes disable, Refclks couldn't change.\n");
- else
- printf("SerDes2 Refclk reconfiguring failed.\n");
-
-#if defined(CONFIG_SYS_FSL_ERRATUM_A006384) || \
- defined(CONFIG_SYS_FSL_ERRATUM_A006475)
- /* Rechecking the SerDes locks after all SerDes configurations
- * are done, As SerDes PLLs may not lock reliably at 5 G VCO
- * and@cold temperatures.
- * Following sequence ensure the proper locking of SerDes PLLs.
- */
- if (SVR_MAJ(get_svr()) == 1) {
- if (check_serdes_pll_locks())
- printf("SerDes plls still not locked properly.\n");
- else
- printf("SerDes plls have been locked well.\n");
- }
-#endif
-
- /* Configure VSC3316 and VSC3308 crossbar switches */
- if (configure_vsc3316_3308())
- printf("VSC:failed to configure VSC3316/3308.\n");
- else
- printf("VSC:VSC3316/3308 successfully configured.\n");
-
- select_i2c_ch_pca(I2C_CH_DEFAULT);
-
- return 0;
-}
-
-unsigned long get_board_sys_clk(void)
-{
- u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
-
- switch ((sysclk_conf & 0x0C) >> 2) {
- case QIXIS_CLK_100:
- return 100000000;
- case QIXIS_CLK_125:
- return 125000000;
- case QIXIS_CLK_133:
- return 133333333;
- }
- return 66666666;
-}
-
-unsigned long get_board_ddr_clk(void)
-{
- u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
-
- switch (ddrclk_conf & 0x03) {
- case QIXIS_CLK_100:
- return 100000000;
- case QIXIS_CLK_125:
- return 125000000;
- case QIXIS_CLK_133:
- return 133333333;
- }
- return 66666666;
-}
-
-static int serdes_refclock(u8 sw, u8 sdclk)
-{
- unsigned int clock;
- int ret = -1;
- u8 brdcfg4;
-
- if (sdclk == 1) {
- brdcfg4 = QIXIS_READ(brdcfg[4]);
- if ((brdcfg4 & CLK_MUX_SEL_MASK) == ETH_PHY_CLK_OUT)
- return SRDS_PLLCR0_RFCK_SEL_125;
- else
- clock = (sw >> 5) & 7;
- } else
- clock = (sw >> 6) & 3;
-
- switch (clock) {
- case 0:
- ret = SRDS_PLLCR0_RFCK_SEL_100;
- break;
- case 1:
- ret = SRDS_PLLCR0_RFCK_SEL_125;
- break;
- case 2:
- ret = SRDS_PLLCR0_RFCK_SEL_156_25;
- break;
- case 3:
- ret = SRDS_PLLCR0_RFCK_SEL_161_13;
- break;
- case 4:
- case 5:
- case 6:
- ret = SRDS_PLLCR0_RFCK_SEL_122_88;
- break;
- default:
- ret = -1;
- break;
- }
-
- return ret;
-}
-
-#define NUM_SRDS_BANKS 2
-
-int misc_init_r(void)
-{
- u8 sw;
- serdes_corenet_t *srds_regs =
- (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
- u32 actual[NUM_SRDS_BANKS];
- unsigned int i;
- int clock;
-
- sw = QIXIS_READ(brdcfg[2]);
- clock = serdes_refclock(sw, 1);
- if (clock >= 0)
- actual[0] = clock;
- else
- printf("Warning: SDREFCLK1 switch setting is unsupported\n");
-
- sw = QIXIS_READ(brdcfg[4]);
- clock = serdes_refclock(sw, 2);
- if (clock >= 0)
- actual[1] = clock;
- else
- printf("Warning: SDREFCLK2 switch setting unsupported\n");
-
- for (i = 0; i < NUM_SRDS_BANKS; i++) {
- u32 pllcr0 = srds_regs->bank[i].pllcr0;
- u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
- if (expected != actual[i]) {
- printf("Warning: SERDES bank %u expects reference clock"
- " %sMHz, but actual is %sMHz\n", i + 1,
- serdes_clock_to_string(expected),
- serdes_clock_to_string(actual[i]));
- }
- }
-
- return 0;
-}
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
- phys_addr_t base;
- phys_size_t size;
-
- ft_cpu_setup(blob, bd);
-
- base = env_get_bootm_low();
- size = env_get_bootm_size();
-
- fdt_fixup_memory(blob, (u64)base, (u64)size);
-
-#ifdef CONFIG_PCI
- pci_of_setup(blob, bd);
-#endif
-
- fdt_fixup_liodn(blob);
-
-#ifdef CONFIG_HAS_FSL_DR_USB
- fsl_fdt_fixup_dr_usb(blob, bd);
-#endif
-
-#ifdef CONFIG_SYS_DPAA_FMAN
- fdt_fixup_fman_ethernet(blob);
- fdt_fixup_board_enet(blob);
-#endif
-
- return 0;
-}
-
-/*
- * Dump board switch settings.
- * The bits that cannot be read/sampled via some FPGA or some
- * registers, they will be displayed as
- * underscore in binary format. mask[] has those bits.
- * Some bits are calculated differently than the actual switches
- * if booting with overriding by FPGA.
- */
-void qixis_dump_switch(void)
-{
- int i;
- u8 sw[5];
-
- /*
- * Any bit with 1 means that bit cannot be reverse engineered.
- * It will be displayed as _ in binary format.
- */
- static const u8 mask[] = {0x07, 0, 0, 0xff, 0};
- char buf[10];
- u8 brdcfg[16], dutcfg[16];
-
- for (i = 0; i < 16; i++) {
- brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i);
- dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i);
- }
-
- sw[0] = ((brdcfg[0] & 0x0f) << 4) | \
- (brdcfg[9] & 0x08);
- sw[1] = ((dutcfg[1] & 0x01) << 7) | \
- ((dutcfg[2] & 0x07) << 4) | \
- ((dutcfg[6] & 0x10) >> 1) | \
- ((dutcfg[6] & 0x80) >> 5) | \
- ((dutcfg[1] & 0x40) >> 5) | \
- (dutcfg[6] & 0x01);
- sw[2] = dutcfg[0];
- sw[3] = 0;
- sw[4] = ((brdcfg[1] & 0x30) << 2) | \
- ((brdcfg[1] & 0xc0) >> 2) | \
- (brdcfg[1] & 0x0f);
-
- puts("DIP switch settings:\n");
- for (i = 0; i < 5; i++) {
- printf("SW%d = 0b%s (0x%02x)\n",
- i + 1, byte_to_binary_mask(sw[i], mask[i], buf), sw[i]);
- }
-}
diff --git a/board/freescale/b4860qds/b4860qds.h b/board/freescale/b4860qds/b4860qds.h
deleted file mode 100644
index 4a8e91b58f..0000000000
--- a/board/freescale/b4860qds/b4860qds.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2011-2012 Freescale Semiconductor, Inc.
- */
-
-#ifndef __CORENET_DS_H__
-#define __CORENET_DS_H__
-
-void fdt_fixup_board_enet(void *blob);
-void pci_of_setup(void *blob, bd_t *bd);
-
-#endif
diff --git a/board/freescale/b4860qds/b4860qds_crossbar_con.h b/board/freescale/b4860qds/b4860qds_crossbar_con.h
deleted file mode 100644
index b9d59c23be..0000000000
--- a/board/freescale/b4860qds/b4860qds_crossbar_con.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2012 Freescale Semiconductor, Inc.
- */
-
-#ifndef __CROSSBAR_CONNECTIONS_H__
-#define __CROSSBAR_CONNECTIONS_H__
-
-#define NUM_CON_VSC3316 8
-#define NUM_CON_VSC3308 4
-
-static const int8_t vsc16_tx_amc[8][2] = { {15, 3}, {0, 2}, {7, 4}, {9, 10},
- {5, 11}, {4, 5}, {2, 6}, {12, 9} };
-
-static int8_t vsc16_tx_sfp[8][2] = { {15, 7}, {0, 1}, {7, 8}, {9, 0},
- {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
-
-static int8_t vsc16_tx_4sfp_sgmii_12_56[8][2] = { {15, 7}, {0, 1},
- {7, 8}, {9, 0}, {2, 14}, {12, 15},
- {-1, -1}, {-1, -1} };
-
-static const int8_t vsc16_tx_4sfp_sgmii_34[8][2] = { {15, 7}, {0, 1},
- {7, 8}, {9, 0}, {5, 14}, {4, 15},
- {-1, -1}, {-1, -1} };
-
-static int8_t vsc16_tx_sfp_sgmii_aurora[8][2] = { {15, 7}, {0, 1},
- {7, 8}, {9, 0}, {5, 14},
- {4, 15}, {2, 12}, {12, 13} };
-
-#ifdef CONFIG_ARCH_B4420
-static int8_t vsc16_tx_sgmii_lane_cd[8][2] = { {5, 14}, {4, 15},
- {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
-#endif
-
-static const int8_t vsc16_tx_aurora[8][2] = { {2, 13}, {12, 12}, {-1, -1},
- {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
-
-static const int8_t vsc16_rx_amc[8][2] = { {3, 15}, {2, 1}, {4, 8}, {10, 9},
- {11, 11}, {5, 10}, {6, 3}, {9, 12} };
-
-static int8_t vsc16_rx_sfp[8][2] = { {8, 15}, {0, 1}, {7, 8}, {1, 9},
- {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
-
-static int8_t vsc16_rx_4sfp_sgmii_12_56[8][2] = { {8, 15}, {0, 1},
- {7, 8}, {1, 9}, {14, 3}, {15, 12},
- {-1, -1}, {-1, -1} };
-
-static const int8_t vsc16_rx_4sfp_sgmii_34[8][2] = { {8, 15}, {0, 1},
- {7, 8}, {1, 9}, {14, 11}, {15, 10},
- {-1, -1}, {-1, -1} };
-
-static int8_t vsc16_rx_sfp_sgmii_aurora[8][2] = { {8, 15}, {0, 1},
- {7, 8}, {1, 9}, {14, 11},
- {15, 10}, {13, 3}, {12, 12} };
-
-#ifdef CONFIG_ARCH_B4420
-static int8_t vsc16_rx_sgmii_lane_cd[8][2] = { {14, 11}, {15, 10},
- {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
-#endif
-
-static const int8_t vsc16_rx_aurora[8][2] = { {13, 3}, {12, 12}, {-1, -1},
- {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
-
-static const int8_t vsc08_tx_amc[4][2] = { {2, 2}, {3, 3}, {7, 4}, {1, 5} };
-
-static const int8_t vsc08_tx_sfp[4][2] = { {2, 1}, {3, 0}, {7, 6}, {1, 7} };
-
-static const int8_t vsc08_rx_amc[4][2] = { {2, 3}, {3, 4}, {4, 7}, {5, 1} };
-
-static const int8_t vsc08_rx_sfp[4][2] = { {1, 3}, {0, 4}, {6, 7}, {7, 1} };
-
-#endif
diff --git a/board/freescale/b4860qds/b4860qds_qixis.h b/board/freescale/b4860qds/b4860qds_qixis.h
deleted file mode 100644
index d4299d8af1..0000000000
--- a/board/freescale/b4860qds/b4860qds_qixis.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2012 Freescale Semiconductor, Inc.
- */
-
-#ifndef __B4860QDS_QIXIS_H__
-#define __B4860QDS_QIXIS_H__
-
-/* Definitions of QIXIS Registers for B4860QDS */
-
-/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */
-#define BRDCFG4_EMISEL_MASK 0xE0
-#define BRDCFG4_EMISEL_SHIFT 5
-
-/* CLK */
-#define QIXIS_CLK_66 0x0
-#define QIXIS_CLK_100 0x1
-#define QIXIS_CLK_125 0x2
-#define QIXIS_CLK_133 0x3
-
-#define QIXIS_SRDS1CLK_122 0x5a
-#define QIXIS_SRDS1CLK_125 0x5e
-
-/* SGMII */
-#define PHY_BASE_ADDR 0x18
-#define PORT_NUM 0x04
-#define REGNUM 0x00
-#endif
diff --git a/board/freescale/b4860qds/b4_pbi.cfg b/board/freescale/b4860qds/b4_pbi.cfg
deleted file mode 100644
index 05377bac5b..0000000000
--- a/board/freescale/b4860qds/b4_pbi.cfg
+++ /dev/null
@@ -1,30 +0,0 @@
-#PBI commands
-#Initialize CPC1
-09010000 00200400
-09138000 00000000
-091380c0 00000100
-#Configure CPC1 as 512KB SRAM
-09010100 00000000
-09010104 fff80009
-09010f00 08000000
-09010000 80000000
-#Configure LAW for CPC1
-09000d00 00000000
-09000d04 fff80000
-09000d08 81000012
-#Configure alternate space
-09000010 00000000
-09000014 ff000000
-09000018 81000000
-#Configure SPI controller
-09110000 80000403
-09110020 2d170008
-09110024 00100008
-09110028 00100008
-0911002c 00100008
-#slowing down the MDC clock to make it <= 2.5 MHZ
-094fc030 00008148
-094fd030 00008148
-#Flush PBL data
-09138000 00000000
-091380c0 00000000
diff --git a/board/freescale/b4860qds/b4_rcw.cfg b/board/freescale/b4860qds/b4_rcw.cfg
deleted file mode 100644
index 597d3914ca..0000000000
--- a/board/freescale/b4860qds/b4_rcw.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-#PBL preamble and RCW header
-aa55aa55 010e0100
-# serdes protocol 0x2A_0x98
-140e0018 0f001218 00000000 00000000
-54980000 9000a000 e8104000 a9000000
-01000000 00000000 00000000 0001b1f8
-00000000 14000020 00000000 00000011
diff --git a/board/freescale/b4860qds/ddr.c b/board/freescale/b4860qds/ddr.c
deleted file mode 100644
index d3aa349ddf..0000000000
--- a/board/freescale/b4860qds/ddr.c
+++ /dev/null
@@ -1,267 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright 2011-2012 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <hwconfig.h>
-#include <fsl_ddr.h>
-#include <init.h>
-#include <log.h>
-#include <asm/mmu.h>
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-#include <asm/fsl_law.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-dimm_params_t ddr_raw_timing = {
- .n_ranks = 2,
- .rank_density = 2147483648u,
- .capacity = 4294967296u,
- .primary_sdram_width = 64,
- .ec_sdram_width = 8,
- .registered_dimm = 0,
- .mirrored_dimm = 1,
- .n_row_addr = 15,
- .n_col_addr = 10,
- .n_banks_per_sdram_device = 8,
- .edc_config = 2, /* ECC */
- .burst_lengths_bitmask = 0x0c,
-
- .tckmin_x_ps = 1071,
- .caslat_x = 0x2fe << 4, /* 5,6,7,8,9,10,11,13 */
- .taa_ps = 13910,
- .twr_ps = 15000,
- .trcd_ps = 13910,
- .trrd_ps = 6000,
- .trp_ps = 13910,
- .tras_ps = 34000,
- .trc_ps = 48910,
- .trfc_ps = 260000,
- .twtr_ps = 7500,
- .trtp_ps = 7500,
- .refresh_rate_ps = 7800000,
- .tfaw_ps = 35000,
-};
-
-int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
- unsigned int controller_number,
- unsigned int dimm_number)
-{
- const char dimm_model[] = "RAW timing DDR";
-
- if ((controller_number == 0) && (dimm_number == 0)) {
- memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
- memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
- memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
- }
-
- return 0;
-}
-
-struct board_specific_parameters {
- u32 n_ranks;
- u32 datarate_mhz_high;
- u32 clk_adjust;
- u32 wrlvl_start;
- u32 wrlvl_ctl_2;
- u32 wrlvl_ctl_3;
- u32 cpo;
- u32 write_data_delay;
- u32 force_2t;
-};
-
-/*
- * This table contains all valid speeds we want to override with board
- * specific parameters. datarate_mhz_high values need to be in ascending order
- * for each n_ranks group.
- */
-static const struct board_specific_parameters udimm0[] = {
- /*
- * memory controller 0
- * num| hi| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
- * ranks| mhz|adjst| start | ctl2 | ctl3 | |delay |
- */
- {2, 1350, 4, 7, 0x09080807, 0x07060607, 0xff, 2, 0},
- {2, 1666, 4, 7, 0x09080806, 0x06050607, 0xff, 2, 0},
- {2, 1900, 3, 7, 0x08070706, 0x06040507, 0xff, 2, 0},
- {1, 1350, 4, 7, 0x09080807, 0x07060607, 0xff, 2, 0},
- {1, 1700, 4, 7, 0x09080806, 0x06050607, 0xff, 2, 0},
- {1, 1900, 3, 7, 0x08070706, 0x06040507, 0xff, 2, 0},
- {}
-};
-
-static const struct board_specific_parameters *udimms[] = {
- udimm0,
-};
-
-void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
- ulong ddr_freq;
-
- if (ctrl_num > 2) {
- printf("Not supported controller number %d\n", ctrl_num);
- return;
- }
- if (!pdimm->n_ranks)
- return;
-
- pbsp = udimms[0];
-
-
- /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
- * freqency and n_banks specified in board_specific_parameters table.
- */
- ddr_freq = get_ddr_freq(0) / 1000000;
- while (pbsp->datarate_mhz_high) {
- if (pbsp->n_ranks == pdimm->n_ranks) {
- if (ddr_freq <= pbsp->datarate_mhz_high) {
- popts->cpo_override = pbsp->cpo;
- popts->write_data_delay =
- pbsp->write_data_delay;
- popts->clk_adjust = pbsp->clk_adjust;
- popts->wrlvl_start = pbsp->wrlvl_start;
- popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
- popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
- popts->twot_en = pbsp->force_2t;
- goto found;
- }
- pbsp_highest = pbsp;
- }
- pbsp++;
- }
-
- if (pbsp_highest) {
- printf("Error: board specific timing not found "
- "for data rate %lu MT/s\n"
- "Trying to use the highest speed (%u) parameters\n",
- ddr_freq, pbsp_highest->datarate_mhz_high);
- popts->cpo_override = pbsp_highest->cpo;
- popts->write_data_delay = pbsp_highest->write_data_delay;
- popts->clk_adjust = pbsp_highest->clk_adjust;
- popts->wrlvl_start = pbsp_highest->wrlvl_start;
- popts->twot_en = pbsp_highest->force_2t;
- } else {
- panic("DIMM is not supported by this board");
- }
-found:
- /*
- * Factors to consider for half-strength driver enable:
- * - number of DIMMs installed
- */
- popts->half_strength_driver_enable = 0;
- /*
- * Write leveling override
- */
- popts->wrlvl_override = 1;
- popts->wrlvl_sample = 0xf;
-
- /*
- * Rtt and Rtt_WR override
- */
- popts->rtt_override = 0;
-
- /* Enable ZQ calibration */
- popts->zq_en = 1;
-
- /* DHC_EN =1, ODT = 75 Ohm */
- popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
- popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
-
- /* optimize cpo for erratum A-009942 */
- popts->cpo_sample = 0x3e;
-}
-
-int dram_init(void)
-{
- phys_size_t dram_size;
-
-#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
- puts("Initializing....using SPD\n");
- dram_size = fsl_ddr_sdram();
-#else
- dram_size = fsl_ddr_sdram_size();
-#endif
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
-
- gd->ram_size = dram_size;
-
- return 0;
-}
-
-unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo,
- unsigned int dbw_cap_adj[])
-{
- int i, j;
- unsigned long long total_mem, current_mem_base, total_ctlr_mem;
- unsigned long long rank_density, ctlr_density = 0;
-
- current_mem_base = 0ull;
- total_mem = 0;
- /*
- * This board has soldered DDR chips. DDRC1 has two rank.
- * DDRC2 has only one rank.
- * Assigning DDRC2 to lower address and DDRC1 to higher address.
- */
- if (pinfo->memctl_opts[0].memctl_interleaving) {
- rank_density = pinfo->dimm_params[0][0].rank_density >>
- dbw_cap_adj[0];
- ctlr_density = rank_density;
-
- debug("rank density is 0x%llx, ctlr density is 0x%llx\n",
- rank_density, ctlr_density);
- for (i = CONFIG_SYS_NUM_DDR_CTLRS - 1; i >= 0; i--) {
- switch (pinfo->memctl_opts[i].memctl_interleaving_mode) {
- case FSL_DDR_CACHE_LINE_INTERLEAVING:
- case FSL_DDR_PAGE_INTERLEAVING:
- case FSL_DDR_BANK_INTERLEAVING:
- case FSL_DDR_SUPERBANK_INTERLEAVING:
- total_ctlr_mem = 2 * ctlr_density;
- break;
- default:
- panic("Unknown interleaving mode");
- }
- pinfo->common_timing_params[i].base_address =
- current_mem_base;
- pinfo->common_timing_params[i].total_mem =
- total_ctlr_mem;
- total_mem = current_mem_base + total_ctlr_mem;
- debug("ctrl %d base 0x%llx\n", i, current_mem_base);
- debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
- }
- } else {
- /*
- * Simple linear assignment if memory
- * controllers are not interleaved.
- */
- for (i = CONFIG_SYS_NUM_DDR_CTLRS - 1; i >= 0; i--) {
- total_ctlr_mem = 0;
- pinfo->common_timing_params[i].base_address =
- current_mem_base;
- for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
- /* Compute DIMM base addresses. */
- unsigned long long cap =
- pinfo->dimm_params[i][j].capacity;
- pinfo->dimm_params[i][j].base_address =
- current_mem_base;
- debug("ctrl %d dimm %d base 0x%llx\n",
- i, j, current_mem_base);
- current_mem_base += cap;
- total_ctlr_mem += cap;
- }
- debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
- pinfo->common_timing_params[i].total_mem =
- total_ctlr_mem;
- total_mem += total_ctlr_mem;
- }
- }
- debug("Total mem by %s is 0x%llx\n", __func__, total_mem);
-
- return total_mem;
-}
diff --git a/board/freescale/b4860qds/eth_b4860qds.c b/board/freescale/b4860qds/eth_b4860qds.c
deleted file mode 100644
index 6d5f3d1fda..0000000000
--- a/board/freescale/b4860qds/eth_b4860qds.c
+++ /dev/null
@@ -1,454 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2012 Freescale Semiconductor, Inc.
- * Author: Sandeep Kumar Singh <sandeep@freescale.com>
- */
-
-/* This file is based on board/freescale/corenet_ds/eth_superhydra.c */
-
-/*
- * This file handles the board muxing between the Fman Ethernet MACs and
- * the RGMII/SGMII/XGMII PHYs on a Freescale B4860 "Centaur". The SGMII
- * PHYs are the two on-board 1Gb ports. There are no RGMII PHY on board.
- * The 10Gb XGMII PHY is provided via the XAUI riser card. There is only
- * one Fman device on B4860. The SERDES configuration is used to determine
- * where the SGMII and XAUI cards exist, and also which Fman MACs are routed
- * to which PHYs. So for a given Fman MAC, there is one and only PHY it
- * connects to. MACs cannot be routed to PHYs dynamically. This configuration
- * is done at boot time by reading SERDES protocol from RCW.
- */
-
-#include <common.h>
-#include <log.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/fsl_serdes.h>
-#include <fm_eth.h>
-#include <fsl_mdio.h>
-#include <malloc.h>
-#include <fdt_support.h>
-#include <fsl_dtsec.h>
-
-#include "../common/ngpixis.h"
-#include "../common/fman.h"
-#include "../common/qixis.h"
-#include "b4860qds_qixis.h"
-
-#define EMI_NONE 0xFFFFFFFF
-
-#ifdef CONFIG_FMAN_ENET
-
-/*
- * Mapping of all 16 SERDES lanes to board slots. A value n(>0) will mean that
- * lane at index is mapped to slot number n. A value of '0' will mean
- * that the mapping must be determined dynamically, or that the lane maps to
- * something other than a board slot
- */
-static u8 lane_to_slot[] = {
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 1, 1, 1, 1,
- 0, 0, 0, 0
-};
-
-/*
- * This function initializes the lane_to_slot[] array. It reads RCW to check
- * if Serdes2{E,F,G,H} is configured as slot 2 or as SFP and initializes
- * lane_to_slot[] accordingly
- */
-static void initialize_lane_to_slot(void)
-{
- unsigned int serdes2_prtcl;
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
- FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
- serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
- debug("Initializing lane to slot: Serdes2 protocol: %x\n",
- serdes2_prtcl);
-
- switch (serdes2_prtcl) {
- case 0x17:
- case 0x18:
- /*
- * Configuration:
- * SERDES: 2
- * Lanes: A,B,C,D: SGMII
- * Lanes: E,F: Aur
- * Lanes: G,H: SRIO
- */
- case 0x91:
- /*
- * Configuration:
- * SERDES: 2
- * Lanes: A,B: SGMII
- * Lanes: C,D: SRIO2
- * Lanes: E,F,G,H: XAUI2
- */
- case 0x93:
- /*
- * Configuration:
- * SERDES: 2
- * Lanes: A,B,C,D: SGMII
- * Lanes: E,F,G,H: XAUI2
- */
- case 0x98:
- /*
- * Configuration:
- * SERDES: 2
- * Lanes: A,B,C,D: XAUI2
- * Lanes: E,F,G,H: XAUI2
- */
- case 0x9a:
- /*
- * Configuration:
- * SERDES: 2
- * Lanes: A,B: PCI
- * Lanes: C,D: SGMII
- * Lanes: E,F,G,H: XAUI2
- */
- case 0x9e:
- /*
- * Configuration:
- * SERDES: 2
- * Lanes: A,B,C,D: PCI
- * Lanes: E,F,G,H: XAUI2
- */
- case 0xb1:
- case 0xb2:
- case 0x8c:
- case 0x8d:
- /*
- * Configuration:
- * SERDES: 2
- * Lanes: A,B,C,D: PCI
- * Lanes: E,F: SGMII 3&4
- * Lanes: G,H: XFI
- */
- case 0xc2:
- /*
- * Configuration:
- * SERDES: 2
- * Lanes: A,B: SGMII
- * Lanes: C,D: SRIO2
- * Lanes: E,F,G,H: XAUI2
- */
- lane_to_slot[12] = 2;
- lane_to_slot[13] = lane_to_slot[12];
- lane_to_slot[14] = lane_to_slot[12];
- lane_to_slot[15] = lane_to_slot[12];
- break;
-
- default:
- printf("Fman: Unsupported SerDes2 Protocol 0x%02x\n",
- serdes2_prtcl);
- break;
- }
- return;
-}
-
-#endif /* #ifdef CONFIG_FMAN_ENET */
-
-int board_eth_init(bd_t *bis)
-{
-#ifdef CONFIG_FMAN_ENET
- struct memac_mdio_info memac_mdio_info;
- struct memac_mdio_info tg_memac_mdio_info;
- unsigned int i;
- unsigned int serdes1_prtcl, serdes2_prtcl;
- int qsgmii;
- struct mii_dev *bus;
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- serdes1_prtcl = in_be32(&gur->rcwsr[4]) &
- FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
- if (!serdes1_prtcl) {
- printf("SERDES1 is not enabled\n");
- return 0;
- }
- serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
- debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl);
-
- serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
- FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
- if (!serdes2_prtcl) {
- printf("SERDES2 is not enabled\n");
- return 0;
- }
- serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
- debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl);
-
- printf("Initializing Fman\n");
-
- initialize_lane_to_slot();
-
- memac_mdio_info.regs =
- (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
- memac_mdio_info.name = DEFAULT_FM_MDIO_NAME;
-
- /* Register the real 1G MDIO bus */
- fm_memac_mdio_init(bis, &memac_mdio_info);
-
- tg_memac_mdio_info.regs =
- (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
- tg_memac_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
-
- /* Register the real 10G MDIO bus */
- fm_memac_mdio_init(bis, &tg_memac_mdio_info);
-
- /*
- * Program the two on board DTSEC PHY addresses assuming that they are
- * all SGMII. RGMII is not supported on this board. Setting SGMII 5 and
- * 6 to on board SGMII phys
- */
- fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR);
- fm_info_set_phy_address(FM1_DTSEC6, CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
-
- switch (serdes1_prtcl) {
- case 0x29:
- case 0x2a:
- /* Serdes 1: A-B SGMII, Configuring DTSEC 5 and 6 */
- debug("Set phy addresses for FM1_DTSEC5:%x, FM1_DTSEC6:%x\n",
- CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR,
- CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
- fm_info_set_phy_address(FM1_DTSEC5,
- CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR);
- fm_info_set_phy_address(FM1_DTSEC6,
- CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
- break;
-#ifdef CONFIG_ARCH_B4420
- case 0x17:
- case 0x18:
- /* Serdes 1: A-D SGMII, Configuring on board dual SGMII Phy */
- debug("Set phy addresses for FM1_DTSEC3:%x, FM1_DTSEC4:%x\n",
- CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR,
- CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
- /* Fixing Serdes clock by programming FPGA register */
- QIXIS_WRITE(brdcfg[4], QIXIS_SRDS1CLK_125);
- fm_info_set_phy_address(FM1_DTSEC3,
- CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR);
- fm_info_set_phy_address(FM1_DTSEC4,
- CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
- break;
-#endif
- default:
- printf("Fman: Unsupported SerDes1 Protocol 0x%02x\n",
- serdes1_prtcl);
- break;
- }
- switch (serdes2_prtcl) {
- case 0x17:
- case 0x18:
- debug("Set phy address on SGMII Riser for FM1_DTSEC1:%x\n",
- CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC1,
- CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC2,
- CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC3,
- CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC4,
- CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR);
- break;
- case 0x48:
- case 0x49:
- debug("Set phy address on SGMII Riser for FM1_DTSEC1:%x\n",
- CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC1,
- CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC2,
- CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC3,
- CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR);
- break;
- case 0xb1:
- case 0xb2:
- case 0x8c:
- case 0x8d:
- debug("Set phy addresses on SGMII Riser for FM1_DTSEC1:%x\n",
- CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC3,
- CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC4,
- CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR);
- /*
- * XFI does not need a PHY to work, but to make U-Boot
- * happy, assign a fake PHY address for a XFI port.
- */
- fm_info_set_phy_address(FM1_10GEC1, 0);
- fm_info_set_phy_address(FM1_10GEC2, 1);
- break;
- case 0x98:
- /* XAUI in Slot1 and Slot2 */
- debug("Set phy address of AMC2PEX-2S for FM1_10GEC1:%x\n",
- CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
- fm_info_set_phy_address(FM1_10GEC1,
- CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
- debug("Set phy address of AMC2PEX-2S for FM1_10GEC2:%x\n",
- CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
- fm_info_set_phy_address(FM1_10GEC2,
- CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
- break;
- case 0x9E:
- /* XAUI in Slot2 */
- debug("Sett phy address of AMC2PEX-2S for FM1_10GEC2:%x\n",
- CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
- fm_info_set_phy_address(FM1_10GEC2,
- CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
- break;
- default:
- printf("Fman: Unsupported SerDes2 Protocol 0x%02x\n",
- serdes2_prtcl);
- break;
- }
-
- /*set PHY address for QSGMII Riser Card on slot2*/
- bus = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
- qsgmii = is_qsgmii_riser_card(bus, PHY_BASE_ADDR, PORT_NUM, REGNUM);
-
- if (qsgmii) {
- switch (serdes2_prtcl) {
- case 0xb2:
- case 0x8d:
- fm_info_set_phy_address(FM1_DTSEC3, PHY_BASE_ADDR);
- fm_info_set_phy_address(FM1_DTSEC4, PHY_BASE_ADDR + 1);
- break;
- default:
- break;
- }
- }
-
- for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
- int idx = i - FM1_DTSEC1;
-
- switch (fm_info_get_enet_if(i)) {
- case PHY_INTERFACE_MODE_SGMII:
- fm_info_set_mdio(i,
- miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
- break;
- case PHY_INTERFACE_MODE_NONE:
- fm_info_set_phy_address(i, 0);
- break;
- default:
- printf("Fman1: DTSEC%u set to unknown interface %i\n",
- idx + 1, fm_info_get_enet_if(i));
- fm_info_set_phy_address(i, 0);
- break;
- }
- }
-
- for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
- int idx = i - FM1_10GEC1;
-
- switch (fm_info_get_enet_if(i)) {
- case PHY_INTERFACE_MODE_XGMII:
- fm_info_set_mdio(i,
- miiphy_get_dev_by_name
- (DEFAULT_FM_TGEC_MDIO_NAME));
- break;
- case PHY_INTERFACE_MODE_NONE:
- fm_info_set_phy_address(i, 0);
- break;
- default:
- printf("Fman1: TGEC%u set to unknown interface %i\n",
- idx + 1, fm_info_get_enet_if(i));
- fm_info_set_phy_address(i, 0);
- break;
- }
- }
-
- cpu_eth_init(bis);
-#endif
-
- return pci_eth_init(bis);
-}
-
-void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
- enum fm_port port, int offset)
-{
- int phy;
- char alias[32];
- struct fixed_link f_link;
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- u32 prtcl2 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
-
- prtcl2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
-
- if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
- phy = fm_info_get_phy_address(port);
-
- sprintf(alias, "phy_sgmii_%x", phy);
- fdt_set_phy_handle(fdt, compat, addr, alias);
- fdt_status_okay_by_alias(fdt, alias);
- } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) {
- /* check if it's XFI interface for 10g */
- switch (prtcl2) {
- case 0x80:
- case 0x81:
- case 0x82:
- case 0x83:
- case 0x84:
- case 0x85:
- case 0x86:
- case 0x87:
- case 0x88:
- case 0x89:
- case 0x8a:
- case 0x8b:
- case 0x8c:
- case 0x8d:
- case 0x8e:
- case 0xb1:
- case 0xb2:
- f_link.phy_id = port;
- f_link.duplex = 1;
- f_link.link_speed = 10000;
- f_link.pause = 0;
- f_link.asym_pause = 0;
-
- fdt_delprop(fdt, offset, "phy-handle");
- fdt_setprop(fdt, offset, "fixed-link", &f_link,
- sizeof(f_link));
- break;
- case 0x98: /* XAUI interface */
- strcpy(alias, "phy_xaui_slot1");
- fdt_status_okay_by_alias(fdt, alias);
-
- strcpy(alias, "phy_xaui_slot2");
- fdt_status_okay_by_alias(fdt, alias);
- break;
- case 0x9e: /* XAUI interface */
- case 0x9a:
- case 0x93:
- case 0x91:
- strcpy(alias, "phy_xaui_slot1");
- fdt_status_okay_by_alias(fdt, alias);
- break;
- case 0x97: /* XAUI interface */
- case 0xc3:
- strcpy(alias, "phy_xaui_slot2");
- fdt_status_okay_by_alias(fdt, alias);
- break;
- default:
- break;
- }
- }
-}
-
-/*
- * Set status to disabled for unused ethernet node
- */
-void fdt_fixup_board_enet(void *fdt)
-{
- int i;
- char alias[32];
-
- for (i = FM1_DTSEC1; i <= FM1_10GEC2; i++) {
- switch (fm_info_get_enet_if(i)) {
- case PHY_INTERFACE_MODE_NONE:
- sprintf(alias, "ethernet%u", i);
- fdt_status_disabled_by_alias(fdt, alias);
- break;
- default:
- break;
- }
- }
-}
diff --git a/board/freescale/b4860qds/law.c b/board/freescale/b4860qds/law.c
deleted file mode 100644
index b39d720068..0000000000
--- a/board/freescale/b4860qds/law.c
+++ /dev/null
@@ -1,28 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2011-2012 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-struct law_entry law_table[] = {
- SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
- SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
-#endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
- SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
-#endif
- SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
- /* Limit DCSR to 32M to access NPC Trace Buffer */
- SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
-#endif
-#ifdef CONFIG_SYS_NAND_BASE_PHYS
- SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
-#endif
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/b4860qds/pci.c b/board/freescale/b4860qds/pci.c
deleted file mode 100644
index 45dd461e77..0000000000
--- a/board/freescale/b4860qds/pci.c
+++ /dev/null
@@ -1,23 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2011-2012 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <init.h>
-#include <pci.h>
-#include <asm/fsl_pci.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <asm/fsl_serdes.h>
-
-void pci_init_board(void)
-{
- fsl_pcie_init_board(0);
-}
-
-void pci_of_setup(void *blob, bd_t *bd)
-{
- FT_FSL_PCI_SETUP;
-}
diff --git a/board/freescale/b4860qds/spl.c b/board/freescale/b4860qds/spl.c
deleted file mode 100644
index fe5ce35013..0000000000
--- a/board/freescale/b4860qds/spl.c
+++ /dev/null
@@ -1,119 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/* Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <clock_legacy.h>
-#include <console.h>
-#include <env.h>
-#include <env_internal.h>
-#include <init.h>
-#include <asm/spl.h>
-#include <malloc.h>
-#include <ns16550.h>
-#include <nand.h>
-#include <i2c.h>
-#include "../common/qixis.h"
-#include "b4860qds_qixis.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-phys_size_t get_effective_memsize(void)
-{
- return CONFIG_SYS_L3_SIZE;
-}
-
-unsigned long get_board_sys_clk(void)
-{
- u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
-
- switch ((sysclk_conf & 0x0C) >> 2) {
- case QIXIS_CLK_100:
- return 100000000;
- case QIXIS_CLK_125:
- return 125000000;
- case QIXIS_CLK_133:
- return 133333333;
- }
- return 66666666;
-}
-
-unsigned long get_board_ddr_clk(void)
-{
- u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
-
- switch (ddrclk_conf & 0x03) {
- case QIXIS_CLK_100:
- return 100000000;
- case QIXIS_CLK_125:
- return 125000000;
- case QIXIS_CLK_133:
- return 133333333;
- }
- return 66666666;
-}
-
-void board_init_f(ulong bootflag)
-{
- u32 plat_ratio, sys_clk, uart_clk;
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
- /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
- memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
-
- /* Update GD pointer */
- gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
-
- /* compiler optimization barrier needed for GCC >= 3.4 */
- __asm__ __volatile__("" : : : "memory");
-
- console_init_f();
-
- /* initialize selected port with appropriate baud rate */
- sys_clk = get_board_sys_clk();
- plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
- uart_clk = sys_clk * plat_ratio / 2;
-
- NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
- uart_clk / 16 / CONFIG_BAUDRATE);
-
- relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
- bd_t *bd;
-
- bd = (bd_t *)(gd + sizeof(gd_t));
- memset(bd, 0, sizeof(bd_t));
- gd->bd = bd;
- bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
- bd->bi_memsize = CONFIG_SYS_L3_SIZE;
-
- arch_cpu_init();
- get_clocks();
- mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
- CONFIG_SPL_RELOC_MALLOC_SIZE);
- gd->flags |= GD_FLG_FULL_MALLOC_INIT;
-
-#ifndef CONFIG_SPL_NAND_BOOT
- env_init();
- env_relocate();
-#else
- /* relocate environment function pointers etc. */
- nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
- (uchar *)SPL_ENV_ADDR);
- gd->env_addr = (ulong)(SPL_ENV_ADDR);
- gd->env_valid = ENV_VALID;
-#endif
-
- i2c_init_all();
-
- puts("\n\n");
-
- dram_init();
-
-#ifdef CONFIG_SPL_NAND_BOOT
- nand_boot();
-#endif
-}
diff --git a/board/freescale/b4860qds/tlb.c b/board/freescale/b4860qds/tlb.c
deleted file mode 100644
index 68e2295cb5..0000000000
--- a/board/freescale/b4860qds/tlb.c
+++ /dev/null
@@ -1,154 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2011-2012 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
- /* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
-
- /* TLB 1 */
- /* *I*** - Covers boot page */
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
- /*
- * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
- * SRAM is at 0xfff00000, it covered the 0xfffff000.
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_1M, 1),
-#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
- /*
- * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the
- * space is at 0xfff00000, it covered the 0xfffff000.
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR,
- CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
- 0, 0, BOOKE_PAGESZ_1M, 1),
-#else
- SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_4K, 1),
-#endif
-
- /* *I*G* - CCSRBAR */
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 1, BOOKE_PAGESZ_16M, 1),
-
- /* *I*G* - Flash, localbus */
- /* This will be changed to *I*G* after relocation to RAM. */
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
- MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
- 0, 2, BOOKE_PAGESZ_256M, 1),
-
-#ifndef CONFIG_SPL_BUILD
- /* *I*G* - PCI */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 3, BOOKE_PAGESZ_256M, 1),
-
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x10000000,
- CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 4, BOOKE_PAGESZ_256M, 1),
-
- /* *I*G* - PCI I/O */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 5, BOOKE_PAGESZ_64K, 1),
-
- /* Bman/Qman */
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
- SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 6, BOOKE_PAGESZ_16M, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
- CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 7, BOOKE_PAGESZ_16M, 1),
-#endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
- SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 8, BOOKE_PAGESZ_16M, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
- CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 9, BOOKE_PAGESZ_16M, 1),
-#endif
-#endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
- SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 10, BOOKE_PAGESZ_32M, 1),
-#endif
-#ifdef CONFIG_SYS_NAND_BASE
- /*
- * *I*G - NAND
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 11, BOOKE_PAGESZ_64K, 1),
-#endif
- SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 12, BOOKE_PAGESZ_4K, 1),
-
- /*
- * *I*G - SRIO
- * entry 14 and 15 has been used hard coded, they will be disabled
- * in cpu_init_f, so we use entry 16 for SRIO2.
- */
-#ifndef CONFIG_SPL_BUILD
-#ifdef CONFIG_SYS_SRIO1_MEM_PHYS
- /* *I*G* - SRIO1 */
- SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT, CONFIG_SYS_SRIO1_MEM_PHYS,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 13, BOOKE_PAGESZ_256M, 1),
-#endif
-#ifdef CONFIG_SYS_SRIO2_MEM_PHYS
- /* *I*G* - SRIO2 */
- SET_TLB_ENTRY(1, CONFIG_SYS_SRIO2_MEM_VIRT, CONFIG_SYS_SRIO2_MEM_PHYS,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 16, BOOKE_PAGESZ_256M, 1),
-#endif
-#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
- /*
- * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for
- * fetching ucode and ENV from master
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR,
- CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
- 0, 17, BOOKE_PAGESZ_1M, 1),
-#endif
-#endif
-
-#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
- SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
- 0, 17, BOOKE_PAGESZ_2G, 1)
-#endif
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/configs/B4420QDS_NAND_defconfig b/configs/B4420QDS_NAND_defconfig
deleted file mode 100644
index 6fcb51a1cd..0000000000
--- a/configs/B4420QDS_NAND_defconfig
+++ /dev/null
@@ -1,69 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x00201000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x140000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_B4420QDS=y
-CONFIG_SYS_CUSTOM_LDSCRIPT=y
-CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_NAND_BOOT=y
-CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_FSL_CAAM=y
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/B4420QDS_SPIFLASH_defconfig b/configs/B4420QDS_SPIFLASH_defconfig
deleted file mode 100644
index 5dc72cb3f2..0000000000
--- a/configs/B4420QDS_SPIFLASH_defconfig
+++ /dev/null
@@ -1,55 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_B4420QDS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_CAAM=y
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/B4420QDS_defconfig b/configs/B4420QDS_defconfig
deleted file mode 100644
index 5f9a88adfa..0000000000
--- a/configs/B4420QDS_defconfig
+++ /dev/null
@@ -1,53 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_B4420QDS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_FSL_CAAM=y
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/B4860QDS_NAND_defconfig b/configs/B4860QDS_NAND_defconfig
deleted file mode 100644
index 0874acd83e..0000000000
--- a/configs/B4860QDS_NAND_defconfig
+++ /dev/null
@@ -1,69 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x00201000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x140000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_B4860QDS=y
-CONFIG_SYS_CUSTOM_LDSCRIPT=y
-CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_NAND_BOOT=y
-CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_FSL_CAAM=y
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/B4860QDS_SECURE_BOOT_defconfig b/configs/B4860QDS_SECURE_BOOT_defconfig
deleted file mode 100644
index 4d7bf5dc39..0000000000
--- a/configs/B4860QDS_SECURE_BOOT_defconfig
+++ /dev/null
@@ -1,56 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_B4860QDS=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/B4860QDS_SPIFLASH_defconfig b/configs/B4860QDS_SPIFLASH_defconfig
deleted file mode 100644
index 566076543f..0000000000
--- a/configs/B4860QDS_SPIFLASH_defconfig
+++ /dev/null
@@ -1,55 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_B4860QDS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_CAAM=y
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/B4860QDS_SRIO_PCIE_BOOT_defconfig b/configs/B4860QDS_SRIO_PCIE_BOOT_defconfig
deleted file mode 100644
index 58195adcbc..0000000000
--- a/configs/B4860QDS_SRIO_PCIE_BOOT_defconfig
+++ /dev/null
@@ -1,49 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_B4860QDS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_GREPENV=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_I2C=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_ENV_IS_IN_REMOTE=y
-CONFIG_ENV_ADDR=0xFFE20000
-CONFIG_FSL_CAAM=y
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_REMOTE=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/B4860QDS_defconfig b/configs/B4860QDS_defconfig
deleted file mode 100644
index 68ff6ed953..0000000000
--- a/configs/B4860QDS_defconfig
+++ /dev/null
@@ -1,53 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_B4860QDS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_FSL_CAAM=y
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h
deleted file mode 100644
index a515bf9530..0000000000
--- a/include/configs/B4860QDS.h
+++ /dev/null
@@ -1,759 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2011-2012 Freescale Semiconductor, Inc.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <linux/stringify.h>
-
-/*
- * B4860 QDS board configuration file
- */
-#ifdef CONFIG_RAMBOOT_PBL
-#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg
-#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg
-#ifndef CONFIG_MTD_RAW_NAND
-#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
-#else
-#define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_PAD_TO 0x40000
-#define CONFIG_SPL_MAX_SIZE 0x28000
-#define RESET_VECTOR_OFFSET 0x27FFC
-#define BOOT_PAGE_OFFSET 0x27000
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
-#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
-#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SPL_SKIP_RELOCATE
-#define CONFIG_SPL_COMMON_INIT_DDR
-#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
-#endif
-#endif
-#endif
-
-#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
-/* Set 1M boot space */
-#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
-#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
- (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
-#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
-#endif
-
-/* High Level Configuration Options */
-#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
-
-#ifndef CONFIG_RESET_VECTOR_ADDRESS
-#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
-#endif
-
-#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
-#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
-#define CONFIG_PCIE1 /* PCIE controller 1 */
-#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
-#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
-
-#ifndef CONFIG_ARCH_B4420
-#define CONFIG_SYS_SRIO
-#define CONFIG_SRIO1 /* SRIO port 1 */
-#define CONFIG_SRIO2 /* SRIO port 2 */
-#define CONFIG_SRIO_PCIE_BOOT_MASTER
-#endif
-
-/* I2C bus multiplexer */
-#define I2C_MUX_PCA_ADDR 0x77
-
-/* VSC Crossbar switches */
-#define CONFIG_VSC_CROSSBAR
-#define I2C_CH_DEFAULT 0x8
-#define I2C_CH_VSC3316 0xc
-#define I2C_CH_VSC3308 0xd
-
-#define VSC3316_TX_ADDRESS 0x70
-#define VSC3316_RX_ADDRESS 0x71
-#define VSC3308_TX_ADDRESS 0x02
-#define VSC3308_RX_ADDRESS 0x03
-
-/* IDT clock synthesizers */
-#define CONFIG_IDT8T49N222A
-#define I2C_CH_IDT 0x9
-
-#define IDT_SERDES1_ADDRESS 0x6E
-#define IDT_SERDES2_ADDRESS 0x6C
-
-/* Voltage monitor on channel 2*/
-#define I2C_MUX_CH_VOL_MONITOR 0xa
-#define I2C_VOL_MONITOR_ADDR 0x40
-#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
-#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
-#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
-
-#define CONFIG_ZM7300
-#define I2C_MUX_CH_DPM 0xa
-#define I2C_DPM_ADDR 0x28
-
-#define CONFIG_ENV_OVERWRITE
-
-#if defined(CONFIG_SPIFLASH)
-#elif defined(CONFIG_SDCARD)
-#define CONFIG_SYS_MMC_ENV_DEV 0
-#endif
-
-#ifndef __ASSEMBLY__
-unsigned long get_board_sys_clk(void);
-unsigned long get_board_ddr_clk(void);
-#endif
-#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
-#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
-
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_SYS_CACHE_STASHING
-#define CONFIG_BTB /* toggle branch predition */
-#define CONFIG_DDR_ECC
-#ifdef CONFIG_DDR_ECC
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
-#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
-#endif
-
-#define CONFIG_ENABLE_36BIT_PHYS
-
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_ADDR_MAP
-#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
-#endif
-
-#if 0
-#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
-#endif
-
-/*
- * Config the L3 Cache as L3 SRAM
- */
-#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
-#define CONFIG_SYS_L3_SIZE 256 << 10
-#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
-#define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
-#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
-#define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
-#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
-
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_DCSRBAR 0xf0000000
-#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
-#endif
-
-/* EEPROM */
-#define CONFIG_ID_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#define CONFIG_SYS_EEPROM_BUS_NUM 0
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
-
-/*
- * DDR Setup
- */
-#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
-
-#define CONFIG_DDR_SPD
-#define CONFIG_SYS_DDR_RAW_TIMING
-
-#define CONFIG_SYS_SPD_BUS_NUM 0
-#define SPD_EEPROM_ADDRESS1 0x51
-#define SPD_EEPROM_ADDRESS2 0x53
-
-#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
-#define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
-
-/*
- * IFC Definitions
- */
-#define CONFIG_SYS_FLASH_BASE 0xe0000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
-#else
-#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
-#endif
-
-#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
-#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
- + 0x8000000) | \
- CSPR_PORT_SIZE_16 | \
- CSPR_MSEL_NOR | \
- CSPR_V)
-#define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
-#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
- CSPR_PORT_SIZE_16 | \
- CSPR_MSEL_NOR | \
- CSPR_V)
-#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
-/* NOR Flash Timing Params */
-#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4)
-#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) | \
- FTIM0_NOR_TEADC(0x04) | \
- FTIM0_NOR_TEAHC(0x20))
-#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
- FTIM1_NOR_TRAD_NOR(0x1A) |\
- FTIM1_NOR_TSEQRAD_NOR(0x13))
-#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x01) | \
- FTIM2_NOR_TCH(0x0E) | \
- FTIM2_NOR_TWPH(0x0E) | \
- FTIM2_NOR_TWP(0x1c))
-#define CONFIG_SYS_NOR_FTIM3 0x0
-
-#define CONFIG_SYS_FLASH_QUIET_TEST
-#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
- + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
-
-#define CONFIG_FSL_QIXIS /* use common QIXIS code */
-#define CONFIG_FSL_QIXIS_V2
-#define QIXIS_BASE 0xffdf0000
-#ifdef CONFIG_PHYS_64BIT
-#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
-#else
-#define QIXIS_BASE_PHYS QIXIS_BASE
-#endif
-#define QIXIS_LBMAP_SWITCH 0x01
-#define QIXIS_LBMAP_MASK 0x0f
-#define QIXIS_LBMAP_SHIFT 0
-#define QIXIS_LBMAP_DFLTBANK 0x00
-#define QIXIS_LBMAP_ALTBANK 0x02
-#define QIXIS_RST_CTL_RESET 0x31
-#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
-#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
-#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
-
-#define CONFIG_SYS_CSPR3_EXT (0xf)
-#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
- | CSPR_PORT_SIZE_8 \
- | CSPR_MSEL_GPCM \
- | CSPR_V)
-#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_CSOR3 0x0
-/* QIXIS Timing parameters for IFC CS3 */
-#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
- FTIM0_GPCM_TEADC(0x0e) | \
- FTIM0_GPCM_TEAHC(0x0e))
-#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
- FTIM1_GPCM_TRAD(0x1f))
-#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
- FTIM2_GPCM_TCH(0x8) | \
- FTIM2_GPCM_TWP(0x1f))
-#define CONFIG_SYS_CS3_FTIM3 0x0
-
-/* NAND Flash on IFC */
-#define CONFIG_NAND_FSL_IFC
-#define CONFIG_SYS_NAND_MAX_ECCPOS 256
-#define CONFIG_SYS_NAND_MAX_OOBFREE 2
-#define CONFIG_SYS_NAND_BASE 0xff800000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
-#else
-#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
-#endif
-
-#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
-#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
- | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
- | CSPR_MSEL_NAND /* MSEL = NAND */ \
- | CSPR_V)
-#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
-
-#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
- | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
- | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
- | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
- | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
- | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
- | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
-
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-
-/* ONFI NAND Flash mode0 Timing Params */
-#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
- FTIM0_NAND_TWP(0x18) | \
- FTIM0_NAND_TWCHT(0x07) | \
- FTIM0_NAND_TWH(0x0a))
-#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
- FTIM1_NAND_TWBE(0x39) | \
- FTIM1_NAND_TRR(0x0e) | \
- FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
- FTIM2_NAND_TREH(0x0a) | \
- FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3 0x0
-
-#define CONFIG_SYS_NAND_DDR_LAW 11
-
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
-
-#if defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
-#else
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
-#endif
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
-#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
-
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
-#else
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-#endif
-
-#if defined(CONFIG_RAMBOOT_PBL)
-#define CONFIG_SYS_RAMBOOT
-#endif
-
-#define CONFIG_HWCONFIG
-
-/* define to use L1 as initial stack */
-#define CONFIG_L1_INIT_RAM
-#define CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
-/* The assembler doesn't like typecast */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
- ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
- CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
-#else
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
-#endif
-#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
-
-/* Serial Port - controlled on board with jumper J8
- * open - index 2
- * shorted - index 1
- */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
-#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
-#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
-#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000
-
-/*
- * RTC configuration
- */
-#define RTC
-#define CONFIG_RTC_DS3231 1
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-
-/*
- * RapidIO
- */
-#ifdef CONFIG_SYS_SRIO
-#ifdef CONFIG_SRIO1
-#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
-#else
-#define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
-#endif
-#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
-#endif
-
-#ifdef CONFIG_SRIO2
-#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
-#else
-#define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
-#endif
-#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
-#endif
-#endif
-
-/*
- * for slave u-boot IMAGE instored in master memory space,
- * PHYS must be aligned based on the SIZE
- */
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
-/*
- * for slave UCODE and ENV instored in master memory space,
- * PHYS must be aligned based on the SIZE
- */
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
-
-/* slave core release by master*/
-#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
-#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
-
-/*
- * SRIO_PCIE_BOOT - SLAVE
- */
-#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
-#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
-#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
- (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
-#endif
-
-/*
- * eSPI - Enhanced SPI
- */
-
-/*
- * MAPLE
- */
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_MAPLE_MEM_PHYS 0xFA0000000ull
-#else
-#define CONFIG_SYS_MAPLE_MEM_PHYS 0xA0000000
-#endif
-
-/*
- * General PCI
- * Memory space is mapped 1-1, but I/O space must start from 0.
- */
-
-/* controller 1, direct to uli, tgtid 3, Base address 20000 */
-#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
-#else
-#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
-#endif
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
-#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
-#else
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
-#endif
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
-
-/* Qman/Bman */
-#ifndef CONFIG_NOBQFMAN
-#define CONFIG_SYS_BMAN_NUM_PORTALS 25
-#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
-#else
-#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
-#endif
-#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
-#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
-#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
-#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
-#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
- CONFIG_SYS_BMAN_CENA_SIZE)
-#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
-#define CONFIG_SYS_QMAN_NUM_PORTALS 25
-#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
-#else
-#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
-#endif
-#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
-#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
-#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
-#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
-#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
- CONFIG_SYS_QMAN_CENA_SIZE)
-#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
-
-#define CONFIG_SYS_DPAA_FMAN
-
-#define CONFIG_SYS_DPAA_RMAN
-
-/* Default address of microcode for the Linux Fman driver */
-#if defined(CONFIG_SPIFLASH)
-/*
- * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
- * env, so we got 0x110000.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
-#elif defined(CONFIG_SDCARD)
-/*
- * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
- * about 545KB (1089 blocks), Env is stored after the image, and the env size is
- * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1130)
-#elif defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_FMAN_FW_ADDR (13 * CONFIG_SYS_NAND_BLOCK_SIZE)
-#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
-/*
- * Slave has no ucode locally, it can fetch this from remote. When implementing
- * in two corenet boards, slave's ucode could be stored in master's memory
- * space, the address can be mapped from slave TLB->slave LAW->
- * slave SRIO or PCIE outbound window->master inbound window->
- * master LAW->the ucode address in master's memory space.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
-#else
-#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
-#endif
-#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
-#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
-#endif /* CONFIG_NOBQFMAN */
-
-#ifdef CONFIG_SYS_DPAA_FMAN
-#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
-#define SGMII_CARD_PORT2_PHY_ADDR 0x10
-#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
-#define SGMII_CARD_PORT4_PHY_ADDR 0x11
-#endif
-
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#endif /* CONFIG_PCI */
-
-#ifdef CONFIG_FMAN_ENET
-#define CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR 0x10
-#define CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR 0x11
-
-/*B4860 QDS AMC2PEX-2S default PHY_ADDR */
-#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7 /*SLOT 1*/
-#define CONFIG_SYS_FM1_10GEC2_PHY_ADDR 0x6 /*SLOT 2*/
-
-#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
-#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
-#define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
-#define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
-
-#define CONFIG_ETHPRIME "FM1 at DTSEC1"
-#endif
-
-#define CONFIG_SYS_FSL_B4860QDS_XFI_ERR
-
-/*
- * Environment
- */
-#define CONFIG_LOADS_ECHO /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
-
-/*
-* USB
-*/
-#define CONFIG_HAS_FSL_DR_USB
-
-#ifdef CONFIG_HAS_FSL_DR_USB
-#ifdef CONFIG_USB_EHCI_HCD
-#define CONFIG_USB_EHCI_FSL
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#endif
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 64 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
-#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-#define CONFIG_ROOTPATH "/opt/nfsroot"
-#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
-
-/* default location for tftp and bootm */
-#define CONFIG_LOADADDR 1000000
-
-#define __USB_PHY_TYPE ulpi
-
-#ifdef CONFIG_ARCH_B4860
-#define HWCONFIG "hwconfig=fsl_ddr:ctlr_intlv=null," \
- "bank_intlv=cs0_cs1;" \
- "en_cpc:cpc2;"
-#else
-#define HWCONFIG "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;"
-#endif
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- HWCONFIG \
- "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
- "netdev=eth0\0" \
- "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
- "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
- "tftpflash=tftpboot $loadaddr $uboot && " \
- "protect off $ubootaddr +$filesize && " \
- "erase $ubootaddr +$filesize && " \
- "cp.b $loadaddr $ubootaddr $filesize && " \
- "protect on $ubootaddr +$filesize && " \
- "cmp.b $loadaddr $ubootaddr $filesize\0" \
- "consoledev=ttyS0\0" \
- "ramdiskaddr=2000000\0" \
- "ramdiskfile=b4860qds/ramdisk.uboot\0" \
- "fdtaddr=1e00000\0" \
- "fdtfile=b4860qds/b4860qds.dtb\0" \
- "bdev=sda3\0"
-
-/* For emulation this causes u-boot to jump to the start of the proof point
- app code automatically */
-#define CONFIG_PROOF_POINTS \
- "setenv bootargs root=/dev/$bdev rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "cpu 1 release 0x29000000 - - -;" \
- "cpu 2 release 0x29000000 - - -;" \
- "cpu 3 release 0x29000000 - - -;" \
- "cpu 4 release 0x29000000 - - -;" \
- "cpu 5 release 0x29000000 - - -;" \
- "cpu 6 release 0x29000000 - - -;" \
- "cpu 7 release 0x29000000 - - -;" \
- "go 0x29000000"
-
-#define CONFIG_HVBOOT \
- "setenv bootargs config-addr=0x60000000; " \
- "bootm 0x01000000 - 0x00f00000"
-
-#define CONFIG_ALU \
- "setenv bootargs root=/dev/$bdev rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "cpu 1 release 0x01000000 - - -;" \
- "cpu 2 release 0x01000000 - - -;" \
- "cpu 3 release 0x01000000 - - -;" \
- "cpu 4 release 0x01000000 - - -;" \
- "cpu 5 release 0x01000000 - - -;" \
- "cpu 6 release 0x01000000 - - -;" \
- "cpu 7 release 0x01000000 - - -;" \
- "go 0x01000000"
-
-#define CONFIG_LINUX \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "setenv ramdiskaddr 0x02000000;" \
- "setenv fdtaddr 0x01e00000;" \
- "setenv loadaddr 0x1000000;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_HDBOOT \
- "setenv bootargs root=/dev/$bdev rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND CONFIG_LINUX
-
-#include <asm/fsl_secure_boot.h>
-
-#endif /* __CONFIG_H */
--
2.25.1
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 02/24] arm: Remove configs/BSC9131RDB_NAND_SYSCLK100_defconfig board
2020-05-27 16:46 [PATCH 00/24] spi: dm-conversion (part2) Jagan Teki
2020-05-27 16:46 ` [PATCH 01/24] arm: Remove configs/B4420QDS_NAND_defconfig board Jagan Teki
@ 2020-05-27 16:46 ` Jagan Teki
2020-05-28 4:17 ` Priyanka Jain
2020-05-27 16:46 ` [PATCH 03/24] arm: Remove configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig board Jagan Teki
` (20 subsequent siblings)
22 siblings, 1 reply; 59+ messages in thread
From: Jagan Teki @ 2020-05-27 16:46 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_SPI by the deadline.
Remove it.
Patch-cc: Poonam Aggrwal <poonam.aggrwal@nxp.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
arch/powerpc/cpu/mpc85xx/Kconfig | 1 -
board/freescale/bsc9131rdb/Kconfig | 12 -
board/freescale/bsc9131rdb/MAINTAINERS | 9 -
board/freescale/bsc9131rdb/Makefile | 21 --
board/freescale/bsc9131rdb/README | 151 --------
board/freescale/bsc9131rdb/bsc9131rdb.c | 82 -----
board/freescale/bsc9131rdb/ddr.c | 170 ---------
board/freescale/bsc9131rdb/law.c | 18 -
board/freescale/bsc9131rdb/spl_minimal.c | 105 ------
board/freescale/bsc9131rdb/tlb.c | 61 ----
configs/BSC9131RDB_NAND_SYSCLK100_defconfig | 64 ----
configs/BSC9131RDB_NAND_defconfig | 63 ----
.../BSC9131RDB_SPIFLASH_SYSCLK100_defconfig | 56 ---
configs/BSC9131RDB_SPIFLASH_defconfig | 56 ---
include/configs/BSC9131RDB.h | 337 ------------------
15 files changed, 1206 deletions(-)
delete mode 100644 board/freescale/bsc9131rdb/Kconfig
delete mode 100644 board/freescale/bsc9131rdb/MAINTAINERS
delete mode 100644 board/freescale/bsc9131rdb/Makefile
delete mode 100644 board/freescale/bsc9131rdb/README
delete mode 100644 board/freescale/bsc9131rdb/bsc9131rdb.c
delete mode 100644 board/freescale/bsc9131rdb/ddr.c
delete mode 100644 board/freescale/bsc9131rdb/law.c
delete mode 100644 board/freescale/bsc9131rdb/spl_minimal.c
delete mode 100644 board/freescale/bsc9131rdb/tlb.c
delete mode 100644 configs/BSC9131RDB_NAND_SYSCLK100_defconfig
delete mode 100644 configs/BSC9131RDB_NAND_defconfig
delete mode 100644 configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig
delete mode 100644 configs/BSC9131RDB_SPIFLASH_defconfig
delete mode 100644 include/configs/BSC9131RDB.h
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index dca83f4408..bb59943232 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -1589,7 +1589,6 @@ config SYS_FSL_LBC_CLK_DIV
Defines divider of platform clock(clock input to
eLBC controller).
-source "board/freescale/bsc9131rdb/Kconfig"
source "board/freescale/bsc9132qds/Kconfig"
source "board/freescale/c29xpcie/Kconfig"
source "board/freescale/corenet_ds/Kconfig"
diff --git a/board/freescale/bsc9131rdb/Kconfig b/board/freescale/bsc9131rdb/Kconfig
deleted file mode 100644
index dd9f765d7d..0000000000
--- a/board/freescale/bsc9131rdb/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_BSC9131RDB
-
-config SYS_BOARD
- default "bsc9131rdb"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "BSC9131RDB"
-
-endif
diff --git a/board/freescale/bsc9131rdb/MAINTAINERS b/board/freescale/bsc9131rdb/MAINTAINERS
deleted file mode 100644
index 272d4ad3aa..0000000000
--- a/board/freescale/bsc9131rdb/MAINTAINERS
+++ /dev/null
@@ -1,9 +0,0 @@
-BSC9131RDB BOARD
-M: Poonam Aggrwal <poonam.aggrwal@nxp.com>
-S: Maintained
-F: board/freescale/bsc9131rdb/
-F: include/configs/BSC9131RDB.h
-F: configs/BSC9131RDB_NAND_defconfig
-F: configs/BSC9131RDB_NAND_SYSCLK100_defconfig
-F: configs/BSC9131RDB_SPIFLASH_defconfig
-F: configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig
diff --git a/board/freescale/bsc9131rdb/Makefile b/board/freescale/bsc9131rdb/Makefile
deleted file mode 100644
index 063db4495e..0000000000
--- a/board/freescale/bsc9131rdb/Makefile
+++ /dev/null
@@ -1,21 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2011-2012 Freescale Semiconductor, Inc.
-
-MINIMAL=
-
-ifdef CONFIG_SPL_BUILD
-ifdef CONFIG_SPL_INIT_MINIMAL
-MINIMAL=y
-endif
-endif
-
-ifdef MINIMAL
-obj-y += spl_minimal.o
-else
-obj-y += bsc9131rdb.o
-obj-y += ddr.o
-endif
-
-obj-y += law.o
-obj-y += tlb.o
diff --git a/board/freescale/bsc9131rdb/README b/board/freescale/bsc9131rdb/README
deleted file mode 100644
index c8405970c1..0000000000
--- a/board/freescale/bsc9131rdb/README
+++ /dev/null
@@ -1,151 +0,0 @@
-Overview
---------
-- BSC9131 is integrated device that targets Femto base station market.
- It combines Power Architecture e500v2 and DSP StarCore SC3850 core
- technologies with MAPLE-B2F baseband acceleration processing elements.
-- It's MAPLE disabled personality is called 9231.
-
-The BSC9131 SoC includes the following function and features:
-. Power Architecture subsystem including a e500 processor with 256-Kbyte shared
- L2 cache
-. StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache
-. The Multi Accelerator Platform Engine for Femto BaseStation Baseband
- Processing (MAPLE-B2F)
-. A multi-standard baseband algorithm accelerator for Channel Decoding/Encoding,
- Fourier Transforms, UMTS chip rate processing, LTE UP/DL Channel processing,
- and CRC algorithms
-. Consists of accelerators for Convolution, Filtering, Turbo Encoding,
- Turbo Decoding, Viterbi decoding, Chiprate processing, and Matrix Inversion
- operations
-. DDR3/3L memory interface with 32-bit data width without ECC and 16-bit with
- ECC, up to 400-MHz clock/800 MHz data rate
-. Dedicated security engine featuring trusted boot
-. DMA controller
-. OCNDMA with four bidirectional channels
-. Interfaces
-. Two triple-speed Gigabit Ethernet controllers featuring network acceleration
- including IEEE 1588. v2 hardware support and virtualization (eTSEC)
-. eTSEC 1 supports RGMII/RMII
-. eTSEC 2 supports RGMII
-. High-speed USB 2.0 host and device controller with ULPI interface
-. Enhanced secure digital (SD/MMC) host controller (eSDHC)
-. Antenna interface controller (AIC), supporting three industry standard
- JESD207/three custom ADI RF interfaces (two dual port and one single port)
- and three MAXIM's MaxPHY serial interfaces
-. ADI lanes support both full duplex FDD support and half duplex TDD support
-. Universal Subscriber Identity Module (USIM) interface that facilitates
- communication to SIM cards or Eurochip pre-paid phone cards
-. TDM with one TDM port
-. Two DUART, four eSPI, and two I2C controllers
-. Integrated Flash memory controller (IFC)
-. TDM with 256 channels
-. GPIO
-. Sixteen 32-bit timers
-
-The e500 core subsystem within the Power Architecture consists of the following:
-. 32-Kbyte L1 instruction cache
-. 32-Kbyte L1 data cache
-. 256-Kbyte L2 cache/L2 memory/L2 stash
-. programmable interrupt controller (PIC)
-. Debug support
-. Timers
-
-The SC3850 core subsystem consists of the following:
-. 32 Kbyte 8-way level 1 instruction cache (L1 ICache)
-. 32 Kbyte 8-way level 1 data cache (L1 DCache)
-. 512 Kbyte 8-way level 2 unified instruction/data cache (M2 memory)
-. Memory management unit (MMU)
-. Enhanced programmable interrupt controller (EPIC)
-. Debug and profiling unit (DPU)
-. Two 32-bit timers
-
-BSC9131RDB board Overview
--------------------------
- 1Gbyte DDR3 (on board DDR)
- 128Mbyte 2K page size NAND Flash
- 256 Kbit M24256 I2C EEPROM
- 128 Mbit SPI Flash memory
- USB-ULPI
- eTSEC1: Connected to RGMII PHY
- eTSEC2: Connected to RGMII PHY
- DUART interface: supports one UARTs up to 115200 bps for console display
- USIM connector
-
-Frequency Combinations Supported
---------------------------------
-Core MHz/CCB MHz/DDR(MT/s)
-1. 1000/500/800
-2. 800/400/667
-
-Boot Methods Supported
------------------------
-1. NAND Flash
-2. SPI Flash
-
-Default Boot Method
---------------------
-NAND boot
-
-Building U-Boot
---------------
-To build the U-Boot for BSC9131RDB:
-1. NAND Flash with sysclk 66MHz(J16 on RDB closed, default)
- make BSC9131RDB_NAND
-2. NAND Flash with sysclk 100MHz(J16 on RDB open)
- make BSC9131RDB_NAND_SYSCLK100
-3. SPI Flash with sysclk 66MHz(J16 on RDB closed, default)
- make BSC9131RDB_SPIFLASH
-4. SPI Flash with sysclk 100MHz(J16 on RDB open)
- make BSC9131RDB_SPIFLASH_SYSCLK100
-
-Memory map
------------
- 0x0000_0000 0x7FFF_FFFF DDR 1G cacheable
- 0xA0000000 0xBFFFFFFF Shared DSP core L2/M2 space 512M
- 0xC100_0000 0xC13F_FFFF MAPLE-2F 4M
- 0xC1F0_0000 0xC1F3_FFFF PA SRAM Region 0 256K
- 0xC1F8_0000 0xC1F9_FFFF PA SRAM Region 1 128K
- 0xFED0_0000 0xFED0_3FFF SEC Secured RAM 16K
- 0xFEE0_0000 0xFEE0_0FFF DSP Boot ROM 4K
- 0xFF60_0000 0xFF6F_FFFF DSP CCSR 1M
- 0xFF70_0000 0xFF7F_FFFF PA CCSR 1M
- 0xFF80_0000 0xFFFF_FFFF Boot Page & NAND Buffer 8M
-
-DDR Memory map
----------------
- 0x0000_0000 0x36FF_FFFF Memory passed onto Linux
- 0x3700_0000 0x37FF_FFFF PowerPC-DSP shared control area
- 0x3800_0000 0x4FFF_FFFF DSP Private area
-
- Out of 880M, passed onto Linux, 1hugetlb page of 256M is reserved for
- data communcation between PowerPC and DSP core.
- Rest is PowerPC private area.
-
-Flashing Images
----------------
-To place a new U-Boot image in the NAND flash and then boot
-with that new image temporarily, use this:
- tftp 1000000 u-boot-nand.bin
- nand erase 0 100000
- nand write 1000000 0 100000
- reset
-
-Using the Device Tree Source File
----------------------------------
-To create the DTB (Device Tree Binary) image file,
-use a command similar to this:
-
- dtc -b 0 -f -I dts -O dtb bsc9131rdb.dts > bsc9131rdb.dtb
-
-Likely, that .dts file will come from here;
-
- linux-2.6/arch/powerpc/boot/dts/bsc9131rdb.dts
-
-Booting Linux
--------------
-Place a linux uImage in the TFTP disk area.
-
- tftp 1000000 uImage
- tftp 2000000 rootfs.ext2.gz.uboot
- tftp c00000 bsc9131rdb.dtb
- bootm 1000000 2000000 c00000
diff --git a/board/freescale/bsc9131rdb/bsc9131rdb.c b/board/freescale/bsc9131rdb/bsc9131rdb.c
deleted file mode 100644
index 75c2aec75d..0000000000
--- a/board/freescale/bsc9131rdb/bsc9131rdb.c
+++ /dev/null
@@ -1,82 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2011-2012 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <image.h>
-#include <init.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/io.h>
-#include <env.h>
-#include <miiphy.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <fsl_mdio.h>
-#include <tsec.h>
-#include <jffs2/load_kernel.h>
-#include <mtd_node.h>
-#include <flash.h>
-#include <netdev.h>
-
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
- clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_CTS_B0_GPIO42);
- setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_CTS_B0_DSP_TMS);
-
- clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_RTS_B0_GPIO43);
- setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_RTS_B0_DSP_TCK |
- MPC85xx_PMUXCR2_UART_CTS_B1_SIM_PD);
- setbits_be32(&gur->halt_req_mask, HALTED_TO_HALT_REQ_MASK_0);
- clrsetbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_IFC_AD_GPIO_MASK |
- MPC85xx_PMUXCR_IFC_AD17_GPO_MASK,
- MPC85xx_PMUXCR_IFC_AD_GPIO |
- MPC85xx_PMUXCR_IFC_AD17_GPO | MPC85xx_PMUXCR_SDHC_USIM);
-
- return 0;
-}
-
-int checkboard(void)
-{
- struct cpu_type *cpu;
-
- cpu = gd->arch.cpu;
- printf("Board: %sRDB\n", cpu->name);
-
- return 0;
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-#ifdef CONFIG_FDT_FIXUP_PARTITIONS
-static const struct node_info nodes[] = {
- { "fsl,ifc-nand", MTD_DEV_TYPE_NAND, },
-};
-#endif
-int ft_board_setup(void *blob, bd_t *bd)
-{
- phys_addr_t base;
- phys_size_t size;
-
- ft_cpu_setup(blob, bd);
-
- base = env_get_bootm_low();
- size = env_get_bootm_size();
-
- fdt_fixup_memory(blob, (u64)base, (u64)size);
-#ifdef CONFIG_FDT_FIXUP_PARTITIONS
- fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
-#endif
-
- fsl_fdt_fixup_dr_usb(blob, bd);
-
- return 0;
-}
-#endif
diff --git a/board/freescale/bsc9131rdb/ddr.c b/board/freescale/bsc9131rdb/ddr.c
deleted file mode 100644
index 0951d7758a..0000000000
--- a/board/freescale/bsc9131rdb/ddr.c
+++ /dev/null
@@ -1,170 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2011-2012 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <init.h>
-#include <vsprintf.h>
-#include <asm/mmu.h>
-#include <asm/immap_85xx.h>
-#include <asm/processor.h>
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-#include <asm/io.h>
-#include <asm/fsl_law.h>
-
-#ifndef CONFIG_SYS_DDR_RAW_TIMING
-#define CONFIG_SYS_DRAM_SIZE 1024
-
-fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
- .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
- .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
- .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
- .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
- .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
- .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
- .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
- .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
- .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
- .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
- .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
- .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
- .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
- .ddr_data_init = CONFIG_MEM_INIT_VALUE,
- .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
- .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
- .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
- .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
- .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
- .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
- .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_800,
- .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
- .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
- .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
-};
-
-fixed_ddr_parm_t fixed_ddr_parm_0[] = {
- {750, 850, &ddr_cfg_regs_800},
- {0, 0, NULL}
-};
-
-unsigned long get_sdram_size(void)
-{
- return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DRAM_SIZE);
-}
-
-/*
- * Fixed sdram init -- doesn't use serial presence detect.
- */
-phys_size_t fixed_sdram(void)
-{
- int i;
- char buf[32];
- fsl_ddr_cfg_regs_t ddr_cfg_regs;
- phys_size_t ddr_size;
- ulong ddr_freq, ddr_freq_mhz;
-
- ddr_freq = get_ddr_freq(0);
- ddr_freq_mhz = ddr_freq / 1000000;
-
- printf("Configuring DDR for %s MT/s data rate\n",
- strmhz(buf, ddr_freq));
-
- for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
- if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) &&
- (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) {
- memcpy(&ddr_cfg_regs, fixed_ddr_parm_0[i].ddr_settings,
- sizeof(ddr_cfg_regs));
- break;
- }
- }
-
- if (fixed_ddr_parm_0[i].max_freq == 0) {
- panic("Unsupported DDR data rate %s MT/s data rate\n",
- strmhz(buf, ddr_freq));
- }
-
- ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
- fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
-
- if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, ddr_size,
- LAW_TRGT_IF_DDR_1) < 0) {
- printf("ERROR setting Local Access Windows for DDR\n");
- return 0;
- }
-
- return ddr_size;
-}
-
-#else /* CONFIG_SYS_DDR_RAW_TIMING */
-/* Micron MT41J256M8HX-15E */
-dimm_params_t ddr_raw_timing = {
- .n_ranks = 1,
- .rank_density = 1073741824u,
- .capacity = 1073741824u,
- .primary_sdram_width = 32,
- .ec_sdram_width = 0,
- .registered_dimm = 0,
- .mirrored_dimm = 0,
- .n_row_addr = 15,
- .n_col_addr = 10,
- .n_banks_per_sdram_device = 8,
- .edc_config = 0,
- .burst_lengths_bitmask = 0x0c,
-
- .tckmin_x_ps = 1870,
- .caslat_x = 0x1e << 4, /* 5,6,7,8 */
- .taa_ps = 13125,
- .twr_ps = 15000,
- .trcd_ps = 13125,
- .trrd_ps = 7500,
- .trp_ps = 13125,
- .tras_ps = 37500,
- .trc_ps = 50625,
- .trfc_ps = 160000,
- .twtr_ps = 7500,
- .trtp_ps = 7500,
- .refresh_rate_ps = 7800000,
- .tfaw_ps = 37500,
-};
-
-int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
- unsigned int controller_number,
- unsigned int dimm_number)
-{
- const char dimm_model[] = "Fixed DDR on board";
-
- if ((controller_number == 0) && (dimm_number == 0)) {
- memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
- memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
- memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
- }
-
- return 0;
-}
-
-void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- int i;
- popts->clk_adjust = 6;
- popts->cpo_override = 0x1f;
- popts->write_data_delay = 2;
- popts->half_strength_driver_enable = 1;
- /* Write leveling override */
- popts->wrlvl_en = 1;
- popts->wrlvl_override = 1;
- popts->wrlvl_sample = 0xf;
- popts->wrlvl_start = 0x8;
- popts->trwt_override = 1;
- popts->trwt = 0;
-
- for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
- popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
- popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
- }
-}
-
-#endif /* CONFIG_SYS_DDR_RAW_TIMING */
diff --git a/board/freescale/bsc9131rdb/law.c b/board/freescale/bsc9131rdb/law.c
deleted file mode 100644
index ccfe4a2410..0000000000
--- a/board/freescale/bsc9131rdb/law.c
+++ /dev/null
@@ -1,18 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2011-2012 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-struct law_entry law_table[] = {
- SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
- SET_LAW(CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS, LAW_SIZE_1M,
- LAW_TRGT_IF_DSP_CCSR),
- SET_LAW(CONFIG_SYS_FSL_DSP_M2_RAM_ADDR, LAW_SIZE_16M,
- LAW_TRGT_IF_OCN_DSP),
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/bsc9131rdb/spl_minimal.c b/board/freescale/bsc9131rdb/spl_minimal.c
deleted file mode 100644
index 4ae9ba06c8..0000000000
--- a/board/freescale/bsc9131rdb/spl_minimal.c
+++ /dev/null
@@ -1,105 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <init.h>
-#include <ns16550.h>
-#include <asm/io.h>
-#include <nand.h>
-#include <linux/compiler.h>
-#include <asm/fsl_law.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/global_data.h>
-#include <linux/delay.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Fixed sdram init -- doesn't use serial presence detect.
- */
-static void sdram_init(void)
-{
- struct ccsr_ddr __iomem *ddr =
- (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
-
- __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
- __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
-#if CONFIG_CHIP_SELECTS_PER_CTRL > 1
- __raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds);
- __raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config);
-#endif
- __raw_writel(CONFIG_SYS_DDR_TIMING_3_800, &ddr->timing_cfg_3);
- __raw_writel(CONFIG_SYS_DDR_TIMING_0_800, &ddr->timing_cfg_0);
- __raw_writel(CONFIG_SYS_DDR_TIMING_1_800, &ddr->timing_cfg_1);
- __raw_writel(CONFIG_SYS_DDR_TIMING_2_800, &ddr->timing_cfg_2);
-
- __raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2);
- __raw_writel(CONFIG_SYS_DDR_MODE_1_800, &ddr->sdram_mode);
- __raw_writel(CONFIG_SYS_DDR_MODE_2_800, &ddr->sdram_mode_2);
-
- __raw_writel(CONFIG_SYS_DDR_INTERVAL_800, &ddr->sdram_interval);
- __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
- __raw_writel(CONFIG_SYS_DDR_CLK_CTRL_800, &ddr->sdram_clk_cntl);
-
- __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_800, &ddr->ddr_wrlvl_cntl);
- __raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4);
- __raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5);
- __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl);
-
- /* Set, but do not enable the memory */
- __raw_writel(CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN, &ddr->sdram_cfg);
-
- asm volatile("sync;isync");
- udelay(500);
-
- /* Let the controller go */
- out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN);
-
- set_next_law(CONFIG_SYS_NAND_DDR_LAW, LAW_SIZE_1G, LAW_TRGT_IF_DDR_1);
-}
-
-void board_init_f(ulong bootflag)
-{
- u32 plat_ratio;
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
- /* initialize selected port with appropriate baud rate */
- plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
- plat_ratio >>= 1;
- gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
-
- NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
- gd->bus_clk / 16 / CONFIG_BAUDRATE);
-
- puts("\nNAND boot... ");
-
- /* Initialize the DDR3 */
- sdram_init();
-
- /* copy code to RAM and jump to it - this should not return */
- /* NOTE - code has to be copied out of NAND buffer before
- * other blocks can be read.
- */
- relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
- nand_boot();
-}
-
-void putc(char c)
-{
- if (c == '\n')
- NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
-
- NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
-}
-
-void puts(const char *str)
-{
- while (*str)
- putc(*str++);
-}
diff --git a/board/freescale/bsc9131rdb/tlb.c b/board/freescale/bsc9131rdb/tlb.c
deleted file mode 100644
index e1aacf0607..0000000000
--- a/board/freescale/bsc9131rdb/tlb.c
+++ /dev/null
@@ -1,61 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2011-2012 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
- /* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
- CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
- CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
- CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
-
- /* TLB 1 */
- /* *I*** - Covers boot page */
- SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_4K, 1),
-#ifdef CONFIG_SPL_NAND_BOOT
- SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 10, BOOKE_PAGESZ_4K, 1),
-#endif
-
- /* *I*G* - CCSRBAR (PA) */
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 1, BOOKE_PAGESZ_1M, 1),
-
- /* CCSRBAR (DSP) */
- SET_TLB_ENTRY(1, CONFIG_SYS_FSL_DSP_CCSRBAR,
- CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 2, BOOKE_PAGESZ_1M, 1),
-
-#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
- SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
- 0, 8, BOOKE_PAGESZ_1G, 1),
-#endif
-
- SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 3, BOOKE_PAGESZ_1M, 1)
-
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/configs/BSC9131RDB_NAND_SYSCLK100_defconfig b/configs/BSC9131RDB_NAND_SYSCLK100_defconfig
deleted file mode 100644
index 64f6dadc22..0000000000
--- a/configs/BSC9131RDB_NAND_SYSCLK100_defconfig
+++ /dev/null
@@ -1,64 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x00201000
-CONFIG_ENV_SIZE=0x20000
-CONFIG_ENV_OFFSET=0xE0000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_TEXT_BASE=0xFFFFE000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_BSC9131RDB=y
-CONFIG_SYS_CUSTOM_LDSCRIPT=y
-CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_CLK_100"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-# CONFIG_MISC_INIT_R is not set
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_NAND_BOOT=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_I2C=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash,"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)"
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_CAAM=y
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-# CONFIG_PCI is not set
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
-CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/BSC9131RDB_NAND_defconfig b/configs/BSC9131RDB_NAND_defconfig
deleted file mode 100644
index eda1ac428c..0000000000
--- a/configs/BSC9131RDB_NAND_defconfig
+++ /dev/null
@@ -1,63 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x00201000
-CONFIG_ENV_SIZE=0x20000
-CONFIG_ENV_OFFSET=0xE0000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_TEXT_BASE=0xFFFFE000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_BSC9131RDB=y
-CONFIG_SYS_CUSTOM_LDSCRIPT=y
-CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-# CONFIG_MISC_INIT_R is not set
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_NAND_BOOT=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_I2C=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash,"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)"
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_CAAM=y
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-# CONFIG_PCI is not set
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
-CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig b/configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig
deleted file mode 100644
index 8ac33150f8..0000000000
--- a/configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig
+++ /dev/null
@@ -1,56 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11000000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_BSC9131RDB=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH,SYS_CLK_100"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-# CONFIG_MISC_INIT_R is not set
-CONFIG_HUSH_PARSER=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_I2C=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash,"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)"
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_CAAM=y
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-# CONFIG_PCI is not set
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
-CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/BSC9131RDB_SPIFLASH_defconfig b/configs/BSC9131RDB_SPIFLASH_defconfig
deleted file mode 100644
index 10d866661b..0000000000
--- a/configs/BSC9131RDB_SPIFLASH_defconfig
+++ /dev/null
@@ -1,56 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11000000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_BSC9131RDB=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-# CONFIG_MISC_INIT_R is not set
-CONFIG_HUSH_PARSER=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_I2C=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash,"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)"
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_CAAM=y
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-# CONFIG_PCI is not set
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
-CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h
deleted file mode 100644
index 879173f6f2..0000000000
--- a/include/configs/BSC9131RDB.h
+++ /dev/null
@@ -1,337 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2011-2012 Freescale Semiconductor, Inc.
- */
-
-/*
- * BSC9131 RDB board configuration file
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_NAND_FSL_IFC
-
-#ifdef CONFIG_SPIFLASH
-#define CONFIG_RAMBOOT_SPIFLASH
-#define CONFIG_SYS_RAMBOOT
-#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
-#endif
-
-#ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SPL_INIT_MINIMAL
-#define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
-
-#define CONFIG_SPL_MAX_SIZE 8192
-#define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
-#define CONFIG_SPL_RELOC_STACK 0x00100000
-#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
-#define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
-#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0
-#endif
-
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
-#else
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-#endif
-
-/* High Level Configuration Options */
-
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on 9131 RDB */
-#if defined(CONFIG_SYS_CLK_100)
-#define CONFIG_SYS_CLK_FREQ 100000000 /* SYSCLK for 9131 RDB */
-#else
-#define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for 9131 RDB */
-#endif
-
-#define CONFIG_HWCONFIG
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_L2_CACHE /* toggle L2 cache */
-#define CONFIG_BTB /* enable branch predition */
-
-/* DDR Setup */
-#undef CONFIG_SYS_DDR_RAW_TIMING
-#undef CONFIG_DDR_SPD
-#define CONFIG_SYS_SPD_BUS_NUM 0
-#define SPD_EEPROM_ADDRESS 0x52 /* I2C access */
-
-#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
-
-#ifndef __ASSEMBLY__
-extern unsigned long get_sdram_size(void);
-#endif
-#define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_CHIP_SELECTS_PER_CTRL 1
-
-#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
-#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
-#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
-
-#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
-#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
-#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
-#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
-
-#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
-#define CONFIG_SYS_DDR_SR_CNTR 0x00000000
-#define CONFIG_SYS_DDR_RCW_1 0x00000000
-#define CONFIG_SYS_DDR_RCW_2 0x00000000
-#define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
-#define CONFIG_SYS_DDR_CONTROL_2 0x24401000
-#define CONFIG_SYS_DDR_TIMING_4 0x00000001
-#define CONFIG_SYS_DDR_TIMING_5 0x02401400
-
-#define CONFIG_SYS_DDR_TIMING_3_800 0x00030000
-#define CONFIG_SYS_DDR_TIMING_0_800 0x00110104
-#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644
-#define CONFIG_SYS_DDR_TIMING_2_800 0x0fa888cf
-#define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000
-#define CONFIG_SYS_DDR_MODE_1_800 0x00441420
-#define CONFIG_SYS_DDR_MODE_2_800 0x8000c000
-#define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100
-#define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608
-
-/*
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- */
-/* relocated CCSRBAR */
-#define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT
-
-#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses */
- /* CONFIG_SYS_IMMR */
-/* DSP CCSRBAR */
-#define CONFIG_SYS_FSL_DSP_CCSRBAR CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
-#define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
-
-/*
- * Memory map
- *
- * 0x0000_0000 0x3FFF_FFFF DDR 1G cacheable
- * 0x8800_0000 0x8810_0000 IFC internal SRAM 1M
- * 0xB000_0000 0xB0FF_FFFF DSP core M2 memory 16M
- * 0xC100_0000 0xC13F_FFFF MAPLE-2F 4M
- * 0xC1F0_0000 0xC1F3_FFFF PA L2 SRAM Region 0 256K
- * 0xC1F8_0000 0xC1F9_FFFF PA L2 SRAM Region 1 128K
- * 0xFED0_0000 0xFED0_3FFF SEC Secured RAM 16K
- * 0xFF60_0000 0xFF6F_FFFF DSP CCSR 1M
- * 0xFF70_0000 0xFF7F_FFFF PA CCSR 1M
- * 0xFF80_0000 0xFFFF_FFFF Boot Page & NAND flash buffer 8M
- *
- */
-
-/*
- * IFC Definitions
- */
-
-/* NAND Flash on IFC */
-#define CONFIG_SYS_NAND_BASE 0xff800000
-#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
-
-#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
- | CSPR_PORT_SIZE_8 /* Port Size = 8 bit*/ \
- | CSPR_MSEL_NAND /* MSEL = NAND */ \
- | CSPR_V)
-#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
-
-#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
- | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
- | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
- | CSOR_NAND_RAL_2 /* RAL = 2Byes */ \
- | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
- | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
- | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
-
-/* NAND Flash Timing Params */
-#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x03) \
- | FTIM0_NAND_TWP(0x05) \
- | FTIM0_NAND_TWCHT(0x02) \
- | FTIM0_NAND_TWH(0x04))
-#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1C) \
- | FTIM1_NAND_TWBE(0x1E) \
- | FTIM1_NAND_TRR(0x07) \
- | FTIM1_NAND_TRP(0x05))
-#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \
- | FTIM2_NAND_TREH(0x04) \
- | FTIM2_NAND_TWHRE(0x11))
-#define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
-
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
-
-#define CONFIG_SYS_NAND_DDR_LAW 11
-
-/* Set up IFC registers for boot location NAND */
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
-
-#define CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000/* End of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
- - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
-
-/* Serial Port */
-#undef CONFIG_SERIAL_SOFTWARE_FIFO
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_NS16550_MIN_FUNCTIONS
-#endif
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
-
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-
-/* I2C EEPROM */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
-
-/* eSPI - Enhanced SPI */
-
-#if defined(CONFIG_TSEC_ENET)
-
-#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
-#define CONFIG_TSEC1 1
-#define CONFIG_TSEC1_NAME "eTSEC1"
-#define CONFIG_TSEC2 1
-#define CONFIG_TSEC2_NAME "eTSEC2"
-
-#define TSEC1_PHY_ADDR 0
-#define TSEC2_PHY_ADDR 3
-
-#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-
-#define TSEC1_PHYIDX 0
-
-#define TSEC2_PHYIDX 0
-
-#define CONFIG_ETHPRIME "eTSEC1"
-
-#endif /* CONFIG_TSEC_ENET */
-
-/*
- * Environment
- */
-#if defined(CONFIG_RAMBOOT_SPIFLASH)
-#elif defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
-#endif
-
-#define CONFIG_LOADS_ECHO /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 64 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
-#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
-#ifdef CONFIG_USB_EHCI_HCD
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_USB_EHCI_FSL
-#define CONFIG_HAS_FSL_DR_USB
-#endif
-
-/*
- * Dynamic MTD Partition support with mtdparts
- */
-
-/*
- * Environment Configuration
- */
-
-#if defined(CONFIG_TSEC_ENET)
-#define CONFIG_HAS_ETH0
-#endif
-
-#define CONFIG_HOSTNAME "BSC9131rdb"
-#define CONFIG_ROOTPATH "/opt/nfsroot"
-#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "uboot=" CONFIG_UBOOTPATH "\0" \
- "loadaddr=1000000\0" \
- "bootfile=uImage\0" \
- "consoledev=ttyS0\0" \
- "ramdiskaddr=2000000\0" \
- "ramdiskfile=rootfs.ext2.gz.uboot\0" \
- "fdtaddr=1e00000\0" \
- "fdtfile=bsc9131rdb.dtb\0" \
- "bdev=sda1\0" \
- "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
- "bootm_size=0x37000000\0" \
- "othbootargs=ramdisk_size=600000 " \
- "default_hugepagesz=256m hugepagesz=256m hugepages=1\0" \
- "usbext2boot=setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs; " \
- "usb start;" \
- "ext2load usb 0:4 $loadaddr $bootfile;" \
- "ext2load usb 0:4 $fdtaddr $fdtfile;" \
- "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs; " \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
-
-#endif /* __CONFIG_H */
--
2.25.1
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 03/24] arm: Remove configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig board
2020-05-27 16:46 [PATCH 00/24] spi: dm-conversion (part2) Jagan Teki
2020-05-27 16:46 ` [PATCH 01/24] arm: Remove configs/B4420QDS_NAND_defconfig board Jagan Teki
2020-05-27 16:46 ` [PATCH 02/24] arm: Remove configs/BSC9131RDB_NAND_SYSCLK100_defconfig board Jagan Teki
@ 2020-05-27 16:46 ` Jagan Teki
2020-05-28 5:26 ` Priyanka Jain
2020-05-27 16:46 ` [PATCH 04/24] arm: Remove configs/C29XPCIE_NAND_defconfig board Jagan Teki
` (19 subsequent siblings)
22 siblings, 1 reply; 59+ messages in thread
From: Jagan Teki @ 2020-05-27 16:46 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_SPI by the deadline.
Remove it.
Patch-cc: Naveen Burmi <naveen.burmi@nxp.com>
Patch-cc: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
arch/powerpc/cpu/mpc85xx/Kconfig | 1 -
board/freescale/bsc9132qds/Kconfig | 14 -
board/freescale/bsc9132qds/MAINTAINERS | 25 -
board/freescale/bsc9132qds/Makefile | 21 -
board/freescale/bsc9132qds/README | 150 -----
board/freescale/bsc9132qds/bsc9132qds.c | 432 --------------
board/freescale/bsc9132qds/ddr.c | 191 ------
board/freescale/bsc9132qds/law.c | 28 -
board/freescale/bsc9132qds/spl_minimal.c | 117 ----
board/freescale/bsc9132qds/tlb.c | 91 ---
...BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig | 66 ---
configs/BSC9132QDS_NAND_DDRCLK100_defconfig | 72 ---
...BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig | 66 ---
configs/BSC9132QDS_NAND_DDRCLK133_defconfig | 72 ---
.../BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig | 65 ---
configs/BSC9132QDS_NOR_DDRCLK100_defconfig | 63 --
.../BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig | 65 ---
configs/BSC9132QDS_NOR_DDRCLK133_defconfig | 63 --
...C9132QDS_SDCARD_DDRCLK100_SECURE_defconfig | 66 ---
configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig | 63 --
...C9132QDS_SDCARD_DDRCLK133_SECURE_defconfig | 66 ---
configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig | 63 --
...132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig | 66 ---
.../BSC9132QDS_SPIFLASH_DDRCLK100_defconfig | 64 --
...132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig | 66 ---
.../BSC9132QDS_SPIFLASH_DDRCLK133_defconfig | 64 --
include/configs/BSC9132QDS.h | 548 ------------------
27 files changed, 2668 deletions(-)
delete mode 100644 board/freescale/bsc9132qds/Kconfig
delete mode 100644 board/freescale/bsc9132qds/MAINTAINERS
delete mode 100644 board/freescale/bsc9132qds/Makefile
delete mode 100644 board/freescale/bsc9132qds/README
delete mode 100644 board/freescale/bsc9132qds/bsc9132qds.c
delete mode 100644 board/freescale/bsc9132qds/ddr.c
delete mode 100644 board/freescale/bsc9132qds/law.c
delete mode 100644 board/freescale/bsc9132qds/spl_minimal.c
delete mode 100644 board/freescale/bsc9132qds/tlb.c
delete mode 100644 configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig
delete mode 100644 configs/BSC9132QDS_NAND_DDRCLK100_defconfig
delete mode 100644 configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig
delete mode 100644 configs/BSC9132QDS_NAND_DDRCLK133_defconfig
delete mode 100644 configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig
delete mode 100644 configs/BSC9132QDS_NOR_DDRCLK100_defconfig
delete mode 100644 configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig
delete mode 100644 configs/BSC9132QDS_NOR_DDRCLK133_defconfig
delete mode 100644 configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig
delete mode 100644 configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig
delete mode 100644 configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig
delete mode 100644 configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig
delete mode 100644 configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig
delete mode 100644 configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig
delete mode 100644 configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig
delete mode 100644 configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig
delete mode 100644 include/configs/BSC9132QDS.h
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index bb59943232..5ca4a6e8ba 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -1589,7 +1589,6 @@ config SYS_FSL_LBC_CLK_DIV
Defines divider of platform clock(clock input to
eLBC controller).
-source "board/freescale/bsc9132qds/Kconfig"
source "board/freescale/c29xpcie/Kconfig"
source "board/freescale/corenet_ds/Kconfig"
source "board/freescale/mpc8536ds/Kconfig"
diff --git a/board/freescale/bsc9132qds/Kconfig b/board/freescale/bsc9132qds/Kconfig
deleted file mode 100644
index e5499e6129..0000000000
--- a/board/freescale/bsc9132qds/Kconfig
+++ /dev/null
@@ -1,14 +0,0 @@
-if TARGET_BSC9132QDS
-
-config SYS_BOARD
- default "bsc9132qds"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "BSC9132QDS"
-
-source "board/freescale/common/Kconfig"
-
-endif
diff --git a/board/freescale/bsc9132qds/MAINTAINERS b/board/freescale/bsc9132qds/MAINTAINERS
deleted file mode 100644
index 95abe3d408..0000000000
--- a/board/freescale/bsc9132qds/MAINTAINERS
+++ /dev/null
@@ -1,25 +0,0 @@
-BSC9132QDS BOARD
-M: Naveen Burmi <naveen.burmi@nxp.com>
-S: Maintained
-F: board/freescale/bsc9132qds/
-F: include/configs/BSC9132QDS.h
-F: configs/BSC9132QDS_NAND_DDRCLK100_defconfig
-F: configs/BSC9132QDS_NAND_DDRCLK133_defconfig
-F: configs/BSC9132QDS_NOR_DDRCLK100_defconfig
-F: configs/BSC9132QDS_NOR_DDRCLK133_defconfig
-F: configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig
-F: configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig
-F: configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig
-F: configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig
-
-BSC9132QDS_NAND_DDRCLK100_SECURE BOARD
-M: Ruchika Gupta <ruchika.gupta@nxp.com>
-S: Maintained
-F: configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig
-F: configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig
-F: configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig
-F: configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig
-F: configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig
-F: configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig
-F: configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig
-F: configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig
diff --git a/board/freescale/bsc9132qds/Makefile b/board/freescale/bsc9132qds/Makefile
deleted file mode 100644
index dcbdf42147..0000000000
--- a/board/freescale/bsc9132qds/Makefile
+++ /dev/null
@@ -1,21 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2013 Freescale Semiconductor, Inc.
-
-MINIMAL=
-
-ifdef CONFIG_SPL_BUILD
-ifdef CONFIG_SPL_INIT_MINIMAL
-MINIMAL=y
-endif
-endif
-
-ifdef MINIMAL
-obj-y += spl_minimal.o
-else
-obj-y += bsc9132qds.o
-obj-y += ddr.o
-endif
-
-obj-y += law.o
-obj-y += tlb.o
diff --git a/board/freescale/bsc9132qds/README b/board/freescale/bsc9132qds/README
deleted file mode 100644
index ede95d41da..0000000000
--- a/board/freescale/bsc9132qds/README
+++ /dev/null
@@ -1,150 +0,0 @@
-Overview
---------
- The BSC9132 is a highly integrated device that targets the evolving
- Microcell, Picocell, and Enterprise-Femto base station market subsegments.
-
- The BSC9132 device combines Power Architecture e500 and DSP StarCore SC3850
- core technologies with MAPLE-B2P baseband acceleration processing elements
- to address the need for a high performance, low cost, integrated solution
- that handles all required processing layers without the need for an
- external device except for an RF transceiver or, in a Micro base station
- configuration, a host device that handles the L3/L4 and handover between
- sectors.
-
- The BSC9132 SoC includes the following function and features:
- - Power Architecture subsystem including two e500 processors with
- 512-Kbyte shared L2 cache
- - Two StarCore SC3850 DSP subsystems, each with a 512-Kbyte private L2
- cache
- - 32 Kbyte of shared M3 memory
- - The Multi Accelerator Platform Engine for Pico BaseStation Baseband
- Processing (MAPLE-B2P)
- - Two DDR3/3L memory interfaces with 32-bit data width (40 bits including
- ECC), up to 1333 MHz data rate
- - Dedicated security engine featuring trusted boot
- - Two DMA controllers
- - OCNDMA with four bidirectional channels
- - SysDMA with sixteen bidirectional channels
- - Interfaces
- - Four-lane SerDes PHY
- - PCI Express controller complies with the PEX Specification-Rev 2.0
- - Two Common Public Radio Interface (CPRI) controller lanes
- - High-speed USB 2.0 host and device controller with ULPI interface
- - Enhanced secure digital (SD/MMC) host controller (eSDHC)
- - Antenna interface controller (AIC), supporting four industry
- standard JESD207/four custom ADI RF interfaces
- - ADI lanes support both full duplex FDD support & half duplex TDD
- - Universal Subscriber Identity Module (USIM) interface that
- facilitates communication to SIM cards or Eurochip pre-paid phone
- cards
- - Two DUART, two eSPI, and two I2C controllers
- - Integrated Flash memory controller (IFC)
- - GPIO
- - Sixteen 32-bit timers
-
-The SC3850 core subsystem consists of the following:
- - 32 KB, 8-way, level 1 instruction cache (L1 ICache)
- - 32 KB, 8-way, level 1 data cache (L1 DCache)
- - 512 KB, 8-way, level 2 unified instruction/data cache (L2 cache/M2 memory)
- - Memory management unit (MMU)
- - Global interrupt controller ( GIC)
- - Debug and profiling unit (DPU)
- - Two 32-bit quad timers
-
-BSC9132QDS board Overview
--------------------------
- 2Gbyte DDR3 (on board DDR), Dual Ranki
- 32Mbyte 16bit NOR flash
- 128Mbyte 2K page size NAND Flash
- 256 Kbit M24256 I2C EEPROM
- 128 Mbit SPI Flash memory
- SD slot
- USB-ULPI
- eTSEC1: Connected to SGMII PHY
- eTSEC2: Connected to SGMII PHY
- PCIe
- CPRI
- SerDes
- I2C RTC
- DUART interface: supports one UARTs up to 115200 bps for console display
-
-Frequency Combinations Supported
---------------------------------
-Core MHz/CCB MHz/DDR(MT/s)
-1. CPU0/CPU1/CCB/DDR: 1000MHz/1000MHz/500MHz/800MHz
- (SYSCLK = 100MHz, DDRCLK = 100MHz)
-2. CPU0/CPU1/CCB/DDR: 1200MHz/1200MHz/600MHz/1330MHz
- (SYSCLK = 100MHz, DDRCLK = 133MHz)
-
-Boot Methods Supported
------------------------
-1. NOR Flash
-2. NAND Flash
-3. SD Card
-4. SPI flash
-
-Default Boot Method
---------------------
-NOR boot
-
-Building U-Boot
---------------
-To build the U-Boot for BSC9132QDS:
-1. NOR Flash
- make BSC9132QDS_NOR_DDRCLK100 : For 100MHZ DDR CLK
- make BSC9132QDS_NOR_DDRCLK133 : For 133MHZ DDR CLK
-2. NAND Flash : It is currently not supported
-3. SPI Flash
- make BSC9132QDS_SPIFLASH_DDRCLK100 : For 100MHZ DDR CLK
- make BSC9132QDS_SPIFLASH_DDRCLK133 : For 133MHZ DDR CLK
-4. SD Card
- make BSC9132QDS_SDCARD_DDRCLK100 : For 100MHZ DDR CLK
- make BSC9132QDS_SDCARD_DDRCLK133 : For 133MHZ DDR CLK
-
-Memory map
------------
- 0x0000_0000 0x7FFF_FFFF DDR 2G cacheable
- 0x8000_0000 0x8FFF_FFFF NOR Flash 256M
- 0x9000_0000 0x9FFF_FFFF PCIe Memory 256M
- 0xA000_0000 0xA7FF_FFFF DSP core1 L2 space 128M
- 0xB000_0000 0xB0FF_FFFF DSP core0 M2 space 16M
- 0xB100_0000 0xB1FF_FFFF DSP core1 M2 space 16M
- 0xC000_0000 0xC000_7FFF M3 Memory 32K
- 0xC001_0000 0xC001_FFFF PCI Express I/O 64K
- 0xC100_0000 0xC13F_FFFF MAPLE-2F 4M
- 0xC1F0_0000 0xC1F7_FFFF PA SRAM Region 0 512K
- 0xC1F8_0000 0xC1FB_FFFF PA SRAM Region 1 512K
- 0xFED0_0000 0xFED0_3FFF SEC Secured RAM 16K
- 0xFEE0_0000 0xFEE0_0FFF DSP Boot ROM 4K
- 0xFF60_0000 0xFF6F_FFFF DSP CCSR 1M
- 0xFF70_0000 0xFF7F_FFFF PA CCSR 1M
- 0xFF80_0000 0xFFFF_FFFF Boot Page & NAND Buffer 8M
-
-Flashing Images
----------------
-To place a new U-Boot image in the NAND flash and then boot
-with that new image temporarily, use this:
- tftp 1000000 u-boot-nand.bin
- nand erase 0 100000
- nand write 1000000 0 100000
- reset
-
-Using the Device Tree Source File
----------------------------------
-To create the DTB (Device Tree Binary) image file,
-use a command similar to this:
-
- dtc -b 0 -f -I dts -O dtb bsc9132qds.dts > bsc9132qds.dtb
-
-Likely, that .dts file will come from here;
-
- linux-2.6/arch/powerpc/boot/dts/bsc9132qds.dts
-
-Booting Linux
--------------
-Place a linux uImage in the TFTP disk area.
-
- tftp 1000000 uImage
- tftp 2000000 rootfs.ext2.gz.uboot
- tftp c00000 bsc9132qds.dtb
- bootm 1000000 2000000 c00000
diff --git a/board/freescale/bsc9132qds/bsc9132qds.c b/board/freescale/bsc9132qds/bsc9132qds.c
deleted file mode 100644
index 6870674f7a..0000000000
--- a/board/freescale/bsc9132qds/bsc9132qds.c
+++ /dev/null
@@ -1,432 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <image.h>
-#include <init.h>
-#include <net.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/io.h>
-#include <env.h>
-#include <miiphy.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <fsl_mdio.h>
-#include <tsec.h>
-#include <mmc.h>
-#include <netdev.h>
-#include <fsl_ifc.h>
-#include <hwconfig.h>
-#include <i2c.h>
-#include <fsl_ddr_sdram.h>
-#include <jffs2/load_kernel.h>
-#include <mtd_node.h>
-#include <flash.h>
-
-#ifdef CONFIG_PCI
-#include <pci.h>
-#include <asm/fsl_pci.h>
-#endif
-
-#include "../common/qixis.h"
-DECLARE_GLOBAL_DATA_PTR;
-
-
-int board_early_init_f(void)
-{
- struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
-
- setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
-
- return 0;
-}
-
-void board_config_serdes_mux(void)
-{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- u32 pordevsr = in_be32(&gur->pordevsr);
- u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
- MPC85xx_PORDEVSR_IO_SEL_SHIFT;
-
- switch (srds_cfg) {
- /* PEX(1) PEX(2) CPRI 2 CPRI 1 */
- case 1:
- case 2:
- case 3:
- case 4:
- case 5:
- case 22:
- case 23:
- case 24:
- case 25:
- case 26:
- QIXIS_WRITE_I2C(brdcfg[4], 0x03);
- break;
-
- /* PEX(1) PEX(2) SGMII1 CPRI 1 */
- case 6:
- case 7:
- case 8:
- case 9:
- case 10:
- case 27:
- case 28:
- case 29:
- case 30:
- case 31:
- QIXIS_WRITE_I2C(brdcfg[4], 0x01);
- break;
-
- /* PEX(1) PEX(2) SGMII1 SGMII2 */
- case 11:
- case 32:
- QIXIS_WRITE_I2C(brdcfg[4], 0x00);
- break;
-
- /* PEX(1) SGMII2 CPRI 2 CPRI 1 */
- case 12:
- case 13:
- case 14:
- case 15:
- case 16:
- case 33:
- case 34:
- case 35:
- case 36:
- case 37:
- QIXIS_WRITE_I2C(brdcfg[4], 0x07);
- break;
-
- /* PEX(1) SGMII2 SGMII1 CPRI 1 */
- case 17:
- case 18:
- case 19:
- case 20:
- case 21:
- case 38:
- case 39:
- case 40:
- case 41:
- case 42:
- QIXIS_WRITE_I2C(brdcfg[4], 0x05);
- break;
-
- /* SGMII1 SGMII2 CPRI 2 CPRI 1 */
- case 43:
- case 44:
- case 45:
- case 46:
- case 47:
- QIXIS_WRITE_I2C(brdcfg[4], 0x0F);
- break;
-
-
- default:
- break;
- }
-}
-
-/* Configure DSP DDR controller */
-void dsp_ddr_configure(void)
-{
- /*
- *There are separate DDR-controllers for DSP and PowerPC side DDR.
- *copy the ddr controller settings from PowerPC side DDR controller
- *to the DSP DDR controller as connected DDR memories are similar.
- */
- struct ccsr_ddr __iomem *pa_ddr =
- (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
- struct ccsr_ddr temp_ddr;
- struct ccsr_ddr __iomem *dsp_ddr =
- (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR;
-
- memcpy(&temp_ddr, pa_ddr, sizeof(struct ccsr_ddr));
- temp_ddr.cs0_bnds = CONFIG_SYS_DDR1_CS0_BNDS;
- temp_ddr.sdram_cfg &= ~SDRAM_CFG_MEM_EN;
- memcpy(dsp_ddr, &temp_ddr, sizeof(struct ccsr_ddr));
- dsp_ddr->sdram_cfg |= SDRAM_CFG_MEM_EN;
-}
-
-int board_early_init_r(void)
-{
-#ifdef CONFIG_MTD_NOR_FLASH
- const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
- int flash_esel = find_tlb_idx((void *)flashbase, 1);
-
- /*
- * Remap Boot flash region to caching-inhibited
- * so that flash can be erased properly.
- */
-
- /* Flush d-cache and invalidate i-cache of any FLASH data */
- flush_dcache();
- invalidate_icache();
-
- if (flash_esel == -1) {
- /* very unlikely unless something is messed up */
- puts("Error: Could not find TLB for FLASH BASE\n");
- flash_esel = 2; /* give our best effort to continue */
- } else {
- /* invalidate existing TLB entry for flash */
- disable_tlb(flash_esel);
- }
-
- set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, flash_esel, BOOKE_PAGESZ_64M, 1);
-
- set_tlb(1, flashbase + 0x4000000,
- CONFIG_SYS_FLASH_BASE_PHYS + 0x4000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, flash_esel+1, BOOKE_PAGESZ_64M, 1);
-#endif
- board_config_serdes_mux();
- dsp_ddr_configure();
- return 0;
-}
-
-#ifdef CONFIG_PCI
-void pci_init_board(void)
-{
- fsl_pcie_init_board(0);
-}
-#endif /* ifdef CONFIG_PCI */
-
-int checkboard(void)
-{
- struct cpu_type *cpu;
- u8 sw;
-
- cpu = gd->arch.cpu;
- printf("Board: %sQDS\n", cpu->name);
-
- printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x,\n",
- QIXIS_READ(id), QIXIS_READ(arch), QIXIS_READ(scver));
-
- sw = QIXIS_READ(brdcfg[0]);
- sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
-
- printf("IFC chip select:");
- switch (sw) {
- case 0:
- printf("NOR\n");
- break;
- case 2:
- printf("Promjet\n");
- break;
- case 4:
- printf("NAND\n");
- break;
- default:
- printf("Invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
- break;
- }
-
- return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
-#ifdef CONFIG_TSEC_ENET
- struct fsl_pq_mdio_info mdio_info;
- struct tsec_info_struct tsec_info[4];
- int num = 0;
-
-#ifdef CONFIG_TSEC1
- SET_STD_TSEC_INFO(tsec_info[num], 1);
- num++;
-
-#endif
-
-#ifdef CONFIG_TSEC2
- SET_STD_TSEC_INFO(tsec_info[num], 2);
- num++;
-#endif
-
- mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
- mdio_info.name = DEFAULT_MII_NAME;
-
- fsl_pq_mdio_init(bis, &mdio_info);
- tsec_eth_init(bis, tsec_info, num);
-#endif
-
- #ifdef CONFIG_PCI
- pci_eth_init(bis);
- #endif
-
- return 0;
-}
-
-#define USBMUX_SEL_MASK 0xc0
-#define USBMUX_SEL_UART2 0xc0
-#define USBMUX_SEL_USB 0x40
-#define SPIMUX_SEL_UART3 0x80
-#define GPS_MUX_SEL_GPS 0x40
-
-#define TSEC_1588_CLKIN_MASK 0x03
-#define CON_XCVR_REF_CLK 0x00
-
-int misc_init_r(void)
-{
- u8 val;
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- u32 porbmsr = in_be32(&gur->porbmsr);
- u32 romloc = (porbmsr >> MPC85xx_PORBMSR_ROMLOC_SHIFT) & 0xf;
-
- /*Configure 1588 clock-in source from RF Card*/
- val = QIXIS_READ_I2C(brdcfg[5]);
- QIXIS_WRITE_I2C(brdcfg[5],
- (val & ~(TSEC_1588_CLKIN_MASK)) | CON_XCVR_REF_CLK);
-
- if (hwconfig("uart2") && hwconfig("usb1")) {
- printf("UART2 and USB cannot work together on the board\n");
- printf("Remove one from hwconfig and reset\n");
- } else {
- if (hwconfig("uart2")) {
- val = QIXIS_READ_I2C(brdcfg[5]);
- QIXIS_WRITE_I2C(brdcfg[5],
- (val & ~(USBMUX_SEL_MASK)) | USBMUX_SEL_UART2);
- clrbits_be32(&gur->pmuxcr3,
- MPC85xx_PMUXCR3_USB_SEL_MASK);
- setbits_be32(&gur->pmuxcr3, MPC85xx_PMUXCR3_UART2_SEL);
- } else {
- /* By default USB should be selected.
- * Programming FPGA to select USB. */
- val = QIXIS_READ_I2C(brdcfg[5]);
- QIXIS_WRITE_I2C(brdcfg[5],
- (val & ~(USBMUX_SEL_MASK)) | USBMUX_SEL_USB);
- }
-
- }
-
- if (hwconfig("sim")) {
- if (romloc == PORBMSR_ROMLOC_NAND_2K ||
- romloc == PORBMSR_ROMLOC_NOR ||
- romloc == PORBMSR_ROMLOC_SPI) {
-
- val = QIXIS_READ_I2C(brdcfg[3]);
- QIXIS_WRITE_I2C(brdcfg[3], val|0x10);
- clrbits_be32(&gur->pmuxcr,
- MPC85xx_PMUXCR0_SIM_SEL_MASK);
- setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR0_SIM_SEL);
- }
- }
-
- if (hwconfig("uart3")) {
- if (romloc == PORBMSR_ROMLOC_NAND_2K ||
- romloc == PORBMSR_ROMLOC_NOR ||
- romloc == PORBMSR_ROMLOC_SDHC) {
-
- /* UART3 and SPI1 (Flashes) are muxed together */
- val = QIXIS_READ_I2C(brdcfg[3]);
- QIXIS_WRITE_I2C(brdcfg[3], (val | SPIMUX_SEL_UART3));
- clrbits_be32(&gur->pmuxcr3,
- MPC85xx_PMUXCR3_UART3_SEL_MASK);
- setbits_be32(&gur->pmuxcr3, MPC85xx_PMUXCR3_UART3_SEL);
-
- /* MUX to select UART3 connection to J24 header
- * or to GPS */
- val = QIXIS_READ_I2C(brdcfg[6]);
- if (hwconfig("gps"))
- QIXIS_WRITE_I2C(brdcfg[6],
- (val | GPS_MUX_SEL_GPS));
- else
- QIXIS_WRITE_I2C(brdcfg[6],
- (val & ~(GPS_MUX_SEL_GPS)));
- }
- }
- return 0;
-}
-
-void fdt_del_node_compat(void *blob, const char *compatible)
-{
- int err;
- int off = fdt_node_offset_by_compatible(blob, -1, compatible);
- if (off < 0) {
- printf("WARNING: could not find compatible node %s: %s.\n",
- compatible, fdt_strerror(off));
- return;
- }
- err = fdt_del_node(blob, off);
- if (err < 0) {
- printf("WARNING: could not remove %s: %s.\n",
- compatible, fdt_strerror(err));
- }
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-#ifdef CONFIG_FDT_FIXUP_PARTITIONS
-static const struct node_info nodes[] = {
- { "cfi-flash", MTD_DEV_TYPE_NOR, },
- { "fsl,ifc-nand", MTD_DEV_TYPE_NAND, },
-};
-#endif
-int ft_board_setup(void *blob, bd_t *bd)
-{
- phys_addr_t base;
- phys_size_t size;
-
- ft_cpu_setup(blob, bd);
-
- base = env_get_bootm_low();
- size = env_get_bootm_size();
-
- #if defined(CONFIG_PCI)
- FT_FSL_PCI_SETUP;
- #endif
-
- fdt_fixup_memory(blob, (u64)base, (u64)size);
-#ifdef CONFIG_FDT_FIXUP_PARTITIONS
- fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
-#endif
-
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- u32 porbmsr = in_be32(&gur->porbmsr);
- u32 romloc = (porbmsr >> MPC85xx_PORBMSR_ROMLOC_SHIFT) & 0xf;
-
- if (!(hwconfig("uart2") && hwconfig("usb1"))) {
- /* If uart2 is there in hwconfig remove usb node from
- * device tree */
-
- if (hwconfig("uart2")) {
- /* remove dts usb node */
- fdt_del_node_compat(blob, "fsl-usb2-dr");
- } else {
- fsl_fdt_fixup_dr_usb(blob, bd);
- fdt_del_node_and_alias(blob, "serial2");
- }
- }
-
- if (hwconfig("uart3")) {
- if (romloc == PORBMSR_ROMLOC_NAND_2K ||
- romloc == PORBMSR_ROMLOC_NOR ||
- romloc == PORBMSR_ROMLOC_SDHC)
- /* Delete SPI node from the device tree */
- fdt_del_node_and_alias(blob, "spi1");
- } else
- fdt_del_node_and_alias(blob, "serial3");
-
- if (hwconfig("sim")) {
- if (romloc == PORBMSR_ROMLOC_NAND_2K ||
- romloc == PORBMSR_ROMLOC_NOR ||
- romloc == PORBMSR_ROMLOC_SPI) {
-
- /* remove dts sdhc node */
- fdt_del_node_compat(blob, "fsl,esdhc");
- } else if (romloc == PORBMSR_ROMLOC_SDHC) {
-
- /* remove dts sim node */
- fdt_del_node_compat(blob, "fsl,sim-v1.0");
- printf("SIM & SDHC can't work together on the board");
- printf("\nRemove sim from hwconfig and reset\n");
- }
- }
-
- return 0;
-}
-#endif
diff --git a/board/freescale/bsc9132qds/ddr.c b/board/freescale/bsc9132qds/ddr.c
deleted file mode 100644
index f4effe5a2d..0000000000
--- a/board/freescale/bsc9132qds/ddr.c
+++ /dev/null
@@ -1,191 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <vsprintf.h>
-#include <asm/mmu.h>
-#include <asm/immap_85xx.h>
-#include <asm/processor.h>
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-#include <asm/io.h>
-#include <asm/fsl_law.h>
-
-#ifndef CONFIG_SYS_DDR_RAW_TIMING
-
-fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
- .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
- .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
- .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
- .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
- .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
- .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
- .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
- .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
- .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
- .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
- .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
- .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
- .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
- .ddr_data_init = CONFIG_MEM_INIT_VALUE,
- .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
- .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
- .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
- .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
- .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
- .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
- .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_800,
- .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
- .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
- .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
-};
-
-fsl_ddr_cfg_regs_t ddr_cfg_regs_1333 = {
- .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
- .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
- .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
- .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1333,
- .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1333,
- .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1333,
- .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1333,
- .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
- .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
- .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1333,
- .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1333,
- .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
- .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1333,
- .ddr_data_init = CONFIG_MEM_INIT_VALUE,
- .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1333,
- .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
- .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
- .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
- .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
- .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
- .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_1333,
- .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
- .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
- .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
-};
-
-
-fixed_ddr_parm_t fixed_ddr_parm_0[] = {
- {750, 850, &ddr_cfg_regs_800},
- {1060, 1333, &ddr_cfg_regs_1333},
- {0, 0, NULL}
-};
-
-/*
- * Fixed sdram init -- doesn't use serial presence detect.
- */
-phys_size_t fixed_sdram(void)
-{
- int i;
- char buf[32];
- fsl_ddr_cfg_regs_t ddr_cfg_regs;
- phys_size_t ddr_size;
- ulong ddr_freq, ddr_freq_mhz;
-
- ddr_freq = get_ddr_freq(0);
- ddr_freq_mhz = ddr_freq / 1000000;
-
- printf("Configuring DDR for %s MT/s data rate\n",
- strmhz(buf, ddr_freq));
-
- for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
- if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) &&
- (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) {
- memcpy(&ddr_cfg_regs, fixed_ddr_parm_0[i].ddr_settings,
- sizeof(ddr_cfg_regs));
- break;
- }
- }
-
- if (fixed_ddr_parm_0[i].max_freq == 0)
- panic("Unsupported DDR data rate %s MT/s data rate\n",
- strmhz(buf, ddr_freq));
-
- ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
- fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
-
- if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, ddr_size,
- LAW_TRGT_IF_DDR_1) < 0) {
- printf("ERROR setting Local Access Windows for DDR\n");
- return 0;
- }
-
- return ddr_size;
-}
-
-#else /* CONFIG_SYS_DDR_RAW_TIMING */
-/* Micron MT41J512M8_187E */
-dimm_params_t ddr_raw_timing = {
- .n_ranks = 1,
- .rank_density = 1073741824u,
- .capacity = 1073741824u,
- .primary_sdram_width = 32,
- .ec_sdram_width = 0,
- .registered_dimm = 0,
- .mirrored_dimm = 0,
- .n_row_addr = 15,
- .n_col_addr = 10,
- .n_banks_per_sdram_device = 8,
- .edc_config = 0,
- .burst_lengths_bitmask = 0x0c,
-
- .tckmin_x_ps = 1870,
- .caslat_x = 0x1e << 4, /* 5,6,7,8 */
- .taa_ps = 13125,
- .twr_ps = 15000,
- .trcd_ps = 13125,
- .trrd_ps = 7500,
- .trp_ps = 13125,
- .tras_ps = 37500,
- .trc_ps = 50625,
- .trfc_ps = 160000,
- .twtr_ps = 7500,
- .trtp_ps = 7500,
- .refresh_rate_ps = 7800000,
- .tfaw_ps = 37500,
-};
-
-int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
- unsigned int controller_number,
- unsigned int dimm_number)
-{
- const char dimm_model[] = "Fixed DDR on board";
-
- if ((controller_number == 0) && (dimm_number == 0)) {
- memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
- memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
- memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
- }
-
- return 0;
-}
-
-void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- int i;
- popts->clk_adjust = 6;
- popts->cpo_override = 0x1f;
- popts->write_data_delay = 2;
- popts->half_strength_driver_enable = 1;
- /* Write leveling override */
- popts->wrlvl_en = 1;
- popts->wrlvl_override = 1;
- popts->wrlvl_sample = 0xf;
- popts->wrlvl_start = 0x8;
- popts->trwt_override = 1;
- popts->trwt = 0;
-
- for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
- popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
- popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
- }
-}
-
-#endif /* CONFIG_SYS_DDR_RAW_TIMING */
diff --git a/board/freescale/bsc9132qds/law.c b/board/freescale/bsc9132qds/law.c
deleted file mode 100644
index 6dca3d1751..0000000000
--- a/board/freescale/bsc9132qds/law.c
+++ /dev/null
@@ -1,28 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-struct law_entry law_table[] = {
- SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_IFC),
-#ifdef CONFIG_SYS_NAND_BASE_PHYS
- SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
-#endif
-#ifdef CONFIG_SYS_FPGA_BASE_PHYS
- SET_LAW(CONFIG_SYS_FPGA_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC),
-#endif
- SET_LAW(CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS, LAW_SIZE_1M,
- LAW_TRGT_IF_DSP_CCSR),
- SET_LAW(CONFIG_SYS_FSL_DSP_M2_RAM_ADDR, LAW_SIZE_32M,
- LAW_TRGT_IF_OCN_DSP),
- SET_LAW(CONFIG_SYS_FSL_DSP_M3_RAM_ADDR, LAW_SIZE_32K,
- LAW_TRGT_IF_CLASS_DSP),
- SET_LAW(CONFIG_SYS_FSL_DSP_DDR_ADDR, LAW_SIZE_1G,
- LAW_TRGT_IF_CLASS_DSP)
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/bsc9132qds/spl_minimal.c b/board/freescale/bsc9132qds/spl_minimal.c
deleted file mode 100644
index dd56ad6b2b..0000000000
--- a/board/freescale/bsc9132qds/spl_minimal.c
+++ /dev/null
@@ -1,117 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <init.h>
-#include <ns16550.h>
-#include <asm/io.h>
-#include <nand.h>
-#include <linux/compiler.h>
-#include <asm/fsl_law.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/global_data.h>
-#include <linux/delay.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static void sdram_init(void)
-{
- struct ccsr_ddr __iomem *ddr =
- (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
-#if CONFIG_DDR_CLK_FREQ == 100000000
- __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
- __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
- __raw_writel(CONFIG_SYS_DDR_CONTROL_800 | SDRAM_CFG_32_BE, &ddr->sdram_cfg);
- __raw_writel(CONFIG_SYS_DDR_CONTROL_2_800, &ddr->sdram_cfg_2);
- __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
-
- __raw_writel(CONFIG_SYS_DDR_TIMING_3_800, &ddr->timing_cfg_3);
- __raw_writel(CONFIG_SYS_DDR_TIMING_0_800, &ddr->timing_cfg_0);
- __raw_writel(CONFIG_SYS_DDR_TIMING_1_800, &ddr->timing_cfg_1);
- __raw_writel(CONFIG_SYS_DDR_TIMING_2_800, &ddr->timing_cfg_2);
- __raw_writel(CONFIG_SYS_DDR_MODE_1_800, &ddr->sdram_mode);
- __raw_writel(CONFIG_SYS_DDR_MODE_2_800, &ddr->sdram_mode_2);
- __raw_writel(CONFIG_SYS_DDR_INTERVAL_800, &ddr->sdram_interval);
- __raw_writel(CONFIG_SYS_DDR_CLK_CTRL_800, &ddr->sdram_clk_cntl);
- __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_800, &ddr->ddr_wrlvl_cntl);
-
- __raw_writel(CONFIG_SYS_DDR_TIMING_4_800, &ddr->timing_cfg_4);
- __raw_writel(CONFIG_SYS_DDR_TIMING_5_800, &ddr->timing_cfg_5);
- __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl);
-#elif CONFIG_DDR_CLK_FREQ == 133000000
- __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
- __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
- __raw_writel(CONFIG_SYS_DDR_CONTROL_1333 | SDRAM_CFG_32_BE, &ddr->sdram_cfg);
- __raw_writel(CONFIG_SYS_DDR_CONTROL_2_1333, &ddr->sdram_cfg_2);
- __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
-
- __raw_writel(CONFIG_SYS_DDR_TIMING_3_1333, &ddr->timing_cfg_3);
- __raw_writel(CONFIG_SYS_DDR_TIMING_0_1333, &ddr->timing_cfg_0);
- __raw_writel(CONFIG_SYS_DDR_TIMING_1_1333, &ddr->timing_cfg_1);
- __raw_writel(CONFIG_SYS_DDR_TIMING_2_1333, &ddr->timing_cfg_2);
- __raw_writel(CONFIG_SYS_DDR_MODE_1_1333, &ddr->sdram_mode);
- __raw_writel(CONFIG_SYS_DDR_MODE_2_1333, &ddr->sdram_mode_2);
- __raw_writel(CONFIG_SYS_DDR_INTERVAL_1333, &ddr->sdram_interval);
- __raw_writel(CONFIG_SYS_DDR_CLK_CTRL_1333, &ddr->sdram_clk_cntl);
- __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_1333, &ddr->ddr_wrlvl_cntl);
-
- __raw_writel(CONFIG_SYS_DDR_TIMING_4_1333, &ddr->timing_cfg_4);
- __raw_writel(CONFIG_SYS_DDR_TIMING_5_1333, &ddr->timing_cfg_5);
- __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl);
-#else
- puts("Not a valid DDR Freq Found! Please Reset\n");
-#endif
- asm volatile("sync;isync");
- udelay(500);
-
- /* Let the controller go */
- out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN);
-
- set_next_law(CONFIG_SYS_NAND_DDR_LAW, LAW_SIZE_1G, LAW_TRGT_IF_DDR_1);
-}
-
-void board_init_f(ulong bootflag)
-{
- u32 plat_ratio;
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
- /* initialize selected port with appropriate baud rate */
- plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
- plat_ratio >>= 1;
- gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
-
- NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
- gd->bus_clk / 16 / CONFIG_BAUDRATE);
-
- puts("\nNAND boot... ");
-
- /* Initialize the DDR3 */
- sdram_init();
-
- /* copy code to RAM and jump to it - this should not return */
- /* NOTE - code has to be copied out of NAND buffer before
- * other blocks can be read.
- */
- relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
- nand_boot();
-}
-
-void putc(char c)
-{
- if (c == '\n')
- NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
-
- NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
-}
-
-void puts(const char *str)
-{
- while (*str)
- putc(*str++);
-}
diff --git a/board/freescale/bsc9132qds/tlb.c b/board/freescale/bsc9132qds/tlb.c
deleted file mode 100644
index 9466814172..0000000000
--- a/board/freescale/bsc9132qds/tlb.c
+++ /dev/null
@@ -1,91 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
- /* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
- CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
- CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
- CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
-
- /* TLB 1 */
- /* *I*** - Covers boot page */
- SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_4K, 1),
-#ifdef CONFIG_SPL_NAND_BOOT
- SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 10, BOOKE_PAGESZ_4K, 1),
-#endif
-
- /* *I*G* - CCSRBAR (PA) */
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 1, BOOKE_PAGESZ_1M, 1),
-
- /* CCSRBAR (DSP) */
- SET_TLB_ENTRY(1, CONFIG_SYS_FSL_DSP_CCSRBAR,
- CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS, MAS3_SW|MAS3_SR,
- MAS2_I|MAS2_G, 0, 2, BOOKE_PAGESZ_1M, 1),
-
-#ifndef CONFIG_SPL_BUILD
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
- MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
- 0, 3, BOOKE_PAGESZ_64M, 1),
-
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x4000000,
- CONFIG_SYS_FLASH_BASE_PHYS + 0x4000000,
- MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
- 0, 4, BOOKE_PAGESZ_64M, 1),
-
-#ifdef CONFIG_PCI
- /* *I*G* - PCI */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 6, BOOKE_PAGESZ_256M, 1),
-
- /* *I*G* - PCI I/O */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 7, BOOKE_PAGESZ_64K, 1),
-#endif
-#endif
-
-#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
- SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
- 0, 8, BOOKE_PAGESZ_1G, 1),
-#endif
-
-#ifdef CONFIG_SYS_FPGA_BASE
- /* *I*G - Board FPGA */
- SET_TLB_ENTRY(1, CONFIG_SYS_FPGA_BASE, CONFIG_SYS_FPGA_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 9, BOOKE_PAGESZ_256K, 1),
-#endif
-
-#ifdef CONFIG_SYS_NAND_BASE_PHYS
- SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 5, BOOKE_PAGESZ_1M, 1),
-#endif
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig b/configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig
deleted file mode 100644
index 83300b204a..0000000000
--- a/configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig
+++ /dev/null
@@ -1,66 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11000000
-CONFIG_ENV_SIZE=0x20000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_BSC9132QDS=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="NAND_SECBOOT,SYS_CLK_100_DDR_100"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=88000000.nor,nand0=ff800000.flash,"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=88000000.nor:256k(dtb),7m(kernel),55m(fs),1m(uboot);ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)"
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y
-CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/BSC9132QDS_NAND_DDRCLK100_defconfig b/configs/BSC9132QDS_NAND_DDRCLK100_defconfig
deleted file mode 100644
index 5f85370a0a..0000000000
--- a/configs/BSC9132QDS_NAND_DDRCLK100_defconfig
+++ /dev/null
@@ -1,72 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x00201000
-CONFIG_ENV_SIZE=0x20000
-CONFIG_ENV_OFFSET=0xE0000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_TEXT_BASE=0xFFFFE000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_BSC9132QDS=y
-CONFIG_SYS_CUSTOM_LDSCRIPT=y
-CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_CLK_100_DDR_100"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_NAND_BOOT=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=88000000.nor,nand0=ff800000.flash,"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=88000000.nor:256k(dtb),7m(kernel),55m(fs),1m(uboot);ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)"
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
-CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig b/configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig
deleted file mode 100644
index 646158bb77..0000000000
--- a/configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig
+++ /dev/null
@@ -1,66 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11000000
-CONFIG_ENV_SIZE=0x20000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_BSC9132QDS=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="NAND_SECBOOT,SYS_CLK_100_DDR_133"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=88000000.nor,nand0=ff800000.flash,"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=88000000.nor:256k(dtb),7m(kernel),55m(fs),1m(uboot);ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)"
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y
-CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/BSC9132QDS_NAND_DDRCLK133_defconfig b/configs/BSC9132QDS_NAND_DDRCLK133_defconfig
deleted file mode 100644
index 82f37fbf1c..0000000000
--- a/configs/BSC9132QDS_NAND_DDRCLK133_defconfig
+++ /dev/null
@@ -1,72 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x00201000
-CONFIG_ENV_SIZE=0x20000
-CONFIG_ENV_OFFSET=0xE0000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_TEXT_BASE=0xFFFFE000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_BSC9132QDS=y
-CONFIG_SYS_CUSTOM_LDSCRIPT=y
-CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_CLK_100_DDR_133"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_NAND_BOOT=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=88000000.nor,nand0=ff800000.flash,"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=88000000.nor:256k(dtb),7m(kernel),55m(fs),1m(uboot);ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)"
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
-CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig b/configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig
deleted file mode 100644
index 25ed8dc6a7..0000000000
--- a/configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig
+++ /dev/null
@@ -1,65 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x8FF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_BSC9132QDS=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_CLK_100_DDR_100"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=88000000.nor,nand0=ff800000.flash,"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=88000000.nor:256k(dtb),7m(kernel),55m(fs),1m(uboot);ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)"
-CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y
-CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/BSC9132QDS_NOR_DDRCLK100_defconfig b/configs/BSC9132QDS_NOR_DDRCLK100_defconfig
deleted file mode 100644
index e0e441de44..0000000000
--- a/configs/BSC9132QDS_NOR_DDRCLK100_defconfig
+++ /dev/null
@@ -1,63 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x8FF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_BSC9132QDS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_CLK_100_DDR_100"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=88000000.nor,nand0=ff800000.flash,"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=88000000.nor:256k(dtb),7m(kernel),55m(fs),1m(uboot);ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)"
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0x8FF20000
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
-CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig b/configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig
deleted file mode 100644
index f7181d69d2..0000000000
--- a/configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig
+++ /dev/null
@@ -1,65 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x8FF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_BSC9132QDS=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_CLK_100_DDR_133"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=88000000.nor,nand0=ff800000.flash,"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=88000000.nor:256k(dtb),7m(kernel),55m(fs),1m(uboot);ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)"
-CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y
-CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/BSC9132QDS_NOR_DDRCLK133_defconfig b/configs/BSC9132QDS_NOR_DDRCLK133_defconfig
deleted file mode 100644
index 0ea77dc3a9..0000000000
--- a/configs/BSC9132QDS_NOR_DDRCLK133_defconfig
+++ /dev/null
@@ -1,63 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x8FF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_BSC9132QDS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_CLK_100_DDR_133"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=88000000.nor,nand0=ff800000.flash,"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=88000000.nor:256k(dtb),7m(kernel),55m(fs),1m(uboot);ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)"
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0x8FF20000
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
-CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig b/configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig
deleted file mode 100644
index 30bdc5d3d2..0000000000
--- a/configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig
+++ /dev/null
@@ -1,66 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11000000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_BSC9132QDS=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SDCARD,SYS_CLK_100_DDR_100"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=88000000.nor,nand0=ff800000.flash,"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=88000000.nor:256k(dtb),7m(kernel),55m(fs),1m(uboot);ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)"
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y
-CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig b/configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig
deleted file mode 100644
index 0e93c0d1c2..0000000000
--- a/configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig
+++ /dev/null
@@ -1,63 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11000000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x0
-CONFIG_MPC85xx=y
-CONFIG_TARGET_BSC9132QDS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SDCARD,SYS_CLK_100_DDR_100"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=88000000.nor,nand0=ff800000.flash,"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=88000000.nor:256k(dtb),7m(kernel),55m(fs),1m(uboot);ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)"
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
-CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig b/configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig
deleted file mode 100644
index ca119d0625..0000000000
--- a/configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig
+++ /dev/null
@@ -1,66 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11000000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_BSC9132QDS=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SDCARD,SYS_CLK_100_DDR_133"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=88000000.nor,nand0=ff800000.flash,"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=88000000.nor:256k(dtb),7m(kernel),55m(fs),1m(uboot);ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)"
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y
-CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig b/configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig
deleted file mode 100644
index 288d4cf883..0000000000
--- a/configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig
+++ /dev/null
@@ -1,63 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11000000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x0
-CONFIG_MPC85xx=y
-CONFIG_TARGET_BSC9132QDS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SDCARD,SYS_CLK_100_DDR_133"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=88000000.nor,nand0=ff800000.flash,"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=88000000.nor:256k(dtb),7m(kernel),55m(fs),1m(uboot);ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)"
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
-CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig b/configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig
deleted file mode 100644
index e30dd9be90..0000000000
--- a/configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig
+++ /dev/null
@@ -1,66 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11000000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_BSC9132QDS=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH,SYS_CLK_100_DDR_100"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=88000000.nor,nand0=ff800000.flash,"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=88000000.nor:256k(dtb),7m(kernel),55m(fs),1m(uboot);ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)"
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y
-CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig b/configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig
deleted file mode 100644
index 8f4d4b8fbb..0000000000
--- a/configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig
+++ /dev/null
@@ -1,64 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11000000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_BSC9132QDS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH,SYS_CLK_100_DDR_100"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=88000000.nor,nand0=ff800000.flash,"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=88000000.nor:256k(dtb),7m(kernel),55m(fs),1m(uboot);ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)"
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
-CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig b/configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig
deleted file mode 100644
index 80c51aa705..0000000000
--- a/configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig
+++ /dev/null
@@ -1,66 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11000000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_BSC9132QDS=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH,SYS_CLK_100_DDR_133"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=88000000.nor,nand0=ff800000.flash,"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=88000000.nor:256k(dtb),7m(kernel),55m(fs),1m(uboot);ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)"
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y
-CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig b/configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig
deleted file mode 100644
index fb16caad9a..0000000000
--- a/configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig
+++ /dev/null
@@ -1,64 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11000000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_BSC9132QDS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH,SYS_CLK_100_DDR_133"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=88000000.nor,nand0=ff800000.flash,"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=88000000.nor:256k(dtb),7m(kernel),55m(fs),1m(uboot);ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)"
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
-CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h
deleted file mode 100644
index ac37ae7cb8..0000000000
--- a/include/configs/BSC9132QDS.h
+++ /dev/null
@@ -1,548 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-/*
- * BSC9132 QDS board configuration file
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#ifdef CONFIG_SDCARD
-#define CONFIG_RAMBOOT_SDCARD
-#define CONFIG_SYS_RAMBOOT
-#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
-#endif
-#ifdef CONFIG_SPIFLASH
-#define CONFIG_RAMBOOT_SPIFLASH
-#define CONFIG_SYS_RAMBOOT
-#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
-#endif
-#ifdef CONFIG_NAND_SECBOOT
-#define CONFIG_RAMBOOT_NAND
-#define CONFIG_SYS_RAMBOOT
-#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
-#endif
-
-#ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SPL_INIT_MINIMAL
-#define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
-
-#define CONFIG_SPL_MAX_SIZE 8192
-#define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
-#define CONFIG_SPL_RELOC_STACK 0x00100000
-#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
-#define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
-#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0
-#endif
-
-#ifndef CONFIG_RESET_VECTOR_ADDRESS
-#define CONFIG_RESET_VECTOR_ADDRESS 0x8ffffffc
-#endif
-
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
-#else
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-#endif
-
-/* High Level Configuration Options */
-#define CONFIG_SYS_HAS_SERDES /* common SERDES init code */
-
-#if defined(CONFIG_PCI)
-#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
-#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
-
-/*
- * PCI Windows
- * Memory space is mapped 1-1, but I/O space must start from 0.
- */
-/* controller 1, Slot 1, tgtid 1, Base address a000 */
-#define CONFIG_SYS_PCIE1_NAME "PCIe Slot"
-#define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000
-#define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCIE1_IO_VIRT 0xC0010000
-#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xC0010000
-
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#endif
-
-#define CONFIG_ENV_OVERWRITE
-
-#if defined(CONFIG_SYS_CLK_100_DDR_100)
-#define CONFIG_SYS_CLK_FREQ 100000000
-#define CONFIG_DDR_CLK_FREQ 100000000
-#elif defined(CONFIG_SYS_CLK_100_DDR_133)
-#define CONFIG_SYS_CLK_FREQ 100000000
-#define CONFIG_DDR_CLK_FREQ 133000000
-#endif
-
-#define CONFIG_HWCONFIG
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_L2_CACHE /* toggle L2 cache */
-#define CONFIG_BTB /* enable branch predition */
-
-/* DDR Setup */
-#define CONFIG_SYS_SPD_BUS_NUM 0
-#define SPD_EEPROM_ADDRESS1 0x54 /* I2C access */
-#define SPD_EEPROM_ADDRESS2 0x56 /* I2C access */
-
-#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
-
-#define CONFIG_SYS_SDRAM_SIZE (1024)
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-
-/* DDR3 Controller Settings */
-#define CONFIG_CHIP_SELECTS_PER_CTRL 1
-#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
-#define CONFIG_SYS_DDR_CS0_CONFIG_1333 0x80004302
-#define CONFIG_SYS_DDR_CS0_CONFIG_800 0x80014302
-#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
-#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
-#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
-#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
-#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
-#define CONFIG_SYS_DDR1_CS0_BNDS 0x0040007F
-
-#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
-#define CONFIG_SYS_DDR_SR_CNTR 0x00000000
-#define CONFIG_SYS_DDR_RCW_1 0x00000000
-#define CONFIG_SYS_DDR_RCW_2 0x00000000
-#define CONFIG_SYS_DDR_CONTROL_800 0x470C0000
-#define CONFIG_SYS_DDR_CONTROL_2_800 0x04401050
-#define CONFIG_SYS_DDR_TIMING_4_800 0x00220001
-#define CONFIG_SYS_DDR_TIMING_5_800 0x03402400
-
-#define CONFIG_SYS_DDR_CONTROL_1333 0x470C0008
-#define CONFIG_SYS_DDR_CONTROL_2_1333 0x24401010
-#define CONFIG_SYS_DDR_TIMING_4_1333 0x00000001
-#define CONFIG_SYS_DDR_TIMING_5_1333 0x03401400
-
-#define CONFIG_SYS_DDR_TIMING_3_800 0x00020000
-#define CONFIG_SYS_DDR_TIMING_0_800 0x00330004
-#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6B4846
-#define CONFIG_SYS_DDR_TIMING_2_800 0x0FA8C8CF
-#define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000
-#define CONFIG_SYS_DDR_MODE_1_800 0x40461520
-#define CONFIG_SYS_DDR_MODE_2_800 0x8000c000
-#define CONFIG_SYS_DDR_INTERVAL_800 0x0C300000
-#define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8655A608
-
-#define CONFIG_SYS_DDR_TIMING_3_1333 0x01061000
-#define CONFIG_SYS_DDR_TIMING_0_1333 0x00440104
-#define CONFIG_SYS_DDR_TIMING_1_1333 0x98913A45
-#define CONFIG_SYS_DDR_TIMING_2_1333 0x0FB8B114
-#define CONFIG_SYS_DDR_CLK_CTRL_1333 0x02800000
-#define CONFIG_SYS_DDR_MODE_1_1333 0x00061A50
-#define CONFIG_SYS_DDR_MODE_2_1333 0x00100000
-#define CONFIG_SYS_DDR_INTERVAL_1333 0x144E0513
-#define CONFIG_SYS_DDR_WRLVL_CONTROL_1333 0x8655F607
-
-/*FIXME: the following params are constant w.r.t diff freq
-combinations. this should be removed later
-*/
-#if CONFIG_DDR_CLK_FREQ == 100000000
-#define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800
-#define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800
-#define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800
-#define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800
-#define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800
-#elif CONFIG_DDR_CLK_FREQ == 133000000
-#define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_1333
-#define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_1333
-#define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_1333
-#define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_1333
-#define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_1333
-#else
-#define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800
-#define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800
-#define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800
-#define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800
-#define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800
-#endif
-
-/* relocated CCSRBAR */
-#define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT
-
-#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
-
-/* DSP CCSRBAR */
-#define CONFIG_SYS_FSL_DSP_CCSRBAR CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
-#define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
-
-/*
- * IFC Definitions
- */
-/* NOR Flash on IFC */
-
-#define CONFIG_SYS_FLASH_BASE 0x88000000
-#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* Max number of sector: 32M */
-
-#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
-
-#define CONFIG_SYS_NOR_CSPR 0x88000101
-#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
-#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(5)
-/* NOR Flash Timing Params */
-
-#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) \
- | FTIM0_NOR_TEADC(0x03) \
- | FTIM0_NOR_TAVDS(0x00) \
- | FTIM0_NOR_TEAHC(0x0f))
-#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1d) \
- | FTIM1_NOR_TRAD_NOR(0x09) \
- | FTIM1_NOR_TSEQRAD_NOR(0x09))
-#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) \
- | FTIM2_NOR_TCH(0x4) \
- | FTIM2_NOR_TWPH(0x7) \
- | FTIM2_NOR_TWP(0x1e))
-#define CONFIG_SYS_NOR_FTIM3 0x0
-
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
-#define CONFIG_SYS_FLASH_QUIET_TEST
-#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
-
-#undef CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-
-/* CFI for NOR Flash */
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
-/* NAND Flash on IFC */
-#define CONFIG_SYS_NAND_BASE 0xff800000
-#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
-
-#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
- | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
- | CSPR_MSEL_NAND /* MSEL = NAND */ \
- | CSPR_V)
-#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
-
-#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
- | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
- | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
- | CSOR_NAND_RAL_2 /* RAL = 2Byes */ \
- | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
- | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
- | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
-
-/* NAND Flash Timing Params */
-#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x03) \
- | FTIM0_NAND_TWP(0x05) \
- | FTIM0_NAND_TWCHT(0x02) \
- | FTIM0_NAND_TWH(0x04))
-#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1c) \
- | FTIM1_NAND_TWBE(0x1e) \
- | FTIM1_NAND_TRR(0x07) \
- | FTIM1_NAND_TRP(0x05))
-#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \
- | FTIM2_NAND_TREH(0x04) \
- | FTIM2_NAND_TWHRE(0x11))
-#define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
-
-#define CONFIG_SYS_NAND_DDR_LAW 11
-
-/* NAND */
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
-
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_FSL_QIXIS
-#endif
-#ifdef CONFIG_FSL_QIXIS
-#define CONFIG_SYS_FPGA_BASE 0xffb00000
-#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
-#define QIXIS_BASE CONFIG_SYS_FPGA_BASE
-#define QIXIS_LBMAP_SWITCH 9
-#define QIXIS_LBMAP_MASK 0x07
-#define QIXIS_LBMAP_SHIFT 0
-#define QIXIS_LBMAP_DFLTBANK 0x00
-#define QIXIS_LBMAP_ALTBANK 0x04
-#define QIXIS_RST_CTL_RESET 0x83
-#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
-#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
-#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
-
-#define CONFIG_SYS_FPGA_BASE_PHYS CONFIG_SYS_FPGA_BASE
-
-#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_FPGA_BASE) \
- | CSPR_PORT_SIZE_8 \
- | CSPR_MSEL_GPCM \
- | CSPR_V)
-#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
-#define CONFIG_SYS_CSOR2 0x0
-/* CPLD Timing parameters for IFC CS3 */
-#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
- FTIM0_GPCM_TEADC(0x0e) | \
- FTIM0_GPCM_TEAHC(0x0e))
-#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
- FTIM1_GPCM_TRAD(0x1f))
-#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
- FTIM2_GPCM_TCH(0x8) | \
- FTIM2_GPCM_TWP(0x1f))
-#define CONFIG_SYS_CS2_FTIM3 0x0
-#endif
-
-/* Set up IFC registers for boot location NOR/NAND */
-#if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_NAND_SECBOOT)
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
-#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
-#else
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
-#endif
-
-#define CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
- - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
-
-/* Serial Port */
-#undef CONFIG_SERIAL_SOFTWARE_FIFO
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_NS16550_MIN_FUNCTIONS
-#endif
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
-#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR + 0x4700)
-#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR + 0x4800)
-
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 400800 /* I2C speed and slave address*/
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_SPEED 400800 /* I2C speed and slave address*/
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
-
-/* I2C EEPROM */
-#define CONFIG_ID_EEPROM
-#ifdef CONFIG_ID_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#endif
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_BUS_NUM 0
-
-/* enable read and write access to EEPROM */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
-
-/* I2C FPGA */
-#define CONFIG_I2C_FPGA
-#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
-
-#define CONFIG_RTC_DS3231
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-
-/*
- * SPI interface will not be available in case of NAND boot SPI CS0 will be
- * used for SLIC
- */
-/* eSPI - Enhanced SPI */
-
-#if defined(CONFIG_TSEC_ENET)
-
-#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
-#define CONFIG_TSEC1 1
-#define CONFIG_TSEC1_NAME "eTSEC1"
-#define CONFIG_TSEC2 1
-#define CONFIG_TSEC2_NAME "eTSEC2"
-
-#define TSEC1_PHY_ADDR 0
-#define TSEC2_PHY_ADDR 1
-
-#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-
-#define TSEC1_PHYIDX 0
-#define TSEC2_PHYIDX 0
-
-#define CONFIG_ETHPRIME "eTSEC1"
-
-/* TBI PHY configuration for SGMII mode */
-#define CONFIG_TSEC_TBICR_SETTINGS ( \
- TBICR_PHY_RESET \
- | TBICR_ANEG_ENABLE \
- | TBICR_FULL_DUPLEX \
- | TBICR_SPEED1_SET \
- )
-
-#endif /* CONFIG_TSEC_ENET */
-
-#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
-#endif
-
-#ifdef CONFIG_USB_EHCI_HCD
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_USB_EHCI_FSL
-#define CONFIG_HAS_FSL_DR_USB
-#endif
-
-/*
- * Environment
- */
-#if defined(CONFIG_RAMBOOT_SDCARD)
-#define CONFIG_FSL_FIXED_MMC_LOCATION
-#define CONFIG_SYS_MMC_ENV_DEV 0
-#elif defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_NAND_SECBOOT)
-#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
-#endif
-
-#define CONFIG_LOADS_ECHO /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 64 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
-#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
-/*
- * Dynamic MTD Partition support with mtdparts
- */
-/*
- * Environment Configuration
- */
-
-#if defined(CONFIG_TSEC_ENET)
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#endif
-
-#define CONFIG_HOSTNAME "BSC9132qds"
-#define CONFIG_ROOTPATH "/opt/nfsroot"
-#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_UBOOTPATH "u-boot.bin"
-
-#ifdef CONFIG_SDCARD
-#define CONFIG_DEF_HWCONFIG "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
-#else
-#define CONFIG_DEF_HWCONFIG "hwconfig=sim;usb1:dr_mode=host,phy_type=ulpi\0"
-#endif
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "uboot=" CONFIG_UBOOTPATH "\0" \
- "loadaddr=1000000\0" \
- "bootfile=uImage\0" \
- "consoledev=ttyS0\0" \
- "ramdiskaddr=2000000\0" \
- "ramdiskfile=rootfs.ext2.gz.uboot\0" \
- "fdtaddr=1e00000\0" \
- "fdtfile=bsc9132qds.dtb\0" \
- "bdev=sda1\0" \
- CONFIG_DEF_HWCONFIG\
- "othbootargs=mem=880M ramdisk_size=600000 " \
- "default_hugepagesz=256m hugepagesz=256m hugepages=1 " \
- "isolcpus=0\0" \
- "usbext2boot=setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs; " \
- "usb start;" \
- "ext2load usb 0:4 $loadaddr $bootfile;" \
- "ext2load usb 0:4 $fdtaddr $fdtfile;" \
- "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
- "debug_halt_off=mw ff7e0e30 0xf0000000;"
-
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_HDBOOT \
- "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "usb start;" \
- "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
- "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs; " \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
-
-#include <asm/fsl_secure_boot.h>
-
-#endif /* __CONFIG_H */
--
2.25.1
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 04/24] arm: Remove configs/C29XPCIE_NAND_defconfig board
2020-05-27 16:46 [PATCH 00/24] spi: dm-conversion (part2) Jagan Teki
` (2 preceding siblings ...)
2020-05-27 16:46 ` [PATCH 03/24] arm: Remove configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig board Jagan Teki
@ 2020-05-27 16:46 ` Jagan Teki
2020-05-28 5:28 ` Priyanka Jain
2020-05-27 16:46 ` [PATCH 05/24] arm: Remove configs/Cyrus_P5020_defconfig board Jagan Teki
` (18 subsequent siblings)
22 siblings, 1 reply; 59+ messages in thread
From: Jagan Teki @ 2020-05-27 16:46 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_SPI by the deadline.
Remove it.
Patch-cc: Po Liu <po.liu@nxp.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
arch/powerpc/cpu/mpc85xx/Kconfig | 1 -
board/freescale/c29xpcie/Kconfig | 14 -
board/freescale/c29xpcie/MAINTAINERS | 10 -
board/freescale/c29xpcie/Makefile | 25 --
board/freescale/c29xpcie/README | 100 -----
board/freescale/c29xpcie/c29xpcie.c | 159 -------
board/freescale/c29xpcie/cpld.c | 133 ------
board/freescale/c29xpcie/cpld.h | 39 --
board/freescale/c29xpcie/ddr.c | 106 -----
board/freescale/c29xpcie/law.c | 18 -
board/freescale/c29xpcie/spl.c | 81 ----
board/freescale/c29xpcie/spl_minimal.c | 63 ---
board/freescale/c29xpcie/tlb.c | 84 ----
configs/C29XPCIE_NAND_defconfig | 70 ----
configs/C29XPCIE_NOR_SECBOOT_defconfig | 55 ---
configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig | 57 ---
configs/C29XPCIE_SPIFLASH_defconfig | 55 ---
configs/C29XPCIE_defconfig | 53 ---
include/configs/C29XPCIE.h | 443 --------------------
19 files changed, 1566 deletions(-)
delete mode 100644 board/freescale/c29xpcie/Kconfig
delete mode 100644 board/freescale/c29xpcie/MAINTAINERS
delete mode 100644 board/freescale/c29xpcie/Makefile
delete mode 100644 board/freescale/c29xpcie/README
delete mode 100644 board/freescale/c29xpcie/c29xpcie.c
delete mode 100644 board/freescale/c29xpcie/cpld.c
delete mode 100644 board/freescale/c29xpcie/cpld.h
delete mode 100644 board/freescale/c29xpcie/ddr.c
delete mode 100644 board/freescale/c29xpcie/law.c
delete mode 100644 board/freescale/c29xpcie/spl.c
delete mode 100644 board/freescale/c29xpcie/spl_minimal.c
delete mode 100644 board/freescale/c29xpcie/tlb.c
delete mode 100644 configs/C29XPCIE_NAND_defconfig
delete mode 100644 configs/C29XPCIE_NOR_SECBOOT_defconfig
delete mode 100644 configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig
delete mode 100644 configs/C29XPCIE_SPIFLASH_defconfig
delete mode 100644 configs/C29XPCIE_defconfig
delete mode 100644 include/configs/C29XPCIE.h
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 5ca4a6e8ba..0ba6fe6daa 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -1589,7 +1589,6 @@ config SYS_FSL_LBC_CLK_DIV
Defines divider of platform clock(clock input to
eLBC controller).
-source "board/freescale/c29xpcie/Kconfig"
source "board/freescale/corenet_ds/Kconfig"
source "board/freescale/mpc8536ds/Kconfig"
source "board/freescale/mpc8541cds/Kconfig"
diff --git a/board/freescale/c29xpcie/Kconfig b/board/freescale/c29xpcie/Kconfig
deleted file mode 100644
index 51e25c39df..0000000000
--- a/board/freescale/c29xpcie/Kconfig
+++ /dev/null
@@ -1,14 +0,0 @@
-if TARGET_C29XPCIE
-
-config SYS_BOARD
- default "c29xpcie"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "C29XPCIE"
-
-source "board/freescale/common/Kconfig"
-
-endif
diff --git a/board/freescale/c29xpcie/MAINTAINERS b/board/freescale/c29xpcie/MAINTAINERS
deleted file mode 100644
index 44af12cdbe..0000000000
--- a/board/freescale/c29xpcie/MAINTAINERS
+++ /dev/null
@@ -1,10 +0,0 @@
-C29XPCIE BOARD
-M: Po Liu <po.liu@nxp.com>
-S: Maintained
-F: board/freescale/c29xpcie/
-F: include/configs/C29XPCIE.h
-F: configs/C29XPCIE_defconfig
-F: configs/C29XPCIE_NAND_defconfig
-F: configs/C29XPCIE_SPIFLASH_defconfig
-F: configs/C29XPCIE_NOR_SECBOOT_defconfig
-F: configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig
diff --git a/board/freescale/c29xpcie/Makefile b/board/freescale/c29xpcie/Makefile
deleted file mode 100644
index 2a9c1be802..0000000000
--- a/board/freescale/c29xpcie/Makefile
+++ /dev/null
@@ -1,25 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2013 Freescale Semiconductor, Inc.
-#
-
-MINIMAL=
-ifdef CONFIG_SPL_BUILD
-ifdef CONFIG_SPL_INIT_MINIMAL
-MINIMAL=y
-endif
-endif
-
-ifdef MINIMAL
-obj-y += spl_minimal.o
-else
-ifdef CONFIG_SPL_BUILD
-obj-y += spl.o
-endif
-obj-y += c29xpcie.o
-obj-y += cpld.o
-obj-y += ddr.o
-endif
-
-obj-y += law.o
-obj-y += tlb.o
diff --git a/board/freescale/c29xpcie/README b/board/freescale/c29xpcie/README
deleted file mode 100644
index 2e249cbb3a..0000000000
--- a/board/freescale/c29xpcie/README
+++ /dev/null
@@ -1,100 +0,0 @@
-Overview
-=========
-C29XPCIE board is a series of Freescale PCIe add-in cards to perform
-as public key crypto accelerator or secure key management module.
-It includes C293PCIE board, C293PCIE board and C291PCIE board.
-The Freescale C29x family is a high performance crypto co-processor.
-It combines a single e500v2 core with necessary SEC engines.
-(maximum core frequency 1000/1200 MHz).
-
-The C29xPCIE board features are as follows:
-Memory subsystem:
- - 512Mbyte unbuffered DDR3 SDRAM discrete devices (32-bit bus)
- - 64 Mbyte NOR flash single-chip memory
- - 4 Gbyte NAND flash memory
- - 1 Mbit AT24C1024 I2C EEPROM
- - 16 Mbyte SPI memory
-
-Interfaces:
- - 10/100/1000 BaseT Ethernet ports:
- - eTSEC1, RGMII: one 10/100/1000 port
- - eTSEC2, RGMII: one 10/100/1000 port
- - DUART interface:
- - DUART interface: supports two UARTs up to 115200 bps for
- console display
-
-Board connectors:
- - Mini-ITX power supply connector
- - JTAG/COP for debugging
-
-Physical Memory Map on C29xPCIE
-===============================
-Address Start Address End Memory type
-0x0_0000_0000 - 0x0_1fff_ffff 512MB DDR
-0xc_0000_0000 - 0xc_8fff_ffff 256MB PCIE memory
-0xf_ec00_0000 - 0xf_efff_ffff 64MB NOR flash
-0xf_ffb0_0000 - 0xf_ffb7_ffff 512KB SRAM
-0xf_ffc0_0000 - 0xf_ffc0_ffff 64KB PCIE IO
-0xf_ffdf_0000 - 0xf_ffdf_0fff 4KB CPLD
-0xf_ffe0_0000 - 0xf_ffef_ffff 1MB CCSR
-
-Serial Port Configuration on C29xPCIE
-=====================================
-Configure the serial port of the attached computer with the following values:
- -Data rate: 115200 bps
- -Number of data bits: 8
- -Parity: None
- -Number of Stop bits: 1
- -Flow Control: Hardware/None
-
-Settings of DIP-switch
-======================
- SW5[1:4]= 1111 and SW5[6]=0 for boot from 16bit NOR flash
- SW5[1:4]= 0110 and SW5[6]=0 for boot from SPI flash
-Note: 1 stands for 'off', 0 stands for 'on'
-
-Build and program U-Boot to NOR flash
-==================================
-1. Build u-boot.bin image example:
- export ARCH=powerpc
- export CROSS_COMPILE=/your_path/powerpc-linux-gnu-
- make C293PCIE
-
-2. Program u-boot.bin into NOR flash
- => tftp $loadaddr $uboot
- => protect off eff40000 +$filesize
- => erase eff40000 +$filesize
- => cp.b $loadaddr eff40000 $filesize
-
-3. Check SW5[1:4]= 1111 and SW5[6]=0, then power on.
-
-Alternate NOR bank
-==================
-There are four banks in C29XPCIE board, example to change bank booting:
-1. Program u-boot.bin into alternate NOR bank
- => tftp $loadaddr $uboot
- => protect off e9f40000 +$filesize
- => erase e9f40000 +$filesize
- => cp.b $loadaddr e9f40000 $filesize
-
-2. Switch to alternate NOR bank
- => cpld_cmd reset altbank [bank]
- - [bank] bank value select 1-4
- - bank 1 on the flash 0x0000000~0x0ffffff
- - bank 2 on the flash 0x1000000~0x1ffffff
- - bank 3 on the flash 0x2000000~0x2ffffff
- - bank 4 on the flash 0x3000000~0x3ffffff
- or set SW5[7]= ON/OFF and SW5[7]= ON/OFF, then power on again.
-
-Build and program U-Boot to SPI flash
-==================================
-1. Build u-boot-spi.bin image
- make C29xPCIE_SPIFLASH_config; make
- Need the boot_format tool to generate u-boot-spi.bin from the u-boot.bin.
-
-2. Program u-boot-spi.bin into SPI flash
- => tftp $loadaddr $uboot-spi
- => sf erase 0 100000
- => sf write $loadaddr 0 $filesize
-
-3. Check SW5[1:4]= 0110 and SW5[6]=0, then power on.
diff --git a/board/freescale/c29xpcie/c29xpcie.c b/board/freescale/c29xpcie/c29xpcie.c
deleted file mode 100644
index 74502c6d18..0000000000
--- a/board/freescale/c29xpcie/c29xpcie.c
+++ /dev/null
@@ -1,159 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <image.h>
-#include <init.h>
-#include <net.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/io.h>
-#include <env.h>
-#include <miiphy.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <fsl_mdio.h>
-#include <tsec.h>
-#include <mmc.h>
-#include <netdev.h>
-#include <pci.h>
-#include <fsl_ifc.h>
-#include <asm/fsl_pci.h>
-
-#include "cpld.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
- struct cpu_type *cpu = gd->arch.cpu;
- struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
-
- printf("Board: %sPCIe, ", cpu->name);
- printf("CPLD Ver: 0x%02x\n", in_8(&cpld_data->cpldver));
-
- return 0;
-}
-
-int board_early_init_f(void)
-{
- struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
-
- /* Clock configuration to access CPLD using IFC(GPCM) */
- setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
-
- return 0;
-}
-
-int board_early_init_r(void)
-{
- const unsigned long flashbase = CONFIG_SYS_FLASH_BASE;
- int flash_esel = find_tlb_idx((void *)flashbase, 1);
-
- /*
- * Remap Boot flash region to caching-inhibited
- * so that flash can be erased properly.
- */
-
- /* Flush d-cache and invalidate i-cache of any FLASH data */
- flush_dcache();
- invalidate_icache();
-
- if (flash_esel == -1) {
- /* very unlikely unless something is messed up */
- puts("Error: Could not find TLB for FLASH BASE\n");
- flash_esel = 1; /* give our best effort to continue */
- } else {
- /* invalidate existing TLB entry for flash */
- disable_tlb(flash_esel);
- }
-
- set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, flash_esel, BOOKE_PAGESZ_64M, 1);
-
- return 0;
-}
-
-#ifdef CONFIG_PCI
-void pci_init_board(void)
-{
- fsl_pcie_init_board(0);
-}
-#endif /* ifdef CONFIG_PCI */
-
-int board_eth_init(bd_t *bis)
-{
-#ifdef CONFIG_TSEC_ENET
- struct fsl_pq_mdio_info mdio_info;
- struct tsec_info_struct tsec_info[2];
- int num = 0;
-
-#ifdef CONFIG_TSEC1
- SET_STD_TSEC_INFO(tsec_info[num], 1);
- num++;
-#endif
-#ifdef CONFIG_TSEC2
- SET_STD_TSEC_INFO(tsec_info[num], 2);
- num++;
-#endif
- if (!num) {
- printf("No TSECs initialized\n");
- return 0;
- }
-
- /* Register 1G MDIO bus */
- mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
- mdio_info.name = DEFAULT_MII_NAME;
-
- fsl_pq_mdio_init(bis, &mdio_info);
-
- tsec_eth_init(bis, tsec_info, num);
-#endif
-
- return pci_eth_init(bis);
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-void fdt_del_sec(void *blob, int offset)
-{
- int nodeoff = 0;
-
- while ((nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,sec-v6.0",
- CONFIG_SYS_CCSRBAR_PHYS + CONFIG_SYS_FSL_SEC_OFFSET
- + offset * CONFIG_SYS_FSL_SEC_IDX_OFFSET)) >= 0) {
- fdt_del_node(blob, nodeoff);
- offset++;
- }
-}
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
- phys_addr_t base;
- phys_size_t size;
- struct cpu_type *cpu;
-
- cpu = gd->arch.cpu;
-
- ft_cpu_setup(blob, bd);
-
- base = env_get_bootm_low();
- size = env_get_bootm_size();
-
-#if defined(CONFIG_PCI)
- FT_FSL_PCI_SETUP;
-#endif
-
- fdt_fixup_memory(blob, (u64)base, (u64)size);
- if (cpu->soc_ver == SVR_C291)
- fdt_del_sec(blob, 1);
- else if (cpu->soc_ver == SVR_C292)
- fdt_del_sec(blob, 2);
-
- return 0;
-}
-#endif
diff --git a/board/freescale/c29xpcie/cpld.c b/board/freescale/c29xpcie/cpld.c
deleted file mode 100644
index 826af428ce..0000000000
--- a/board/freescale/c29xpcie/cpld.c
+++ /dev/null
@@ -1,133 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/**
- * Copyright 2013 Freescale Semiconductor
- * Author: Mingkai Hu <Mingkai.hu@freescale.com>
- * Po Liu <Po.Liu@freescale.com>
- *
- * This file provides support for the board-specific CPLD used on some Freescale
- * reference boards.
- *
- * The following macros need to be defined:
- *
- * CONFIG_SYS_CPLD_BASE - The virtual address of the base of the
- * CPLD register map
- *
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/io.h>
-#include <linux/delay.h>
-
-#include "cpld.h"
-/**
- * Set the boot bank to the alternate bank
- */
-void cpld_set_altbank(u8 banksel)
-{
- struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
- u8 reg11;
-
- reg11 = in_8(&cpld_data->flhcsr);
-
- switch (banksel) {
- case 1:
- out_8(&cpld_data->flhcsr, (reg11 & CPLD_BANKSEL_MASK)
- | CPLD_BANKSEL_EN | CPLD_SELECT_BANK1);
- break;
- case 2:
- out_8(&cpld_data->flhcsr, (reg11 & CPLD_BANKSEL_MASK)
- | CPLD_BANKSEL_EN | CPLD_SELECT_BANK2);
- break;
- case 3:
- out_8(&cpld_data->flhcsr, (reg11 & CPLD_BANKSEL_MASK)
- | CPLD_BANKSEL_EN | CPLD_SELECT_BANK3);
- break;
- case 4:
- out_8(&cpld_data->flhcsr, (reg11 & CPLD_BANKSEL_MASK)
- | CPLD_BANKSEL_EN | CPLD_SELECT_BANK4);
- break;
- default:
- printf("Invalid value! [1-4]\n");
- return;
- }
-
- udelay(100);
- do_reset(NULL, 0, 0, NULL);
-}
-
-/**
- * Set the boot bank to the default bank
- */
-void cpld_set_defbank(void)
-{
- cpld_set_altbank(4);
-}
-
-#ifdef DEBUG
-static void cpld_dump_regs(void)
-{
- struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
-
- printf("chipid1 = 0x%02x\n", in_8(&cpld_data->chipid1));
- printf("chipid2 = 0x%02x\n", in_8(&cpld_data->chipid2));
- printf("hwver = 0x%02x\n", in_8(&cpld_data->hwver));
- printf("cpldver = 0x%02x\n", in_8(&cpld_data->cpldver));
- printf("rstcon = 0x%02x\n", in_8(&cpld_data->rstcon));
- printf("flhcsr = 0x%02x\n", in_8(&cpld_data->flhcsr));
- printf("wdcsr = 0x%02x\n", in_8(&cpld_data->wdcsr));
- printf("wdkick = 0x%02x\n", in_8(&cpld_data->wdkick));
- printf("fancsr = 0x%02x\n", in_8(&cpld_data->fancsr));
- printf("ledcsr = 0x%02x\n", in_8(&cpld_data->ledcsr));
- printf("misc = 0x%02x\n", in_8(&cpld_data->misccsr));
- printf("bootor = 0x%02x\n", in_8(&cpld_data->bootor));
- printf("bootcfg1 = 0x%02x\n", in_8(&cpld_data->bootcfg1));
- printf("bootcfg2 = 0x%02x\n", in_8(&cpld_data->bootcfg2));
- printf("bootcfg3 = 0x%02x\n", in_8(&cpld_data->bootcfg3));
- printf("bootcfg4 = 0x%02x\n", in_8(&cpld_data->bootcfg4));
- putc('\n');
-}
-#endif
-
-#ifndef CONFIG_SPL_BUILD
-int cpld_cmd(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
-{
- int rc = 0;
- unsigned char value;
-
- if (argc <= 1)
- return cmd_usage(cmdtp);
-
- if (strcmp(argv[1], "reset") == 0) {
- if (!strcmp(argv[2], "altbank") && argv[3]) {
- value = (u8)simple_strtoul(argv[3], NULL, 16);
- cpld_set_altbank(value);
- } else if (!argv[2])
- cpld_set_defbank();
- else
- cmd_usage(cmdtp);
-#ifdef DEBUG
- } else if (strcmp(argv[1], "dump") == 0) {
- cpld_dump_regs();
-#endif
- } else
- rc = cmd_usage(cmdtp);
-
- return rc;
-}
-
-U_BOOT_CMD(
- cpld_cmd, CONFIG_SYS_MAXARGS, 1, cpld_cmd,
- "Reset the board using the CPLD sequencer",
- "reset - hard reset to default bank 4\n"
- "cpld_cmd reset altbank [bank]- reset to alternate bank\n"
- " - [bank] bank value select 1-4\n"
- " - bank 1 on the flash 0x0000000~0x0ffffff\n"
- " - bank 2 on the flash 0x1000000~0x1ffffff\n"
- " - bank 3 on the flash 0x2000000~0x2ffffff\n"
- " - bank 4 on the flash 0x3000000~0x3ffffff\n"
-#ifdef DEBUG
- "cpld_cmd dump - display the CPLD registers\n"
-#endif
- );
-#endif
diff --git a/board/freescale/c29xpcie/cpld.h b/board/freescale/c29xpcie/cpld.h
deleted file mode 100644
index 02e9160854..0000000000
--- a/board/freescale/c29xpcie/cpld.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/**
- * Copyright 2013 Freescale Semiconductor
- * Author: Mingkai Hu <Mingkai.Hu@freescale.com>
- * Po Liu <Po.Liu@freescale.com>
- *
- * This file provides support for the ngPIXIS, a board-specific FPGA used on
- * some Freescale reference boards.
- */
-
-/*
- * CPLD register set. Feel free to add board-specific #ifdefs where necessary.
- */
-struct cpld_data {
- u8 chipid1; /* 0x0 - CPLD Chip ID1 Register */
- u8 chipid2; /* 0x1 - CPLD Chip ID2 Register */
- u8 hwver; /* 0x2 - Hardware Version Register */
- u8 cpldver; /* 0x3 - Software Version Register */
- u8 res[12];
- u8 rstcon; /* 0x10 - Reset control register */
- u8 flhcsr; /* 0x11 - Flash control and status Register */
- u8 wdcsr; /* 0x12 - Watchdog control and status Register */
- u8 wdkick; /* 0x13 - Watchdog kick Register */
- u8 fancsr; /* 0x14 - Fan control and status Register */
- u8 ledcsr; /* 0x15 - LED control and status Register */
- u8 misccsr; /* 0x16 - Misc control and status Register */
- u8 bootor; /* 0x17 - Boot configure override Register */
- u8 bootcfg1; /* 0x18 - Boot configure 1 Register */
- u8 bootcfg2; /* 0x19 - Boot configure 2 Register */
- u8 bootcfg3; /* 0x1a - Boot configure 3 Register */
- u8 bootcfg4; /* 0x1b - Boot configure 4 Register */
-};
-
-#define CPLD_BANKSEL_EN 0x02
-#define CPLD_BANKSEL_MASK 0x3f
-#define CPLD_SELECT_BANK1 0xc0
-#define CPLD_SELECT_BANK2 0x80
-#define CPLD_SELECT_BANK3 0x40
-#define CPLD_SELECT_BANK4 0x00
diff --git a/board/freescale/c29xpcie/ddr.c b/board/freescale/c29xpcie/ddr.c
deleted file mode 100644
index 5795a27f65..0000000000
--- a/board/freescale/c29xpcie/ddr.c
+++ /dev/null
@@ -1,106 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <asm/fsl_law.h>
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-
-#include "cpld.h"
-
-#define C29XPCIE_HARDWARE_REVA 0x40
-/*
- * Micron MT41J128M16HA-15E
- * */
-dimm_params_t ddr_raw_timing = {
- .n_ranks = 1,
- .rank_density = 536870912u,
- .capacity = 536870912u,
- .primary_sdram_width = 32,
- .ec_sdram_width = 8,
- .registered_dimm = 0,
- .mirrored_dimm = 0,
- .n_row_addr = 14,
- .n_col_addr = 10,
- .n_banks_per_sdram_device = 8,
- .edc_config = 2,
- .burst_lengths_bitmask = 0x0c,
-
- .tckmin_x_ps = 1650,
- .caslat_x = 0x7e << 4, /* 5,6,7,8,9,10 */
- .taa_ps = 14050,
- .twr_ps = 15000,
- .trcd_ps = 13500,
- .trrd_ps = 75000,
- .trp_ps = 13500,
- .tras_ps = 40000,
- .trc_ps = 49500,
- .trfc_ps = 160000,
- .twtr_ps = 75000,
- .trtp_ps = 75000,
- .refresh_rate_ps = 7800000,
- .tfaw_ps = 30000,
-};
-
-int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
- unsigned int controller_number,
- unsigned int dimm_number)
-{
- const char dimm_model[] = "Fixed DDR on board";
-
- if ((controller_number == 0) && (dimm_number == 0)) {
- memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
- memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
- memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
- }
-
- return 0;
-}
-
-void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
- int i;
-
- popts->clk_adjust = 4;
- popts->cpo_override = 0x1f;
- popts->write_data_delay = 4;
- popts->half_strength_driver_enable = 1;
- popts->bstopre = 0x3cf;
- popts->quad_rank_present = 1;
- popts->rtt_override = 1;
- popts->rtt_override_value = 1;
- popts->dynamic_power = 1;
- /* Write leveling override */
- popts->wrlvl_en = 1;
- popts->wrlvl_override = 1;
- popts->wrlvl_sample = 0xf;
- popts->wrlvl_start = 0x4;
- popts->trwt_override = 1;
- popts->trwt = 0;
-
- if (in_8(&cpld_data->hwver) == C29XPCIE_HARDWARE_REVA)
- popts->ecc_mode = 0;
-
- for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
- popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
- popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
- }
-}
-
-void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
-{
- int ret = i2c_read(i2c_address, 0, 2, (uint8_t *)spd,
- sizeof(generic_spd_eeprom_t));
-
- if (ret) {
- printf("DDR: failed to read SPD from address %u\n",
- i2c_address);
- memset(spd, 0, sizeof(generic_spd_eeprom_t));
- }
-}
diff --git a/board/freescale/c29xpcie/law.c b/board/freescale/c29xpcie/law.c
deleted file mode 100644
index 6d441d87a7..0000000000
--- a/board/freescale/c29xpcie/law.c
+++ /dev/null
@@ -1,18 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-struct law_entry law_table[] = {
- SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_IFC),
- SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
- SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
- SET_LAW(CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS, LAW_SIZE_512K,
- LAW_TRGT_IF_PLATFORM_SRAM),
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/c29xpcie/spl.c b/board/freescale/c29xpcie/spl.c
deleted file mode 100644
index 421c2d4b1f..0000000000
--- a/board/freescale/c29xpcie/spl.c
+++ /dev/null
@@ -1,81 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/* Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <clock_legacy.h>
-#include <console.h>
-#include <env_internal.h>
-#include <init.h>
-#include <ns16550.h>
-#include <malloc.h>
-#include <mmc.h>
-#include <nand.h>
-#include <i2c.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-phys_size_t get_effective_memsize(void)
-{
- return CONFIG_SYS_L2_SIZE;
-}
-
-void board_init_f(ulong bootflag)
-{
- u32 plat_ratio;
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
- console_init_f();
-
- /* initialize selected port with appropriate baud rate */
- plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
- plat_ratio >>= 1;
- gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
-
- NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
- gd->bus_clk / 16 / CONFIG_BAUDRATE);
-
- /* copy code to RAM and jump to it - this should not return */
- /* NOTE - code has to be copied out of NAND buffer before
- * other blocks can be read.
- */
- relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
- /* Pointer is writable since we allocated a register for it */
- gd = (gd_t *)CONFIG_SPL_GD_ADDR;
- bd_t *bd;
-
- memset(gd, 0, sizeof(gd_t));
- bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
- memset(bd, 0, sizeof(bd_t));
- gd->bd = bd;
- bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
- bd->bi_memsize = CONFIG_SYS_L2_SIZE;
-
- arch_cpu_init();
- get_clocks();
- mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
- CONFIG_SPL_RELOC_MALLOC_SIZE);
- gd->flags |= GD_FLG_FULL_MALLOC_INIT;
-
- /* relocate environment function pointers etc. */
- nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
- (uchar *)SPL_ENV_ADDR);
- gd->env_addr = (ulong)(SPL_ENV_ADDR);
- gd->env_valid = ENV_VALID;
-
- i2c_init_all();
-
- dram_init();
-
-#ifdef CONFIG_SPL_NAND_BOOT
- puts("TPL\n");
-#else
- puts("SPL\n");
-#endif
-
- nand_boot();
-}
diff --git a/board/freescale/c29xpcie/spl_minimal.c b/board/freescale/c29xpcie/spl_minimal.c
deleted file mode 100644
index 8193afdf6a..0000000000
--- a/board/freescale/c29xpcie/spl_minimal.c
+++ /dev/null
@@ -1,63 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/* Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <init.h>
-#include <mpc85xx.h>
-#include <asm/io.h>
-#include <ns16550.h>
-#include <nand.h>
-#include <asm/mmu.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_law.h>
-#include <asm/global_data.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void board_init_f(ulong bootflag)
-{
- u32 plat_ratio;
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
-#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
- set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
- set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
-#endif
-
- /* initialize selected port with appropriate baud rate */
- plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
- plat_ratio >>= 1;
- gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
-
- NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
- gd->bus_clk / 16 / CONFIG_BAUDRATE);
-
- puts("\nNAND boot...\n");
-
- /* copy code to RAM and jump to it - this should not return */
- /* NOTE - code has to be copied out of NAND buffer before
- * other blocks can be read.
- */
- relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
- puts("SPL\n");
- nand_boot();
-}
-
-void putc(char c)
-{
- if (c == '\n')
- NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
-
- NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
-}
-
-void puts(const char *str)
-{
- while (*str)
- putc(*str++);
-}
diff --git a/board/freescale/c29xpcie/tlb.c b/board/freescale/c29xpcie/tlb.c
deleted file mode 100644
index ef844a0b3d..0000000000
--- a/board/freescale/c29xpcie/tlb.c
+++ /dev/null
@@ -1,84 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
- /* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
- CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
- CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
- CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
-
- /* TLB 1 */
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_1M, 1),
-
-#ifndef CONFIG_SPL_BUILD
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
- MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
- 0, 1, BOOKE_PAGESZ_64M, 1),
-
-#ifdef CONFIG_PCI
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 2, BOOKE_PAGESZ_256M, 1),
-
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 3, BOOKE_PAGESZ_256K, 1),
-#endif
-#endif
-
- SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 4, BOOKE_PAGESZ_64K, 1),
-
- SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 5, BOOKE_PAGESZ_64K, 1),
-
- SET_TLB_ENTRY(1, CONFIG_SYS_PLATFORM_SRAM_BASE,
- CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 6, BOOKE_PAGESZ_256K, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_PLATFORM_SRAM_BASE + 0x40000,
- CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS + 0x40000,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 7, BOOKE_PAGESZ_256K, 1),
-
-#if defined(CONFIG_SYS_RAMBOOT) || \
- (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
- SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE,
- CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
- 0, 8, BOOKE_PAGESZ_256M, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
- CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
- 0, 9, BOOKE_PAGESZ_256M, 1),
-#endif
-
-#ifdef CONFIG_SYS_INIT_L2_ADDR
- SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
- 0, 12, BOOKE_PAGESZ_256K, 1)
-#endif
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/configs/C29XPCIE_NAND_defconfig b/configs/C29XPCIE_NAND_defconfig
deleted file mode 100644
index cdcf50eee8..0000000000
--- a/configs/C29XPCIE_NAND_defconfig
+++ /dev/null
@@ -1,70 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11001000
-CONFIG_ENV_SIZE=0x100000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_TPL_LIBCOMMON_SUPPORT=y
-CONFIG_TPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_TEXT_BASE=0xFF800000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_C29XPCIE=y
-CONFIG_SYS_CUSTOM_LDSCRIPT=y
-CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=-1
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_TPL=y
-CONFIG_TPL_ENV_SUPPORT=y
-CONFIG_TPL_I2C_SUPPORT=y
-CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_TPL_NAND_SUPPORT=y
-CONFIG_TPL_SERIAL_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_EEPROM=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_DOS_PARTITION=y
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_CAAM=y
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/C29XPCIE_NOR_SECBOOT_defconfig b/configs/C29XPCIE_NOR_SECBOOT_defconfig
deleted file mode 100644
index e43c72860a..0000000000
--- a/configs/C29XPCIE_NOR_SECBOOT_defconfig
+++ /dev/null
@@ -1,55 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_C29XPCIE=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=-1
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_EEPROM=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_DOS_PARTITION=y
-CONFIG_DM=y
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig b/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig
deleted file mode 100644
index b7eb77e2a0..0000000000
--- a/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig
+++ /dev/null
@@ -1,57 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11000000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_C29XPCIE=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
-CONFIG_BOOTDELAY=-1
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_EEPROM=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_DOS_PARTITION=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/C29XPCIE_SPIFLASH_defconfig b/configs/C29XPCIE_SPIFLASH_defconfig
deleted file mode 100644
index 9bfdcd0461..0000000000
--- a/configs/C29XPCIE_SPIFLASH_defconfig
+++ /dev/null
@@ -1,55 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11000000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_C29XPCIE=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
-CONFIG_BOOTDELAY=-1
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_EEPROM=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_DOS_PARTITION=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_CAAM=y
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/C29XPCIE_defconfig b/configs/C29XPCIE_defconfig
deleted file mode 100644
index 3e7f19692a..0000000000
--- a/configs/C29XPCIE_defconfig
+++ /dev/null
@@ -1,53 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_C29XPCIE=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=-1
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_EEPROM=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_DOS_PARTITION=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_FSL_CAAM=y
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h
deleted file mode 100644
index 9a8cba6b7c..0000000000
--- a/include/configs/C29XPCIE.h
+++ /dev/null
@@ -1,443 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-/*
- * C29XPCIE board configuration file
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <linux/stringify.h>
-
-#ifdef CONFIG_SPIFLASH
-#define CONFIG_RAMBOOT_SPIFLASH
-#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
-#endif
-
-#ifdef CONFIG_MTD_RAW_NAND
-#ifdef CONFIG_TPL_BUILD
-#define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_NAND_INIT
-#define CONFIG_TPL_DRIVERS_MISC_SUPPORT
-#define CONFIG_SPL_COMMON_INIT_DDR
-#define CONFIG_SPL_MAX_SIZE (128 << 10)
-#define CONFIG_TPL_TEXT_BASE 0xf8f81000
-#define CONFIG_SYS_MPC85XX_NO_RESETVEC
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
-#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
-#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
-#elif defined(CONFIG_SPL_BUILD)
-#define CONFIG_SPL_INIT_MINIMAL
-#define CONFIG_SPL_NAND_MINIMAL
-#define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_MAX_SIZE 8192
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
-#define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
-#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
-#endif
-#define CONFIG_SPL_PAD_TO 0x20000
-#define CONFIG_TPL_PAD_TO 0x20000
-#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
-#endif
-
-#ifndef CONFIG_RESET_VECTOR_ADDRESS
-#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
-#endif
-
-#ifdef CONFIG_TPL_BUILD
-#define CONFIG_SYS_MONITOR_BASE CONFIG_TPL_TEXT_BASE
-#elif defined(CONFIG_SPL_BUILD)
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
-#else
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-#endif
-
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
-#endif
-
-/* High Level Configuration Options */
-#define CONFIG_SYS_HAS_SERDES /* common SERDES init code */
-
-#ifdef CONFIG_PCI
-#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
-#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
-
-/*
- * PCI Windows
- * Memory space is mapped 1-1, but I/O space must start from 0.
- */
-/* controller 1, Slot 1, tgtid 1, Base address a000 */
-#define CONFIG_SYS_PCIE1_NAME "Slot 1"
-#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
-#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
-#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
-
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#endif
-
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_DDR_CLK_FREQ 100000000
-#define CONFIG_SYS_CLK_FREQ 66666666
-
-#define CONFIG_HWCONFIG
-
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_L2_CACHE /* toggle L2 cache */
-#define CONFIG_BTB /* toggle branch predition */
-
-
-#define CONFIG_ENABLE_36BIT_PHYS
-
-#define CONFIG_ADDR_MAP 1
-#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
-
-/* DDR Setup */
-#define CONFIG_DDR_SPD
-#define CONFIG_SYS_SPD_BUS_NUM 0
-#define SPD_EEPROM_ADDRESS 0x50
-#define CONFIG_SYS_DDR_RAW_TIMING
-
-/* DDR ECC Setup*/
-#define CONFIG_DDR_ECC
-#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
-
-#define CONFIG_SYS_SDRAM_SIZE 512
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_CHIP_SELECTS_PER_CTRL 1
-
-#define CONFIG_SYS_CCSRBAR 0xffe00000
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
-
-/* Platform SRAM setting */
-#define CONFIG_SYS_PLATFORM_SRAM_BASE 0xffb00000
-#define CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS \
- (0xf00000000ull | CONFIG_SYS_PLATFORM_SRAM_BASE)
-#define CONFIG_SYS_PLATFORM_SRAM_SIZE (512 << 10)
-
-/*
- * IFC Definitions
- */
-/* NOR Flash on IFC */
-#define CONFIG_SYS_FLASH_BASE 0xec000000
-#define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
-
-#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
-
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-
-#define CONFIG_SYS_FLASH_QUIET_TEST
-#define CONFIG_FLASH_SHOW_PROGRESS 45
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* in ms */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* in ms */
-
-/* 16Bit NOR Flash - S29GL512S10TFI01 */
-#define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
- CSPR_PORT_SIZE_16 | \
- CSPR_MSEL_NOR | \
- CSPR_V)
-#define CONFIG_SYS_NOR_AMASK IFC_AMASK(64*1024*1024)
-#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4)
-
-#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
- FTIM0_NOR_TEADC(0x5) | \
- FTIM0_NOR_TEAHC(0x5))
-#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
- FTIM1_NOR_TRAD_NOR(0x1A) |\
- FTIM1_NOR_TSEQRAD_NOR(0x13))
-#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
- FTIM2_NOR_TCH(0x4) | \
- FTIM2_NOR_TWPH(0x0E) | \
- FTIM2_NOR_TWP(0x1c))
-#define CONFIG_SYS_NOR_FTIM3 0x0
-
-/* CFI for NOR Flash */
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
-/* NAND Flash on IFC */
-#define CONFIG_NAND_FSL_IFC
-#define CONFIG_SYS_NAND_BASE 0xff800000
-#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
-
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
-
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BLOCK_SIZE (1024 * 1024)
-
-/* 8Bit NAND Flash - K9F1G08U0B */
-#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
- | CSPR_PORT_SIZE_8 \
- | CSPR_MSEL_NAND \
- | CSPR_V)
-#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
-#define CONFIG_SYS_NAND_OOBSIZE 0x00000280 /* 640b */
-#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
- | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
- | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
- | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
- | CSOR_NAND_PGS_8K /* Page Size = 8K */ \
- | CSOR_NAND_SPRZ_CSOR_EXT /*oob in csor_ext*/\
- | CSOR_NAND_PB(128)) /*128 Pages Per Block*/
-#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x01) | \
- FTIM0_NAND_TWP(0x0c) | \
- FTIM0_NAND_TWCHT(0x08) | \
- FTIM0_NAND_TWH(0x06))
-#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x28) | \
- FTIM1_NAND_TWBE(0x1d) | \
- FTIM1_NAND_TRR(0x08) | \
- FTIM1_NAND_TRP(0x0c))
-#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0c) | \
- FTIM2_NAND_TREH(0x0a) | \
- FTIM2_NAND_TWHRE(0x18))
-#define CONFIG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x04))
-
-#define CONFIG_SYS_NAND_DDR_LAW 11
-
-/* Set up IFC registers for boot location NOR/NAND */
-#ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CSOR0_EXT CONFIG_SYS_NAND_OOBSIZE
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
-#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
-#else
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CSOR1_EXT CONFIG_SYS_NAND_OOBSIZE
-#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
-#endif
-
-/* CPLD on IFC, selected by CS2 */
-#define CONFIG_SYS_CPLD_BASE 0xffdf0000
-#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull \
- | CONFIG_SYS_CPLD_BASE)
-
-#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
- | CSPR_PORT_SIZE_8 \
- | CSPR_MSEL_GPCM \
- | CSPR_V)
-#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
-#define CONFIG_SYS_CSOR2 0x0
-/* CPLD Timing parameters for IFC CS2 */
-#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
- FTIM0_GPCM_TEADC(0x0e) | \
- FTIM0_GPCM_TEAHC(0x0e))
-#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
- FTIM1_GPCM_TRAD(0x1f))
-#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
- FTIM2_GPCM_TCH(0x8) | \
- FTIM2_GPCM_TWP(0x1f))
-#define CONFIG_SYS_CS2_FTIM3 0x0
-
-#if defined(CONFIG_RAMBOOT_SPIFLASH)
-#define CONFIG_SYS_RAMBOOT
-#endif
-
-#define CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
- - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024)
-
-/*
- * Config the L2 Cache as L2 SRAM
- */
-#if defined(CONFIG_SPL_BUILD)
-#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
-#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
-#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
-#define CONFIG_SYS_L2_SIZE (256 << 10)
-#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
-#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
-#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
-#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024)
-#define CONFIG_SPL_RELOC_MALLOC_SIZE (96 << 10)
-#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
-#elif defined(CONFIG_MTD_RAW_NAND)
-#ifdef CONFIG_TPL_BUILD
-#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
-#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
-#define CONFIG_SYS_L2_SIZE (256 << 10)
-#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
-#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
-#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
-#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
-#define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
-#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
-#else
-#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
-#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
-#define CONFIG_SYS_L2_SIZE (256 << 10)
-#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
-#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000)
-#define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
-#endif
-#endif
-#endif
-
-/* Serial Port */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
-#define CONFIG_NS16550_MIN_FUNCTIONS
-#endif
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
-
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C2_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
-
-/* I2C EEPROM */
-/* enable read and write access to EEPROM */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
-
-/* eSPI - Enhanced SPI */
-
-#ifdef CONFIG_TSEC_ENET
-#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
-#define CONFIG_TSEC1 1
-#define CONFIG_TSEC1_NAME "eTSEC1"
-#define CONFIG_TSEC2 1
-#define CONFIG_TSEC2_NAME "eTSEC2"
-
-/* Default mode is RGMII mode */
-#define TSEC1_PHY_ADDR 0
-#define TSEC2_PHY_ADDR 2
-
-#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-
-#define CONFIG_ETHPRIME "eTSEC1"
-#endif /* CONFIG_TSEC_ENET */
-
-/*
- * Environment
- */
-#if defined(CONFIG_SYS_RAMBOOT)
-#elif defined(CONFIG_MTD_RAW_NAND)
-#ifdef CONFIG_TPL_BUILD
-#define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
-#else
-#define CONFIG_ENV_RANGE CONFIG_ENV_SIZE
-#endif
-#endif
-
-#define CONFIG_LOADS_ECHO
-#define CONFIG_SYS_LOADS_BAUD_CHANGE
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 64 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
-#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-
-/*
- * Environment Configuration
- */
-
-#ifdef CONFIG_TSEC_ENET
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#endif
-
-#define CONFIG_ROOTPATH "/opt/nfsroot"
-#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */
-
-/* default location for tftp and bootm */
-#define CONFIG_LOADADDR 1000000
-
-#define CONFIG_DEF_HWCONFIG fsl_ddr:ecc=on
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \
- "netdev=eth0\0" \
- "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
- "loadaddr=1000000\0" \
- "consoledev=ttyS0\0" \
- "ramdiskaddr=2000000\0" \
- "ramdiskfile=rootfs.ext2.gz.uboot\0" \
- "fdtaddr=1e00000\0" \
- "fdtfile=name/of/device-tree.dtb\0" \
- "othbootargs=ramdisk_size=600000\0" \
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs; " \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
-
-#include <asm/fsl_secure_boot.h>
-
-#endif /* __CONFIG_H */
--
2.25.1
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 05/24] arm: Remove configs/Cyrus_P5020_defconfig board
2020-05-27 16:46 [PATCH 00/24] spi: dm-conversion (part2) Jagan Teki
` (3 preceding siblings ...)
2020-05-27 16:46 ` [PATCH 04/24] arm: Remove configs/C29XPCIE_NAND_defconfig board Jagan Teki
@ 2020-05-27 16:46 ` Jagan Teki
2020-05-27 16:46 ` [PATCH 06/24] arm: Remove configs/MPC8536DS_36BIT_defconfig board Jagan Teki
` (17 subsequent siblings)
22 siblings, 0 replies; 59+ messages in thread
From: Jagan Teki @ 2020-05-27 16:46 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_SPI by the deadline.
Remove it.
Patch-cc: Andy Fleming <afleming@gmail.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
arch/powerpc/cpu/mpc85xx/Kconfig | 1 -
board/varisys/cyrus/Kconfig | 14 -
board/varisys/cyrus/MAINTAINERS | 7 -
board/varisys/cyrus/Makefile | 8 -
board/varisys/cyrus/README | 19 --
board/varisys/cyrus/cyrus.c | 117 -------
board/varisys/cyrus/cyrus.h | 9 -
board/varisys/cyrus/ddr.c | 191 -----------
board/varisys/cyrus/eth.c | 100 ------
board/varisys/cyrus/law.c | 26 --
board/varisys/cyrus/pbi.cfg | 35 --
board/varisys/cyrus/pci.c | 23 --
board/varisys/cyrus/rcw_p5020_v2.cfg | 11 -
board/varisys/cyrus/rcw_p5040.cfg | 11 -
board/varisys/cyrus/tlb.c | 105 ------
configs/Cyrus_P5020_defconfig | 45 ---
configs/Cyrus_P5040_defconfig | 45 ---
include/configs/cyrus.h | 466 ---------------------------
18 files changed, 1233 deletions(-)
delete mode 100644 board/varisys/cyrus/Kconfig
delete mode 100644 board/varisys/cyrus/MAINTAINERS
delete mode 100644 board/varisys/cyrus/Makefile
delete mode 100644 board/varisys/cyrus/README
delete mode 100644 board/varisys/cyrus/cyrus.c
delete mode 100644 board/varisys/cyrus/cyrus.h
delete mode 100644 board/varisys/cyrus/ddr.c
delete mode 100644 board/varisys/cyrus/eth.c
delete mode 100644 board/varisys/cyrus/law.c
delete mode 100644 board/varisys/cyrus/pbi.cfg
delete mode 100644 board/varisys/cyrus/pci.c
delete mode 100644 board/varisys/cyrus/rcw_p5020_v2.cfg
delete mode 100644 board/varisys/cyrus/rcw_p5040.cfg
delete mode 100644 board/varisys/cyrus/tlb.c
delete mode 100644 configs/Cyrus_P5020_defconfig
delete mode 100644 configs/Cyrus_P5040_defconfig
delete mode 100644 include/configs/cyrus.h
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 0ba6fe6daa..f58755873c 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -1617,7 +1617,6 @@ source "board/gdsys/p1022/Kconfig"
source "board/keymile/Kconfig"
source "board/sbc8548/Kconfig"
source "board/socrates/Kconfig"
-source "board/varisys/cyrus/Kconfig"
source "board/xes/xpedite520x/Kconfig"
source "board/xes/xpedite537x/Kconfig"
source "board/xes/xpedite550x/Kconfig"
diff --git a/board/varisys/cyrus/Kconfig b/board/varisys/cyrus/Kconfig
deleted file mode 100644
index a0389f8fa1..0000000000
--- a/board/varisys/cyrus/Kconfig
+++ /dev/null
@@ -1,14 +0,0 @@
-if TARGET_CYRUS_P5020 || TARGET_CYRUS_P5040
-
-config SYS_BOARD
- default "cyrus"
-
-config SYS_VENDOR
- default "varisys"
-
-config SYS_CONFIG_NAME
- default "cyrus"
-
-source "board/freescale/common/Kconfig"
-
-endif
diff --git a/board/varisys/cyrus/MAINTAINERS b/board/varisys/cyrus/MAINTAINERS
deleted file mode 100644
index 53b4a886bd..0000000000
--- a/board/varisys/cyrus/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-Cyrus BOARD
-M: Andy Fleming <afleming@gmail.com>
-S: Maintained
-F: board/varisys/cyrus/
-F: include/configs/cyrus.h
-F: configs/Cyrus_P5020_defconfig
-F: configs/Cyrus_P5040_defconfig
diff --git a/board/varisys/cyrus/Makefile b/board/varisys/cyrus/Makefile
deleted file mode 100644
index 15b3fb2964..0000000000
--- a/board/varisys/cyrus/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-
-obj-y += $(BOARD).o
-obj-y += ddr.o
-obj-y += law.o
-obj-y += tlb.o
-obj-y += eth.o
-obj-$(CONFIG_PCI) += pci.o
diff --git a/board/varisys/cyrus/README b/board/varisys/cyrus/README
deleted file mode 100644
index 9595dcb7cc..0000000000
--- a/board/varisys/cyrus/README
+++ /dev/null
@@ -1,19 +0,0 @@
-Rebuilding u-boot for Cyrus
-
-The Cyrus defconfigs are Cyrus_P5020_defconfig and Cyrus_P5040_defconfig.
-
-They currently disable size optimization in order to avoid a relocation
-bug in some versions of GCC. As the output size is a constant, the size
-optimization is not currently important.
-
-Cyrus boots off a microSD card in a slot on the motherboard. This requires
-that the u-boot is built for the Pre-Boot Loader on the P5020/P5040.
-In order to reflash u-boot, you must download u-boot.pbl, then write it
-onto the card. To do that from u-boot:
-
-> tftp 1000000 u-boot.pbl
-> mmc write 1000000 8 672
-
-If you want to do this via a card reader in linux:
-
-> dd if=u-boot.pbl of=/dev/sdX bs=512 oseek=8
diff --git a/board/varisys/cyrus/cyrus.c b/board/varisys/cyrus/cyrus.c
deleted file mode 100644
index a42910f600..0000000000
--- a/board/varisys/cyrus/cyrus.c
+++ /dev/null
@@ -1,117 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Based on corenet_ds.c
- */
-
-#include <common.h>
-#include <command.h>
-#include <env.h>
-#include <fdt_support.h>
-#include <image.h>
-#include <init.h>
-#include <netdev.h>
-#include <linux/compiler.h>
-#include <asm/mmu.h>
-#include <asm/processor.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_law.h>
-#include <asm/fsl_serdes.h>
-#include <asm/fsl_portals.h>
-#include <asm/fsl_liodn.h>
-#include <fm_eth.h>
-#include <pci.h>
-
-#include "cyrus.h"
-#include "../common/eeprom.h"
-
-#define GPIO_OPENDRAIN 0x30000000
-#define GPIO_DIR 0x3c000004
-#define GPIO_INITIAL 0x30000000
-#define GPIO_VGA_SWITCH 0x00001000
-
-int checkboard(void)
-{
- printf("Board: CYRUS\n");
-
- return 0;
-}
-
-int board_early_init_f(void)
-{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
-
- /*
- * Only use DDR1_MCK0/3 and DDR2_MCK0/3
- * disable DDR1_MCK1/2/4/5 and DDR2_MCK1/2/4/5 to reduce
- * the noise introduced by these unterminated and unused clock pairs.
- */
- setbits_be32(&gur->ddrclkdr, 0x001B001B);
-
- /* Set GPIO reset lines to open-drain, tristate */
- setbits_be32(&pgpio->gpdat, GPIO_INITIAL);
- setbits_be32(&pgpio->gpodr, GPIO_OPENDRAIN);
-
- /* Set GPIO Direction */
- setbits_be32(&pgpio->gpdir, GPIO_DIR);
-
- return 0;
-}
-
-int board_early_init_r(void)
-{
- fsl_lbc_t *lbc = LBC_BASE_ADDR;
-
- out_be32(&lbc->lbcr, 0);
- /* 1 clock LALE cycle */
- out_be32(&lbc->lcrr, 0x80000000 | CONFIG_SYS_LBC_LCRR);
-
- set_liodns();
-
-#ifdef CONFIG_SYS_DPAA_QBMAN
- setup_qbman_portals();
-#endif
- print_lbc_regs();
- return 0;
-}
-
-int misc_init_r(void)
-{
- return 0;
-}
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
- phys_addr_t base;
- phys_size_t size;
-
- ft_cpu_setup(blob, bd);
-
- base = env_get_bootm_low();
- size = env_get_bootm_size();
-
- fdt_fixup_memory(blob, (u64)base, (u64)size);
-
-#ifdef CONFIG_PCI
- pci_of_setup(blob, bd);
-#endif
-
- fdt_fixup_liodn(blob);
- fsl_fdt_fixup_dr_usb(blob, bd);
-
-#ifdef CONFIG_SYS_DPAA_FMAN
- fdt_fixup_fman_ethernet(blob);
-#endif
-
- return 0;
-}
-
-int mac_read_from_eeprom(void)
-{
- init_eeprom(CONFIG_SYS_EEPROM_BUS_NUM,
- CONFIG_SYS_I2C_EEPROM_ADDR,
- CONFIG_SYS_I2C_EEPROM_ADDR_LEN);
-
- return mac_read_from_eeprom_common();
-}
diff --git a/board/varisys/cyrus/cyrus.h b/board/varisys/cyrus/cyrus.h
deleted file mode 100644
index df037a59a0..0000000000
--- a/board/varisys/cyrus/cyrus.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-
-#ifndef __CYRUS_H
-#define __CYRUS_H
-
-void fdt_fixup_board_enet(void *blob);
-void pci_of_setup(void *blob, bd_t *bd);
-
-#endif
diff --git a/board/varisys/cyrus/ddr.c b/board/varisys/cyrus/ddr.c
deleted file mode 100644
index 7949eb88c0..0000000000
--- a/board/varisys/cyrus/ddr.c
+++ /dev/null
@@ -1,191 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Based on corenet_ds ddr code
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <hwconfig.h>
-#include <init.h>
-#include <log.h>
-#include <asm/mmu.h>
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-#include <asm/fsl_law.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-
-struct board_specific_parameters {
- u32 n_ranks;
- u32 datarate_mhz_high;
- u32 clk_adjust;
- u32 wrlvl_start;
- u32 cpo;
- u32 write_data_delay;
- u32 force_2t;
-};
-
-/*
- * This table contains all valid speeds we want to override with board
- * specific parameters. datarate_mhz_high values need to be in ascending order
- * for each n_ranks group.
- */
-static const struct board_specific_parameters udimm0[] = {
- /*
- * memory controller 0
- * num| hi| clk| wrlvl | cpo |wrdata|2T
- * ranks| mhz|adjst| start | |delay |
- */
- {4, 850, 4, 6, 0xff, 2, 0},
- {4, 950, 5, 7, 0xff, 2, 0},
- {4, 1050, 5, 8, 0xff, 2, 0},
- {4, 1250, 5, 10, 0xff, 2, 0},
- {4, 1350, 5, 11, 0xff, 2, 0},
- {4, 1666, 5, 12, 0xff, 2, 0},
- {2, 850, 5, 6, 0xff, 2, 0},
- {2, 1050, 5, 7, 0xff, 2, 0},
- {2, 1250, 4, 6, 0xff, 2, 0},
- {2, 1350, 5, 7, 0xff, 2, 0},
- {2, 1666, 5, 8, 0xff, 2, 0},
- {1, 1250, 4, 6, 0xff, 2, 0},
- {1, 1335, 4, 7, 0xff, 2, 0},
- {1, 1666, 4, 8, 0xff, 2, 0},
- {}
-};
-
-/*
- * The two slots have slightly different timing. The center values are good
- * for both slots. We use identical speed tables for them. In future use, if
- * DIMMs have fewer center values that require two separated tables, copy the
- * udimm0 table to udimm1 and make changes to clk_adjust and wrlvl_start.
- */
-static const struct board_specific_parameters *udimms[] = {
- udimm0,
- udimm0,
-};
-
-static const struct board_specific_parameters rdimm0[] = {
- /*
- * memory controller 0
- * num| hi| clk| wrlvl | cpo |wrdata|2T
- * ranks| mhz|adjst| start | |delay |
- */
- {4, 850, 4, 6, 0xff, 2, 0},
- {4, 950, 5, 7, 0xff, 2, 0},
- {4, 1050, 5, 8, 0xff, 2, 0},
- {4, 1250, 5, 10, 0xff, 2, 0},
- {4, 1350, 5, 11, 0xff, 2, 0},
- {4, 1666, 5, 12, 0xff, 2, 0},
- {2, 850, 4, 6, 0xff, 2, 0},
- {2, 1050, 4, 7, 0xff, 2, 0},
- {2, 1666, 4, 8, 0xff, 2, 0},
- {1, 850, 4, 5, 0xff, 2, 0},
- {1, 950, 4, 7, 0xff, 2, 0},
- {1, 1666, 4, 8, 0xff, 2, 0},
- {}
-};
-
-/*
- * The two slots have slightly different timing. See comments above.
- */
-static const struct board_specific_parameters *rdimms[] = {
- rdimm0,
- rdimm0,
-};
-
-void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
- ulong ddr_freq;
-
- if (ctrl_num > 1) {
- printf("Wrong parameter for controller number %d", ctrl_num);
- return;
- }
- if (!pdimm->n_ranks)
- return;
-
- if (popts->registered_dimm_en)
- pbsp = rdimms[ctrl_num];
- else
- pbsp = udimms[ctrl_num];
-
-
- /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
- * freqency and n_banks specified in board_specific_parameters table.
- */
- ddr_freq = get_ddr_freq(0) / 1000000;
- while (pbsp->datarate_mhz_high) {
- if (pbsp->n_ranks == pdimm->n_ranks) {
- if (ddr_freq <= pbsp->datarate_mhz_high) {
- popts->cpo_override = pbsp->cpo;
- popts->write_data_delay =
- pbsp->write_data_delay;
- popts->clk_adjust = pbsp->clk_adjust;
- popts->wrlvl_start = pbsp->wrlvl_start;
- popts->twot_en = pbsp->force_2t;
- goto found;
- }
- pbsp_highest = pbsp;
- }
- pbsp++;
- }
-
- if (pbsp_highest) {
- printf("Error: board specific timing not found for data rate %lu MT/s!\nTrying to use the highest speed (%u) parameters\n",
- ddr_freq, pbsp_highest->datarate_mhz_high);
- popts->cpo_override = pbsp_highest->cpo;
- popts->write_data_delay = pbsp_highest->write_data_delay;
- popts->clk_adjust = pbsp_highest->clk_adjust;
- popts->wrlvl_start = pbsp_highest->wrlvl_start;
- popts->twot_en = pbsp_highest->force_2t;
- } else {
- panic("DIMM is not supported by this board");
- }
-found:
- /*
- * Factors to consider for half-strength driver enable:
- * - number of DIMMs installed
- */
- popts->half_strength_driver_enable = 0;
- /*
- * Write leveling override
- */
- popts->wrlvl_override = 1;
- popts->wrlvl_sample = 0xf;
-
- /*
- * Rtt and Rtt_WR override
- */
- popts->rtt_override = 0;
-
- /* Enable ZQ calibration */
- popts->zq_en = 1;
-
- /* DHC_EN =1, ODT = 60 Ohm */
- popts->ddr_cdr1 = DDR_CDR1_DHC_EN;
-}
-
-int dram_init(void)
-{
- phys_size_t dram_size;
-
- puts("Initializing....");
-
- if (!fsl_use_spd())
- panic("Cyrus only supports using SPD for DRAM\n");
-
- puts("using SPD\n");
- dram_size = fsl_ddr_sdram();
-
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
-
- debug(" DDR: ");
- gd->ram_size = dram_size;
-
- return 0;
-}
diff --git a/board/varisys/cyrus/eth.c b/board/varisys/cyrus/eth.c
deleted file mode 100644
index 45b21fba32..0000000000
--- a/board/varisys/cyrus/eth.c
+++ /dev/null
@@ -1,100 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Author Adrian Cox
- * Based somewhat on board/freescale/corenet_ds/eth_hydra.c
- */
-
-#include <common.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/fsl_serdes.h>
-#include <fm_eth.h>
-#include <fsl_mdio.h>
-#include <malloc.h>
-#include <fdt_support.h>
-#include <fsl_dtsec.h>
-
-#ifdef CONFIG_FMAN_ENET
-
-#define FIRST_PORT_ADDR 3
-#define SECOND_PORT_ADDR 7
-
-#ifdef CONFIG_ARCH_P5040
-#define FIRST_PORT FM1_DTSEC5
-#define SECOND_PORT FM2_DTSEC5
-#else
-#define FIRST_PORT FM1_DTSEC4
-#define SECOND_PORT FM1_DTSEC5
-#endif
-
-#define IS_VALID_PORT(p) ((p) == FIRST_PORT || (p) == SECOND_PORT)
-
-static void cyrus_phy_tuning(int phy)
-{
- /*
- * Enable RGMII delay on Tx and Rx for CPU port
- */
- printf("Tuning PHY @ %d\n", phy);
-
- /* sets address 0x104 or reg 260 for writing */
- miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0xb, 0x8104);
- /* Sets RXC/TXC to +0.96ns and TX_CTL/RX_CTL to -0.84ns */
- miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0xc, 0xf0f0);
- /* sets address 0x105 or reg 261 for writing */
- miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0xb, 0x8105);
- /* writes to address 0x105 , RXD[3..0] to -0. */
- miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0xc, 0x0000);
- /* sets address 0x106 or reg 261 for writing */
- miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0xb, 0x8106);
- /* writes to address 0x106 , TXD[3..0] to -0.84ns */
- miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0xc, 0x0000);
- /* force re-negotiation */
- miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0x0, 0x1340);
-}
-#endif
-
-int board_eth_init(bd_t *bis)
-{
-#ifdef CONFIG_FMAN_ENET
- struct fsl_pq_mdio_info dtsec_mdio_info;
- unsigned int i;
-
- printf("Initializing Fman\n");
-
-
- /* Register the real 1G MDIO bus */
- dtsec_mdio_info.regs =
- (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
- dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
-
- fsl_pq_mdio_init(bis, &dtsec_mdio_info);
-
-
- fm_info_set_phy_address(FIRST_PORT, FIRST_PORT_ADDR);
- fm_info_set_mdio(FIRST_PORT,
- miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
- fm_info_set_phy_address(SECOND_PORT, SECOND_PORT_ADDR);
- fm_info_set_mdio(SECOND_PORT,
- miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
-
- /* Never disable DTSEC1 - it controls MDIO */
- for (i = FM1_DTSEC2; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
- if (!IS_VALID_PORT(i))
- fm_disable_port(i);
- }
-
-#ifdef CONFIG_ARCH_P5040
- for (i = FM2_DTSEC2; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
- if (!IS_VALID_PORT(i))
- fm_disable_port(i);
- }
-#endif
-
- cpu_eth_init(bis);
-
- cyrus_phy_tuning(FIRST_PORT_ADDR);
- cyrus_phy_tuning(SECOND_PORT_ADDR);
-#endif
-
- return pci_eth_init(bis);
-}
diff --git a/board/varisys/cyrus/law.c b/board/varisys/cyrus/law.c
deleted file mode 100644
index 8b1b118b55..0000000000
--- a/board/varisys/cyrus/law.c
+++ /dev/null
@@ -1,26 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Author: Adrian Cox
- * Based on corenet_ds law files.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-struct law_entry law_table[] = {
- SET_LAW(CONFIG_SYS_LBC0_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC),
- SET_LAW(CONFIG_SYS_LBC1_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
- SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_BMAN),
-#endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
- SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_QMAN),
-#endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
- /* Limit DCSR to 32M to access NPC Trace Buffer */
- SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
-#endif
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/varisys/cyrus/pbi.cfg b/board/varisys/cyrus/pbi.cfg
deleted file mode 100644
index 9b330ddcc4..0000000000
--- a/board/varisys/cyrus/pbi.cfg
+++ /dev/null
@@ -1,35 +0,0 @@
-#
-# Copyright 2012 Freescale Semiconductor, Inc.
-#
-# Refer docs/README.pblimage for more details about how-to configure
-# and create PBL boot image
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-#PBI commands
-#Initialize CPC1 as 1MB SRAM
-09010000 00200400
-09138000 00000000
-091380c0 00000100
-09010100 00000000
-09010104 fff0000b
-09010f00 08000000
-09010000 80000000
-#Configure LAW for CPC1
-09000d00 00000000
-09000d04 fff00000
-09000d08 81000013
-09000010 00000000
-09000014 ff000000
-09000018 81000000
-#Initialize eSPI controller, default configuration is slow for eSPI to
-#load data, this configuration comes from u-boot eSPI driver.
-09110000 80000403
-09110020 2d170008
-09110024 00100008
-09110028 00100008
-0911002c 00100008
-#Flush PBL data
-09138000 00000000
-091380c0 00000000
diff --git a/board/varisys/cyrus/pci.c b/board/varisys/cyrus/pci.c
deleted file mode 100644
index 66c4b30eb1..0000000000
--- a/board/varisys/cyrus/pci.c
+++ /dev/null
@@ -1,23 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2007-2011 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <init.h>
-#include <pci.h>
-#include <asm/fsl_pci.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <asm/fsl_serdes.h>
-
-void pci_init_board(void)
-{
- fsl_pcie_init_board(0);
-}
-
-void pci_of_setup(void *blob, bd_t *bd)
-{
- FT_FSL_PCI_SETUP;
-}
diff --git a/board/varisys/cyrus/rcw_p5020_v2.cfg b/board/varisys/cyrus/rcw_p5020_v2.cfg
deleted file mode 100644
index 9188080605..0000000000
--- a/board/varisys/cyrus/rcw_p5020_v2.cfg
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Default RCW for Cyrus P5020
-#
-
-#PBL preamble and RCW header
-aa55aa55 010e0100
-#64 bytes RCW data
-0c540000 00000000 1e1e0000 00000000
-44808c00 ff002000 68000000 45000000
-00000000 00000000 00000000 0003000f
-a0000000 00000000 00000000 00000000
diff --git a/board/varisys/cyrus/rcw_p5040.cfg b/board/varisys/cyrus/rcw_p5040.cfg
deleted file mode 100644
index 5284481568..0000000000
--- a/board/varisys/cyrus/rcw_p5040.cfg
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Default RCW for Cyrus P5040
-#
-
-#PBL preamble and RCW header
-aa55aa55 010e0100
-#64 bytes RCW data
-90e00000 00000000 acac9800 00440000
-44808c00 ff29a000 68000000 61000000
-00000000 00000000 00000000 0003000f
-a0000000 00000000 00000000 00000000
diff --git a/board/varisys/cyrus/tlb.c b/board/varisys/cyrus/tlb.c
deleted file mode 100644
index b1af3e04d6..0000000000
--- a/board/varisys/cyrus/tlb.c
+++ /dev/null
@@ -1,105 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Author: Adrian Cox
- * Based on corenet_ds tlb code
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
- /* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS,
- MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
- MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
- MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
- MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
-
- /* TLB 1 */
- /* *I*** - Covers boot page */
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
- /*
- * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
- * SRAM is at 0xfff00000, it covered the 0xfffff000.
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_1M, 1),
-#else
- SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_4K, 1),
-#endif
-
- /* *I*G* - CCSRBAR */
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 1, BOOKE_PAGESZ_16M, 1),
-
- /* Local Bus */
- SET_TLB_ENTRY(1, CONFIG_SYS_LBC0_BASE, CONFIG_SYS_LBC0_BASE_PHYS,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 2, BOOKE_PAGESZ_64K, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_LBC1_BASE, CONFIG_SYS_LBC1_BASE_PHYS,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 3, BOOKE_PAGESZ_4K, 1),
-
- /* *I*G* - PCI */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 4, BOOKE_PAGESZ_1G, 1),
-
- /* *I*G* - PCI */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000,
- CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 5, BOOKE_PAGESZ_256M, 1),
-
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000,
- CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 6, BOOKE_PAGESZ_256M, 1),
-
- /* *I*G* - PCI I/O */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 7, BOOKE_PAGESZ_256K, 1),
-
- /* Bman/Qman */
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
- SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
- MAS3_SW|MAS3_SR, 0,
- 0, 9, BOOKE_PAGESZ_1M, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000,
- CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 10, BOOKE_PAGESZ_1M, 1),
-#endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
- SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
- MAS3_SW|MAS3_SR, 0,
- 0, 11, BOOKE_PAGESZ_1M, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000,
- CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 12, BOOKE_PAGESZ_1M, 1),
-#endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
- SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 13, BOOKE_PAGESZ_4M, 1),
-#endif
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/configs/Cyrus_P5020_defconfig b/configs/Cyrus_P5020_defconfig
deleted file mode 100644
index 19fc741eb7..0000000000
--- a/configs/Cyrus_P5020_defconfig
+++ /dev/null
@@ -1,45 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0xCF400
-CONFIG_MPC85xx=y
-CONFIG_TARGET_CYRUS_P5020=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL"
-CONFIG_BOOTDELAY=10
-CONFIG_CONSOLE_MUX=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_ESDHC=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_MICREL=y
-CONFIG_PHY_MICREL_KSZ90X1=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_KEYBOARD=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/Cyrus_P5040_defconfig b/configs/Cyrus_P5040_defconfig
deleted file mode 100644
index 9c6919f387..0000000000
--- a/configs/Cyrus_P5040_defconfig
+++ /dev/null
@@ -1,45 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0xCF400
-CONFIG_MPC85xx=y
-CONFIG_TARGET_CYRUS_P5040=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL"
-CONFIG_BOOTDELAY=10
-CONFIG_CONSOLE_MUX=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_ESDHC=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_MICREL=y
-CONFIG_PHY_MICREL_KSZ90X1=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_KEYBOARD=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/cyrus.h b/include/configs/cyrus.h
deleted file mode 100644
index 052e6018a3..0000000000
--- a/include/configs/cyrus.h
+++ /dev/null
@@ -1,466 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Based on corenet_ds.h
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <linux/stringify.h>
-
-#if !defined(CONFIG_ARCH_P5020) && !defined(CONFIG_ARCH_P5040)
-#error Must call Cyrus CONFIG with a specific CPU enabled.
-#endif
-
-#define CONFIG_SDCARD
-#define CONFIG_FSL_SATA_V2
-#define CONFIG_PCIE3
-#define CONFIG_PCIE4
-#ifdef CONFIG_ARCH_P5020
-#define CONFIG_SYS_FSL_RAID_ENGINE
-#define CONFIG_SYS_DPAA_RMAN
-#endif
-#define CONFIG_SYS_DPAA_PME
-
-/*
- * Corenet DS style board configuration file
- */
-#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
-#define CONFIG_SYS_FSL_PBL_PBI board/varisys/cyrus/pbi.cfg
-#if defined(CONFIG_ARCH_P5020)
-#define CONFIG_SYS_CLK_FREQ 133000000
-#define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5020_v2.cfg
-#elif defined(CONFIG_ARCH_P5040)
-#define CONFIG_SYS_CLK_FREQ 100000000
-#define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5040.cfg
-#endif
-
-/* High Level Configuration Options */
-#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
-
-#define CONFIG_SYS_MMC_MAX_DEVICE 1
-
-#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
-#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
-#define CONFIG_PCIE1 /* PCIE controller 1 */
-#define CONFIG_PCIE2 /* PCIE controller 2 */
-#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
-#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
-
-#define CONFIG_ENV_OVERWRITE
-
-#if defined(CONFIG_SDCARD)
-#define CONFIG_FSL_FIXED_MMC_LOCATION
-#define CONFIG_SYS_MMC_ENV_DEV 0
-#endif
-
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_SYS_CACHE_STASHING
-#define CONFIG_BACKSIDE_L2_CACHE
-#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
-#define CONFIG_BTB /* toggle branch predition */
-#define CONFIG_DDR_ECC
-#ifdef CONFIG_DDR_ECC
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
-#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
-#endif
-
-#define CONFIG_ENABLE_36BIT_PHYS
-
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_ADDR_MAP
-#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
-#endif
-
-/* test POST memory test */
-#undef CONFIG_POST
-
-/*
- * Config the L3 Cache as L3 SRAM
- */
-#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
-#else
-#define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
-#endif
-#define CONFIG_SYS_L3_SIZE (1024 << 10)
-#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
-
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_DCSRBAR 0xf0000000
-#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
-#endif
-
-/*
- * DDR Setup
- */
-#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
-
-#define CONFIG_DDR_SPD
-
-#define CONFIG_SYS_SPD_BUS_NUM 1
-#define SPD_EEPROM_ADDRESS1 0x51
-#define SPD_EEPROM_ADDRESS2 0x52
-#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
-
-/*
- * Local Bus Definitions
- */
-
-#define CONFIG_SYS_LBC0_BASE 0xe0000000 /* Start of LBC Registers */
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_LBC0_BASE_PHYS 0xfe0000000ull
-#else
-#define CONFIG_SYS_LBC0_BASE_PHYS CONFIG_SYS_LBC0_BASE
-#endif
-
-#define CONFIG_SYS_LBC1_BASE 0xe1000000 /* Start of LBC Registers */
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_LBC1_BASE_PHYS 0xfe1000000ull
-#else
-#define CONFIG_SYS_LBC1_BASE_PHYS CONFIG_SYS_LBC1_BASE
-#endif
-
-/* Set the local bus clock 1/16 of platform clock */
-#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_16 | LCRR_EADC_1)
-
-#define CONFIG_SYS_BR0_PRELIM \
-(BR_PHYS_ADDR(CONFIG_SYS_LBC0_BASE_PHYS) | BR_PS_16 | BR_V)
-#define CONFIG_SYS_BR1_PRELIM \
-(BR_PHYS_ADDR(CONFIG_SYS_LBC1_BASE_PHYS) | BR_PS_16 | BR_V)
-
-#define CONFIG_SYS_OR0_PRELIM 0xfff00010
-#define CONFIG_SYS_OR1_PRELIM 0xfff00010
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-
-#if defined(CONFIG_RAMBOOT_PBL)
-#define CONFIG_SYS_RAMBOOT
-#endif
-
-#define CONFIG_HWCONFIG
-
-/* define to use L1 as initial stack */
-#define CONFIG_L1_INIT_RAM
-#define CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
-/* The assembler doesn't like typecast */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
- ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
- CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
-#else
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
-#endif
-#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
-
-/* Serial Port - controlled on board with jumper J8
- * open - index 2
- * shorted - index 1
- */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
-{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
-#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
-#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_I2C_CMD_TREE
-#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
-#define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
-#define CONFIG_SYS_FSL_I2C3_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
-#define CONFIG_SYS_FSL_I2C4_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
-
-#define CONFIG_ID_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#define CONFIG_SYS_EEPROM_BUS_NUM 0
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
-
-#define CONFIG_SYS_I2C_GENERIC_MAC
-#define CONFIG_SYS_I2C_MAC1_BUS 3
-#define CONFIG_SYS_I2C_MAC1_CHIP_ADDR 0x57
-#define CONFIG_SYS_I2C_MAC1_DATA_ADDR 0xf2
-#define CONFIG_SYS_I2C_MAC2_BUS 0
-#define CONFIG_SYS_I2C_MAC2_CHIP_ADDR 0x50
-#define CONFIG_SYS_I2C_MAC2_DATA_ADDR 0xfa
-
-#define CONFIG_RTC_MCP79411 1
-#define CONFIG_SYS_RTC_BUS_NUM 3
-#define CONFIG_SYS_I2C_RTC_ADDR 0x6f
-
-/*
- * eSPI - Enhanced SPI
- */
-
-/*
- * General PCI
- * Memory space is mapped 1-1, but I/O space must start from 0.
- */
-
-/* controller 1, direct to uli, tgtid 3, Base address 20000 */
-#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
-#else
-#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
-#endif
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
-#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
-#else
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
-#endif
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
-
-/* controller 2, Slot 2, tgtid 2, Base address 201000 */
-#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
-#else
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
-#endif
-#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
-#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
-#else
-#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
-#endif
-#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
-
-/* controller 3, Slot 1, tgtid 1, Base address 202000 */
-#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
-#else
-#define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000
-#endif
-#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
-#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
-#else
-#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
-#endif
-#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
-
-/* controller 4, Base address 203000 */
-#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
-#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
-#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
-
-/* Qman/Bman */
-#define CONFIG_SYS_BMAN_NUM_PORTALS 10
-#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
-#else
-#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
-#endif
-#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
-#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
-#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
-#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
-#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
- CONFIG_SYS_BMAN_CENA_SIZE)
-#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
-#define CONFIG_SYS_QMAN_NUM_PORTALS 10
-#define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
-#else
-#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
-#endif
-#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
-#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
-#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
-#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
-#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
- CONFIG_SYS_QMAN_CENA_SIZE)
-#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
-
-#define CONFIG_SYS_DPAA_FMAN
-/* Default address of microcode for the Linux Fman driver */
-/*
- * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
- * about 825KB (1650 blocks), Env is stored after the image, and the env size is
- * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
-
-#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
-#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
-
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#endif /* CONFIG_PCI */
-
-/* SATA */
-#ifdef CONFIG_FSL_SATA_V2
-#define CONFIG_SYS_SATA_MAX_DEVICE 2
-#define CONFIG_SATA1
-#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
-#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
-#define CONFIG_SATA2
-#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
-#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
-
-#define CONFIG_LBA48
-#endif
-
-#ifdef CONFIG_FMAN_ENET
-#define CONFIG_SYS_TBIPA_VALUE 8
-#define CONFIG_ETHPRIME "FM1 at DTSEC4"
-#endif
-
-/*
- * Environment
- */
-#define CONFIG_LOADS_ECHO /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
-
-/*
- * USB
- */
-#define CONFIG_HAS_FSL_DR_USB
-#define CONFIG_HAS_FSL_MPH_USB
-
-#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
-#define CONFIG_USB_EHCI_FSL
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_EHCI_IS_TDI
- /* _VIA_CONTROL_EP */
-#endif
-
-#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
-#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 64 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
-#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-#define CONFIG_ROOTPATH "/opt/nfsroot"
-#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
-
-/* default location for tftp and bootm */
-#define CONFIG_LOADADDR 1000000
-
-#define __USB_PHY_TYPE utmi
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
-"hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
-"bank_intlv=cs0_cs1;" \
-"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
-"usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
-"netdev=eth0\0" \
-"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
-"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
-"consoledev=ttyS0\0" \
-"ramdiskaddr=2000000\0" \
-"fdtaddr=1e00000\0" \
-"bdev=sda3\0"
-
-#define CONFIG_HDBOOT \
-"setenv bootargs root=/dev/$bdev rw " \
-"console=$consoledev,$baudrate $othbootargs;" \
-"tftp $loadaddr $bootfile;" \
-"tftp $fdtaddr $fdtfile;" \
-"bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_NFSBOOTCOMMAND \
-"setenv bootargs root=/dev/nfs rw " \
-"nfsroot=$serverip:$rootpath " \
-"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
-"console=$consoledev,$baudrate $othbootargs;" \
-"tftp $loadaddr $bootfile;" \
-"tftp $fdtaddr $fdtfile;" \
-"bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
-"setenv bootargs root=/dev/ram rw " \
-"console=$consoledev,$baudrate $othbootargs;" \
-"tftp $ramdiskaddr $ramdiskfile;" \
-"tftp $loadaddr $bootfile;" \
-"tftp $fdtaddr $fdtfile;" \
-"bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
-
-#include <asm/fsl_secure_boot.h>
-
-#endif /* __CONFIG_H */
--
2.25.1
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 06/24] arm: Remove configs/MPC8536DS_36BIT_defconfig board
2020-05-27 16:46 [PATCH 00/24] spi: dm-conversion (part2) Jagan Teki
` (4 preceding siblings ...)
2020-05-27 16:46 ` [PATCH 05/24] arm: Remove configs/Cyrus_P5020_defconfig board Jagan Teki
@ 2020-05-27 16:46 ` Jagan Teki
2020-05-28 5:32 ` Priyanka Jain
2020-05-27 16:46 ` [PATCH 07/24] arm: Remove configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig board Jagan Teki
` (16 subsequent siblings)
22 siblings, 1 reply; 59+ messages in thread
From: Jagan Teki @ 2020-05-27 16:46 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_SPI by the deadline.
Remove it.
Patch-cc: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
arch/powerpc/cpu/mpc85xx/Kconfig | 1 -
board/freescale/mpc8536ds/Kconfig | 12 -
board/freescale/mpc8536ds/MAINTAINERS | 9 -
board/freescale/mpc8536ds/Makefile | 10 -
board/freescale/mpc8536ds/README | 127 -----
board/freescale/mpc8536ds/ddr.c | 59 ---
board/freescale/mpc8536ds/law.c | 19 -
board/freescale/mpc8536ds/mpc8536ds.c | 293 ------------
board/freescale/mpc8536ds/tlb.c | 70 ---
configs/MPC8536DS_36BIT_defconfig | 61 ---
configs/MPC8536DS_SDCARD_defconfig | 60 ---
configs/MPC8536DS_SPIFLASH_defconfig | 61 ---
configs/MPC8536DS_defconfig | 60 ---
include/configs/MPC8536DS.h | 642 --------------------------
14 files changed, 1484 deletions(-)
delete mode 100644 board/freescale/mpc8536ds/Kconfig
delete mode 100644 board/freescale/mpc8536ds/MAINTAINERS
delete mode 100644 board/freescale/mpc8536ds/Makefile
delete mode 100644 board/freescale/mpc8536ds/README
delete mode 100644 board/freescale/mpc8536ds/ddr.c
delete mode 100644 board/freescale/mpc8536ds/law.c
delete mode 100644 board/freescale/mpc8536ds/mpc8536ds.c
delete mode 100644 board/freescale/mpc8536ds/tlb.c
delete mode 100644 configs/MPC8536DS_36BIT_defconfig
delete mode 100644 configs/MPC8536DS_SDCARD_defconfig
delete mode 100644 configs/MPC8536DS_SPIFLASH_defconfig
delete mode 100644 configs/MPC8536DS_defconfig
delete mode 100644 include/configs/MPC8536DS.h
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index f58755873c..1842d71f24 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -1590,7 +1590,6 @@ config SYS_FSL_LBC_CLK_DIV
eLBC controller).
source "board/freescale/corenet_ds/Kconfig"
-source "board/freescale/mpc8536ds/Kconfig"
source "board/freescale/mpc8541cds/Kconfig"
source "board/freescale/mpc8544ds/Kconfig"
source "board/freescale/mpc8548cds/Kconfig"
diff --git a/board/freescale/mpc8536ds/Kconfig b/board/freescale/mpc8536ds/Kconfig
deleted file mode 100644
index 1a6a9d4598..0000000000
--- a/board/freescale/mpc8536ds/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MPC8536DS
-
-config SYS_BOARD
- default "mpc8536ds"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "MPC8536DS"
-
-endif
diff --git a/board/freescale/mpc8536ds/MAINTAINERS b/board/freescale/mpc8536ds/MAINTAINERS
deleted file mode 100644
index 5ce5164e49..0000000000
--- a/board/freescale/mpc8536ds/MAINTAINERS
+++ /dev/null
@@ -1,9 +0,0 @@
-MPC8536DS BOARD
-M: Priyanka Jain <priyanka.jain@nxp.com>
-S: Maintained
-F: board/freescale/mpc8536ds/
-F: include/configs/MPC8536DS.h
-F: configs/MPC8536DS_defconfig
-F: configs/MPC8536DS_36BIT_defconfig
-F: configs/MPC8536DS_SDCARD_defconfig
-F: configs/MPC8536DS_SPIFLASH_defconfig
diff --git a/board/freescale/mpc8536ds/Makefile b/board/freescale/mpc8536ds/Makefile
deleted file mode 100644
index 6b936aa299..0000000000
--- a/board/freescale/mpc8536ds/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2008 Freescale Semiconductor.
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-
-obj-y += mpc8536ds.o
-obj-y += ddr.o
-obj-y += law.o
-obj-y += tlb.o
diff --git a/board/freescale/mpc8536ds/README b/board/freescale/mpc8536ds/README
deleted file mode 100644
index 2a38bd6dda..0000000000
--- a/board/freescale/mpc8536ds/README
+++ /dev/null
@@ -1,127 +0,0 @@
-Overview:
-=========
-
-The MPC8536E integrates a PowerPC processor core with system logic
-required for imaging, networking, and communications applications.
-
-Boot from NAND:
-===============
-
-The MPC8536E is capable of booting from NAND flash which uses the image
-u-boot-nand.bin. This image contains two parts: a first stage image(also
-call 4K NAND loader and a second stage image. The former is appended to
-the latter to produce u-boot-nand.bin.
-
-The bootup process can be divided into two stages: the first stage will
-configure the L2SRAM, then copy the second stage image to L2SRAM and jump
-to it. The second stage image is to configure all the hardware and boot up
-to U-Boot command line.
-
-The 4K NAND loader's code comes from the corresponding nand_spl directory,
-along with the code twisted by CONFIG_NAND_SPL. The macro CONFIG_NAND_SPL
-is mainly used to shrink the code size to the 4K size limitation.
-
-The macro CONFIG_SYS_RAMBOOT is used to control the code to produce the
-second stage image. It's set in the board config file when boot from NAND
-is selected.
-
-Build and boot steps
---------------------
-
-1. Building image
- make MPC8536DS_NAND_config
- make CROSS_COMPILE=powerpc-none-linux-gnuspe- all
-
-2. Change dip-switch
- SW2[5-8] = 1011
- SW9[1-3] = 101
- Note: 1 stands for 'on', 0 stands for 'off'
-
-3. Flash image
- tftp 1000000 u-boot-nand.bin
- nand erase 0 a0000
- nand write 1000000 0 a0000
-
-Boot from On-chip ROM:
-======================
-
-The MPC8536E is capable of booting from the on-chip ROM - boot from eSDHC
-and boot from eSPI. When power on, the porcessor excutes the ROM code to
-initialize the eSPI/eSDHC controller, and loads the mian U-Boot image from
-the memory device that interfaced to the controller, such as the SDCard or
-SPI EEPROM, to the target memory, e.g. SDRAM or L2SRAM, then boot from it.
-
-The memory device should contain a specific data structure with control word
-and config word at the fixed address. The config word direct the process how
-to config the memory device, and the control word direct the processor where
-to find the image on the memory device, or where copy the main image to. The
-user can use any method to store the data structure to the memory device, only
-if store it on the assigned address.
-
-Build and boot steps
---------------------
-
-For boot from eSDHC:
-1. Build image
- make MPC8536DS_SDCARD_config
- make CROSS_COMPILE=powerpc-none-linux-gnuspe- all
-
-2. Change dip-switch
- SW2[5-8] = 0111
- SW3[1] = 0
- SW8[7] = 0 - The on-board SD/MMC slot is active
- SW8[7] = 1 - The externel SD/MMC slot is active
-
-3. Put image to SDCard
- Put the follwing info at the assigned address on the SDCard:
-
- Offset | Data | Description
- --------------------------------------------------------
- | 0x40-0x43 | 0x424F4F54 | BOOT signature |
- --------------------------------------------------------
- | 0x48-0x4B | 0x00080000 | u-boot.bin's size |
- --------------------------------------------------------
- | 0x50-0x53 | 0x???????? | u-boot.bin's Addr on SDCard |
- --------------------------------------------------------
- | 0x58-0x5B | 0xF8F80000 | Target Address |
- -------------------------------------------------------
- | 0x60-0x63 | 0xF8FFF000 | Execution Starting Address |
- --------------------------------------------------------
- | 0x68-0x6B | 0x6 | Number of Config Addr/Data |
- --------------------------------------------------------
- | 0x80-0x83 | 0xFF720100 | Config Addr 1 |
- | 0x84-0x87 | 0xF8F80000 | Config Data 1 |
- --------------------------------------------------------
- | 0x88-0x8b | 0xFF720e44 | Config Addr 2 |
- | 0x8c-0x8f | 0x0000000C | Config Data 2 |
- --------------------------------------------------------
- | 0x90-0x93 | 0xFF720000 | Config Addr 3 |
- | 0x94-0x97 | 0x80010000 | Config Data 3 |
- --------------------------------------------------------
- | 0x98-0x9b | 0xFF72e40c | Config Addr 4 |
- | 0x9c-0x9f | 0x00000040 | Config Data 4 |
- --------------------------------------------------------
- | 0xa0-0xa3 | 0x40000001 | Config Addr 5 |
- | 0xa4-0xa7 | 0x00000100 | Config Data 5 |
- --------------------------------------------------------
- | 0xa8-0xab | 0x80000001 | Config Addr 6 |
- | 0xac-0xaf | 0x80000001 | Config Data 6 |
- --------------------------------------------------------
- | ...... |
- --------------------------------------------------------
- | 0x???????? | u-boot.bin |
- --------------------------------------------------------
-
- then insert the SDCard to the active slot to boot up.
-
-For boot from eSPI:
-1. Build image
- make MPC8536DS_SPIFLASH_config
- make CROSS_COMPILE=powerpc-none-linux-gnuspe- all
-
-2. Change dip-switch
- SW2[5-8] = 0110
-
-3. Put image to SPI flash
- Put the info in the above table onto the SPI flash, then
- boot up.
diff --git a/board/freescale/mpc8536ds/ddr.c b/board/freescale/mpc8536ds/ddr.c
deleted file mode 100644
index 8319ae8245..0000000000
--- a/board/freescale/mpc8536ds/ddr.c
+++ /dev/null
@@ -1,59 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-
-void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- /*
- * Factors to consider for clock adjust:
- * - number of chips on bus
- * - position of slot
- * - DDR1 vs. DDR2?
- * - ???
- *
- * This needs to be determined on a board-by-board basis.
- * 0110 3/4 cycle late
- * 0111 7/8 cycle late
- */
- popts->clk_adjust = 7;
-
- /*
- * Factors to consider for CPO:
- * - frequency
- * - ddr1 vs. ddr2
- */
- popts->cpo_override = 10;
-
- /*
- * Factors to consider for write data delay:
- * - number of DIMMs
- *
- * 1 = 1/4 clock delay
- * 2 = 1/2 clock delay
- * 3 = 3/4 clock delay
- * 4 = 1 clock delay
- * 5 = 5/4 clock delay
- * 6 = 3/2 clock delay
- */
- popts->write_data_delay = 3;
-
- /*
- * Factors to consider for half-strength driver enable:
- * - number of DIMMs installed
- */
- popts->half_strength_driver_enable = 0;
-
- /*
- * For wake up arp feature, we need enable auto self refresh
- */
- popts->auto_self_refresh_en = 1;
- popts->sr_it = 0x6;
-}
diff --git a/board/freescale/mpc8536ds/law.c b/board/freescale/mpc8536ds/law.c
deleted file mode 100644
index d59b12d82c..0000000000
--- a/board/freescale/mpc8536ds/law.c
+++ /dev/null
@@ -1,19 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-struct law_entry law_table[] = {
- SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
- SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
- SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c
deleted file mode 100644
index 5907a7b428..0000000000
--- a/board/freescale/mpc8536ds/mpc8536ds.c
+++ /dev/null
@@ -1,293 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008-2012 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <init.h>
-#include <log.h>
-#include <net.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_pci.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/io.h>
-#include <asm/fsl_serdes.h>
-#include <spd.h>
-#include <miiphy.h>
-#include <linux/delay.h>
-#include <linux/libfdt.h>
-#include <spd_sdram.h>
-#include <fdt_support.h>
-#include <fsl_mdio.h>
-#include <tsec.h>
-#include <netdev.h>
-#include <sata.h>
-
-#include "../common/sgmii_riser.h"
-
-int board_early_init_f (void)
-{
-#ifdef CONFIG_MMC
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-
- setbits_be32(&gur->pmuxcr,
- (MPC85xx_PMUXCR_SDHC_CD |
- MPC85xx_PMUXCR_SDHC_WP));
-
- /* The MPC8536DS board insert the SDHC_WP pin for erratum NMG_eSDHC118,
- * however, this erratum only applies to MPC8536 Rev1.0.
- * So set SDHC_WP to active-low when use MPC8536 Rev1.1 and greater.*/
- if ((((SVR_MAJ(get_svr()) & 0x7) == 0x1) &&
- (SVR_MIN(get_svr()) >= 0x1))
- || (SVR_MAJ(get_svr() & 0x7) > 0x1))
- setbits_be32(&gur->gencfgr, MPC85xx_GENCFGR_SDHC_WP_INV);
-#endif
- return 0;
-}
-
-int checkboard (void)
-{
- u8 vboot;
- u8 *pixis_base = (u8 *)PIXIS_BASE;
-
- printf("Board: MPC8536DS Sys ID: 0x%02x, "
- "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
- in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
- in_8(pixis_base + PIXIS_PVER));
-
- vboot = in_8(pixis_base + PIXIS_VBOOT);
- switch ((vboot & PIXIS_VBOOT_LBMAP) >> 5) {
- case PIXIS_VBOOT_LBMAP_NOR0:
- puts ("vBank: 0\n");
- break;
- case PIXIS_VBOOT_LBMAP_NOR1:
- puts ("vBank: 1\n");
- break;
- case PIXIS_VBOOT_LBMAP_NOR2:
- puts ("vBank: 2\n");
- break;
- case PIXIS_VBOOT_LBMAP_NOR3:
- puts ("vBank: 3\n");
- break;
- case PIXIS_VBOOT_LBMAP_PJET:
- puts ("Promjet\n");
- break;
- case PIXIS_VBOOT_LBMAP_NAND:
- puts ("NAND\n");
- break;
- }
-
- return 0;
-}
-
-#if !defined(CONFIG_SPD_EEPROM)
-/*
- * Fixed sdram init -- doesn't use serial presence detect.
- */
-
-phys_size_t fixed_sdram (void)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- struct ccsr_ddr __iomem *ddr = &immap->im_ddr;
- uint d_init;
-
- ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
- ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
-
- ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
- ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
- ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
- ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
- ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
- ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
- ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
- ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
- ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
- ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
-
-#if defined (CONFIG_DDR_ECC)
- ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
- ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
- ddr->err_sbe = CONFIG_SYS_DDR_SBE;
-#endif
- asm("sync;isync");
-
- udelay(500);
-
- ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
-
-#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
- d_init = 1;
- debug("DDR - 1st controller: memory initializing\n");
- /*
- * Poll until memory is initialized.
- * 512 Meg at 400 might hit this 200 times or so.
- */
- while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
- udelay(1000);
- }
- debug("DDR: memory initialized\n\n");
- asm("sync; isync");
- udelay(500);
-#endif
-
- return 512 * 1024 * 1024;
-}
-
-#endif
-
-#ifdef CONFIG_PCI1
-static struct pci_controller pci1_hose;
-#endif
-
-#ifdef CONFIG_PCI
-void pci_init_board(void)
-{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- struct fsl_pci_info pci_info;
- u32 devdisr, pordevsr;
- u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
- int first_free_busno;
-
- first_free_busno = fsl_pcie_init_board(0);
-
-#ifdef CONFIG_PCI1
- devdisr = in_be32(&gur->devdisr);
- pordevsr = in_be32(&gur->pordevsr);
- porpllsr = in_be32(&gur->porpllsr);
-
- pci_speed = 66666000;
- pci_32 = 1;
- pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
- pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
-
- if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
- SET_STD_PCI_INFO(pci_info, 1);
- set_next_law(pci_info.mem_phys,
- law_size_bits(pci_info.mem_size), pci_info.law);
- set_next_law(pci_info.io_phys,
- law_size_bits(pci_info.io_size), pci_info.law);
-
- pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
- printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
- (pci_32) ? 32 : 64,
- (pci_speed == 33333000) ? "33" :
- (pci_speed == 66666000) ? "66" : "unknown",
- pci_clk_sel ? "sync" : "async",
- pci_agent ? "agent" : "host",
- pci_arb ? "arbiter" : "external-arbiter",
- pci_info.regs);
-
- first_free_busno = fsl_pci_init_port(&pci_info,
- &pci1_hose, first_free_busno);
- } else {
- printf("PCI: disabled\n");
- }
-
- puts("\n");
-#else
- setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
-#endif
-}
-#endif
-
-int board_early_init_r(void)
-{
- const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
- int flash_esel = find_tlb_idx((void *)flashbase, 1);
-
- /*
- * Remap Boot flash + PROMJET region to caching-inhibited
- * so that flash can be erased properly.
- */
-
- /* Flush d-cache and invalidate i-cache of any FLASH data */
- flush_dcache();
- invalidate_icache();
-
- if (flash_esel == -1) {
- /* very unlikely unless something is messed up */
- puts("Error: Could not find TLB for FLASH BASE\n");
- flash_esel = 1; /* give our best effort to continue */
- } else {
- /* invalidate existing TLB entry for flash + promjet */
- disable_tlb(flash_esel);
- }
-
- set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
- 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */
-
- return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
-#ifdef CONFIG_TSEC_ENET
- struct fsl_pq_mdio_info mdio_info;
- struct tsec_info_struct tsec_info[2];
- int num = 0;
-
-#ifdef CONFIG_TSEC1
- SET_STD_TSEC_INFO(tsec_info[num], 1);
- if (is_serdes_configured(SGMII_TSEC1)) {
- puts("eTSEC1 is in sgmii mode.\n");
- tsec_info[num].phyaddr = 0;
- tsec_info[num].flags |= TSEC_SGMII;
- }
- num++;
-#endif
-#ifdef CONFIG_TSEC3
- SET_STD_TSEC_INFO(tsec_info[num], 3);
- if (is_serdes_configured(SGMII_TSEC3)) {
- puts("eTSEC3 is in sgmii mode.\n");
- tsec_info[num].phyaddr = 1;
- tsec_info[num].flags |= TSEC_SGMII;
- }
- num++;
-#endif
-
- if (!num) {
- printf("No TSECs initialized\n");
- return 0;
- }
-
-#ifdef CONFIG_FSL_SGMII_RISER
- if (is_serdes_configured(SGMII_TSEC1) ||
- is_serdes_configured(SGMII_TSEC3)) {
- fsl_sgmii_riser_init(tsec_info, num);
- }
-#endif
-
- mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
- mdio_info.name = DEFAULT_MII_NAME;
- fsl_pq_mdio_init(bis, &mdio_info);
-
- tsec_eth_init(bis, tsec_info, num);
-#endif
- return pci_eth_init(bis);
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, bd_t *bd)
-{
- ft_cpu_setup(blob, bd);
-
- FT_FSL_PCI_SETUP;
-
-#ifdef CONFIG_FSL_SGMII_RISER
- fsl_sgmii_riser_fdt_fixup(blob);
-#endif
-
-#ifdef CONFIG_HAS_FSL_MPH_USB
- fsl_fdt_fixup_dr_usb(blob, bd);
-#endif
-
- return 0;
-}
-#endif
diff --git a/board/freescale/mpc8536ds/tlb.c b/board/freescale/mpc8536ds/tlb.c
deleted file mode 100644
index 5df4788e0a..0000000000
--- a/board/freescale/mpc8536ds/tlb.c
+++ /dev/null
@@ -1,70 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
- /* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
-
- SET_TLB_ENTRY(0, PIXIS_BASE, PIXIS_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_4K, 0),
-
- /* TLB 1 */
- /* *I*G* - CCSRBAR */
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_1M, 1),
-
- /* W**G* - Flash/promjet, localbus */
- /* This will be changed to *I*G* after relocation to RAM. */
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
- MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
- 0, 1, BOOKE_PAGESZ_256M, 1),
-
- /* *I*G* - PCI */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 2, BOOKE_PAGESZ_1G, 1),
-
- /* *I*G* - PCI I/O */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_VIRT, CONFIG_SYS_PCI1_IO_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 3, BOOKE_PAGESZ_256K, 1),
-
- /* *I*G - NAND */
- SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 4, BOOKE_PAGESZ_1M, 1),
-
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
- /* *I*G - L2SRAM */
- SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 5, BOOKE_PAGESZ_256K, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
- CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 6, BOOKE_PAGESZ_256K, 1),
-#endif
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/configs/MPC8536DS_36BIT_defconfig b/configs/MPC8536DS_36BIT_defconfig
deleted file mode 100644
index e60890e2d0..0000000000
--- a/configs/MPC8536DS_36BIT_defconfig
+++ /dev/null
@@ -1,61 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_MPC8536DS=y
-CONFIG_PHYS_64BIT=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-# CONFIG_CONSOLE_MUX is not set
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_SYS_FSL_DDR2=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_VIDEO=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8536DS_SDCARD_defconfig b/configs/MPC8536DS_SDCARD_defconfig
deleted file mode 100644
index 9f653661f4..0000000000
--- a/configs/MPC8536DS_SDCARD_defconfig
+++ /dev/null
@@ -1,60 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xf8f40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x0
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_MPC8536DS=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
-CONFIG_BOOTDELAY=10
-# CONFIG_CONSOLE_MUX is not set
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_SYS_FSL_DDR2=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_VIDEO=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8536DS_SPIFLASH_defconfig b/configs/MPC8536DS_SPIFLASH_defconfig
deleted file mode 100644
index 866d719564..0000000000
--- a/configs/MPC8536DS_SPIFLASH_defconfig
+++ /dev/null
@@ -1,61 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xf8f40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0xF0000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_MPC8536DS=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
-CONFIG_BOOTDELAY=10
-# CONFIG_CONSOLE_MUX is not set
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_SYS_FSL_DDR2=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_VIDEO=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8536DS_defconfig b/configs/MPC8536DS_defconfig
deleted file mode 100644
index 9366e7a757..0000000000
--- a/configs/MPC8536DS_defconfig
+++ /dev/null
@@ -1,60 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_MPC8536DS=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-# CONFIG_CONSOLE_MUX is not set
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_SYS_FSL_DDR2=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_VIDEO=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h
deleted file mode 100644
index 340574a985..0000000000
--- a/include/configs/MPC8536DS.h
+++ /dev/null
@@ -1,642 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2007-2009,2010-2012 Freescale Semiconductor, Inc.
- */
-
-/*
- * mpc8536ds board configuration file
- *
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <linux/stringify.h>
-
-#include "../board/freescale/common/ics307_clk.h"
-
-#ifdef CONFIG_SDCARD
-#define CONFIG_RAMBOOT_SDCARD 1
-#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
-#endif
-
-#ifdef CONFIG_SPIFLASH
-#define CONFIG_RAMBOOT_SPIFLASH 1
-#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
-#endif
-
-#ifndef CONFIG_RESET_VECTOR_ADDRESS
-#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
-#endif
-
-#ifndef CONFIG_SYS_MONITOR_BASE
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-#endif
-
-#define CONFIG_PCI1 1 /* Enable PCI controller 1 */
-#define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */
-#define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */
-#define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */
-#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
-#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
-#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
-
-
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
-#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
-#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
-
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_L2_CACHE /* toggle L2 cache */
-#define CONFIG_BTB /* toggle branch predition */
-
-#define CONFIG_ENABLE_36BIT_PHYS 1
-
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_ADDR_MAP 1
-#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
-#endif
-
-/*
- * Config the L2 Cache as L2 SRAM
- */
-#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
-#else
-#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
-#endif
-#define CONFIG_SYS_L2_SIZE (512 << 10)
-#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
-
-#define CONFIG_SYS_CCSRBAR 0xffe00000
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
-
-#if defined(CONFIG_NAND_SPL)
-#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
-#endif
-
-/* DDR Setup */
-#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
-#define CONFIG_DDR_SPD
-
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
-#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
-
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_CHIP_SELECTS_PER_CTRL 2
-
-/* I2C addresses of SPD EEPROMs */
-#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
-#define CONFIG_SYS_SPD_BUS_NUM 1
-
-/* These are used when DDR doesn't use SPD. */
-#define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */
-#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F
-#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */
-#define CONFIG_SYS_DDR_TIMING_3 0x00000000
-#define CONFIG_SYS_DDR_TIMING_0 0x00260802
-#define CONFIG_SYS_DDR_TIMING_1 0x3935d322
-#define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
-#define CONFIG_SYS_DDR_MODE_1 0x00480432
-#define CONFIG_SYS_DDR_MODE_2 0x00000000
-#define CONFIG_SYS_DDR_INTERVAL 0x06180100
-#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
-#define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
-#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
-#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
-#define CONFIG_SYS_DDR_CONTROL 0xC3008000 /* Type = DDR2 */
-#define CONFIG_SYS_DDR_CONTROL2 0x04400010
-
-#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
-#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
-#define CONFIG_SYS_DDR_SBE 0x00010000
-
-/* Make sure required options are set */
-#ifndef CONFIG_SPD_EEPROM
-#error ("CONFIG_SPD_EEPROM is required")
-#endif
-
-#undef CONFIG_CLOCKS_IN_MHZ
-
-/*
- * Memory map -- xxx -this is wrong, needs updating
- *
- * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
- * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
- * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
- * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
- *
- * Localbus cacheable (TBD)
- * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
- *
- * Localbus non-cacheable
- * 0xe000_0000 0xe7ff_ffff Promjet/free 128M non-cacheable
- * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
- * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
- * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
- * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
- * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
- */
-
-/*
- * Local Bus Definitions
- */
-#define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
-#else
-#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
-#endif
-
-#define CONFIG_FLASH_BR_PRELIM \
- (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V)
-#define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
-
-#define CONFIG_SYS_BR1_PRELIM \
- (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
- | BR_PS_16 | BR_V)
-#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
-
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, \
- CONFIG_SYS_FLASH_BASE_PHYS }
-#define CONFIG_SYS_FLASH_QUIET_TEST
-#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
-#undef CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-
-#if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
-#define CONFIG_SYS_RAMBOOT
-#else
-#undef CONFIG_SYS_RAMBOOT
-#endif
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
-
-#define CONFIG_HWCONFIG /* enable hwconfig */
-#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
-#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
-#ifdef CONFIG_PHYS_64BIT
-#define PIXIS_BASE_PHYS 0xfffdf0000ull
-#else
-#define PIXIS_BASE_PHYS PIXIS_BASE
-#endif
-
-#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
-#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
-
-#define PIXIS_ID 0x0 /* Board ID at offset 0 */
-#define PIXIS_VER 0x1 /* Board version at offset 1 */
-#define PIXIS_PVER 0x2 /* PIXIS FPGA version@offset 2 */
-#define PIXIS_CSR 0x3 /* PIXIS General control/status register */
-#define PIXIS_RST 0x4 /* PIXIS Reset Control register */
-#define PIXIS_PWR 0x5 /* PIXIS Power status register */
-#define PIXIS_AUX 0x6 /* Auxiliary 1 register */
-#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
-#define PIXIS_AUX2 0x8 /* Auxiliary 2 register */
-#define PIXIS_VCTL 0x10 /* VELA Control Register */
-#define PIXIS_VSTAT 0x11 /* VELA Status Register */
-#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
-#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
-#define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */
-#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
-#define PIXIS_VBOOT_LBMAP 0xe0 /* VBOOT - CFG_LBMAP */
-#define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */
-#define PIXIS_VBOOT_LBMAP_NOR1 0x01 /* cfg_lbmap - boot from NOR 1 */
-#define PIXIS_VBOOT_LBMAP_NOR2 0x02 /* cfg_lbmap - boot from NOR 2 */
-#define PIXIS_VBOOT_LBMAP_NOR3 0x03 /* cfg_lbmap - boot from NOR 3 */
-#define PIXIS_VBOOT_LBMAP_PJET 0x04 /* cfg_lbmap - boot from projet */
-#define PIXIS_VBOOT_LBMAP_NAND 0x05 /* cfg_lbmap - boot from NAND */
-#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
-#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
-#define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */
-#define PIXIS_VSYSCLK0 0x1A /* VELA SYSCLK0 Register */
-#define PIXIS_VSYSCLK1 0x1B /* VELA SYSCLK1 Register */
-#define PIXIS_VSYSCLK2 0x1C /* VELA SYSCLK2 Register */
-#define PIXIS_VDDRCLK0 0x1D /* VELA DDRCLK0 Register */
-#define PIXIS_VDDRCLK1 0x1E /* VELA DDRCLK1 Register */
-#define PIXIS_VDDRCLK2 0x1F /* VELA DDRCLK2 Register */
-#define PIXIS_VWATCH 0x24 /* Watchdog Register */
-#define PIXIS_LED 0x25 /* LED Register */
-
-#define PIXIS_SPD_SYSCLK 0x7 /* SYSCLK option */
-
-/* old pixis referenced names */
-#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
-#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
-#define CONFIG_SYS_PIXIS_VBOOT_MASK 0x4e
-
-#define CONFIG_SYS_INIT_RAM_LOCK 1
-#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
-
-#ifndef CONFIG_NAND_SPL
-#define CONFIG_SYS_NAND_BASE 0xffa00000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
-#else
-#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
-#endif
-#else
-#define CONFIG_SYS_NAND_BASE 0xfff00000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull
-#else
-#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
-#endif
-#endif
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\
- CONFIG_SYS_NAND_BASE + 0x40000, \
- CONFIG_SYS_NAND_BASE + 0x80000, \
- CONFIG_SYS_NAND_BASE + 0xC0000}
-#define CONFIG_SYS_MAX_NAND_DEVICE 4
-#define CONFIG_NAND_FSL_ELBC 1
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
-
-/* NAND boot: 4K NAND loader config */
-#define CONFIG_SYS_NAND_SPL_SIZE 0x1000
-#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
-#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
-#define CONFIG_SYS_NAND_U_BOOT_START \
- (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
-#define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
-#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
-#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
-
-/* NAND flash config */
-#define CONFIG_SYS_NAND_BR_PRELIM \
- (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
- | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
- | BR_PS_8 /* Port Size = 8 bit */ \
- | BR_MS_FCM /* MSEL = FCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
- | OR_FCM_PGS /* Large Page*/ \
- | OR_FCM_CSCT \
- | OR_FCM_CST \
- | OR_FCM_CHT \
- | OR_FCM_SCY_1 \
- | OR_FCM_TRLX \
- | OR_FCM_EHTR)
-
-#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
-#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
-#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
-#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-
-#define CONFIG_SYS_BR4_PRELIM \
- (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \
- | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
- | BR_PS_8 /* Port Size = 8 bit */ \
- | BR_MS_FCM /* MSEL = FCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-#define CONFIG_SYS_BR5_PRELIM \
- (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000) \
- | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
- | BR_PS_8 /* Port Size = 8 bit */ \
- | BR_MS_FCM /* MSEL = FCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-
-#define CONFIG_SYS_BR6_PRELIM \
- (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000) \
- | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
- | BR_PS_8 /* Port Size = 8 bit */ \
- | BR_MS_FCM /* MSEL = FCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-
-/* Serial Port - controlled on board with jumper J8
- * open - index 2
- * shorted - index 1
- */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-#ifdef CONFIG_NAND_SPL
-#define CONFIG_NS16550_MIN_FUNCTIONS
-#endif
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
-
-/*
- * I2C
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-#define CONFIG_SYS_FSL_I2C2_SPEED 400000
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
-
-/*
- * I2C2 EEPROM
- */
-#define CONFIG_ID_EEPROM
-#ifdef CONFIG_ID_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#endif
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_BUS_NUM 1
-
-/*
- * General PCI
- * Memory space is mapped 1-1, but I/O space must start from 0.
- */
-
-#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCI1_MEM_BUS 0xf0000000
-#define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull
-#else
-#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
-#endif
-#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000
-#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCI1_IO_PHYS 0xfffc00000ull
-#else
-#define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000
-#endif
-#define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */
-
-/* controller 1, Slot 1, tgtid 1, Base address a000 */
-#define CONFIG_SYS_PCIE1_NAME "Slot 1"
-#define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xf8000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc10000000ull
-#else
-#define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000
-#endif
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x08000000 /* 128M */
-#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc10000
-#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc10000ull
-#else
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc10000
-#endif
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
-
-/* controller 2, Slot 2, tgtid 2, Base address 9000 */
-#define CONFIG_SYS_PCIE2_NAME "Slot 2"
-#define CONFIG_SYS_PCIE2_MEM_VIRT 0x98000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xf8000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc18000000ull
-#else
-#define CONFIG_SYS_PCIE2_MEM_BUS 0x98000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS 0x98000000
-#endif
-#define CONFIG_SYS_PCIE2_MEM_SIZE 0x08000000 /* 128M */
-#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000
-#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc20000ull
-#else
-#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000
-#endif
-#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
-
-/* controller 3, direct to uli, tgtid 3, Base address 8000 */
-#define CONFIG_SYS_PCIE3_NAME "Slot 3"
-#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
-#else
-#define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000
-#endif
-#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc30000
-#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc30000ull
-#else
-#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc30000
-#endif
-#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
-
-#if defined(CONFIG_PCI)
-/*PCIE video card used*/
-#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE3_IO_VIRT
-
-/*PCI video card used*/
-/*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/
-
-/* video */
-
-#if defined(CONFIG_VIDEO)
-#define CONFIG_BIOSEMU
-#define CONFIG_ATI_RADEON_FB
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_VIRT
-#endif
-
-#undef CONFIG_EEPRO100
-#undef CONFIG_TULIP
-
-#ifndef CONFIG_PCI_PNP
- #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS
- #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS
- #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
-#endif
-
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-
-#endif /* CONFIG_PCI */
-
-/* SATA */
-#define CONFIG_SYS_SATA_MAX_DEVICE 2
-#define CONFIG_SATA1
-#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
-#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
-#define CONFIG_SATA2
-#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
-#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
-
-#ifdef CONFIG_FSL_SATA
-#define CONFIG_LBA48
-#endif
-
-#if defined(CONFIG_TSEC_ENET)
-
-#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
-#define CONFIG_TSEC1 1
-#define CONFIG_TSEC1_NAME "eTSEC1"
-#define CONFIG_TSEC3 1
-#define CONFIG_TSEC3_NAME "eTSEC3"
-
-#define CONFIG_FSL_SGMII_RISER 1
-#define SGMII_RISER_PHY_OFFSET 0x1c
-
-#define TSEC1_PHY_ADDR 1 /* TSEC1 -> PHY1 */
-#define TSEC3_PHY_ADDR 0 /* TSEC3 -> PHY0 */
-
-#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-
-#define TSEC1_PHYIDX 0
-#define TSEC3_PHYIDX 0
-
-#define CONFIG_ETHPRIME "eTSEC1"
-
-#endif /* CONFIG_TSEC_ENET */
-
-/*
- * Environment
- */
-
-#if defined(CONFIG_SYS_RAMBOOT)
-#if defined(CONFIG_RAMBOOT_SPIFLASH)
-#elif defined(CONFIG_RAMBOOT_SDCARD)
-#define CONFIG_FSL_FIXED_MMC_LOCATION
-#define CONFIG_SYS_MMC_ENV_DEV 0
-#endif
-#endif
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
-#endif
-
-/*
- * USB
- */
-#define CONFIG_HAS_FSL_MPH_USB
-#ifdef CONFIG_HAS_FSL_MPH_USB
-#ifdef CONFIG_USB_EHCI_HCD
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_USB_EHCI_FSL
-#endif
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 64 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
-#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-
-/* The mac addresses for all ethernet interface */
-#if defined(CONFIG_TSEC_ENET)
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#define CONFIG_HAS_ETH2
-#define CONFIG_HAS_ETH3
-#endif
-
-#define CONFIG_IPADDR 192.168.1.254
-
-#define CONFIG_HOSTNAME "unknown"
-#define CONFIG_ROOTPATH "/opt/nfsroot"
-#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
-
-#define CONFIG_SERVERIP 192.168.1.1
-#define CONFIG_GATEWAYIP 192.168.1.1
-#define CONFIG_NETMASK 255.255.255.0
-
-/* default location for tftp and bootm */
-#define CONFIG_LOADADDR 1000000
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
-"netdev=eth0\0" \
-"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
-"tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
- " +$filesize; " \
- "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
- " +$filesize; " \
- "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
- " $filesize; " \
- "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
- " +$filesize; " \
- "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
- " $filesize\0" \
-"consoledev=ttyS0\0" \
-"ramdiskaddr=2000000\0" \
-"ramdiskfile=8536ds/ramdisk.uboot\0" \
-"fdtaddr=1e00000\0" \
-"fdtfile=8536ds/mpc8536ds.dtb\0" \
-"bdev=sda3\0" \
-"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
-
-#define CONFIG_HDBOOT \
- "setenv bootargs root=/dev/$bdev rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
-
-#endif /* __CONFIG_H */
--
2.25.1
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 07/24] arm: Remove configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig board
2020-05-27 16:46 [PATCH 00/24] spi: dm-conversion (part2) Jagan Teki
` (5 preceding siblings ...)
2020-05-27 16:46 ` [PATCH 06/24] arm: Remove configs/MPC8536DS_36BIT_defconfig board Jagan Teki
@ 2020-05-27 16:46 ` Jagan Teki
2020-05-28 7:05 ` Priyanka Jain
2020-05-27 16:46 ` [PATCH 08/24] arm: Remove configs/P1020MBG-PC_36BIT_SDCARD_defconfig board Jagan Teki
` (15 subsequent siblings)
22 siblings, 1 reply; 59+ messages in thread
From: Jagan Teki @ 2020-05-27 16:46 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_SPI by the deadline.
Remove it.
Patch-cc: Qiang Zhao <qiang.zhao@nxp.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
arch/powerpc/cpu/mpc85xx/Kconfig | 1 -
board/freescale/p1010rdb/Kconfig | 14 -
board/freescale/p1010rdb/MAINTAINERS | 33 -
board/freescale/p1010rdb/Makefile | 24 -
board/freescale/p1010rdb/README.P1010RDB-PA | 208 -----
board/freescale/p1010rdb/README.P1010RDB-PB | 188 -----
board/freescale/p1010rdb/ddr.c | 235 ------
board/freescale/p1010rdb/law.c | 16 -
board/freescale/p1010rdb/p1010rdb.c | 731 -----------------
board/freescale/p1010rdb/spl.c | 114 ---
board/freescale/p1010rdb/spl_minimal.c | 65 --
board/freescale/p1010rdb/tlb.c | 90 --
.../P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig | 63 --
configs/P1010RDB-PA_36BIT_NAND_defconfig | 85 --
.../P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig | 62 --
configs/P1010RDB-PA_36BIT_NOR_defconfig | 67 --
configs/P1010RDB-PA_36BIT_SDCARD_defconfig | 79 --
...010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig | 64 --
configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig | 81 --
configs/P1010RDB-PA_NAND_SECBOOT_defconfig | 62 --
configs/P1010RDB-PA_NAND_defconfig | 84 --
configs/P1010RDB-PA_NOR_SECBOOT_defconfig | 60 --
configs/P1010RDB-PA_NOR_defconfig | 66 --
configs/P1010RDB-PA_SDCARD_defconfig | 78 --
.../P1010RDB-PA_SPIFLASH_SECBOOT_defconfig | 63 --
configs/P1010RDB-PA_SPIFLASH_defconfig | 80 --
.../P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig | 63 --
configs/P1010RDB-PB_36BIT_NAND_defconfig | 85 --
.../P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig | 62 --
configs/P1010RDB-PB_36BIT_NOR_defconfig | 67 --
configs/P1010RDB-PB_36BIT_SDCARD_defconfig | 79 --
...010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig | 64 --
configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig | 81 --
configs/P1010RDB-PB_NAND_SECBOOT_defconfig | 62 --
configs/P1010RDB-PB_NAND_defconfig | 84 --
configs/P1010RDB-PB_NOR_SECBOOT_defconfig | 61 --
configs/P1010RDB-PB_NOR_defconfig | 66 --
configs/P1010RDB-PB_SDCARD_defconfig | 78 --
.../P1010RDB-PB_SPIFLASH_SECBOOT_defconfig | 63 --
configs/P1010RDB-PB_SPIFLASH_defconfig | 80 --
include/configs/P1010RDB.h | 766 ------------------
41 files changed, 4474 deletions(-)
delete mode 100644 board/freescale/p1010rdb/Kconfig
delete mode 100644 board/freescale/p1010rdb/MAINTAINERS
delete mode 100644 board/freescale/p1010rdb/Makefile
delete mode 100644 board/freescale/p1010rdb/README.P1010RDB-PA
delete mode 100644 board/freescale/p1010rdb/README.P1010RDB-PB
delete mode 100644 board/freescale/p1010rdb/ddr.c
delete mode 100644 board/freescale/p1010rdb/law.c
delete mode 100644 board/freescale/p1010rdb/p1010rdb.c
delete mode 100644 board/freescale/p1010rdb/spl.c
delete mode 100644 board/freescale/p1010rdb/spl_minimal.c
delete mode 100644 board/freescale/p1010rdb/tlb.c
delete mode 100644 configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig
delete mode 100644 configs/P1010RDB-PA_36BIT_NAND_defconfig
delete mode 100644 configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig
delete mode 100644 configs/P1010RDB-PA_36BIT_NOR_defconfig
delete mode 100644 configs/P1010RDB-PA_36BIT_SDCARD_defconfig
delete mode 100644 configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig
delete mode 100644 configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
delete mode 100644 configs/P1010RDB-PA_NAND_SECBOOT_defconfig
delete mode 100644 configs/P1010RDB-PA_NAND_defconfig
delete mode 100644 configs/P1010RDB-PA_NOR_SECBOOT_defconfig
delete mode 100644 configs/P1010RDB-PA_NOR_defconfig
delete mode 100644 configs/P1010RDB-PA_SDCARD_defconfig
delete mode 100644 configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig
delete mode 100644 configs/P1010RDB-PA_SPIFLASH_defconfig
delete mode 100644 configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig
delete mode 100644 configs/P1010RDB-PB_36BIT_NAND_defconfig
delete mode 100644 configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig
delete mode 100644 configs/P1010RDB-PB_36BIT_NOR_defconfig
delete mode 100644 configs/P1010RDB-PB_36BIT_SDCARD_defconfig
delete mode 100644 configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig
delete mode 100644 configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
delete mode 100644 configs/P1010RDB-PB_NAND_SECBOOT_defconfig
delete mode 100644 configs/P1010RDB-PB_NAND_defconfig
delete mode 100644 configs/P1010RDB-PB_NOR_SECBOOT_defconfig
delete mode 100644 configs/P1010RDB-PB_NOR_defconfig
delete mode 100644 configs/P1010RDB-PB_SDCARD_defconfig
delete mode 100644 configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig
delete mode 100644 configs/P1010RDB-PB_SPIFLASH_defconfig
delete mode 100644 include/configs/P1010RDB.h
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 1842d71f24..ece589ba90 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -1597,7 +1597,6 @@ source "board/freescale/mpc8555cds/Kconfig"
source "board/freescale/mpc8568mds/Kconfig"
source "board/freescale/mpc8569mds/Kconfig"
source "board/freescale/mpc8572ds/Kconfig"
-source "board/freescale/p1010rdb/Kconfig"
source "board/freescale/p1022ds/Kconfig"
source "board/freescale/p1023rdb/Kconfig"
source "board/freescale/p1_p2_rdb_pc/Kconfig"
diff --git a/board/freescale/p1010rdb/Kconfig b/board/freescale/p1010rdb/Kconfig
deleted file mode 100644
index 3adac4af1e..0000000000
--- a/board/freescale/p1010rdb/Kconfig
+++ /dev/null
@@ -1,14 +0,0 @@
-if TARGET_P1010RDB_PA || TARGET_P1010RDB_PB
-
-config SYS_BOARD
- default "p1010rdb"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "P1010RDB"
-
-source "board/freescale/common/Kconfig"
-
-endif
diff --git a/board/freescale/p1010rdb/MAINTAINERS b/board/freescale/p1010rdb/MAINTAINERS
deleted file mode 100644
index c9f7fa3e2a..0000000000
--- a/board/freescale/p1010rdb/MAINTAINERS
+++ /dev/null
@@ -1,33 +0,0 @@
-P1010RDB BOARD
-M: Qiang Zhao <qiang.zhao@nxp.com>
-S: Maintained
-F: board/freescale/p1010rdb/
-F: include/configs/P1010RDB.h
-F: configs/P1010RDB-PA_36BIT_NAND_defconfig
-F: configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig
-F: configs/P1010RDB-PA_36BIT_NOR_defconfig
-F: configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig
-F: configs/P1010RDB-PA_36BIT_SDCARD_defconfig
-F: configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
-F: configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig
-F: configs/P1010RDB-PA_NAND_defconfig
-F: configs/P1010RDB-PA_NAND_SECBOOT_defconfig
-F: configs/P1010RDB-PA_NOR_defconfig
-F: configs/P1010RDB-PA_NOR_SECBOOT_defconfig
-F: configs/P1010RDB-PA_SDCARD_defconfig
-F: configs/P1010RDB-PA_SPIFLASH_defconfig
-F: configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig
-F: configs/P1010RDB-PB_36BIT_NAND_defconfig
-F: configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig
-F: configs/P1010RDB-PB_36BIT_NOR_defconfig
-F: configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig
-F: configs/P1010RDB-PB_36BIT_SDCARD_defconfig
-F: configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
-F: configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig
-F: configs/P1010RDB-PB_NAND_defconfig
-F: configs/P1010RDB-PB_NAND_SECBOOT_defconfig
-F: configs/P1010RDB-PB_NOR_defconfig
-F: configs/P1010RDB-PB_NOR_SECBOOT_defconfig
-F: configs/P1010RDB-PB_SDCARD_defconfig
-F: configs/P1010RDB-PB_SPIFLASH_defconfig
-F: configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig
diff --git a/board/freescale/p1010rdb/Makefile b/board/freescale/p1010rdb/Makefile
deleted file mode 100644
index 36b34c70aa..0000000000
--- a/board/freescale/p1010rdb/Makefile
+++ /dev/null
@@ -1,24 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2010-2011 Freescale Semiconductor, Inc.
-
-MINIMAL=
-
-ifdef CONFIG_SPL_BUILD
-ifdef CONFIG_SPL_INIT_MINIMAL
-MINIMAL=y
-endif
-endif
-
-ifdef MINIMAL
-obj-y += spl_minimal.o
-else
-ifdef CONFIG_SPL_BUILD
-obj-y += spl.o
-endif
-obj-y += p1010rdb.o
-obj-y += ddr.o
-endif
-
-obj-y += law.o
-obj-y += tlb.o
diff --git a/board/freescale/p1010rdb/README.P1010RDB-PA b/board/freescale/p1010rdb/README.P1010RDB-PA
deleted file mode 100644
index 105942f7a5..0000000000
--- a/board/freescale/p1010rdb/README.P1010RDB-PA
+++ /dev/null
@@ -1,208 +0,0 @@
-Overview
-=========
-The P1010RDB is a Freescale reference design board that hosts the P1010 SoC.
-
-The P1010 is a cost-effective, low-power, highly integrated host processor
-based on a Power Architecture e500v2 core (maximum core frequency 800/1000 MHz),
-that addresses the requirements of several routing, gateways, storage, consumer,
-and industrial applications. Applications of interest include the main CPUs and
-I/O processors in network attached storage (NAS), the voice over IP (VoIP)
-router/gateway, and wireless LAN (WLAN) and industrial controllers.
-
-The P1010RDB board features are as follows:
-Memory subsystem:
- - 1Gbyte unbuffered DDR3 SDRAM discrete devices (32-bit bus)
- - 32 Mbyte NOR flash single-chip memory
- - 32 Mbyte NAND flash memory
- - 256 Kbit M24256 I2C EEPROM
- - 16 Mbyte SPI memory
- - I2C Board EEPROM 128x8 bit memory
- - SD/MMC connector to interface with the SD memory card
-Interfaces:
- - PCIe:
- - Lane0: x1 mini-PCIe slot
- - Lane1: x1 PCIe standard slot
- - SATA:
- - 1 internal SATA connector to 2.5? 160G SATA2 HDD
- - 1 eSATA connector to rear panel
- - 10/100/1000 BaseT Ethernet ports:
- - eTSEC1, RGMII: one 10/100/1000 port using Vitesse VSC8641XKO
- - eTSEC2, SGMII: one 10/100/1000 port using Vitesse VSC8221
- - eTSEC3, SGMII: one 10/100/1000 port using Vitesse VSC8221
- - USB 2.0 port:
- - x1 USB2.0 port via an external ULPI PHY to micro-AB connector
- - x1 USB2.0 port via an internal UTMI PHY to micro-AB connector
- - FlexCAN ports:
- - 2 DB-9 female connectors for FlexCAN bus(revision 2.0B)
- interface;
- - DUART interface:
- - DUART interface: supports two UARTs up to 115200 bps for
- console display
- - RJ45 connectors are used for these 2 UART ports.
- - TDM
- - 2 FXS ports connected via an external SLIC to the TDM interface.
- SLIC is controllled via SPI.
- - 1 FXO port connected via a relay to FXS for switchover to POTS
-Board connectors:
- - Mini-ITX power supply connector
- - JTAG/COP for debugging
-IEEE Std. 1588 signals for test and measurement
-Real-time clock on I2C bus
-POR
- - support critical POR setting changed via switch on board
-PCB
- - 6-layer routing (4-layer signals, 2-layer power and ground)
-
-
-Physical Memory Map on P1010RDB
-===============================
-Address Start Address End Memory type Attributes
-0x0000_0000 0x3fff_ffff DDR 1G Cacheable
-0xa000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable
-0xee00_0000 0xefff_ffff NOR Flash 32M non-cacheable
-0xffc2_0000 0xffc5_ffff PCI IO range 256K non-cacheable
-0xffa0_0000 0xffaf_ffff NAND Flash 1M cacheable
-0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable
-0xffd0_0000 0xffd0_3fff L1 for Stack 16K Cacheable TLB0
-0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
-
-
-Serial Port Configuration on P1010RDB
-=====================================
-Configure the serial port of the attached computer with the following values:
- -Data rate: 115200 bps
- -Number of data bits: 8
- -Parity: None
- -Number of Stop bits: 1
- -Flow Control: Hardware/None
-
-
-Settings of DIP-switch
-======================
- SW4[1:4]= 1111 and SW6[4]=0 for boot from 16bit NOR flash
- SW4[1:4]= 1000 and SW6[4]=1 for boot from 8bit NAND flash
- SW4[1:4]= 0110 and SW6[4]=0 for boot from SPI flash
-Note: 1 stands for 'on', 0 stands for 'off'
-
-
-Setting of hwconfig
-===================
-If FlexCAN or TDM is needed, please set "fsl_p1010mux:tdm_can=can" or
-"fsl_p1010mux:tdm_can=tdm" explicitly in u-booot prompt as below for example:
-setenv hwconfig "fsl_p1010mux:tdm_can=tdm;usb1:dr_mode=host,phy_type=utmi"
-By default, don't set fsl_p1010mux:tdm_can, in this case, spi chip selection
-is set to spi-flash instead of to SLIC/TDM/DAC and tdm_can_sel is set to TDM
-instead of to CAN/UART1.
-
-
-Build and burn U-Boot to NOR flash
-==================================
-1. Build u-boot.bin image
- export ARCH=powerpc
- export CROSS_COMPILE=/your_path/powerpc-linux-gnu-
- make P1010RDB_NOR
-
-2. Burn u-boot.bin into NOR flash
- => tftp $loadaddr $uboot
- => protect off eff40000 +$filesize
- => erase eff40000 +$filesize
- => cp.b $loadaddr eff40000 $filesize
-
-3. Check SW4[1:4]= 1111 and SW6[4]=0, then power on.
-
-
-Alternate NOR bank
-==================
-1. Burn u-boot.bin into alternate NOR bank
- => tftp $loadaddr $uboot
- => protect off eef40000 +$filesize
- => erase eef40000 +$filesize
- => cp.b $loadaddr eef40000 $filesize
-
-2. Switch to alternate NOR bank
- => mw.b ffb00009 1
- => reset
- or set SW1[8]= ON
-
-SW1[8]= OFF: Upper bank used for booting start
-SW1[8]= ON: Lower bank used for booting start
-CPLD NOR bank selection register address 0xFFB00009 Bit[0]:
-0 - boot from upper 4 sectors
-1 - boot from lower 4 sectors
-
-
-Build and burn U-Boot to NAND flash
-===================================
-1. Build u-boot.bin image
- export ARCH=powerpc
- export CROSS_COMPILE=/your_path/powerpc-linux-gnu-
- make P1010RDB_NAND
-
-2. Burn u-boot-nand.bin into NAND flash
- => tftp $loadaddr $uboot-nand
- => nand erase 0 $filesize
- => nand write $loadaddr 0 $filesize
-
-3. Check SW4[1:4]= 1000 and SW6[4]=1, then power on.
-
-
-Build and burn U-Boot to SPI flash
-==================================
-1. Build u-boot-spi.bin image
- make P1010RDB_SPIFLASH_config; make
- Boot up kernel with rootfs.ext2.gz.uboot.p1010rdb
- Download u-boot.bin to linux and you can find some config files
- under /usr/share such as config_xx.dat. Do below command:
- boot_format config_ddr3_1gb_p1010rdb_800M.dat u-boot.bin -spi \
- u-boot-spi.bin
- to generate u-boot-spi.bin.
-
-2. Burn u-boot-spi.bin into SPI flash
- => tftp $loadaddr $uboot-spi
- => sf erase 0 100000
- => sf write $loadaddr 0 $filesize
-
-3. Check SW4[1:4]= 0110 and SW6[4]=0, then power on.
-
-
-CPLD POR setting registers
-==========================
-1. Set POR switch selection register (addr 0xFFB00011) to 0.
-2. Write CPLD POR registers (BCSR0~BCSR3, addr 0xFFB00014~0xFFB00017) with
- proper values.
- If change boot ROM location to NOR or NAND flash, need write the IFC_CS0
- switch command by I2C.
-3. Send reset command.
- After reset, the new POR setting will be implemented.
-
-Two examples are given in below:
-Switch from NOR to NAND boot with default frequency:
- => i2c dev 0
- => i2c mw 18 1 f9
- => i2c mw 18 3 f0
- => mw.b ffb00011 0
- => mw.b ffb00017 1
- => reset
-Switch from NAND to NOR boot with Core/CCB/DDR (800/400/667 MHz):
- => i2c dev 0
- => i2c mw 18 1 f1
- => i2c mw 18 3 f0
- => mw.b ffb00011 0
- => mw.b ffb00014 2
- => mw.b ffb00015 5
- => mw.b ffb00016 3
- => mw.b ffb00017 f
- => reset
-
-
-Boot Linux from network using TFTP on P1010RDB
-==============================================
-Place uImage, p1010rdb.dtb and rootfs files in the TFTP disk area.
- => tftp 1000000 uImage
- => tftp 2000000 p1010rdb.dtb
- => tftp 3000000 rootfs.ext2.gz.uboot.p1010rdb
- => bootm 1000000 3000000 2000000
-
-
-For more details, please refer to P1010RDB User Guide and access website
-www.freescale.com
diff --git a/board/freescale/p1010rdb/README.P1010RDB-PB b/board/freescale/p1010rdb/README.P1010RDB-PB
deleted file mode 100644
index dc82f0df09..0000000000
--- a/board/freescale/p1010rdb/README.P1010RDB-PB
+++ /dev/null
@@ -1,188 +0,0 @@
-Overview
-=========
-The P1010RDB-PB is a Freescale Reference Design Board that hosts the P1010 SoC.
-P1010RDB-PB is a variation of previous P1010RDB-PA board.
-
-The P1010 is a cost-effective, low-power, highly integrated host processor
-based on a Power Architecture e500v2 core (maximum core frequency 1GHz),that
-addresses the requirements of several routing, gateways, storage, consumer,
-and industrial applications. Applications of interest include the main CPUs and
-I/O processors in network attached storage (NAS), the voice over IP (VoIP)
-router/gateway, and wireless LAN (WLAN) and industrial controllers.
-
-The P1010RDB-PB board features are as following:
-Memory subsystem:
- - 1G bytes unbuffered DDR3 SDRAM discrete devices (32-bit bus)
- - 32M bytes NOR flash single-chip memory
- - 2G bytes NAND flash memory
- - 16M bytes SPI memory
- - 256K bit M24256 I2C EEPROM
- - I2C Board EEPROM 128x8 bit memory
- - SD/MMC connector to interface with the SD memory card
-Interfaces:
- - Three 10/100/1000 BaseT Ethernet ports (One RGMII and two SGMII)
- - PCIe 2.0: two x1 mini-PCIe slots
- - SATA 2.0: two SATA interfaces
- - USB 2.0: one USB interface
- - FlexCAN: two FlexCAN interfaces (revision 2.0B)
- - UART: one USB-to-Serial interface
- - TDM: 2 FXS ports connected via an external SLIC to the TDM interface.
- 1 FXO port connected via a relay to FXS for switchover to POTS
-
-Board connectors:
- - Mini-ITX power supply connector
- - JTAG/COP for debugging
-
-POR: support critical POR setting changed via switch on board
-PCB: 6-layer routing (4-layer signals, 2-layer power and ground)
-
-Physical Memory Map on P1010RDB
-===============================
-Address Start Address End Memory type Attributes
-0x0000_0000 0x3fff_ffff DDR 1G Cacheable
-0xa000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable
-0xee00_0000 0xefff_ffff NOR Flash 32M non-cacheable
-0xffc2_0000 0xffc5_ffff PCI IO range 256K non-cacheable
-0xffa0_0000 0xffaf_ffff NAND Flash 1M cacheable
-0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable
-0xffd0_0000 0xffd0_3fff L1 for Stack 16K Cacheable TLB0
-0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
-
-
-Serial Port Configuration on P1010RDB
-=====================================
-Configure the serial port of the attached computer with the following values:
- -Data rate: 115200 bps
- -Number of data bits: 8
- -Parity: None
- -Number of Stop bits: 1
- -Flow Control: Hardware/None
-
-
-P1010RDB-PB default DIP-switch settings
-=======================================
-SW1[1:8]= 10101010
-SW2[1:8]= 11011000
-SW3[1:8]= 10010000
-SW4[1:4]= 1010
-SW5[1:8]= 11111010
-
-
-P1010RDB-PB boot mode settings via DIP-switch
-=============================================
-SW4[1:4]= 1111 and SW3[3:4]= 00 for 16bit NOR boot
-SW4[1:4]= 1010 and SW3[3:4]= 01 for 8bit NAND boot
-SW4[1:4]= 0110 and SW3[3:4]= 00 for SPI boot
-SW4[1:4]= 0111 and SW3[3:4]= 10 for SD boot
-Note: 1 stands for 'on', 0 stands for 'off'
-
-
-Switch P1010RDB-PB boot mode via software without setting DIP-switch
-====================================================================
-=> run boot_bank0 (boot from NOR bank0)
-=> run boot_bank1 (boot from NOR bank1)
-=> run boot_nand (boot from NAND flash)
-=> run boot_spi (boot from SPI flash)
-=> run boot_sd (boot from SD card)
-
-
-Frequency combination support on P1010RDB-PB
-=============================================
-SW1[4:7] SW5[1] SW5[5:8] SW2[2] Core(MHz) Platform(MHz) DDR(MT/s)
-0101 1 1010 0 800 400 800
-1001 1 1010 0 800 400 667
-1010 1 1100 0 667 333 667
-1000 0 1010 0 533 266 667
-0101 1 1010 1 1000 400 800
-1001 1 1010 1 1000 400 667
-
-
-Setting of pin mux
-==================
-Since pins multiplexing, TDM and CAN are muxed with SPI flash.
-SDHC is muxed with IFC. IFC and SPI flash are enabled by default.
-
-To enable TDM:
-=> setenv hwconfig fsl_p1010mux:tdm_can=tdm
-=> save;reset
-
-To enable FlexCAN:
-=> setenv hwconfig fsl_p1010mux:tdm_can=can
-=> save;reset
-
-To enable SDHC in case of NOR/NAND/SPI boot
- a) For temporary use case in runtime without reboot system
- run 'mux sdhc' in U-Boot to validate SDHC with invalidating IFC.
-
- b) For long-term use case
- set 'esdhc' in hwconfig and save it.
-
-To enable IFC in case of SD boot
- a) For temporary use case in runtime without reboot system
- run 'mux ifc' in U-Boot to validate IFC with invalidating SDHC.
-
- b) For long-term use case
- set 'ifc' in hwconfig and save it.
-
-
-Build images for different boot mode
-====================================
-First setup cross compile environment on build host
- $ export ARCH=powerpc
- $ export CROSS_COMPILE=<your-compiler-path>/powerpc-linux-gnu-
-
-1. For NOR boot
- $ make P1010RDB-PB_NOR
-
-2. For NAND boot
- $ make P1010RDB-PB_NAND
-
-3. For SPI boot
- $ make P1010RDB-PB_SPIFLASH
-
-4. For SD boot
- $ make P1010RDB-PB_SDCARD
-
-
-Steps to program images to flash for different boot mode
-========================================================
-1. NOR boot
- => tftp 1000000 u-boot.bin
- For bank0
- => pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize
- set SW1[8]=0, SW4[1:4]= 1111 and SW3[3:4]= 00, then power on the board
-
- For bank1
- => pro off all;era eef40000 eeffffff;cp.b 1000000 eef40000 $filesize
- set SW1[8]=1, SW4[1:4]= 1111 and SW3[3:4]= 00, then power on the board
-
-2. NAND boot
- => tftp 1000000 u-boot-nand.bin
- => nand erase 0 $filesize; nand write $loadaddr 0 $filesize
- Set SW4[1:4]= 1010 and SW3[3:4]= 01, then power on the board
-
-3. SPI boot
- 1) cat p1010rdb-config-header.bin u-boot.bin > u-boot-spi-combined.bin
- 2) => tftp 1000000 u-boot-spi-combined.bin
- 3) => sf probe 0; sf erase 0 100000; sf write 1000000 0 100000
- set SW4[1:4]= 0110 and SW3[3:4]= 00, then power on the board
-
-4. SD boot
- 1) cat p1010rdb-config-header.bin u-boot.bin > u-boot-sd-combined.bin
- 2) => tftp 1000000 u-boot-sd-combined.bin
- 3) => mux sdhc
- 4) => mmc write 1000000 0 1050
- set SW4[1:4]= 0111 and SW3[3:4]= 10, then power on the board
-
-
-Boot Linux from network using TFTP on P1010RDB-PB
-=================================================
-Place uImage, p1010rdb.dtb and rootfs files in the TFTP download path.
- => tftp 1000000 uImage
- => tftp 2000000 p1010rdb.dtb
- => tftp 3000000 rootfs.ext2.gz.uboot.p1010rdb
- => bootm 1000000 3000000 2000000
-
-
-For more details, please refer to P1010RDB-PB User Guide and access website
-www.freescale.com and Freescale QorIQ SDK Infocenter document.
diff --git a/board/freescale/p1010rdb/ddr.c b/board/freescale/p1010rdb/ddr.c
deleted file mode 100644
index 71f6259b60..0000000000
--- a/board/freescale/p1010rdb/ddr.c
+++ /dev/null
@@ -1,235 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2010-2011 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <vsprintf.h>
-#include <asm/mmu.h>
-#include <asm/immap_85xx.h>
-#include <asm/processor.h>
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-#include <asm/io.h>
-#include <asm/fsl_law.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifndef CONFIG_SYS_DDR_RAW_TIMING
-#define CONFIG_SYS_DRAM_SIZE 1024
-
-fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
- .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
- .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
- .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
- .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
- .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
- .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
- .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
- .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
- .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
- .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
- .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
- .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
- .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
- .ddr_data_init = CONFIG_MEM_INIT_VALUE,
- .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
- .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
- .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
- .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
- .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
- .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
- .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_800,
- .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
- .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
- .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
-};
-
-fsl_ddr_cfg_regs_t ddr_cfg_regs_667 = {
- .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
- .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
- .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
- .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_667,
- .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_667,
- .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_667,
- .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_667,
- .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
- .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
- .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_667,
- .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_667,
- .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
- .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_667,
- .ddr_data_init = CONFIG_MEM_INIT_VALUE,
- .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_667,
- .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
- .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
- .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
- .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
- .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
- .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_667,
- .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
- .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
- .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
-};
-
-fixed_ddr_parm_t fixed_ddr_parm_0[] = {
- {750, 850, &ddr_cfg_regs_800},
- {607, 749, &ddr_cfg_regs_667},
- {0, 0, NULL}
-};
-
-unsigned long get_sdram_size(void)
-{
- struct cpu_type *cpu;
- phys_size_t ddr_size;
-
- cpu = gd->arch.cpu;
- /* P1014 and it's derivatives support max 16it DDR width */
- if (cpu->soc_ver == SVR_P1014)
- ddr_size = (CONFIG_SYS_DRAM_SIZE / 2);
- else
- ddr_size = CONFIG_SYS_DRAM_SIZE;
-
- return ddr_size;
-}
-
-/*
- * Fixed sdram init -- doesn't use serial presence detect.
- */
-phys_size_t fixed_sdram(void)
-{
- int i;
- char buf[32];
- fsl_ddr_cfg_regs_t ddr_cfg_regs;
- phys_size_t ddr_size;
- ulong ddr_freq, ddr_freq_mhz;
- struct cpu_type *cpu;
-
-#if defined(CONFIG_SYS_RAMBOOT)
- return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
-#endif
-
- ddr_freq = get_ddr_freq(0);
- ddr_freq_mhz = ddr_freq / 1000000;
-
- printf("Configuring DDR for %s MT/s data rate\n",
- strmhz(buf, ddr_freq));
-
- for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
- if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) &&
- (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) {
- memcpy(&ddr_cfg_regs, fixed_ddr_parm_0[i].ddr_settings,
- sizeof(ddr_cfg_regs));
- break;
- }
- }
-
- if (fixed_ddr_parm_0[i].max_freq == 0)
- panic("Unsupported DDR data rate %s MT/s data rate\n",
- strmhz(buf, ddr_freq));
-
- cpu = gd->arch.cpu;
- /* P1014 and it's derivatives support max 16bit DDR width */
- if (cpu->soc_ver == SVR_P1014) {
- ddr_cfg_regs.ddr_sdram_cfg &= ~SDRAM_CFG_DBW_MASK;
- ddr_cfg_regs.ddr_sdram_cfg |= SDRAM_CFG_16_BE;
- /* divide SA and EA by two and then mask the rest so we don't
- * write to reserved fields */
- ddr_cfg_regs.cs[0].bnds = (CONFIG_SYS_DDR_CS0_BNDS >> 1) & 0x0fff0fff;
- }
-
- ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
- fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
-
- if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, ddr_size,
- LAW_TRGT_IF_DDR_1) < 0) {
- printf("ERROR setting Local Access Windows for DDR\n");
- return 0;
- }
-
- return ddr_size;
-}
-
-#else /* CONFIG_SYS_DDR_RAW_TIMING */
-/*
- * Samsung K4B2G0846C-HCF8
- * The following timing are for "downshift"
- * i.e. to use CL9 part as CL7
- * otherwise, tAA, tRCD, tRP will be 13500ps
- * and tRC will be 49500ps
- */
-dimm_params_t ddr_raw_timing = {
- .n_ranks = 1,
- .rank_density = 1073741824u,
- .capacity = 1073741824u,
- .primary_sdram_width = 32,
- .ec_sdram_width = 0,
- .registered_dimm = 0,
- .mirrored_dimm = 0,
- .n_row_addr = 15,
- .n_col_addr = 10,
- .n_banks_per_sdram_device = 8,
- .edc_config = 0,
- .burst_lengths_bitmask = 0x0c,
-
- .tckmin_x_ps = 1875,
- .caslat_x = 0x1e << 4, /* 5,6,7,8 */
- .taa_ps = 13125,
- .twr_ps = 15000,
- .trcd_ps = 13125,
- .trrd_ps = 7500,
- .trp_ps = 13125,
- .tras_ps = 37500,
- .trc_ps = 50625,
- .trfc_ps = 160000,
- .twtr_ps = 7500,
- .trtp_ps = 7500,
- .refresh_rate_ps = 7800000,
- .tfaw_ps = 37500,
-};
-
-int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
- unsigned int controller_number,
- unsigned int dimm_number)
-{
- const char dimm_model[] = "Fixed DDR on board";
-
- if ((controller_number == 0) && (dimm_number == 0)) {
- memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
- memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
- memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
- }
-
- return 0;
-}
-
-void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- struct cpu_type *cpu;
- int i;
- popts->clk_adjust = 6;
- popts->cpo_override = 0x1f;
- popts->write_data_delay = 2;
- popts->half_strength_driver_enable = 1;
- /* Write leveling override */
- popts->wrlvl_en = 1;
- popts->wrlvl_override = 1;
- popts->wrlvl_sample = 0xf;
- popts->wrlvl_start = 0x8;
- popts->trwt_override = 1;
- popts->trwt = 0;
-
- cpu = gd->arch.cpu;
- /* P1014 and it's derivatives support max 16it DDR width */
- if (cpu->soc_ver == SVR_P1014)
- popts->data_bus_width = DDR_DATA_BUS_WIDTH_16;
-
- for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
- popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
- popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
- }
-}
-
-#endif /* CONFIG_SYS_DDR_RAW_TIMING */
diff --git a/board/freescale/p1010rdb/law.c b/board/freescale/p1010rdb/law.c
deleted file mode 100644
index debf571482..0000000000
--- a/board/freescale/p1010rdb/law.c
+++ /dev/null
@@ -1,16 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2010-2011 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-struct law_entry law_table[] = {
- SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_IFC),
- SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC),
- SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c
deleted file mode 100644
index 66ccc0bd1e..0000000000
--- a/board/freescale/p1010rdb/p1010rdb.c
+++ /dev/null
@@ -1,731 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2010-2011 Freescale Semiconductor, Inc.
- * Copyright 2020 NXP
- */
-
-#include <common.h>
-#include <command.h>
-#include <image.h>
-#include <init.h>
-#include <net.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/io.h>
-#include <env.h>
-#include <miiphy.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <fsl_mdio.h>
-#include <tsec.h>
-#include <mmc.h>
-#include <netdev.h>
-#include <pci.h>
-#include <asm/fsl_serdes.h>
-#include <fsl_ifc.h>
-#include <asm/fsl_pci.h>
-#include <hwconfig.h>
-#include <i2c.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define GPIO4_PCIE_RESET_SET 0x08000000
-#define MUX_CPLD_CAN_UART 0x00
-#define MUX_CPLD_TDM 0x01
-#define MUX_CPLD_SPICS0_FLASH 0x00
-#define MUX_CPLD_SPICS0_SLIC 0x02
-#define PMUXCR1_IFC_MASK 0x00ffff00
-#define PMUXCR1_SDHC_MASK 0x00fff000
-#define PMUXCR1_SDHC_ENABLE 0x00555000
-
-enum {
- MUX_TYPE_IFC,
- MUX_TYPE_SDHC,
- MUX_TYPE_SPIFLASH,
- MUX_TYPE_TDM,
- MUX_TYPE_CAN,
- MUX_TYPE_CS0_NOR,
- MUX_TYPE_CS0_NAND,
-};
-
-enum {
- I2C_READ_BANK,
- I2C_READ_PCB_VER,
-};
-
-static uint sd_ifc_mux;
-
-struct cpld_data {
- u8 cpld_ver; /* cpld revision */
-#if defined(CONFIG_TARGET_P1010RDB_PA)
- u8 pcba_ver; /* pcb revision number */
- u8 twindie_ddr3;
- u8 res1[6];
- u8 bank_sel; /* NOR Flash bank */
- u8 res2[5];
- u8 usb2_sel;
- u8 res3[1];
- u8 porsw_sel;
- u8 tdm_can_sel;
- u8 spi_cs0_sel; /* SPI CS0 SLIC/SPI Flash */
- u8 por0; /* POR Options */
- u8 por1; /* POR Options */
- u8 por2; /* POR Options */
- u8 por3; /* POR Options */
-#elif defined(CONFIG_TARGET_P1010RDB_PB)
- u8 rom_loc;
-#endif
-};
-
-int board_early_init_f(void)
-{
- ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
- struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
- /* Clock configuration to access CPLD using IFC(GPCM) */
- setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
- /*
- * Reset PCIe slots via GPIO4
- */
- setbits_be32(&pgpio->gpdir, GPIO4_PCIE_RESET_SET);
- setbits_be32(&pgpio->gpdat, GPIO4_PCIE_RESET_SET);
-
- return 0;
-}
-
-int board_early_init_r(void)
-{
- const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
- int flash_esel = find_tlb_idx((void *)flashbase, 1);
-
- /*
- * Remap Boot flash region to caching-inhibited
- * so that flash can be erased properly.
- */
-
- /* Flush d-cache and invalidate i-cache of any FLASH data */
- flush_dcache();
- invalidate_icache();
-
- if (flash_esel == -1) {
- /* very unlikely unless something is messed up */
- puts("Error: Could not find TLB for FLASH BASE\n");
- flash_esel = 2; /* give our best effort to continue */
- } else {
- /* invalidate existing TLB entry for flash */
- disable_tlb(flash_esel);
- }
-
- set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, flash_esel, BOOKE_PAGESZ_16M, 1);
-
- set_tlb(1, flashbase + 0x1000000,
- CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, flash_esel+1, BOOKE_PAGESZ_16M, 1);
- return 0;
-}
-
-#if defined(CONFIG_PCI) && !defined(CONFIG_DM_PCI)
-void pci_init_board(void)
-{
- fsl_pcie_init_board(0);
-}
-#endif /* ifdef CONFIG_PCI */
-
-int config_board_mux(int ctrl_type)
-{
- ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- u8 tmp;
-
-#ifdef CONFIG_DM_I2C
- struct udevice *dev;
- int ret;
-#if defined(CONFIG_TARGET_P1010RDB_PA)
- struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
-
- ret = i2c_get_chip_for_busnum(I2C_PCA9557_BUS_NUM,
- I2C_PCA9557_ADDR1, 1, &dev);
- if (ret) {
- printf("%s: Cannot find udev for a bus %d\n",
- __func__, I2C_PCA9557_BUS_NUM);
- return ret;
- }
- switch (ctrl_type) {
- case MUX_TYPE_IFC:
- tmp = 0xf0;
- dm_i2c_write(dev, 3, &tmp, 1);
- tmp = 0x01;
- dm_i2c_write(dev, 1, &tmp, 1);
- sd_ifc_mux = MUX_TYPE_IFC;
- clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK);
- break;
- case MUX_TYPE_SDHC:
- tmp = 0xf0;
- dm_i2c_write(dev, 3, &tmp, 1);
- tmp = 0x05;
- dm_i2c_write(dev, 1, &tmp, 1);
- sd_ifc_mux = MUX_TYPE_SDHC;
- clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK,
- PMUXCR1_SDHC_ENABLE);
- break;
- case MUX_TYPE_SPIFLASH:
- out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_FLASH);
- break;
- case MUX_TYPE_TDM:
- out_8(&cpld_data->tdm_can_sel, MUX_CPLD_TDM);
- out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_SLIC);
- break;
- case MUX_TYPE_CAN:
- out_8(&cpld_data->tdm_can_sel, MUX_CPLD_CAN_UART);
- break;
- default:
- break;
- }
-#elif defined(CONFIG_TARGET_P1010RDB_PB)
- ret = i2c_get_chip_for_busnum(I2C_PCA9557_BUS_NUM,
- I2C_PCA9557_ADDR2, 1, &dev);
- if (ret) {
- printf("%s: Cannot find udev for a bus %d\n",
- __func__, I2C_PCA9557_BUS_NUM);
- return ret;
- }
- switch (ctrl_type) {
- case MUX_TYPE_IFC:
- dm_i2c_read(dev, 0, &tmp, 1);
- clrbits_8(&tmp, 0x04);
- dm_i2c_write(dev, 1, &tmp, 1);
- dm_i2c_read(dev, 3, &tmp, 1);
- clrbits_8(&tmp, 0x04);
- dm_i2c_write(dev, 3, &tmp, 1);
- sd_ifc_mux = MUX_TYPE_IFC;
- clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK);
- break;
- case MUX_TYPE_SDHC:
- dm_i2c_read(dev, 0, &tmp, 1);
- setbits_8(&tmp, 0x04);
- dm_i2c_write(dev, 1, &tmp, 1);
- dm_i2c_read(dev, 3, &tmp, 1);
- clrbits_8(&tmp, 0x04);
- dm_i2c_write(dev, 3, &tmp, 1);
- sd_ifc_mux = MUX_TYPE_SDHC;
- clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK,
- PMUXCR1_SDHC_ENABLE);
- break;
- case MUX_TYPE_SPIFLASH:
- dm_i2c_read(dev, 0, &tmp, 1);
- clrbits_8(&tmp, 0x80);
- dm_i2c_write(dev, 1, &tmp, 1);
- dm_i2c_read(dev, 3, &tmp, 1);
- clrbits_8(&tmp, 0x80);
- dm_i2c_write(dev, 3, &tmp, 1);
- break;
- case MUX_TYPE_TDM:
- dm_i2c_read(dev, 0, &tmp, 1);
- setbits_8(&tmp, 0x82);
- dm_i2c_write(dev, 1, &tmp, 1);
- dm_i2c_read(dev, 3, &tmp, 1);
- clrbits_8(&tmp, 0x82);
- dm_i2c_write(dev, 3, &tmp, 1);
- break;
- case MUX_TYPE_CAN:
- dm_i2c_read(dev, 0, &tmp, 1);
- clrbits_8(&tmp, 0x02);
- dm_i2c_write(dev, 1, &tmp, 1);
- dm_i2c_read(dev, 3, &tmp, 1);
- clrbits_8(&tmp, 0x02);
- dm_i2c_write(dev, 3, &tmp, 1);
- break;
- case MUX_TYPE_CS0_NOR:
- dm_i2c_read(dev, 0, &tmp, 1);
- clrbits_8(&tmp, 0x08);
- dm_i2c_write(dev, 1, &tmp, 1);
- dm_i2c_read(dev, 3, &tmp, 1);
- clrbits_8(&tmp, 0x08);
- dm_i2c_write(dev, 3, &tmp, 1);
- break;
- case MUX_TYPE_CS0_NAND:
- dm_i2c_read(dev, 0, &tmp, 1);
- setbits_8(&tmp, 0x08);
- dm_i2c_write(dev, 1, &tmp, 1);
- dm_i2c_read(dev, 3, &tmp, 1);
- clrbits_8(&tmp, 0x08);
- dm_i2c_write(dev, 3, &tmp, 1);
- break;
- default:
- break;
- }
-#endif
-#else
-#if defined(CONFIG_TARGET_P1010RDB_PA)
- struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
-
- switch (ctrl_type) {
- case MUX_TYPE_IFC:
- i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
- tmp = 0xf0;
- i2c_write(I2C_PCA9557_ADDR1, 3, 1, &tmp, 1);
- tmp = 0x01;
- i2c_write(I2C_PCA9557_ADDR1, 1, 1, &tmp, 1);
- sd_ifc_mux = MUX_TYPE_IFC;
- clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK);
- break;
- case MUX_TYPE_SDHC:
- i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
- tmp = 0xf0;
- i2c_write(I2C_PCA9557_ADDR1, 3, 1, &tmp, 1);
- tmp = 0x05;
- i2c_write(I2C_PCA9557_ADDR1, 1, 1, &tmp, 1);
- sd_ifc_mux = MUX_TYPE_SDHC;
- clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK,
- PMUXCR1_SDHC_ENABLE);
- break;
- case MUX_TYPE_SPIFLASH:
- out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_FLASH);
- break;
- case MUX_TYPE_TDM:
- out_8(&cpld_data->tdm_can_sel, MUX_CPLD_TDM);
- out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_SLIC);
- break;
- case MUX_TYPE_CAN:
- out_8(&cpld_data->tdm_can_sel, MUX_CPLD_CAN_UART);
- break;
- default:
- break;
- }
-#elif defined(CONFIG_TARGET_P1010RDB_PB)
- uint orig_bus = i2c_get_bus_num();
- i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
-
- switch (ctrl_type) {
- case MUX_TYPE_IFC:
- i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
- clrbits_8(&tmp, 0x04);
- i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
- i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
- clrbits_8(&tmp, 0x04);
- i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
- sd_ifc_mux = MUX_TYPE_IFC;
- clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK);
- break;
- case MUX_TYPE_SDHC:
- i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
- setbits_8(&tmp, 0x04);
- i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
- i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
- clrbits_8(&tmp, 0x04);
- i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
- sd_ifc_mux = MUX_TYPE_SDHC;
- clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK,
- PMUXCR1_SDHC_ENABLE);
- break;
- case MUX_TYPE_SPIFLASH:
- i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
- clrbits_8(&tmp, 0x80);
- i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
- i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
- clrbits_8(&tmp, 0x80);
- i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
- break;
- case MUX_TYPE_TDM:
- i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
- setbits_8(&tmp, 0x82);
- i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
- i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
- clrbits_8(&tmp, 0x82);
- i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
- break;
- case MUX_TYPE_CAN:
- i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
- clrbits_8(&tmp, 0x02);
- i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
- i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
- clrbits_8(&tmp, 0x02);
- i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
- break;
- case MUX_TYPE_CS0_NOR:
- i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
- clrbits_8(&tmp, 0x08);
- i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
- i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
- clrbits_8(&tmp, 0x08);
- i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
- break;
- case MUX_TYPE_CS0_NAND:
- i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
- setbits_8(&tmp, 0x08);
- i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
- i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
- clrbits_8(&tmp, 0x08);
- i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
- break;
- default:
- break;
- }
- i2c_set_bus_num(orig_bus);
-#endif
-#endif
- return 0;
-}
-
-#ifdef CONFIG_TARGET_P1010RDB_PB
-int i2c_pca9557_read(int type)
-{
- u8 val;
- int bus_num = I2C_PCA9557_BUS_NUM;
-
-#ifdef CONFIG_DM_I2C
- struct udevice *dev;
- int ret;
-
- ret = i2c_get_chip_for_busnum(bus_num, I2C_PCA9557_ADDR2, 1, &dev);
- if (ret) {
- printf("%s: Cannot find udev for a bus %d\n",
- __func__, bus_num);
- return ret;
- }
- dm_i2c_read(dev, 0, &val, 1);
-#else
- i2c_set_bus_num(bus_num);
- i2c_read(I2C_PCA9557_ADDR2, 0, 1, &val, 1);
-#endif
-
- switch (type) {
- case I2C_READ_BANK:
- val = (val & 0x10) >> 4;
- break;
- case I2C_READ_PCB_VER:
- val = ((val & 0x60) >> 5) + 1;
- break;
- default:
- break;
- }
-
- return val;
-}
-#endif
-
-int checkboard(void)
-{
- struct cpu_type *cpu;
- struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
- u8 val;
-
- cpu = gd->arch.cpu;
-#if defined(CONFIG_TARGET_P1010RDB_PA)
- printf("Board: %sRDB-PA, ", cpu->name);
-#elif defined(CONFIG_TARGET_P1010RDB_PB)
- printf("Board: %sRDB-PB, ", cpu->name);
-#ifdef CONFIG_DM_I2C
- struct udevice *dev;
- int ret;
-
- ret = i2c_get_chip_for_busnum(I2C_PCA9557_BUS_NUM, I2C_PCA9557_ADDR2,
- 1, &dev);
- if (ret) {
- printf("%s: Cannot find udev for a bus %d\n", __func__,
- I2C_PCA9557_BUS_NUM);
- return ret;
- }
- val = 0x0; /* no polarity inversion */
- dm_i2c_write(dev, 2, &val, 1);
-#else
- i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
- i2c_init(CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE);
- val = 0x0; /* no polarity inversion */
- i2c_write(I2C_PCA9557_ADDR2, 2, 1, &val, 1);
-#endif
-#endif
-
-#ifdef CONFIG_SDCARD
- /* switch to IFC to read info from CPLD */
- config_board_mux(MUX_TYPE_IFC);
-#endif
-
-#if defined(CONFIG_TARGET_P1010RDB_PA)
- val = (in_8(&cpld_data->pcba_ver) & 0xf);
- printf("PCB: v%x.0\n", val);
-#elif defined(CONFIG_TARGET_P1010RDB_PB)
- val = in_8(&cpld_data->cpld_ver);
- printf("CPLD: v%x.%x, ", val >> 4, val & 0xf);
- printf("PCB: v%x.0, ", i2c_pca9557_read(I2C_READ_PCB_VER));
- val = in_8(&cpld_data->rom_loc) & 0xf;
- puts("Boot from: ");
- switch (val) {
- case 0xf:
- config_board_mux(MUX_TYPE_CS0_NOR);
- printf("NOR vBank%d\n", i2c_pca9557_read(I2C_READ_BANK));
- break;
- case 0xe:
- puts("SDHC\n");
- val = 0x60; /* set pca9557 pin input/output */
-#ifdef CONFIG_DM_I2C
- dm_i2c_write(dev, 3, &val, 1);
-#else
- i2c_write(I2C_PCA9557_ADDR2, 3, 1, &val, 1);
-#endif
- break;
- case 0x5:
- config_board_mux(MUX_TYPE_IFC);
- config_board_mux(MUX_TYPE_CS0_NAND);
- puts("NAND\n");
- break;
- case 0x6:
- config_board_mux(MUX_TYPE_IFC);
- puts("SPI\n");
- break;
- default:
- puts("unknown\n");
- break;
- }
-#endif
- return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
-#ifdef CONFIG_TSEC_ENET
- struct fsl_pq_mdio_info mdio_info;
- struct tsec_info_struct tsec_info[4];
- struct cpu_type *cpu;
- int num = 0;
-
- cpu = gd->arch.cpu;
-
-#ifdef CONFIG_TSEC1
- SET_STD_TSEC_INFO(tsec_info[num], 1);
- num++;
-#endif
-#ifdef CONFIG_TSEC2
- SET_STD_TSEC_INFO(tsec_info[num], 2);
- num++;
-#endif
-#ifdef CONFIG_TSEC3
- /* P1014 and it's derivatives do not support eTSEC3 */
- if (cpu->soc_ver != SVR_P1014) {
- SET_STD_TSEC_INFO(tsec_info[num], 3);
- num++;
- }
-#endif
- if (!num) {
- printf("No TSECs initialized\n");
- return 0;
- }
-
- mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
- mdio_info.name = DEFAULT_MII_NAME;
-
- fsl_pq_mdio_init(bis, &mdio_info);
-
- tsec_eth_init(bis, tsec_info, num);
-#endif
-
- return pci_eth_init(bis);
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-void fdt_del_flexcan(void *blob)
-{
- int nodeoff = 0;
-
- while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
- "fsl,p1010-flexcan")) >= 0) {
- fdt_del_node(blob, nodeoff);
- }
-}
-
-void fdt_del_spi_flash(void *blob)
-{
- int nodeoff = 0;
-
- while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
- "spansion,s25sl12801")) >= 0) {
- fdt_del_node(blob, nodeoff);
- }
-}
-
-void fdt_del_spi_slic(void *blob)
-{
- int nodeoff = 0;
-
- while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
- "zarlink,le88266")) >= 0) {
- fdt_del_node(blob, nodeoff);
- }
-}
-
-void fdt_del_tdm(void *blob)
-{
- int nodeoff = 0;
-
- while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
- "fsl,starlite-tdm")) >= 0) {
- fdt_del_node(blob, nodeoff);
- }
-}
-
-void fdt_del_sdhc(void *blob)
-{
- int nodeoff = 0;
-
- while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
- "fsl,esdhc")) >= 0) {
- fdt_del_node(blob, nodeoff);
- }
-}
-
-void fdt_del_ifc(void *blob)
-{
- int nodeoff = 0;
-
- while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
- "fsl,ifc")) >= 0) {
- fdt_del_node(blob, nodeoff);
- }
-}
-
-void fdt_disable_uart1(void *blob)
-{
- int nodeoff;
-
- nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,ns16550",
- CONFIG_SYS_NS16550_COM2);
-
- if (nodeoff > 0) {
- fdt_status_disabled(blob, nodeoff);
- } else {
- printf("WARNING unable to set status for fsl,ns16550 "
- "uart1: %s\n", fdt_strerror(nodeoff));
- }
-}
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
- phys_addr_t base;
- phys_size_t size;
- struct cpu_type *cpu;
-
- cpu = gd->arch.cpu;
-
- ft_cpu_setup(blob, bd);
-
- base = env_get_bootm_low();
- size = env_get_bootm_size();
-
-#if defined(CONFIG_PCI) && !defined(CONFIG_DM_PCI)
- FT_FSL_PCI_SETUP;
-#endif
-
- fdt_fixup_memory(blob, (u64)base, (u64)size);
-
-#if defined(CONFIG_HAS_FSL_DR_USB)
- fsl_fdt_fixup_dr_usb(blob, bd);
-#endif
-
- /* P1014 and it's derivatives don't support CAN and eTSEC3 */
- if (cpu->soc_ver == SVR_P1014) {
- fdt_del_flexcan(blob);
- fdt_del_node_and_alias(blob, "ethernet2");
- }
-
- /* Delete IFC node as IFC pins are multiplexing with SDHC */
- if (sd_ifc_mux != MUX_TYPE_IFC)
- fdt_del_ifc(blob);
- else
- fdt_del_sdhc(blob);
-
- if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) {
- fdt_del_tdm(blob);
- fdt_del_spi_slic(blob);
- } else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) {
- fdt_del_flexcan(blob);
- fdt_del_spi_flash(blob);
- fdt_disable_uart1(blob);
- } else {
- /*
- * If we don't set fsl_p1010mux:tdm_can to "can" or "tdm"
- * explicitly, defaultly spi_cs_sel to spi-flash instead of
- * to tdm/slic.
- */
- fdt_del_tdm(blob);
- fdt_del_flexcan(blob);
- fdt_disable_uart1(blob);
- }
-
- return 0;
-}
-#endif
-
-#ifdef CONFIG_SDCARD
-int board_mmc_init(bd_t *bis)
-{
- config_board_mux(MUX_TYPE_SDHC);
- return -1;
-}
-#else
-void board_reset(void)
-{
- /* mux to IFC to enable CPLD for reset */
- if (sd_ifc_mux != MUX_TYPE_IFC)
- config_board_mux(MUX_TYPE_IFC);
-}
-#endif
-
-
-int misc_init_r(void)
-{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-
- if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) {
- clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN1_TDM |
- MPC85xx_PMUXCR_CAN1_UART |
- MPC85xx_PMUXCR_CAN2_TDM |
- MPC85xx_PMUXCR_CAN2_UART);
- config_board_mux(MUX_TYPE_CAN);
- } else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) {
- clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_UART |
- MPC85xx_PMUXCR_CAN1_UART);
- setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_TDM |
- MPC85xx_PMUXCR_CAN1_TDM);
- clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_GPIO);
- setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_TDM);
- config_board_mux(MUX_TYPE_TDM);
- } else {
- /* defaultly spi_cs_sel to flash */
- config_board_mux(MUX_TYPE_SPIFLASH);
- }
-
- if (hwconfig("esdhc"))
- config_board_mux(MUX_TYPE_SDHC);
- else if (hwconfig("ifc"))
- config_board_mux(MUX_TYPE_IFC);
-
-#ifdef CONFIG_TARGET_P1010RDB_PB
- setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_GPIO01_DRVVBUS);
-#endif
- return 0;
-}
-
-#ifndef CONFIG_SPL_BUILD
-static int pin_mux_cmd(struct cmd_tbl *cmdtp, int flag, int argc,
- char *const argv[])
-{
- if (argc < 2)
- return CMD_RET_USAGE;
- if (strcmp(argv[1], "ifc") == 0)
- config_board_mux(MUX_TYPE_IFC);
- else if (strcmp(argv[1], "sdhc") == 0)
- config_board_mux(MUX_TYPE_SDHC);
- else
- return CMD_RET_USAGE;
- return 0;
-}
-
-U_BOOT_CMD(
- mux, 2, 0, pin_mux_cmd,
- "configure multiplexing pin for IFC/SDHC bus in runtime",
- "bus_type (e.g. mux sdhc)"
-);
-#endif
diff --git a/board/freescale/p1010rdb/spl.c b/board/freescale/p1010rdb/spl.c
deleted file mode 100644
index 159d14b024..0000000000
--- a/board/freescale/p1010rdb/spl.c
+++ /dev/null
@@ -1,114 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/* Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <clock_legacy.h>
-#include <console.h>
-#include <env.h>
-#include <env_internal.h>
-#include <init.h>
-#include <ns16550.h>
-#include <malloc.h>
-#include <mmc.h>
-#include <nand.h>
-#include <i2c.h>
-#include <fsl_esdhc.h>
-#include <spi_flash.h>
-#include "../common/spl.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-phys_size_t get_effective_memsize(void)
-{
- return CONFIG_SYS_L2_SIZE;
-}
-
-void board_init_f(ulong bootflag)
-{
- u32 plat_ratio;
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
- struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
-
- console_init_f();
-
- /* Clock configuration to access CPLD using IFC(GPCM) */
- setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
-
-#ifdef CONFIG_TARGET_P1010RDB_PB
- setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_GPIO01_DRVVBUS);
-#endif
-
- /* initialize selected port with appropriate baud rate */
- plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
- plat_ratio >>= 1;
- gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
-
- NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
- gd->bus_clk / 16 / CONFIG_BAUDRATE);
-
-#ifdef CONFIG_SPL_MMC_BOOT
- puts("\nSD boot...\n");
-#elif defined(CONFIG_SPL_SPI_BOOT)
- puts("\nSPI Flash boot...\n");
-#endif
- /* copy code to RAM and jump to it - this should not return */
- /* NOTE - code has to be copied out of NAND buffer before
- * other blocks can be read.
- */
- relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
- /* Pointer is writable since we allocated a register for it */
- gd = (gd_t *)CONFIG_SPL_GD_ADDR;
- bd_t *bd;
-
- memset(gd, 0, sizeof(gd_t));
- bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
- memset(bd, 0, sizeof(bd_t));
- gd->bd = bd;
- bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
- bd->bi_memsize = CONFIG_SYS_L2_SIZE;
-
- arch_cpu_init();
- get_clocks();
- mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
- CONFIG_SPL_RELOC_MALLOC_SIZE);
- gd->flags |= GD_FLG_FULL_MALLOC_INIT;
-
-#ifndef CONFIG_SPL_NAND_BOOT
- env_init();
-#endif
-#ifdef CONFIG_SPL_MMC_BOOT
- mmc_initialize(bd);
-#endif
-
- /* relocate environment function pointers etc. */
-#ifdef CONFIG_SPL_NAND_BOOT
- nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
- (uchar *)SPL_ENV_ADDR);
- gd->env_addr = (ulong)(SPL_ENV_ADDR);
- gd->env_valid = ENV_VALID;
-#else
- env_relocate();
-#endif
-
- i2c_init_all();
-
- dram_init();
-#ifdef CONFIG_SPL_NAND_BOOT
- puts("\nTertiary program loader running in sram...");
-#else
- puts("\nSecond program loader running in sram...");
-#endif
-
-#ifdef CONFIG_SPL_MMC_BOOT
- mmc_boot();
-#elif defined(CONFIG_SPL_SPI_BOOT)
- fsl_spi_boot();
-#elif defined(CONFIG_SPL_NAND_BOOT)
- nand_boot();
-#endif
-}
diff --git a/board/freescale/p1010rdb/spl_minimal.c b/board/freescale/p1010rdb/spl_minimal.c
deleted file mode 100644
index 0bb2c83872..0000000000
--- a/board/freescale/p1010rdb/spl_minimal.c
+++ /dev/null
@@ -1,65 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2011 Freescale Semiconductor, Inc.
- */
-#include <common.h>
-#include <init.h>
-#include <mpc85xx.h>
-#include <asm/io.h>
-#include <ns16550.h>
-#include <nand.h>
-#include <asm/mmu.h>
-#include <asm/immap_85xx.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/fsl_law.h>
-#include <asm/global_data.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void board_init_f(ulong bootflag)
-{
- u32 plat_ratio;
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
-#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
- set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
- set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
-#endif
-
- /* initialize selected port with appropriate baud rate */
- plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
- plat_ratio >>= 1;
- gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
-
- NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
- gd->bus_clk / 16 / CONFIG_BAUDRATE);
-
- puts("\nNAND boot... ");
-
- /* copy code to RAM and jump to it - this should not return */
- /* NOTE - code has to be copied out of NAND buffer before
- * other blocks can be read.
- */
-
- relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
- puts("\nSecond program loader running in sram...");
- nand_boot();
-}
-
-void putc(char c)
-{
- if (c == '\n')
- NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
-
- NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
-}
-
-void puts(const char *str)
-{
- while (*str)
- putc(*str++);
-}
diff --git a/board/freescale/p1010rdb/tlb.c b/board/freescale/p1010rdb/tlb.c
deleted file mode 100644
index 04faefe994..0000000000
--- a/board/freescale/p1010rdb/tlb.c
+++ /dev/null
@@ -1,90 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2010-2011 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
- /* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
- CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
- CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
- CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
-
- /* TLB 1 */
- /* *I*** - Covers boot page */
- SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_4K, 1),
-#ifdef CONFIG_SPL_NAND_BOOT
- SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 10, BOOKE_PAGESZ_4K, 1),
-#endif
-
- /* *I*G* - CCSRBAR */
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 1, BOOKE_PAGESZ_1M, 1),
-
-#ifndef CONFIG_SPL_BUILD
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
- MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
- 0, 2, BOOKE_PAGESZ_16M, 1),
-
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x1000000,
- CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000,
- MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
- 0, 3, BOOKE_PAGESZ_16M, 1),
-
-#ifdef CONFIG_PCI
- /* *I*G* - PCI */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 4, BOOKE_PAGESZ_1G, 1),
-
- /* *I*G* - PCI I/O */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 5, BOOKE_PAGESZ_256K, 1),
-#endif
-#endif
-
- /* *I*G - Board CPLD */
- SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 6, BOOKE_PAGESZ_256K, 1),
-
- SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 7, BOOKE_PAGESZ_1M, 1),
-
-#if defined(CONFIG_SYS_RAMBOOT) || \
- (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
- SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
- 0, 8, BOOKE_PAGESZ_1G, 1),
-#endif
-
-#ifdef CONFIG_SYS_INIT_L2_ADDR
- /* *I*G - L2SRAM */
- SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
- 0, 11, BOOKE_PAGESZ_256K, 1)
-#endif
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig b/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig
deleted file mode 100644
index c1044520d7..0000000000
--- a/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig
+++ /dev/null
@@ -1,63 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11000000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P1010RDB_PA=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_PHYS_64BIT=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="NAND_SECBOOT"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
-CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P1010RDB-PA_36BIT_NAND_defconfig b/configs/P1010RDB-PA_36BIT_NAND_defconfig
deleted file mode 100644
index da04cab014..0000000000
--- a/configs/P1010RDB-PA_36BIT_NAND_defconfig
+++ /dev/null
@@ -1,85 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11001000
-CONFIG_ENV_SIZE=0x4000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_TPL_LIBCOMMON_SUPPORT=y
-CONFIG_TPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_TEXT_BASE=0xFF800000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P1010RDB_PA=y
-CONFIG_PHYS_64BIT=y
-CONFIG_SYS_CUSTOM_LDSCRIPT=y
-CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_NAND_BOOT=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_TPL=y
-CONFIG_TPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_TPL_ENV_SUPPORT=y
-CONFIG_TPL_I2C_SUPPORT=y
-CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_TPL_NAND_SUPPORT=y
-CONFIG_TPL_SERIAL_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b"
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_DM_I2C=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
diff --git a/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig b/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig
deleted file mode 100644
index 723f6ca2bb..0000000000
--- a/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig
+++ /dev/null
@@ -1,62 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P1010RDB_PA=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_PHYS_64BIT=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
-CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P1010RDB-PA_36BIT_NOR_defconfig b/configs/P1010RDB-PA_36BIT_NOR_defconfig
deleted file mode 100644
index e6edd395e7..0000000000
--- a/configs/P1010RDB-PA_36BIT_NOR_defconfig
+++ /dev/null
@@ -1,67 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P1010RDB_PA=y
-CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
-CONFIG_PHYS_64BIT=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b"
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_DM_I2C=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
diff --git a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
deleted file mode 100644
index dcd606b0c2..0000000000
--- a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
+++ /dev/null
@@ -1,79 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x0
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_TEXT_BASE=0xD0001000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P1010RDB_PA=y
-CONFIG_PHYS_64BIT=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_MMC_BOOT=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b"
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_DM_I2C=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig
deleted file mode 100644
index 9987cde995..0000000000
--- a/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig
+++ /dev/null
@@ -1,64 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11000000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P1010RDB_PA=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_PHYS_64BIT=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
deleted file mode 100644
index c0800c8d7d..0000000000
--- a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
+++ /dev/null
@@ -1,81 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_SPL_TEXT_BASE=0xD0001000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P1010RDB_PA=y
-CONFIG_PHYS_64BIT=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_SPI_BOOT=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b"
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_DM_I2C=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
diff --git a/configs/P1010RDB-PA_NAND_SECBOOT_defconfig b/configs/P1010RDB-PA_NAND_SECBOOT_defconfig
deleted file mode 100644
index 9691fd2bd4..0000000000
--- a/configs/P1010RDB-PA_NAND_SECBOOT_defconfig
+++ /dev/null
@@ -1,62 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11000000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P1010RDB_PA=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="NAND_SECBOOT"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
-CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P1010RDB-PA_NAND_defconfig b/configs/P1010RDB-PA_NAND_defconfig
deleted file mode 100644
index 29ba692ca1..0000000000
--- a/configs/P1010RDB-PA_NAND_defconfig
+++ /dev/null
@@ -1,84 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11001000
-CONFIG_ENV_SIZE=0x4000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_TPL_LIBCOMMON_SUPPORT=y
-CONFIG_TPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_TEXT_BASE=0xFF800000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P1010RDB_PA=y
-CONFIG_SYS_CUSTOM_LDSCRIPT=y
-CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_NAND_BOOT=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_TPL=y
-CONFIG_TPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_TPL_ENV_SUPPORT=y
-CONFIG_TPL_I2C_SUPPORT=y
-CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_TPL_NAND_SUPPORT=y
-CONFIG_TPL_SERIAL_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa"
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_DM_I2C=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
diff --git a/configs/P1010RDB-PA_NOR_SECBOOT_defconfig b/configs/P1010RDB-PA_NOR_SECBOOT_defconfig
deleted file mode 100644
index 49351264cb..0000000000
--- a/configs/P1010RDB-PA_NOR_SECBOOT_defconfig
+++ /dev/null
@@ -1,60 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P1010RDB_PA=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
-CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P1010RDB-PA_NOR_defconfig b/configs/P1010RDB-PA_NOR_defconfig
deleted file mode 100644
index d8f87b5dac..0000000000
--- a/configs/P1010RDB-PA_NOR_defconfig
+++ /dev/null
@@ -1,66 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P1010RDB_PA=y
-CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa"
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_DM_I2C=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
diff --git a/configs/P1010RDB-PA_SDCARD_defconfig b/configs/P1010RDB-PA_SDCARD_defconfig
deleted file mode 100644
index 9711082529..0000000000
--- a/configs/P1010RDB-PA_SDCARD_defconfig
+++ /dev/null
@@ -1,78 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x0
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_TEXT_BASE=0xD0001000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P1010RDB_PA=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_MMC_BOOT=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa"
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_DM_I2C=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
diff --git a/configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig
deleted file mode 100644
index b31bdff00d..0000000000
--- a/configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig
+++ /dev/null
@@ -1,63 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11000000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P1010RDB_PA=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P1010RDB-PA_SPIFLASH_defconfig b/configs/P1010RDB-PA_SPIFLASH_defconfig
deleted file mode 100644
index de2ac2235f..0000000000
--- a/configs/P1010RDB-PA_SPIFLASH_defconfig
+++ /dev/null
@@ -1,80 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_SPL_TEXT_BASE=0xD0001000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P1010RDB_PA=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_SPI_BOOT=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa"
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_DM_I2C=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
diff --git a/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig b/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig
deleted file mode 100644
index 66bdebbf99..0000000000
--- a/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig
+++ /dev/null
@@ -1,63 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11000000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P1010RDB_PB=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_PHYS_64BIT=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="NAND_SECBOOT"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
-CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P1010RDB-PB_36BIT_NAND_defconfig b/configs/P1010RDB-PB_36BIT_NAND_defconfig
deleted file mode 100644
index 9f4876dd13..0000000000
--- a/configs/P1010RDB-PB_36BIT_NAND_defconfig
+++ /dev/null
@@ -1,85 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11001000
-CONFIG_ENV_SIZE=0x4000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_TPL_LIBCOMMON_SUPPORT=y
-CONFIG_TPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_TEXT_BASE=0xFF800000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P1010RDB_PB=y
-CONFIG_PHYS_64BIT=y
-CONFIG_SYS_CUSTOM_LDSCRIPT=y
-CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_NAND_BOOT=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_TPL=y
-CONFIG_TPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_TPL_ENV_SUPPORT=y
-CONFIG_TPL_I2C_SUPPORT=y
-CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_TPL_NAND_SUPPORT=y
-CONFIG_TPL_SERIAL_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b"
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_DM_I2C=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
diff --git a/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig b/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig
deleted file mode 100644
index f2e40668ea..0000000000
--- a/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig
+++ /dev/null
@@ -1,62 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P1010RDB_PB=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_PHYS_64BIT=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
-CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P1010RDB-PB_36BIT_NOR_defconfig b/configs/P1010RDB-PB_36BIT_NOR_defconfig
deleted file mode 100644
index e85af32e2c..0000000000
--- a/configs/P1010RDB-PB_36BIT_NOR_defconfig
+++ /dev/null
@@ -1,67 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P1010RDB_PB=y
-CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
-CONFIG_PHYS_64BIT=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b"
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_DM_I2C=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
diff --git a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
deleted file mode 100644
index 45feab4ee4..0000000000
--- a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
+++ /dev/null
@@ -1,79 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x0
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_TEXT_BASE=0xD0001000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P1010RDB_PB=y
-CONFIG_PHYS_64BIT=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_MMC_BOOT=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b"
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_DM_I2C=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig
deleted file mode 100644
index 50b5c5f1c5..0000000000
--- a/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig
+++ /dev/null
@@ -1,64 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11000000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P1010RDB_PB=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_PHYS_64BIT=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
deleted file mode 100644
index 3cd94f84ea..0000000000
--- a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
+++ /dev/null
@@ -1,81 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_SPL_TEXT_BASE=0xD0001000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P1010RDB_PB=y
-CONFIG_PHYS_64BIT=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_SPI_BOOT=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b"
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_DM_I2C=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
diff --git a/configs/P1010RDB-PB_NAND_SECBOOT_defconfig b/configs/P1010RDB-PB_NAND_SECBOOT_defconfig
deleted file mode 100644
index 17708dee47..0000000000
--- a/configs/P1010RDB-PB_NAND_SECBOOT_defconfig
+++ /dev/null
@@ -1,62 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11000000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P1010RDB_PB=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="NAND_SECBOOT"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
-CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P1010RDB-PB_NAND_defconfig b/configs/P1010RDB-PB_NAND_defconfig
deleted file mode 100644
index ddfe7b43a1..0000000000
--- a/configs/P1010RDB-PB_NAND_defconfig
+++ /dev/null
@@ -1,84 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11001000
-CONFIG_ENV_SIZE=0x4000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_TPL_LIBCOMMON_SUPPORT=y
-CONFIG_TPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_TEXT_BASE=0xFF800000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P1010RDB_PB=y
-CONFIG_SYS_CUSTOM_LDSCRIPT=y
-CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_NAND_BOOT=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_TPL=y
-CONFIG_TPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_TPL_ENV_SUPPORT=y
-CONFIG_TPL_I2C_SUPPORT=y
-CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_TPL_NAND_SUPPORT=y
-CONFIG_TPL_SERIAL_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb"
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_DM_I2C=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
diff --git a/configs/P1010RDB-PB_NOR_SECBOOT_defconfig b/configs/P1010RDB-PB_NOR_SECBOOT_defconfig
deleted file mode 100644
index be455a0c8f..0000000000
--- a/configs/P1010RDB-PB_NOR_SECBOOT_defconfig
+++ /dev/null
@@ -1,61 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P1010RDB_PB=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
-CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P1010RDB-PB_NOR_defconfig b/configs/P1010RDB-PB_NOR_defconfig
deleted file mode 100644
index 6011f8a9d8..0000000000
--- a/configs/P1010RDB-PB_NOR_defconfig
+++ /dev/null
@@ -1,66 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P1010RDB_PB=y
-CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb"
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_DM_I2C=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
diff --git a/configs/P1010RDB-PB_SDCARD_defconfig b/configs/P1010RDB-PB_SDCARD_defconfig
deleted file mode 100644
index 65f86fff60..0000000000
--- a/configs/P1010RDB-PB_SDCARD_defconfig
+++ /dev/null
@@ -1,78 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x0
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_TEXT_BASE=0xD0001000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P1010RDB_PB=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_MMC_BOOT=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb"
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_DM_I2C=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
diff --git a/configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig
deleted file mode 100644
index ce3d7c4d6b..0000000000
--- a/configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig
+++ /dev/null
@@ -1,63 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11000000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P1010RDB_PB=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P1010RDB-PB_SPIFLASH_defconfig b/configs/P1010RDB-PB_SPIFLASH_defconfig
deleted file mode 100644
index f71ee19ba6..0000000000
--- a/configs/P1010RDB-PB_SPIFLASH_defconfig
+++ /dev/null
@@ -1,80 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_SPL_TEXT_BASE=0xD0001000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P1010RDB_PB=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_SPI_BOOT=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb"
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_DM_I2C=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h
deleted file mode 100644
index 8f709a6cac..0000000000
--- a/include/configs/P1010RDB.h
+++ /dev/null
@@ -1,766 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2010-2011 Freescale Semiconductor, Inc.
- * Copyright 2020 NXP
- */
-
-/*
- * P010 RDB board configuration file
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <linux/stringify.h>
-
-#include <asm/config_mpc85xx.h>
-#define CONFIG_NAND_FSL_IFC
-
-#ifdef CONFIG_SDCARD
-#define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
-#define CONFIG_SPL_PAD_TO 0x18000
-#define CONFIG_SPL_MAX_SIZE (96 * 1024)
-#define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10)
-#define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
-#define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
-#define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10)
-#define CONFIG_SYS_MPC85XX_NO_RESETVEC
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SPL_COMMON_INIT_DDR
-#endif
-#endif
-
-#ifdef CONFIG_SPIFLASH
-#ifdef CONFIG_NXP_ESBC
-#define CONFIG_RAMBOOT_SPIFLASH
-#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
-#else
-#define CONFIG_SPL_SPI_FLASH_MINIMAL
-#define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
-#define CONFIG_SPL_PAD_TO 0x18000
-#define CONFIG_SPL_MAX_SIZE (96 * 1024)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10)
-#define CONFIG_SYS_MPC85XX_NO_RESETVEC
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SPL_COMMON_INIT_DDR
-#endif
-#endif
-#endif
-
-#ifdef CONFIG_MTD_RAW_NAND
-#ifdef CONFIG_NXP_ESBC
-#define CONFIG_SPL_INIT_MINIMAL
-#define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
-
-#define CONFIG_SPL_MAX_SIZE 8192
-#define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
-#define CONFIG_SPL_RELOC_STACK 0x00100000
-#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
-#define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
-#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0
-#else
-#ifdef CONFIG_TPL_BUILD
-#define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_NAND_INIT
-#define CONFIG_SPL_COMMON_INIT_DDR
-#define CONFIG_SPL_MAX_SIZE (128 << 10)
-#define CONFIG_TPL_TEXT_BASE 0xD0001000
-#define CONFIG_SYS_MPC85XX_NO_RESETVEC
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
-#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
-#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
-#elif defined(CONFIG_SPL_BUILD)
-#define CONFIG_SPL_INIT_MINIMAL
-#define CONFIG_SPL_NAND_MINIMAL
-#define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_MAX_SIZE 8192
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000
-#define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000
-#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
-#endif
-#define CONFIG_SPL_PAD_TO 0x20000
-#define CONFIG_TPL_PAD_TO 0x20000
-#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
-#endif
-#endif
-
-#ifdef CONFIG_NAND_SECBOOT /* NAND Boot */
-#define CONFIG_RAMBOOT_NAND
-#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
-#endif
-
-#ifndef CONFIG_RESET_VECTOR_ADDRESS
-#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
-#endif
-
-#ifdef CONFIG_TPL_BUILD
-#define CONFIG_SYS_MONITOR_BASE CONFIG_TPL_TEXT_BASE
-#elif defined(CONFIG_SPL_BUILD)
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
-#else
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-#endif
-
-/* High Level Configuration Options */
-#define CONFIG_SYS_HAS_SERDES /* common SERDES init code */
-
-#if defined(CONFIG_PCI)
-#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
-#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
-#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
-
-/*
- * PCI Windows
- * Memory space is mapped 1-1, but I/O space must start from 0.
- */
-/* controller 1, Slot 1, tgtid 1, Base address a000 */
-#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
-#else
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
-#endif
-#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
-#else
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
-#endif
-
-/* controller 2, Slot 2, tgtid 2, Base address 9000 */
-#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
-#else
-#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
-#endif
-#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
-#else
-#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
-#endif
-
-#if !defined(CONFIG_DM_PCI)
-#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_SYS_PCIE1_NAME "mini PCIe Slot"
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
-#else
-#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
-#endif
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
-
-#if defined(CONFIG_TARGET_P1010RDB_PA)
-#define CONFIG_SYS_PCIE2_NAME "PCIe Slot"
-#elif defined(CONFIG_TARGET_P1010RDB_PB)
-#define CONFIG_SYS_PCIE2_NAME "mini PCIe Slot"
-#endif
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
-#else
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
-#endif
-#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
-#endif
-
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#endif
-
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1010 RDB */
-#define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for P1010 RDB */
-
-#define CONFIG_HWCONFIG
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_L2_CACHE /* toggle L2 cache */
-#define CONFIG_BTB /* toggle branch predition */
-
-
-#define CONFIG_ENABLE_36BIT_PHYS
-
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_ADDR_MAP 1
-#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
-#endif
-
-/* DDR Setup */
-#define CONFIG_SYS_DDR_RAW_TIMING
-#define CONFIG_DDR_SPD
-#define CONFIG_SYS_SPD_BUS_NUM 1
-#define SPD_EEPROM_ADDRESS 0x52
-
-#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
-
-#ifndef __ASSEMBLY__
-extern unsigned long get_sdram_size(void);
-#endif
-#define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_CHIP_SELECTS_PER_CTRL 1
-
-/* DDR3 Controller Settings */
-#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
-#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
-#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
-#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
-#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
-#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
-#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
-#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
-#define CONFIG_SYS_DDR_SR_CNTR 0x00000000
-#define CONFIG_SYS_DDR_RCW_1 0x00000000
-#define CONFIG_SYS_DDR_RCW_2 0x00000000
-#define CONFIG_SYS_DDR_CONTROL 0xc70c0008 /* Type = DDR3 */
-#define CONFIG_SYS_DDR_CONTROL_2 0x24401000
-#define CONFIG_SYS_DDR_TIMING_4 0x00000001
-#define CONFIG_SYS_DDR_TIMING_5 0x03402400
-
-#define CONFIG_SYS_DDR_TIMING_3_800 0x00030000
-#define CONFIG_SYS_DDR_TIMING_0_800 0x00110104
-#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644
-#define CONFIG_SYS_DDR_TIMING_2_800 0x0FA888CF
-#define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000
-#define CONFIG_SYS_DDR_MODE_1_800 0x00441420
-#define CONFIG_SYS_DDR_MODE_2_800 0x00000000
-#define CONFIG_SYS_DDR_INTERVAL_800 0x0C300100
-#define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608
-
-/* settings for DDR3@667MT/s */
-#define CONFIG_SYS_DDR_TIMING_3_667 0x00010000
-#define CONFIG_SYS_DDR_TIMING_0_667 0x00110004
-#define CONFIG_SYS_DDR_TIMING_1_667 0x5d59e544
-#define CONFIG_SYS_DDR_TIMING_2_667 0x0FA890CD
-#define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000
-#define CONFIG_SYS_DDR_MODE_1_667 0x00441210
-#define CONFIG_SYS_DDR_MODE_2_667 0x00000000
-#define CONFIG_SYS_DDR_INTERVAL_667 0x0a280000
-#define CONFIG_SYS_DDR_WRLVL_CONTROL_667 0x8675F608
-
-#define CONFIG_SYS_CCSRBAR 0xffe00000
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
-
-/* Don't relocate CCSRBAR while in NAND_SPL */
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
-#endif
-
-/*
- * Memory map
- *
- * 0x0000_0000 0x3fff_ffff DDR 1G cacheable
- * 0x8000_0000 0xbfff_ffff PCI Express Mem 1.5G non-cacheable
- * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
- *
- * Localbus non-cacheable
- * 0xff80_0000 0xff8f_ffff NAND Flash 1M non-cacheable
- * 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable
- * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
- * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
- */
-
-/*
- * IFC Definitions
- */
-/* NOR Flash on IFC */
-
-#define CONFIG_SYS_FLASH_BASE 0xee000000
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */
-
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
-#else
-#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
-#endif
-
-#define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
- CSPR_PORT_SIZE_16 | \
- CSPR_MSEL_NOR | \
- CSPR_V)
-#define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024)
-#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7)
-/* NOR Flash Timing Params */
-#define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \
- FTIM0_NOR_TEADC(0x5) | \
- FTIM0_NOR_TEAHC(0x5)
-#define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \
- FTIM1_NOR_TRAD_NOR(0x0f)
-#define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \
- FTIM2_NOR_TCH(0x4) | \
- FTIM2_NOR_TWP(0x1c)
-#define CONFIG_SYS_NOR_FTIM3 0x0
-
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
-#define CONFIG_SYS_FLASH_QUIET_TEST
-#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
-
-#undef CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-
-/* CFI for NOR Flash */
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
-/* NAND Flash on IFC */
-#define CONFIG_SYS_NAND_BASE 0xff800000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
-#else
-#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
-#endif
-
-#define CONFIG_MTD_PARTITION
-
-#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
- | CSPR_PORT_SIZE_8 \
- | CSPR_MSEL_NAND \
- | CSPR_V)
-#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
-
-#if defined(CONFIG_TARGET_P1010RDB_PA)
-#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
- | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
- | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
- | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \
- | CSOR_NAND_PGS_512 /* Page Size = 512b */ \
- | CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \
- | CSOR_NAND_PB(32)) /* 32 Pages Per Block */
-#define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
-
-#elif defined(CONFIG_TARGET_P1010RDB_PB)
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
- | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
- | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
- | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
- | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
- | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
- | CSOR_NAND_PB(128)) /*Pages Per Block = 128 */
-#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
-#endif
-
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-
-#if defined(CONFIG_TARGET_P1010RDB_PA)
-/* NAND Flash Timing Params */
-#define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \
- FTIM0_NAND_TWP(0x0C) | \
- FTIM0_NAND_TWCHT(0x04) | \
- FTIM0_NAND_TWH(0x05)
-#define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \
- FTIM1_NAND_TWBE(0x1d) | \
- FTIM1_NAND_TRR(0x07) | \
- FTIM1_NAND_TRP(0x0c)
-#define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \
- FTIM2_NAND_TREH(0x05) | \
- FTIM2_NAND_TWHRE(0x0f)
-#define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
-
-#elif defined(CONFIG_TARGET_P1010RDB_PB)
-/* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */
-/* ONFI NAND Flash mode0 Timing Params */
-#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \
- FTIM0_NAND_TWP(0x18) | \
- FTIM0_NAND_TWCHT(0x07) | \
- FTIM0_NAND_TWH(0x0a))
-#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \
- FTIM1_NAND_TWBE(0x39) | \
- FTIM1_NAND_TRR(0x0e) | \
- FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
- FTIM2_NAND_TREH(0x0a) | \
- FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3 0x0
-#endif
-
-#define CONFIG_SYS_NAND_DDR_LAW 11
-
-/* Set up IFC registers for boot location NOR/NAND */
-#if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_NAND_SECBOOT)
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
-#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
-#else
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
-#endif
-
-/* CPLD on IFC */
-#define CONFIG_SYS_CPLD_BASE 0xffb00000
-
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull
-#else
-#define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
-#endif
-
-#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
- | CSPR_PORT_SIZE_8 \
- | CSPR_MSEL_GPCM \
- | CSPR_V)
-#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
-#define CONFIG_SYS_CSOR3 0x0
-/* CPLD Timing parameters for IFC CS3 */
-#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
- FTIM0_GPCM_TEADC(0x0e) | \
- FTIM0_GPCM_TEAHC(0x0e))
-#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
- FTIM1_GPCM_TRAD(0x1f))
-#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
- FTIM2_GPCM_TCH(0x8) | \
- FTIM2_GPCM_TWP(0x1f))
-#define CONFIG_SYS_CS3_FTIM3 0x0
-
-#if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \
- defined(CONFIG_RAMBOOT_NAND)
-#define CONFIG_SYS_RAMBOOT
-#else
-#undef CONFIG_SYS_RAMBOOT
-#endif
-
-#ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399
-#if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT)
-#define CONFIG_A003399_NOR_WORKAROUND
-#endif
-#endif
-
-#define CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
- - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
-
-/*
- * Config the L2 Cache as L2 SRAM
- */
-#if defined(CONFIG_SPL_BUILD)
-#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
-#define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
-#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
-#define CONFIG_SYS_L2_SIZE (256 << 10)
-#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
-#define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000
-#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
-#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
-#define CONFIG_SPL_RELOC_MALLOC_SIZE (128 << 10)
-#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 96 * 1024)
-#elif defined(CONFIG_MTD_RAW_NAND)
-#ifdef CONFIG_TPL_BUILD
-#define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
-#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
-#define CONFIG_SYS_L2_SIZE (256 << 10)
-#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
-#define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000
-#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
-#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
-#define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
-#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
-#else
-#define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
-#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
-#define CONFIG_SYS_L2_SIZE (256 << 10)
-#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
-#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000)
-#define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
-#endif
-#endif
-#endif
-
-/* Serial Port */
-#undef CONFIG_SERIAL_SOFTWARE_FIFO
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
-#define CONFIG_NS16550_MIN_FUNCTIONS
-#endif
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
-
-/* I2C */
-#ifndef CONFIG_DM_I2C
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-#define CONFIG_SYS_FSL_I2C2_SPEED 400000
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
-#else
-#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
-#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
-#endif
-#define I2C_PCA9557_ADDR1 0x18
-#define I2C_PCA9557_ADDR2 0x19
-#define I2C_PCA9557_BUS_NUM 0
-#define CONFIG_SYS_I2C_FSL
-
-/* I2C EEPROM */
-#if defined(CONFIG_TARGET_P1010RDB_PB)
-#define CONFIG_ID_EEPROM
-#ifdef CONFIG_ID_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#endif
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
-#define CONFIG_SYS_EEPROM_BUS_NUM 0
-#define MAX_NUM_PORTS 9 /* for 128Bytes EEPROM */
-#endif
-/* enable read and write access to EEPROM */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
-
-/* RTC */
-#define CONFIG_RTC_PT7C4338
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-
-/*
- * SPI interface will not be available in case of NAND boot SPI CS0 will be
- * used for SLIC
- */
-#if !defined(CONFIG_MTD_RAW_NAND) || !defined(CONFIG_NAND_SECBOOT)
-/* eSPI - Enhanced SPI */
-#endif
-
-#if defined(CONFIG_TSEC_ENET)
-#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
-#define CONFIG_TSEC1 1
-#define CONFIG_TSEC1_NAME "eTSEC1"
-#define CONFIG_TSEC2 1
-#define CONFIG_TSEC2_NAME "eTSEC2"
-#define CONFIG_TSEC3 1
-#define CONFIG_TSEC3_NAME "eTSEC3"
-
-#define TSEC1_PHY_ADDR 1
-#define TSEC2_PHY_ADDR 0
-#define TSEC3_PHY_ADDR 2
-
-#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-
-#define TSEC1_PHYIDX 0
-#define TSEC2_PHYIDX 0
-#define TSEC3_PHYIDX 0
-
-#define CONFIG_ETHPRIME "eTSEC1"
-
-/* TBI PHY configuration for SGMII mode */
-#define CONFIG_TSEC_TBICR_SETTINGS ( \
- TBICR_PHY_RESET \
- | TBICR_ANEG_ENABLE \
- | TBICR_FULL_DUPLEX \
- | TBICR_SPEED1_SET \
- )
-
-#endif /* CONFIG_TSEC_ENET */
-
-/* SATA */
-#define CONFIG_FSL_SATA_V2
-
-#ifdef CONFIG_FSL_SATA
-#define CONFIG_SYS_SATA_MAX_DEVICE 2
-#define CONFIG_SATA1
-#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
-#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
-#define CONFIG_SATA2
-#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
-#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
-
-#define CONFIG_LBA48
-#endif /* #ifdef CONFIG_FSL_SATA */
-
-#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
-#endif
-
-#define CONFIG_HAS_FSL_DR_USB
-
-#if defined(CONFIG_HAS_FSL_DR_USB)
-#ifdef CONFIG_USB_EHCI_HCD
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_USB_EHCI_FSL
-#endif
-#endif
-
-/*
- * Environment
- */
-#if defined(CONFIG_SDCARD)
-#define CONFIG_FSL_FIXED_MMC_LOCATION
-#define CONFIG_SYS_MMC_ENV_DEV 0
-#elif defined(CONFIG_MTD_RAW_NAND)
-#ifdef CONFIG_TPL_BUILD
-#define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
-#else
-#if defined(CONFIG_TARGET_P1010RDB_PA)
-#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */
-#elif defined(CONFIG_TARGET_P1010RDB_PB)
-#define CONFIG_ENV_RANGE (32 * CONFIG_ENV_SIZE) /* new block size 512K */
-#endif
-#endif
-#endif
-
-#define CONFIG_LOADS_ECHO /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI_HCD) \
- || defined(CONFIG_FSL_SATA)
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 64 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
-#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-
-#if defined(CONFIG_TSEC_ENET)
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#define CONFIG_HAS_ETH2
-#endif
-
-#define CONFIG_ROOTPATH "/opt/nfsroot"
-#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */
-
-/* default location for tftp and bootm */
-#define CONFIG_LOADADDR 1000000
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \
- "netdev=eth0\0" \
- "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
- "loadaddr=1000000\0" \
- "consoledev=ttyS0\0" \
- "ramdiskaddr=2000000\0" \
- "ramdiskfile=rootfs.ext2.gz.uboot\0" \
- "fdtaddr=1e00000\0" \
- "fdtfile=p1010rdb.dtb\0" \
- "bdev=sda1\0" \
- "hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \
- "othbootargs=ramdisk_size=600000\0" \
- "usbfatboot=setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs; " \
- "usb start;" \
- "fatload usb 0:2 $loadaddr $bootfile;" \
- "fatload usb 0:2 $fdtaddr $fdtfile;" \
- "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
- "usbext2boot=setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs; " \
- "usb start;" \
- "ext2load usb 0:4 $loadaddr $bootfile;" \
- "ext2load usb 0:4 $fdtaddr $fdtfile;" \
- "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
- CONFIG_BOOTMODE
-
-#if defined(CONFIG_TARGET_P1010RDB_PA)
-#define CONFIG_BOOTMODE \
- "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
- "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \
- "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
- "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \
- "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \
- "mw.b ffb00011 0; mw.b ffb00017 1; reset\0"
-
-#elif defined(CONFIG_TARGET_P1010RDB_PB)
-#define CONFIG_BOOTMODE \
- "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
- "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \
- "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
- "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \
- "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \
- "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \
- "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \
- "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \
- "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \
- "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0"
-#endif
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs; " \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
-
-#include <asm/fsl_secure_boot.h>
-
-#endif /* __CONFIG_H */
--
2.25.1
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 08/24] arm: Remove configs/P1020MBG-PC_36BIT_SDCARD_defconfig board
2020-05-27 16:46 [PATCH 00/24] spi: dm-conversion (part2) Jagan Teki
` (6 preceding siblings ...)
2020-05-27 16:46 ` [PATCH 07/24] arm: Remove configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig board Jagan Teki
@ 2020-05-27 16:46 ` Jagan Teki
2020-05-28 7:07 ` Priyanka Jain
2020-05-27 16:46 ` [PATCH 09/24] arm: Remove configs/P1022DS_36BIT_NAND_defconfig board Jagan Teki
` (14 subsequent siblings)
22 siblings, 1 reply; 59+ messages in thread
From: Jagan Teki @ 2020-05-27 16:46 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_SPI by the deadline.
Remove it.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
arch/powerpc/cpu/mpc85xx/Kconfig | 1 -
board/freescale/p1_p2_rdb_pc/Kconfig | 19 -
board/freescale/p1_p2_rdb_pc/MAINTAINERS | 51 --
board/freescale/p1_p2_rdb_pc/Makefile | 24 -
board/freescale/p1_p2_rdb_pc/README | 66 --
board/freescale/p1_p2_rdb_pc/ddr.c | 292 ------
board/freescale/p1_p2_rdb_pc/law.c | 22 -
board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 536 -----------
board/freescale/p1_p2_rdb_pc/spl.c | 123 ---
board/freescale/p1_p2_rdb_pc/spl_minimal.c | 63 --
board/freescale/p1_p2_rdb_pc/tlb.c | 110 ---
configs/P1020MBG-PC_36BIT_SDCARD_defconfig | 67 --
configs/P1020MBG-PC_36BIT_defconfig | 55 --
configs/P1020MBG-PC_SDCARD_defconfig | 66 --
configs/P1020MBG-PC_defconfig | 54 --
configs/P1020RDB-PC_36BIT_NAND_defconfig | 85 --
configs/P1020RDB-PC_36BIT_SDCARD_defconfig | 80 --
configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 82 --
configs/P1020RDB-PC_36BIT_defconfig | 69 --
configs/P1020RDB-PC_NAND_defconfig | 84 --
configs/P1020RDB-PC_SDCARD_defconfig | 79 --
configs/P1020RDB-PC_SPIFLASH_defconfig | 81 --
configs/P1020RDB-PC_defconfig | 68 --
configs/P1020RDB-PD_NAND_defconfig | 88 --
configs/P1020RDB-PD_SDCARD_defconfig | 83 --
configs/P1020RDB-PD_SPIFLASH_defconfig | 85 --
configs/P1020RDB-PD_defconfig | 72 --
configs/P1020UTM-PC_36BIT_SDCARD_defconfig | 67 --
configs/P1020UTM-PC_36BIT_defconfig | 55 --
configs/P1020UTM-PC_SDCARD_defconfig | 66 --
configs/P1020UTM-PC_defconfig | 54 --
configs/P1021RDB-PC_36BIT_NAND_defconfig | 84 --
configs/P1021RDB-PC_36BIT_SDCARD_defconfig | 79 --
configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig | 81 --
configs/P1021RDB-PC_36BIT_defconfig | 67 --
configs/P1021RDB-PC_NAND_defconfig | 83 --
configs/P1021RDB-PC_SDCARD_defconfig | 78 --
configs/P1021RDB-PC_SPIFLASH_defconfig | 80 --
configs/P1021RDB-PC_defconfig | 66 --
configs/P1024RDB_36BIT_defconfig | 61 --
configs/P1024RDB_NAND_defconfig | 77 --
configs/P1024RDB_SDCARD_defconfig | 71 --
configs/P1024RDB_SPIFLASH_defconfig | 73 --
configs/P1024RDB_defconfig | 60 --
configs/P1025RDB_36BIT_defconfig | 63 --
configs/P1025RDB_NAND_defconfig | 80 --
configs/P1025RDB_SDCARD_defconfig | 73 --
configs/P1025RDB_SPIFLASH_defconfig | 76 --
configs/P1025RDB_defconfig | 62 --
configs/P2020RDB-PC_36BIT_NAND_defconfig | 90 --
configs/P2020RDB-PC_36BIT_SDCARD_defconfig | 85 --
configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 87 --
configs/P2020RDB-PC_36BIT_defconfig | 74 --
configs/P2020RDB-PC_NAND_defconfig | 89 --
configs/P2020RDB-PC_SDCARD_defconfig | 84 --
configs/P2020RDB-PC_SPIFLASH_defconfig | 86 --
configs/P2020RDB-PC_defconfig | 73 --
include/configs/p1_p2_rdb_pc.h | 881 -------------------
58 files changed, 5610 deletions(-)
delete mode 100644 board/freescale/p1_p2_rdb_pc/Kconfig
delete mode 100644 board/freescale/p1_p2_rdb_pc/MAINTAINERS
delete mode 100644 board/freescale/p1_p2_rdb_pc/Makefile
delete mode 100644 board/freescale/p1_p2_rdb_pc/README
delete mode 100644 board/freescale/p1_p2_rdb_pc/ddr.c
delete mode 100644 board/freescale/p1_p2_rdb_pc/law.c
delete mode 100644 board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
delete mode 100644 board/freescale/p1_p2_rdb_pc/spl.c
delete mode 100644 board/freescale/p1_p2_rdb_pc/spl_minimal.c
delete mode 100644 board/freescale/p1_p2_rdb_pc/tlb.c
delete mode 100644 configs/P1020MBG-PC_36BIT_SDCARD_defconfig
delete mode 100644 configs/P1020MBG-PC_36BIT_defconfig
delete mode 100644 configs/P1020MBG-PC_SDCARD_defconfig
delete mode 100644 configs/P1020MBG-PC_defconfig
delete mode 100644 configs/P1020RDB-PC_36BIT_NAND_defconfig
delete mode 100644 configs/P1020RDB-PC_36BIT_SDCARD_defconfig
delete mode 100644 configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
delete mode 100644 configs/P1020RDB-PC_36BIT_defconfig
delete mode 100644 configs/P1020RDB-PC_NAND_defconfig
delete mode 100644 configs/P1020RDB-PC_SDCARD_defconfig
delete mode 100644 configs/P1020RDB-PC_SPIFLASH_defconfig
delete mode 100644 configs/P1020RDB-PC_defconfig
delete mode 100644 configs/P1020RDB-PD_NAND_defconfig
delete mode 100644 configs/P1020RDB-PD_SDCARD_defconfig
delete mode 100644 configs/P1020RDB-PD_SPIFLASH_defconfig
delete mode 100644 configs/P1020RDB-PD_defconfig
delete mode 100644 configs/P1020UTM-PC_36BIT_SDCARD_defconfig
delete mode 100644 configs/P1020UTM-PC_36BIT_defconfig
delete mode 100644 configs/P1020UTM-PC_SDCARD_defconfig
delete mode 100644 configs/P1020UTM-PC_defconfig
delete mode 100644 configs/P1021RDB-PC_36BIT_NAND_defconfig
delete mode 100644 configs/P1021RDB-PC_36BIT_SDCARD_defconfig
delete mode 100644 configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig
delete mode 100644 configs/P1021RDB-PC_36BIT_defconfig
delete mode 100644 configs/P1021RDB-PC_NAND_defconfig
delete mode 100644 configs/P1021RDB-PC_SDCARD_defconfig
delete mode 100644 configs/P1021RDB-PC_SPIFLASH_defconfig
delete mode 100644 configs/P1021RDB-PC_defconfig
delete mode 100644 configs/P1024RDB_36BIT_defconfig
delete mode 100644 configs/P1024RDB_NAND_defconfig
delete mode 100644 configs/P1024RDB_SDCARD_defconfig
delete mode 100644 configs/P1024RDB_SPIFLASH_defconfig
delete mode 100644 configs/P1024RDB_defconfig
delete mode 100644 configs/P1025RDB_36BIT_defconfig
delete mode 100644 configs/P1025RDB_NAND_defconfig
delete mode 100644 configs/P1025RDB_SDCARD_defconfig
delete mode 100644 configs/P1025RDB_SPIFLASH_defconfig
delete mode 100644 configs/P1025RDB_defconfig
delete mode 100644 configs/P2020RDB-PC_36BIT_NAND_defconfig
delete mode 100644 configs/P2020RDB-PC_36BIT_SDCARD_defconfig
delete mode 100644 configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
delete mode 100644 configs/P2020RDB-PC_36BIT_defconfig
delete mode 100644 configs/P2020RDB-PC_NAND_defconfig
delete mode 100644 configs/P2020RDB-PC_SDCARD_defconfig
delete mode 100644 configs/P2020RDB-PC_SPIFLASH_defconfig
delete mode 100644 configs/P2020RDB-PC_defconfig
delete mode 100644 include/configs/p1_p2_rdb_pc.h
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index ece589ba90..dbb991319b 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -1599,7 +1599,6 @@ source "board/freescale/mpc8569mds/Kconfig"
source "board/freescale/mpc8572ds/Kconfig"
source "board/freescale/p1022ds/Kconfig"
source "board/freescale/p1023rdb/Kconfig"
-source "board/freescale/p1_p2_rdb_pc/Kconfig"
source "board/freescale/p1_twr/Kconfig"
source "board/freescale/p2041rdb/Kconfig"
source "board/freescale/qemu-ppce500/Kconfig"
diff --git a/board/freescale/p1_p2_rdb_pc/Kconfig b/board/freescale/p1_p2_rdb_pc/Kconfig
deleted file mode 100644
index 2f9640b67c..0000000000
--- a/board/freescale/p1_p2_rdb_pc/Kconfig
+++ /dev/null
@@ -1,19 +0,0 @@
-if TARGET_P1020MBG || \
- TARGET_P1020RDB_PC || \
- TARGET_P1020RDB_PD || \
- TARGET_P1020UTM || \
- TARGET_P1021RDB || \
- TARGET_P1024RDB || \
- TARGET_P1025RDB || \
- TARGET_P2020RDB
-
-config SYS_BOARD
- default "p1_p2_rdb_pc"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "p1_p2_rdb_pc"
-
-endif
diff --git a/board/freescale/p1_p2_rdb_pc/MAINTAINERS b/board/freescale/p1_p2_rdb_pc/MAINTAINERS
deleted file mode 100644
index c2e924798e..0000000000
--- a/board/freescale/p1_p2_rdb_pc/MAINTAINERS
+++ /dev/null
@@ -1,51 +0,0 @@
-P1_P2_RDB_PC BOARD
-#M: -
-S: Maintained
-F: board/freescale/p1_p2_rdb_pc/
-F: include/configs/p1_p2_rdb_pc.h
-F: configs/P1020MBG-PC_defconfig
-F: configs/P1020MBG-PC_36BIT_defconfig
-F: configs/P1020MBG-PC_36BIT_SDCARD_defconfig
-F: configs/P1020MBG-PC_SDCARD_defconfig
-F: configs/P1020RDB-PC_defconfig
-F: configs/P1020RDB-PC_36BIT_defconfig
-F: configs/P1020RDB-PC_36BIT_NAND_defconfig
-F: configs/P1020RDB-PC_36BIT_SDCARD_defconfig
-F: configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
-F: configs/P1020RDB-PC_NAND_defconfig
-F: configs/P1020RDB-PC_SDCARD_defconfig
-F: configs/P1020RDB-PC_SPIFLASH_defconfig
-F: configs/P1020RDB-PD_defconfig
-F: configs/P1020RDB-PD_NAND_defconfig
-F: configs/P1020RDB-PD_SDCARD_defconfig
-F: configs/P1020RDB-PD_SPIFLASH_defconfig
-F: configs/P1020UTM-PC_defconfig
-F: configs/P1020UTM-PC_36BIT_defconfig
-F: configs/P1020UTM-PC_36BIT_SDCARD_defconfig
-F: configs/P1020UTM-PC_SDCARD_defconfig
-F: configs/P1021RDB-PC_defconfig
-F: configs/P1021RDB-PC_36BIT_defconfig
-F: configs/P1021RDB-PC_36BIT_NAND_defconfig
-F: configs/P1021RDB-PC_36BIT_SDCARD_defconfig
-F: configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig
-F: configs/P1021RDB-PC_NAND_defconfig
-F: configs/P1021RDB-PC_SDCARD_defconfig
-F: configs/P1021RDB-PC_SPIFLASH_defconfig
-F: configs/P1024RDB_defconfig
-F: configs/P1024RDB_36BIT_defconfig
-F: configs/P1024RDB_NAND_defconfig
-F: configs/P1024RDB_SDCARD_defconfig
-F: configs/P1024RDB_SPIFLASH_defconfig
-F: configs/P1025RDB_defconfig
-F: configs/P1025RDB_36BIT_defconfig
-F: configs/P1025RDB_NAND_defconfig
-F: configs/P1025RDB_SDCARD_defconfig
-F: configs/P1025RDB_SPIFLASH_defconfig
-F: configs/P2020RDB-PC_defconfig
-F: configs/P2020RDB-PC_36BIT_defconfig
-F: configs/P2020RDB-PC_36BIT_NAND_defconfig
-F: configs/P2020RDB-PC_36BIT_SDCARD_defconfig
-F: configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
-F: configs/P2020RDB-PC_NAND_defconfig
-F: configs/P2020RDB-PC_SDCARD_defconfig
-F: configs/P2020RDB-PC_SPIFLASH_defconfig
diff --git a/board/freescale/p1_p2_rdb_pc/Makefile b/board/freescale/p1_p2_rdb_pc/Makefile
deleted file mode 100644
index a7736d8332..0000000000
--- a/board/freescale/p1_p2_rdb_pc/Makefile
+++ /dev/null
@@ -1,24 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2010-2011 Freescale Semiconductor, Inc.
-
-MINIMAL=
-
-ifdef CONFIG_SPL_BUILD
-ifdef CONFIG_SPL_INIT_MINIMAL
-MINIMAL=y
-endif
-endif
-
-ifdef MINIMAL
-obj-y += spl_minimal.o
-else
-ifdef CONFIG_SPL_BUILD
-obj-y += spl.o
-endif
-obj-y += p1_p2_rdb_pc.o
-obj-y += ddr.o
-endif
-
-obj-y += law.o
-obj-y += tlb.o
diff --git a/board/freescale/p1_p2_rdb_pc/README b/board/freescale/p1_p2_rdb_pc/README
deleted file mode 100644
index b85cf0209e..0000000000
--- a/board/freescale/p1_p2_rdb_pc/README
+++ /dev/null
@@ -1,66 +0,0 @@
-Overview
---------
-P1_P2_RDB_PC represents a set of boards including
- P1020MSBG-PC
- P1020RDB-PC
- P1020RDB-PD
- P1020UTM-PC
- P1021RDB-PC
- P1024RDB
- P1025RDB
- P2020RDB-PC
-
-They have similar design of P1020RDB but have DDR3 instead of DDR2. P2020RDB-PC
-has 64-bit DDR. All others have 32-bit DDR.
-
-Key features on these boards include:
- * DDR3
- * NOR flash
- * NAND flash (on RDB's only)
- * SPI flash (on RDB's only)
- * SDHC/MMC card slot
- * VSC7385 Ethernet switch (on P1020MBG, P1020RDB, & P1021RDB)
- * PCIE slot and mini-PCIE slots
-
-As these boards use soldered DDR chips not regular DIMMs, an on-board EEPROM
-is used to store SPD data. In case of absent or corrupted SPD, falling back
-to timing data embedded in the source code will be used. Raw timing data is
-extracted from DDR chip datasheet. Different speeds of DDR are supported with
-this approach. ODT option is forced to fit this set of boards, again because
-they don't have regular DIMMs.
-
-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS is defined as 5ms to meet specification
-for writing timing.
-
-VSC firmware Address is defined by default in config file for eTSEC1.
-
-SD width is based off DIP switch. DIP switch is detected on the
-board by reading i2c bus and setting the appropriate mux values.
-
-Some boards have QE module in the silicon (P1021 and P1025). QE and eLBC have
-pins multiplexing. QE function needs to be disabled to access Nor Flash and
-CPLD. QE-UEC and QE-UART can be enabled for linux kernel by setting "qe"
-in hwconfig. In addition, QE-UEC and QE-TDM also have pins multiplexing, to
-enable QE-TDM for linux kernel, set "qe;tdm" in hwconfig. Syntax is as below
-
-'setenv hwconfig qe' to enable QE UEC/UART and disable Nor-Flash/CPLD.
-'setenv hwconfig 'qe;tdm'' to enalbe QE TDM and disable Nor-Flash/CPLD.
-
-Device tree support and how to enable it for different configs
---------------------------------------------------------------
-Device tree support is available for p1020rdb and p2020rdb for below mentioned boot,
-1. NOR Boot
-2. NAND Boot
-3. SD Boot
-4. SPIFLASH Boot
-
-To enable device tree support for other boot, below configs need to be
-enabled in relative defconfig file,
-1. CONFIG_DEFAULT_DEVICE_TREE="p1020rdb" (Change default device tree name if required)
-2. CONFIG_OF_CONTROL
-3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at
- CONFIG_RESET_VECTOR_ADDRESS - 0xffc
-
-If device tree support is enabled in defconfig,
-1. use 'u-boot-with-dtb.bin' for NOR boot.
-2. use 'u-boot-with-spl.bin' for other boot.
diff --git a/board/freescale/p1_p2_rdb_pc/ddr.c b/board/freescale/p1_p2_rdb_pc/ddr.c
deleted file mode 100644
index 2346f6a0c2..0000000000
--- a/board/freescale/p1_p2_rdb_pc/ddr.c
+++ /dev/null
@@ -1,292 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright 2010-2011 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <vsprintf.h>
-#include <asm/mmu.h>
-#include <asm/immap_85xx.h>
-#include <asm/processor.h>
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-#include <asm/io.h>
-#include <asm/fsl_law.h>
-
-#ifdef CONFIG_SYS_DDR_RAW_TIMING
-#if defined(CONFIG_P1020RDB_PROTO) || \
- defined(CONFIG_TARGET_P1021RDB) || \
- defined(CONFIG_TARGET_P1020UTM)
-/* Micron MT41J256M8_187E */
-dimm_params_t ddr_raw_timing = {
- .n_ranks = 1,
- .rank_density = 1073741824u,
- .capacity = 1073741824u,
- .primary_sdram_width = 32,
- .ec_sdram_width = 0,
- .registered_dimm = 0,
- .mirrored_dimm = 0,
- .n_row_addr = 15,
- .n_col_addr = 10,
- .n_banks_per_sdram_device = 8,
- .edc_config = 0,
- .burst_lengths_bitmask = 0x0c,
-
- .tckmin_x_ps = 1870,
- .caslat_x = 0x1e << 4, /* 5,6,7,8 */
- .taa_ps = 13125,
- .twr_ps = 15000,
- .trcd_ps = 13125,
- .trrd_ps = 7500,
- .trp_ps = 13125,
- .tras_ps = 37500,
- .trc_ps = 50625,
- .trfc_ps = 160000,
- .twtr_ps = 7500,
- .trtp_ps = 7500,
- .refresh_rate_ps = 7800000,
- .tfaw_ps = 37500,
-};
-#elif defined(CONFIG_TARGET_P2020RDB)
-/* Micron MT41J128M16_15E */
-dimm_params_t ddr_raw_timing = {
- .n_ranks = 1,
- .rank_density = 1073741824u,
- .capacity = 1073741824u,
- .primary_sdram_width = 64,
- .ec_sdram_width = 0,
- .registered_dimm = 0,
- .mirrored_dimm = 0,
- .n_row_addr = 14,
- .n_col_addr = 10,
- .n_banks_per_sdram_device = 8,
- .edc_config = 0,
- .burst_lengths_bitmask = 0x0c,
-
- .tckmin_x_ps = 1500,
- .caslat_x = 0x7e << 4, /* 5,6,7,8,9,10 */
- .taa_ps = 13500,
- .twr_ps = 15000,
- .trcd_ps = 13500,
- .trrd_ps = 6000,
- .trp_ps = 13500,
- .tras_ps = 36000,
- .trc_ps = 49500,
- .trfc_ps = 160000,
- .twtr_ps = 7500,
- .trtp_ps = 7500,
- .refresh_rate_ps = 7800000,
- .tfaw_ps = 30000,
-};
-#elif (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
-/* Micron MT41J512M8_187E */
-dimm_params_t ddr_raw_timing = {
- .n_ranks = 2,
- .rank_density = 1073741824u,
- .capacity = 2147483648u,
- .primary_sdram_width = 32,
- .ec_sdram_width = 0,
- .registered_dimm = 0,
- .mirrored_dimm = 0,
- .n_row_addr = 15,
- .n_col_addr = 10,
- .n_banks_per_sdram_device = 8,
- .edc_config = 0,
- .burst_lengths_bitmask = 0x0c,
-
- .tckmin_x_ps = 1870,
- .caslat_x = 0x1e << 4, /* 5,6,7,8 */
- .taa_ps = 13125,
- .twr_ps = 15000,
- .trcd_ps = 13125,
- .trrd_ps = 7500,
- .trp_ps = 13125,
- .tras_ps = 37500,
- .trc_ps = 50625,
- .trfc_ps = 160000,
- .twtr_ps = 7500,
- .trtp_ps = 7500,
- .refresh_rate_ps = 7800000,
- .tfaw_ps = 37500,
-};
-#elif defined(CONFIG_TARGET_P1020RDB_PC)
-/*
- * Samsung K4B2G0846C-HCF8
- * The following timing are for "downshift"
- * i.e. to use CL9 part as CL7
- * otherwise, tAA, tRCD, tRP will be 13500ps
- * and tRC will be 49500ps
- */
-dimm_params_t ddr_raw_timing = {
- .n_ranks = 1,
- .rank_density = 1073741824u,
- .capacity = 1073741824u,
- .primary_sdram_width = 32,
- .ec_sdram_width = 0,
- .registered_dimm = 0,
- .mirrored_dimm = 0,
- .n_row_addr = 15,
- .n_col_addr = 10,
- .n_banks_per_sdram_device = 8,
- .edc_config = 0,
- .burst_lengths_bitmask = 0x0c,
-
- .tckmin_x_ps = 1875,
- .caslat_x = 0x1e << 4, /* 5,6,7,8 */
- .taa_ps = 13125,
- .twr_ps = 15000,
- .trcd_ps = 13125,
- .trrd_ps = 7500,
- .trp_ps = 13125,
- .tras_ps = 37500,
- .trc_ps = 50625,
- .trfc_ps = 160000,
- .twtr_ps = 7500,
- .trtp_ps = 7500,
- .refresh_rate_ps = 7800000,
- .tfaw_ps = 37500,
-};
-#elif defined(CONFIG_TARGET_P1024RDB) || \
- defined(CONFIG_TARGET_P1025RDB)
-/*
- * Samsung K4B2G0846C-HCH9
- * The following timing are for "downshift"
- * i.e. to use CL9 part as CL7
- * otherwise, tAA, tRCD, tRP will be 13500ps
- * and tRC will be 49500ps
- */
-dimm_params_t ddr_raw_timing = {
- .n_ranks = 1,
- .rank_density = 1073741824u,
- .capacity = 1073741824u,
- .primary_sdram_width = 32,
- .ec_sdram_width = 0,
- .registered_dimm = 0,
- .mirrored_dimm = 0,
- .n_row_addr = 15,
- .n_col_addr = 10,
- .n_banks_per_sdram_device = 8,
- .edc_config = 0,
- .burst_lengths_bitmask = 0x0c,
-
- .tckmin_x_ps = 1500,
- .caslat_x = 0x3e << 4, /* 5,6,7,8,9 */
- .taa_ps = 13125,
- .twr_ps = 15000,
- .trcd_ps = 13125,
- .trrd_ps = 6000,
- .trp_ps = 13125,
- .tras_ps = 36000,
- .trc_ps = 49125,
- .trfc_ps = 160000,
- .twtr_ps = 7500,
- .trtp_ps = 7500,
- .refresh_rate_ps = 7800000,
- .tfaw_ps = 30000,
-};
-#else
-#error Missing raw timing data for this board
-#endif
-
-int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
- unsigned int controller_number,
- unsigned int dimm_number)
-{
- const char dimm_model[] = "Fixed DDR on board";
-
- if ((controller_number == 0) && (dimm_number == 0)) {
- memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
- memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
- memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
- }
-
- return 0;
-}
-#endif /* CONFIG_SYS_DDR_RAW_TIMING */
-
-#ifdef CONFIG_SYS_DDR_CS0_BNDS
-/* Fixed sdram init -- doesn't use serial presence detect. */
-phys_size_t fixed_sdram(void)
-{
- sys_info_t sysinfo;
- char buf[32];
- size_t ddr_size;
- fsl_ddr_cfg_regs_t ddr_cfg_regs = {
- .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
- .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
- .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
-#if CONFIG_CHIP_SELECTS_PER_CTRL > 1
- .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
- .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
- .cs[1].config_2 = CONFIG_SYS_DDR_CS1_CONFIG_2,
-#endif
- .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3,
- .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0,
- .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1,
- .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2,
- .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
- .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
- .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1,
- .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2,
- .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
- .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL,
- .ddr_data_init = CONFIG_SYS_DDR_DATA_INIT,
- .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL,
- .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
- .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
- .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
- .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
- .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
- .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
- .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
- .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
- .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
- };
-
- get_sys_info(&sysinfo);
- printf("Configuring DDR for %s MT/s data rate\n",
- strmhz(buf, sysinfo.freq_ddrbus));
-
- ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
-
- fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
-
- if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
- ddr_size, LAW_TRGT_IF_DDR_1) < 0) {
- printf("ERROR setting Local Access Windows for DDR\n");
- return 0;
- };
-
- return ddr_size;
-}
-#endif
-
-void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- int i;
- popts->clk_adjust = 6;
- popts->cpo_override = 0x1f;
- popts->write_data_delay = 2;
- popts->half_strength_driver_enable = 1;
- /* Write leveling override */
- popts->wrlvl_en = 1;
- popts->wrlvl_override = 1;
- popts->wrlvl_sample = 0xf;
- popts->wrlvl_start = 0x8;
- popts->trwt_override = 1;
- popts->trwt = 0;
-
- if (pdimm->primary_sdram_width == 64)
- popts->data_bus_width = 0;
- else if (pdimm->primary_sdram_width == 32)
- popts->data_bus_width = 1;
- else
- printf("Error in DDR bus width configuration!\n");
-
- for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
- popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
- popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
- }
-}
diff --git a/board/freescale/p1_p2_rdb_pc/law.c b/board/freescale/p1_p2_rdb_pc/law.c
deleted file mode 100644
index 5f4d713ca5..0000000000
--- a/board/freescale/p1_p2_rdb_pc/law.c
+++ /dev/null
@@ -1,22 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2010-2011 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-struct law_entry law_table[] = {
- SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
- SET_LAW(CONFIG_SYS_PMC_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC),
-#ifdef CONFIG_VSC7385_ENET
- SET_LAW(CONFIG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
-#endif
- SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
-#ifdef CONFIG_SYS_NAND_BASE_PHYS
- SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_32K, LAW_TRGT_IF_LBC),
-#endif
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
deleted file mode 100644
index 1353debc0e..0000000000
--- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
+++ /dev/null
@@ -1,536 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2010-2011, 2013 Freescale Semiconductor, Inc.
- * Copyright 2020 NXP
- */
-
-#include <common.h>
-#include <command.h>
-#include <env.h>
-#include <hang.h>
-#include <hwconfig.h>
-#include <image.h>
-#include <init.h>
-#include <net.h>
-#include <pci.h>
-#include <i2c.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_pci.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/io.h>
-#include <asm/fsl_law.h>
-#include <asm/fsl_lbc.h>
-#include <asm/mp.h>
-#include <miiphy.h>
-#include <linux/delay.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <fsl_mdio.h>
-#include <tsec.h>
-#include <vsc7385.h>
-#include <ioports.h>
-#include <asm/fsl_serdes.h>
-#include <netdev.h>
-
-#ifdef CONFIG_QE
-
-#define GPIO_GETH_SW_PORT 1
-#define GPIO_GETH_SW_PIN 29
-#define GPIO_GETH_SW_DATA (1 << (31 - GPIO_GETH_SW_PIN))
-
-#define GPIO_SLIC_PORT 1
-#define GPIO_SLIC_PIN 30
-#define GPIO_SLIC_DATA (1 << (31 - GPIO_SLIC_PIN))
-
-#if defined(CONFIG_TARGET_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
-#define GPIO_DDR_RST_PORT 1
-#define GPIO_DDR_RST_PIN 8
-#define GPIO_DDR_RST_DATA (1 << (31 - GPIO_DDR_RST_PIN))
-
-#define GPIO_2BIT_MASK (0x3 << (32 - (GPIO_DDR_RST_PIN + 1) * 2))
-#endif
-
-#if defined(CONFIG_TARGET_P1025RDB) || defined(CONFIG_TARGET_P1021RDB)
-#define PCA_IOPORT_I2C_ADDR 0x23
-#define PCA_IOPORT_OUTPUT_CMD 0x2
-#define PCA_IOPORT_CFG_CMD 0x6
-#define PCA_IOPORT_QE_PIN_ENABLE 0xf8
-#define PCA_IOPORT_QE_TDM_ENABLE 0xf6
-#endif
-
-const qe_iop_conf_t qe_iop_conf_tab[] = {
- /* GPIO */
- {1, 1, 2, 0, 0}, /* GPIO7/PB1 - LOAD_DEFAULT_N */
-#if defined(CONFIG_TARGET_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
- {1, 8, 1, 1, 0}, /* GPIO10/PB8 - DDR_RST */
-#endif
- {0, 15, 1, 0, 0}, /* GPIO11/A15 - WDI */
- {GPIO_GETH_SW_PORT, GPIO_GETH_SW_PIN, 1, 0, 0}, /* RST_GETH_SW_N */
- {GPIO_SLIC_PORT, GPIO_SLIC_PIN, 1, 0, 0}, /* RST_SLIC_N */
-
-#ifdef CONFIG_TARGET_P1025RDB
- /* QE_MUX_MDC */
- {1, 19, 1, 0, 1}, /* QE_MUX_MDC */
-
- /* QE_MUX_MDIO */
- {1, 20, 3, 0, 1}, /* QE_MUX_MDIO */
-
- /* UCC_1_MII */
- {0, 23, 2, 0, 2}, /* CLK12 */
- {0, 24, 2, 0, 1}, /* CLK9 */
- {0, 7, 1, 0, 2}, /* ENET1_TXD0_SER1_TXD0 */
- {0, 9, 1, 0, 2}, /* ENET1_TXD1_SER1_TXD1 */
- {0, 11, 1, 0, 2}, /* ENET1_TXD2_SER1_TXD2 */
- {0, 12, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3 */
- {0, 6, 2, 0, 2}, /* ENET1_RXD0_SER1_RXD0 */
- {0, 10, 2, 0, 2}, /* ENET1_RXD1_SER1_RXD1 */
- {0, 14, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2 */
- {0, 15, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3 */
- {0, 5, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */
- {0, 13, 1, 0, 2}, /* ENET1_TX_ER */
- {0, 4, 2, 0, 2}, /* ENET1_RX_DV_SER1_CTS_B */
- {0, 8, 2, 0, 2}, /* ENET1_RX_ER_SER1_CD_B */
- {0, 17, 2, 0, 2}, /* ENET1_CRS */
- {0, 16, 2, 0, 2}, /* ENET1_COL */
-
- /* UCC_5_RMII */
- {1, 11, 2, 0, 1}, /* CLK13 */
- {1, 7, 1, 0, 2}, /* ENET5_TXD0_SER5_TXD0 */
- {1, 10, 1, 0, 2}, /* ENET5_TXD1_SER5_TXD1 */
- {1, 6, 2, 0, 2}, /* ENET5_RXD0_SER5_RXD0 */
- {1, 9, 2, 0, 2}, /* ENET5_RXD1_SER5_RXD1 */
- {1, 5, 1, 0, 2}, /* ENET5_TX_EN_SER5_RTS_B */
- {1, 4, 2, 0, 2}, /* ENET5_RX_DV_SER5_CTS_B */
- {1, 8, 2, 0, 2}, /* ENET5_RX_ER_SER5_CD_B */
-#endif
-
- {0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */
-};
-#endif
-
-struct cpld_data {
- u8 cpld_rev_major;
- u8 pcba_rev;
- u8 wd_cfg;
- u8 rst_bps_sw;
- u8 load_default_n;
- u8 rst_bps_wd;
- u8 bypass_enable;
- u8 bps_led;
- u8 status_led; /* offset: 0x8 */
- u8 fxo_led; /* offset: 0x9 */
- u8 fxs_led; /* offset: 0xa */
- u8 rev4[2];
- u8 system_rst; /* offset: 0xd */
- u8 bps_out;
- u8 rev5[3];
- u8 cpld_rev_minor;
-};
-
-#define CPLD_WD_CFG 0x03
-#define CPLD_RST_BSW 0x00
-#define CPLD_RST_BWD 0x00
-#define CPLD_BYPASS_EN 0x03
-#define CPLD_STATUS_LED 0x01
-#define CPLD_FXO_LED 0x01
-#define CPLD_FXS_LED 0x0F
-#define CPLD_SYS_RST 0x00
-
-void board_cpld_init(void)
-{
- struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
-
- out_8(&cpld_data->wd_cfg, CPLD_WD_CFG);
- out_8(&cpld_data->status_led, CPLD_STATUS_LED);
- out_8(&cpld_data->fxo_led, CPLD_FXO_LED);
- out_8(&cpld_data->fxs_led, CPLD_FXS_LED);
- out_8(&cpld_data->system_rst, CPLD_SYS_RST);
-}
-
-void board_gpio_init(void)
-{
-#ifdef CONFIG_QE
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- par_io_t *par_io = (par_io_t *) &(gur->qe_par_io);
-
-#if defined(CONFIG_TARGET_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
- /* reset DDR3 */
- setbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdat, GPIO_DDR_RST_DATA);
- udelay(1000);
- clrbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdat, GPIO_DDR_RST_DATA);
- udelay(1000);
- setbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdat, GPIO_DDR_RST_DATA);
- /* disable CE_PB8 */
- clrbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdir1, GPIO_2BIT_MASK);
-#endif
- /* Enable VSC7385 switch */
- setbits_be32(&par_io[GPIO_GETH_SW_PORT].cpdat, GPIO_GETH_SW_DATA);
-
- /* Enable SLIC */
- setbits_be32(&par_io[GPIO_SLIC_PORT].cpdat, GPIO_SLIC_DATA);
-#else
-
- ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
-
- /*
- * GPIO10 DDR Reset, open drain
- * GPIO7 LOAD_DEFAULT_N Input
- * GPIO11 WDI (watchdog input)
- * GPIO12 Ethernet Switch Reset
- * GPIO13 SLIC Reset
- */
-
- setbits_be32(&pgpio->gpdir, 0x02130000);
-#if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SPL)
- /* init DDR3 reset signal */
- setbits_be32(&pgpio->gpdir, 0x00200000);
- setbits_be32(&pgpio->gpodr, 0x00200000);
- clrbits_be32(&pgpio->gpdat, 0x00200000);
- udelay(1000);
- setbits_be32(&pgpio->gpdat, 0x00200000);
- udelay(1000);
- clrbits_be32(&pgpio->gpdir, 0x00200000);
-#endif
-
-#ifdef CONFIG_VSC7385_ENET
- /* reset VSC7385 Switch */
- setbits_be32(&pgpio->gpdir, 0x00080000);
- setbits_be32(&pgpio->gpdat, 0x00080000);
-#endif
-
-#ifdef CONFIG_SLIC
- /* reset SLIC */
- setbits_be32(&pgpio->gpdir, 0x00040000);
- setbits_be32(&pgpio->gpdat, 0x00040000);
-#endif
-#endif
-}
-
-int board_early_init_f(void)
-{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-
- setbits_be32(&gur->pmuxcr,
- (MPC85xx_PMUXCR_SDHC_CD | MPC85xx_PMUXCR_SDHC_WP));
- clrbits_be32(&gur->sdhcdcr, SDHCDCR_CD_INV);
-
- clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
- setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TDM_ENA);
-
- board_gpio_init();
- board_cpld_init();
-
- return 0;
-}
-
-int checkboard(void)
-{
- struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- u8 in, out, io_config, val;
- int bus_num = CONFIG_SYS_SPD_BUS_NUM;
-
- printf("Board: %s CPLD: V%d.%d PCBA: V%d.0\n", CONFIG_BOARDNAME,
- in_8(&cpld_data->cpld_rev_major) & 0x0F,
- in_8(&cpld_data->cpld_rev_minor) & 0x0F,
- in_8(&cpld_data->pcba_rev) & 0x0F);
-
- /* Initialize i2c early for rom_loc and flash bank information */
- #if defined(CONFIG_DM_I2C)
- struct udevice *dev;
- int ret;
-
- ret = i2c_get_chip_for_busnum(bus_num, CONFIG_SYS_I2C_PCA9557_ADDR,
- 1, &dev);
- if (ret) {
- printf("%s: Cannot find udev for a bus %d\n", __func__,
- bus_num);
- return -ENXIO;
- }
-
- if (dm_i2c_read(dev, 0, &in, 1) < 0 ||
- dm_i2c_read(dev, 1, &out, 1) < 0 ||
- dm_i2c_read(dev, 3, &io_config, 1) < 0) {
- printf("Error reading i2c boot information!\n");
- return 0; /* Don't want to hang() on this error */
- }
- #else /* Non DM I2C support - will be removed */
- i2c_set_bus_num(bus_num);
-
- if (i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 0, 1, &in, 1) < 0 ||
- i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 1, 1, &out, 1) < 0 ||
- i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 3, 1, &io_config, 1) < 0) {
- printf("Error reading i2c boot information!\n");
- return 0; /* Don't want to hang() on this error */
- }
- #endif
-
- val = (in & io_config) | (out & (~io_config));
-
- puts("rom_loc: ");
- if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SD) {
- puts("sd");
-#ifdef __SW_BOOT_SPI
- } else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SPI) {
- puts("spi");
-#endif
-#ifdef __SW_BOOT_NAND
- } else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_NAND) {
- puts("nand");
-#endif
-#ifdef __SW_BOOT_PCIE
- } else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_PCIE) {
- puts("pcie");
-#endif
- } else {
- if (val & 0x2)
- puts("nor lower bank");
- else
- puts("nor upper bank");
- }
- puts("\n");
-
- if (val & 0x1) {
- setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
- puts("SD/MMC : 8-bit Mode\n");
- puts("eSPI : Disabled\n");
- } else {
- puts("SD/MMC : 4-bit Mode\n");
- puts("eSPI : Enabled\n");
- }
-
- return 0;
-}
-
-#if defined(CONFIG_PCI) && !defined(CONFIG_DM_PCI)
-void pci_init_board(void)
-{
- fsl_pcie_init_board(0);
-}
-#endif
-
-int board_early_init_r(void)
-{
- const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
- int flash_esel = find_tlb_idx((void *)flashbase, 1);
-
- /*
- * Remap Boot flash region to caching-inhibited
- * so that flash can be erased properly.
- */
-
- /* Flush d-cache and invalidate i-cache of any FLASH data */
- flush_dcache();
- invalidate_icache();
-
- if (flash_esel == -1) {
- /* very unlikely unless something is messed up */
- puts("Error: Could not find TLB for FLASH BASE\n");
- flash_esel = 2; /* give our best effort to continue */
- } else {
- /* invalidate existing TLB entry for flash */
- disable_tlb(flash_esel);
- }
-
- set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,/* perms, wimge */
- 0, flash_esel, BOOKE_PAGESZ_64M, 1);/* ts, esel, tsize, iprot */
- return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
- struct fsl_pq_mdio_info mdio_info;
- struct tsec_info_struct tsec_info[4];
- ccsr_gur_t *gur __attribute__((unused)) =
- (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- int num = 0;
-#ifdef CONFIG_VSC7385_ENET
- char *tmp;
- unsigned int vscfw_addr;
-#endif
-
-#ifdef CONFIG_TSEC1
- SET_STD_TSEC_INFO(tsec_info[num], 1);
- num++;
-#endif
-#ifdef CONFIG_TSEC2
- SET_STD_TSEC_INFO(tsec_info[num], 2);
- if (is_serdes_configured(SGMII_TSEC2)) {
- printf("eTSEC2 is in sgmii mode.\n");
- tsec_info[num].flags |= TSEC_SGMII;
- }
- num++;
-#endif
-#ifdef CONFIG_TSEC3
- SET_STD_TSEC_INFO(tsec_info[num], 3);
- num++;
-#endif
-
- if (!num) {
- printf("No TSECs initialized\n");
- return 0;
- }
-
-#ifdef CONFIG_VSC7385_ENET
- /* If a VSC7385 microcode image is present, then upload it. */
- tmp = env_get("vscfw_addr");
- if (tmp) {
- vscfw_addr = simple_strtoul(tmp, NULL, 16);
- printf("uploading VSC7385 microcode from %x\n", vscfw_addr);
- if (vsc7385_upload_firmware((void *) vscfw_addr,
- CONFIG_VSC7385_IMAGE_SIZE))
- puts("Failure uploading VSC7385 microcode.\n");
- } else
- puts("No address specified for VSC7385 microcode.\n");
-#endif
-
- mdio_info.regs = TSEC_GET_MDIO_REGS_BASE(1);
- mdio_info.name = DEFAULT_MII_NAME;
-
- fsl_pq_mdio_init(bis, &mdio_info);
-
- tsec_eth_init(bis, tsec_info, num);
-
-#if defined(CONFIG_UEC_ETH)
- /* QE0 and QE3 need to be exposed for UCC1 and UCC5 Eth mode */
- setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE0);
- setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE3);
-
- uec_standard_init(bis);
-#endif
-
- return pci_eth_init(bis);
-}
-
-#if defined(CONFIG_QE) && \
- (defined(CONFIG_TARGET_P1025RDB) || defined(CONFIG_TARGET_P1021RDB))
-static void fdt_board_fixup_qe_pins(void *blob)
-{
- unsigned int oldbus;
- u8 val8;
- int node;
- fsl_lbc_t *lbc = LBC_BASE_ADDR;
-
- if (hwconfig("qe")) {
- /* For QE and eLBC pins multiplexing,
- * there is a PCA9555 device on P1025RDB.
- * It control the multiplex pins' functions,
- * and setting the PCA9555 can switch the
- * function between QE and eLBC.
- */
- oldbus = i2c_get_bus_num();
- i2c_set_bus_num(0);
- if (hwconfig("tdm"))
- val8 = PCA_IOPORT_QE_TDM_ENABLE;
- else
- val8 = PCA_IOPORT_QE_PIN_ENABLE;
- i2c_write(PCA_IOPORT_I2C_ADDR, PCA_IOPORT_CFG_CMD,
- 1, &val8, 1);
- i2c_write(PCA_IOPORT_I2C_ADDR, PCA_IOPORT_OUTPUT_CMD,
- 1, &val8, 1);
- i2c_set_bus_num(oldbus);
- /* if run QE TDM, Set ABSWP to implement
- * conversion of addresses in the eLBC.
- */
- if (hwconfig("tdm")) {
- set_lbc_or(2, CONFIG_PMC_OR_PRELIM);
- set_lbc_br(2, CONFIG_PMC_BR_PRELIM);
- setbits_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
- }
- } else {
- node = fdt_path_offset(blob, "/qe");
- if (node >= 0)
- fdt_del_node(blob, node);
- }
-
- return;
-}
-#endif
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int ft_board_setup(void *blob, bd_t *bd)
-{
- phys_addr_t base;
- phys_size_t size;
-#if defined(CONFIG_TARGET_P1020RDB_PD) || defined(CONFIG_TARGET_P1020RDB_PC)
- const char *soc_usb_compat = "fsl-usb2-dr";
- int usb_err, usb1_off, usb2_off;
-#endif
-#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
- int err;
-#endif
-
- ft_cpu_setup(blob, bd);
-
- base = env_get_bootm_low();
- size = env_get_bootm_size();
-
- fdt_fixup_memory(blob, (u64)base, (u64)size);
-
-#if !defined(CONFIG_DM_PCI)
- FT_FSL_PCI_SETUP;
-#endif
-
-#ifdef CONFIG_QE
- do_fixup_by_compat(blob, "fsl,qe", "status", "okay",
- sizeof("okay"), 0);
-#if defined(CONFIG_TARGET_P1025RDB) || defined(CONFIG_TARGET_P1021RDB)
- fdt_board_fixup_qe_pins(blob);
-#endif
-#endif
-
-#if defined(CONFIG_HAS_FSL_DR_USB)
- fsl_fdt_fixup_dr_usb(blob, bd);
-#endif
-
-#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
- /* Delete eLBC node as it is muxed with USB2 controller */
- if (hwconfig("usb2")) {
- const char *soc_elbc_compat = "fsl,p1020-elbc";
- int off = fdt_node_offset_by_compatible(blob, -1,
- soc_elbc_compat);
- if (off < 0) {
- printf("WARNING: could not find compatible node %s\n",
- soc_elbc_compat);
- return off;
- }
- err = fdt_del_node(blob, off);
- if (err < 0) {
- printf("WARNING: could not remove %s\n",
- soc_elbc_compat);
- return err;
- }
- return 0;
- }
-#endif
-
-#if defined(CONFIG_TARGET_P1020RDB_PD) || defined(CONFIG_TARGET_P1020RDB_PC)
-/* Delete USB2 node as it is muxed with eLBC */
- usb1_off = fdt_node_offset_by_compatible(blob, -1,
- soc_usb_compat);
- if (usb1_off < 0) {
- printf("WARNING: could not find compatible node %s\n",
- soc_usb_compat);
- return usb1_off;
- }
- usb2_off = fdt_node_offset_by_compatible(blob, usb1_off,
- soc_usb_compat);
- if (usb2_off < 0) {
- printf("WARNING: could not find compatible node %s\n",
- soc_usb_compat);
- return usb2_off;
- }
- usb_err = fdt_del_node(blob, usb2_off);
- if (usb_err < 0) {
- printf("WARNING: could not remove %s\n", soc_usb_compat);
- return usb_err;
- }
-#endif
-
- return 0;
-}
-#endif
diff --git a/board/freescale/p1_p2_rdb_pc/spl.c b/board/freescale/p1_p2_rdb_pc/spl.c
deleted file mode 100644
index 6ed0a816d9..0000000000
--- a/board/freescale/p1_p2_rdb_pc/spl.c
+++ /dev/null
@@ -1,123 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <clock_legacy.h>
-#include <console.h>
-#include <env.h>
-#include <env_internal.h>
-#include <init.h>
-#include <ns16550.h>
-#include <malloc.h>
-#include <mmc.h>
-#include <nand.h>
-#include <i2c.h>
-#include <fsl_esdhc.h>
-#include <spi_flash.h>
-#include "../common/spl.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-phys_size_t get_effective_memsize(void)
-{
- return CONFIG_SYS_L2_SIZE;
-}
-
-void board_init_f(ulong bootflag)
-{
- u32 plat_ratio, bus_clk;
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
- console_init_f();
-
- /* Set pmuxcr to allow both i2c1 and i2c2 */
- setbits_be32(&gur->pmuxcr, in_be32(&gur->pmuxcr) | 0x1000);
- setbits_be32(&gur->pmuxcr,
- in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA);
-
- /* Read back the register to synchronize the write. */
- in_be32(&gur->pmuxcr);
-
-#ifdef CONFIG_SPL_SPI_BOOT
- clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
-#endif
-
- /* initialize selected port with appropriate baud rate */
- plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
- plat_ratio >>= 1;
- bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
- gd->bus_clk = bus_clk;
-
- NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
- bus_clk / 16 / CONFIG_BAUDRATE);
-#ifdef CONFIG_SPL_MMC_BOOT
- puts("\nSD boot...\n");
-#elif defined(CONFIG_SPL_SPI_BOOT)
- puts("\nSPI Flash boot...\n");
-#endif
-
- /* copy code to RAM and jump to it - this should not return */
- /* NOTE - code has to be copied out of NAND buffer before
- * other blocks can be read.
- */
- relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
- /* Pointer is writable since we allocated a register for it */
- gd = (gd_t *)CONFIG_SPL_GD_ADDR;
- bd_t *bd;
-
- memset(gd, 0, sizeof(gd_t));
- bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
- memset(bd, 0, sizeof(bd_t));
- gd->bd = bd;
- bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
- bd->bi_memsize = CONFIG_SYS_L2_SIZE;
-
- arch_cpu_init();
- get_clocks();
- mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
- CONFIG_SPL_RELOC_MALLOC_SIZE);
- gd->flags |= GD_FLG_FULL_MALLOC_INIT;
-
-#ifndef CONFIG_SPL_NAND_BOOT
- env_init();
-#endif
-#ifdef CONFIG_SPL_MMC_BOOT
- mmc_initialize(bd);
-#endif
- /* relocate environment function pointers etc. */
-#ifdef CONFIG_SPL_NAND_BOOT
- nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
- (uchar *)SPL_ENV_ADDR);
- gd->env_addr = (ulong)(SPL_ENV_ADDR);
- gd->env_valid = ENV_VALID;
-#else
- env_relocate();
-#endif
-
-#ifdef CONFIG_SYS_I2C
- i2c_init_all();
-#else
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-#endif
-
- dram_init();
-#ifdef CONFIG_SPL_NAND_BOOT
- puts("Tertiary program loader running in sram...");
-#else
- puts("Second program loader running in sram...\n");
-#endif
-
-#ifdef CONFIG_SPL_MMC_BOOT
- mmc_boot();
-#elif defined(CONFIG_SPL_SPI_BOOT)
- fsl_spi_boot();
-#elif defined(CONFIG_SPL_NAND_BOOT)
- nand_boot();
-#endif
-}
diff --git a/board/freescale/p1_p2_rdb_pc/spl_minimal.c b/board/freescale/p1_p2_rdb_pc/spl_minimal.c
deleted file mode 100644
index ced5f3c3b5..0000000000
--- a/board/freescale/p1_p2_rdb_pc/spl_minimal.c
+++ /dev/null
@@ -1,63 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2011 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <init.h>
-#include <ns16550.h>
-#include <asm/io.h>
-#include <nand.h>
-#include <linux/compiler.h>
-#include <asm/fsl_law.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/global_data.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void board_init_f(ulong bootflag)
-{
- u32 plat_ratio;
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
-#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
- set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
- set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
-#endif
-
- /* initialize selected port with appropriate baud rate */
- plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
- plat_ratio >>= 1;
- gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
-
- NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
- gd->bus_clk / 16 / CONFIG_BAUDRATE);
-
- puts("\nNAND boot... ");
-
- /* copy code to RAM and jump to it - this should not return */
- /* NOTE - code has to be copied out of NAND buffer before
- * other blocks can be read.
- */
- relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
- puts("\nSecond program loader running in sram...");
- nand_boot();
-}
-
-void putc(char c)
-{
- if (c == '\n')
- NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
-
- NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
-}
-
-void puts(const char *str)
-{
- while (*str)
- putc(*str++);
-}
diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c
deleted file mode 100644
index 14971f0476..0000000000
--- a/board/freescale/p1_p2_rdb_pc/tlb.c
+++ /dev/null
@@ -1,110 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2010-2011 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
- /* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
-
- /* TLB 1 */
- /* *I*** - Covers boot page */
- SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I,
- 0, 0, BOOKE_PAGESZ_4K, 1),
-
- /* *I*G* - CCSRBAR */
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 1, BOOKE_PAGESZ_1M, 1),
-
-#ifndef CONFIG_SPL_BUILD
- /* W**G* - Flash/promjet, localbus */
- /* This will be changed to *I*G* after relocation to RAM. */
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
- MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
- 0, 2, BOOKE_PAGESZ_64M, 1),
-
-#ifdef CONFIG_PCI
- /* *I*G* - PCI memory 1.5G */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 3, BOOKE_PAGESZ_1G, 1),
-
- /* *I*G* - PCI I/O effective: 192K */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 4, BOOKE_PAGESZ_256K, 1),
-#endif
-
-#ifdef CONFIG_VSC7385_ENET
- /* *I*G - VSC7385 Switch */
- SET_TLB_ENTRY(1, CONFIG_SYS_VSC7385_BASE, CONFIG_SYS_VSC7385_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 5, BOOKE_PAGESZ_1M, 1),
-#endif
-
- SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 6, BOOKE_PAGESZ_1M, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_PMC_BASE, CONFIG_SYS_PMC_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 10, BOOKE_PAGESZ_64K, 1),
-#endif /* not SPL */
-
-#ifdef CONFIG_SYS_NAND_BASE
- /* *I*G - NAND */
- SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 7, BOOKE_PAGESZ_1M, 1),
-#endif
-
-#if defined(CONFIG_SYS_RAMBOOT) || \
- (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
- /* *I*G - eSDHC/eSPI/NAND boot */
- SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
- 0, 8, BOOKE_PAGESZ_1G, 1),
-
-#if defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD)
- /* 2G DDR on P1020MBG, map the second 1G */
- SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
- CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 9, BOOKE_PAGESZ_1G, 1),
-#endif /* TARGET_P1020MBG */
-#endif /* RAMBOOT/SPL */
-
-#ifdef CONFIG_SYS_INIT_L2_ADDR
- /* *I*G - L2SRAM */
- SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
- 0, 11, BOOKE_PAGESZ_256K, 1),
-#if CONFIG_SYS_L2_SIZE >= (256 << 10)
- SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
- CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 12, BOOKE_PAGESZ_256K, 1)
-#endif
-#endif
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/configs/P1020MBG-PC_36BIT_SDCARD_defconfig b/configs/P1020MBG-PC_36BIT_SDCARD_defconfig
deleted file mode 100644
index 91d46e4727..0000000000
--- a/configs/P1020MBG-PC_36BIT_SDCARD_defconfig
+++ /dev/null
@@ -1,67 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x0
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_TEXT_BASE=0xf8f81000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P1020MBG=y
-CONFIG_PHYS_64BIT=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
-CONFIG_BOOTDELAY=10
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_MMC_BOOT=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P1020MBG-PC_36BIT_defconfig b/configs/P1020MBG-PC_36BIT_defconfig
deleted file mode 100644
index 7930af3b73..0000000000
--- a/configs/P1020MBG-PC_36BIT_defconfig
+++ /dev/null
@@ -1,55 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P1020MBG=y
-CONFIG_PHYS_64BIT=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P1020MBG-PC_SDCARD_defconfig b/configs/P1020MBG-PC_SDCARD_defconfig
deleted file mode 100644
index 708a4bbfbf..0000000000
--- a/configs/P1020MBG-PC_SDCARD_defconfig
+++ /dev/null
@@ -1,66 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x0
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_TEXT_BASE=0xf8f81000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P1020MBG=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
-CONFIG_BOOTDELAY=10
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_MMC_BOOT=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P1020MBG-PC_defconfig b/configs/P1020MBG-PC_defconfig
deleted file mode 100644
index 4ff3712d0f..0000000000
--- a/configs/P1020MBG-PC_defconfig
+++ /dev/null
@@ -1,54 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P1020MBG=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig b/configs/P1020RDB-PC_36BIT_NAND_defconfig
deleted file mode 100644
index 6ee52fe5e7..0000000000
--- a/configs/P1020RDB-PC_36BIT_NAND_defconfig
+++ /dev/null
@@ -1,85 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11001000
-CONFIG_ENV_SIZE=0x4000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_TPL_LIBCOMMON_SUPPORT=y
-CONFIG_TPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_TEXT_BASE=0xFF800000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P1020RDB_PC=y
-CONFIG_PHYS_64BIT=y
-CONFIG_SYS_CUSTOM_LDSCRIPT=y
-CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_NAND_BOOT=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_TPL=y
-CONFIG_TPL_ENV_SUPPORT=y
-CONFIG_TPL_I2C_SUPPORT=y
-CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_TPL_NAND_SUPPORT=y
-CONFIG_TPL_SERIAL_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc_36b"
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
diff --git a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
deleted file mode 100644
index 489b91d8e7..0000000000
--- a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
+++ /dev/null
@@ -1,80 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x0
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_TEXT_BASE=0xf8f81000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P1020RDB_PC=y
-CONFIG_PHYS_64BIT=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
-CONFIG_BOOTDELAY=10
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_MMC_BOOT=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc_36b"
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
diff --git a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
deleted file mode 100644
index 4a8e4e3726..0000000000
--- a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
+++ /dev/null
@@ -1,82 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_SPL_TEXT_BASE=0xf8f81000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P1020RDB_PC=y
-CONFIG_PHYS_64BIT=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
-CONFIG_BOOTDELAY=10
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_SPI_BOOT=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc_36b"
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
diff --git a/configs/P1020RDB-PC_36BIT_defconfig b/configs/P1020RDB-PC_36BIT_defconfig
deleted file mode 100644
index f9a4b735ca..0000000000
--- a/configs/P1020RDB-PC_36BIT_defconfig
+++ /dev/null
@@ -1,69 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P1020RDB_PC=y
-CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
-CONFIG_PHYS_64BIT=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc_36b"
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_DM=y
-CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
diff --git a/configs/P1020RDB-PC_NAND_defconfig b/configs/P1020RDB-PC_NAND_defconfig
deleted file mode 100644
index 5c8231cba2..0000000000
--- a/configs/P1020RDB-PC_NAND_defconfig
+++ /dev/null
@@ -1,84 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11001000
-CONFIG_ENV_SIZE=0x4000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_TPL_LIBCOMMON_SUPPORT=y
-CONFIG_TPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_TEXT_BASE=0xFF800000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P1020RDB_PC=y
-CONFIG_SYS_CUSTOM_LDSCRIPT=y
-CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_NAND_BOOT=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_TPL=y
-CONFIG_TPL_ENV_SUPPORT=y
-CONFIG_TPL_I2C_SUPPORT=y
-CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_TPL_NAND_SUPPORT=y
-CONFIG_TPL_SERIAL_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc"
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
diff --git a/configs/P1020RDB-PC_SDCARD_defconfig b/configs/P1020RDB-PC_SDCARD_defconfig
deleted file mode 100644
index ad2bb90a49..0000000000
--- a/configs/P1020RDB-PC_SDCARD_defconfig
+++ /dev/null
@@ -1,79 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x0
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_TEXT_BASE=0xf8f81000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P1020RDB_PC=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
-CONFIG_BOOTDELAY=10
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_MMC_BOOT=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc"
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
diff --git a/configs/P1020RDB-PC_SPIFLASH_defconfig b/configs/P1020RDB-PC_SPIFLASH_defconfig
deleted file mode 100644
index b8055e49b0..0000000000
--- a/configs/P1020RDB-PC_SPIFLASH_defconfig
+++ /dev/null
@@ -1,81 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_SPL_TEXT_BASE=0xf8f81000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P1020RDB_PC=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
-CONFIG_BOOTDELAY=10
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_SPI_BOOT=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc"
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
diff --git a/configs/P1020RDB-PC_defconfig b/configs/P1020RDB-PC_defconfig
deleted file mode 100644
index a71985374e..0000000000
--- a/configs/P1020RDB-PC_defconfig
+++ /dev/null
@@ -1,68 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P1020RDB_PC=y
-CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc"
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_DM=y
-CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
diff --git a/configs/P1020RDB-PD_NAND_defconfig b/configs/P1020RDB-PD_NAND_defconfig
deleted file mode 100644
index 0043fd5f66..0000000000
--- a/configs/P1020RDB-PD_NAND_defconfig
+++ /dev/null
@@ -1,88 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11001000
-CONFIG_ENV_SIZE=0x20000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_TPL_LIBCOMMON_SUPPORT=y
-CONFIG_TPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_TEXT_BASE=0xFF800000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P1020RDB_PD=y
-CONFIG_SYS_CUSTOM_LDSCRIPT=y
-CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_NAND_BOOT=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_TPL=y
-CONFIG_TPL_ENV_SUPPORT=y
-CONFIG_TPL_I2C_SUPPORT=y
-CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_TPL_NAND_SUPPORT=y
-CONFIG_TPL_SERIAL_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=ec000000.nor"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=ec000000.nor:128k(dtb),6016k(kernel),57088k(fs),1m(vsc7385-firmware),1280k(u-boot)"
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pd"
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
diff --git a/configs/P1020RDB-PD_SDCARD_defconfig b/configs/P1020RDB-PD_SDCARD_defconfig
deleted file mode 100644
index cb0a8aec65..0000000000
--- a/configs/P1020RDB-PD_SDCARD_defconfig
+++ /dev/null
@@ -1,83 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x0
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_TEXT_BASE=0xf8f81000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P1020RDB_PD=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
-CONFIG_BOOTDELAY=10
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_MMC_BOOT=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=ec000000.nor"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=ec000000.nor:128k(dtb),6016k(kernel),57088k(fs),1m(vsc7385-firmware),1280k(u-boot)"
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pd"
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
diff --git a/configs/P1020RDB-PD_SPIFLASH_defconfig b/configs/P1020RDB-PD_SPIFLASH_defconfig
deleted file mode 100644
index 35e60ca856..0000000000
--- a/configs/P1020RDB-PD_SPIFLASH_defconfig
+++ /dev/null
@@ -1,85 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_SPL_TEXT_BASE=0xf8f81000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P1020RDB_PD=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
-CONFIG_BOOTDELAY=10
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_SPI_BOOT=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=ec000000.nor"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=ec000000.nor:128k(dtb),6016k(kernel),57088k(fs),1m(vsc7385-firmware),1280k(u-boot)"
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pd"
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
diff --git a/configs/P1020RDB-PD_defconfig b/configs/P1020RDB-PD_defconfig
deleted file mode 100644
index d7f19c3d96..0000000000
--- a/configs/P1020RDB-PD_defconfig
+++ /dev/null
@@ -1,72 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P1020RDB_PD=y
-CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=ec000000.nor"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=ec000000.nor:128k(dtb),6016k(kernel),57088k(fs),1m(vsc7385-firmware),1280k(u-boot)"
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pd"
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_DM=y
-CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
diff --git a/configs/P1020UTM-PC_36BIT_SDCARD_defconfig b/configs/P1020UTM-PC_36BIT_SDCARD_defconfig
deleted file mode 100644
index 4b00005624..0000000000
--- a/configs/P1020UTM-PC_36BIT_SDCARD_defconfig
+++ /dev/null
@@ -1,67 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x0
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_TEXT_BASE=0xf8f81000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P1020UTM=y
-CONFIG_PHYS_64BIT=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
-CONFIG_BOOTDELAY=10
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_MMC_BOOT=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P1020UTM-PC_36BIT_defconfig b/configs/P1020UTM-PC_36BIT_defconfig
deleted file mode 100644
index 968d3edbcf..0000000000
--- a/configs/P1020UTM-PC_36BIT_defconfig
+++ /dev/null
@@ -1,55 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P1020UTM=y
-CONFIG_PHYS_64BIT=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P1020UTM-PC_SDCARD_defconfig b/configs/P1020UTM-PC_SDCARD_defconfig
deleted file mode 100644
index 93302a12b0..0000000000
--- a/configs/P1020UTM-PC_SDCARD_defconfig
+++ /dev/null
@@ -1,66 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x0
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_TEXT_BASE=0xf8f81000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P1020UTM=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
-CONFIG_BOOTDELAY=10
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_MMC_BOOT=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P1020UTM-PC_defconfig b/configs/P1020UTM-PC_defconfig
deleted file mode 100644
index c41ac7bfd4..0000000000
--- a/configs/P1020UTM-PC_defconfig
+++ /dev/null
@@ -1,54 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P1020UTM=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P1021RDB-PC_36BIT_NAND_defconfig b/configs/P1021RDB-PC_36BIT_NAND_defconfig
deleted file mode 100644
index ba1d836552..0000000000
--- a/configs/P1021RDB-PC_36BIT_NAND_defconfig
+++ /dev/null
@@ -1,84 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11001000
-CONFIG_ENV_SIZE=0x4000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_TPL_LIBCOMMON_SUPPORT=y
-CONFIG_TPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_TEXT_BASE=0xFF800000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P1021RDB=y
-CONFIG_PHYS_64BIT=y
-CONFIG_SYS_CUSTOM_LDSCRIPT=y
-CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_NAND_BOOT=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_TPL=y
-CONFIG_TPL_ENV_SUPPORT=y
-CONFIG_TPL_I2C_SUPPORT=y
-CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_TPL_NAND_SUPPORT=y
-CONFIG_TPL_SERIAL_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=fef000000.nor"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9728k(fs),256k(qe-ucode-firmware),1280k(u-boot)"
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P1021RDB-PC_36BIT_SDCARD_defconfig b/configs/P1021RDB-PC_36BIT_SDCARD_defconfig
deleted file mode 100644
index 30b8372a5b..0000000000
--- a/configs/P1021RDB-PC_36BIT_SDCARD_defconfig
+++ /dev/null
@@ -1,79 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x0
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_TEXT_BASE=0xf8f81000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P1021RDB=y
-CONFIG_PHYS_64BIT=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
-CONFIG_BOOTDELAY=10
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_MMC_BOOT=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=fef000000.nor"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9728k(fs),256k(qe-ucode-firmware),1280k(u-boot)"
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig
deleted file mode 100644
index 37bc209d98..0000000000
--- a/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig
+++ /dev/null
@@ -1,81 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_SPL_TEXT_BASE=0xf8f81000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P1021RDB=y
-CONFIG_PHYS_64BIT=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
-CONFIG_BOOTDELAY=10
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_SPI_BOOT=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=fef000000.nor"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9728k(fs),256k(qe-ucode-firmware),1280k(u-boot)"
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P1021RDB-PC_36BIT_defconfig b/configs/P1021RDB-PC_36BIT_defconfig
deleted file mode 100644
index ca1be9c112..0000000000
--- a/configs/P1021RDB-PC_36BIT_defconfig
+++ /dev/null
@@ -1,67 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P1021RDB=y
-CONFIG_PHYS_64BIT=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=fef000000.nor"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9728k(fs),256k(qe-ucode-firmware),1280k(u-boot)"
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P1021RDB-PC_NAND_defconfig b/configs/P1021RDB-PC_NAND_defconfig
deleted file mode 100644
index 1b38da48f7..0000000000
--- a/configs/P1021RDB-PC_NAND_defconfig
+++ /dev/null
@@ -1,83 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11001000
-CONFIG_ENV_SIZE=0x4000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_TPL_LIBCOMMON_SUPPORT=y
-CONFIG_TPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_TEXT_BASE=0xFF800000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P1021RDB=y
-CONFIG_SYS_CUSTOM_LDSCRIPT=y
-CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_NAND_BOOT=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_TPL=y
-CONFIG_TPL_ENV_SUPPORT=y
-CONFIG_TPL_I2C_SUPPORT=y
-CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_TPL_NAND_SUPPORT=y
-CONFIG_TPL_SERIAL_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=ef000000.nor"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=ef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9728k(fs),256k(qe-ucode-firmware),1280k(u-boot)"
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P1021RDB-PC_SDCARD_defconfig b/configs/P1021RDB-PC_SDCARD_defconfig
deleted file mode 100644
index 242b9eb3c9..0000000000
--- a/configs/P1021RDB-PC_SDCARD_defconfig
+++ /dev/null
@@ -1,78 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x0
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_TEXT_BASE=0xf8f81000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P1021RDB=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
-CONFIG_BOOTDELAY=10
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_MMC_BOOT=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=ef000000.nor"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=ef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9728k(fs),256k(qe-ucode-firmware),1280k(u-boot)"
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P1021RDB-PC_SPIFLASH_defconfig b/configs/P1021RDB-PC_SPIFLASH_defconfig
deleted file mode 100644
index 6792e3f45a..0000000000
--- a/configs/P1021RDB-PC_SPIFLASH_defconfig
+++ /dev/null
@@ -1,80 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_SPL_TEXT_BASE=0xf8f81000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P1021RDB=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
-CONFIG_BOOTDELAY=10
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_SPI_BOOT=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=ef000000.nor"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=ef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9728k(fs),256k(qe-ucode-firmware),1280k(u-boot)"
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P1021RDB-PC_defconfig b/configs/P1021RDB-PC_defconfig
deleted file mode 100644
index 54010afb56..0000000000
--- a/configs/P1021RDB-PC_defconfig
+++ /dev/null
@@ -1,66 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P1021RDB=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=ef000000.nor"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=ef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9728k(fs),256k(qe-ucode-firmware),1280k(u-boot)"
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P1024RDB_36BIT_defconfig b/configs/P1024RDB_36BIT_defconfig
deleted file mode 100644
index 5116fac64a..0000000000
--- a/configs/P1024RDB_36BIT_defconfig
+++ /dev/null
@@ -1,61 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P1024RDB=y
-CONFIG_PHYS_64BIT=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P1024RDB_NAND_defconfig b/configs/P1024RDB_NAND_defconfig
deleted file mode 100644
index 2e2eda74f0..0000000000
--- a/configs/P1024RDB_NAND_defconfig
+++ /dev/null
@@ -1,77 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11001000
-CONFIG_ENV_SIZE=0x4000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_TPL_LIBCOMMON_SUPPORT=y
-CONFIG_TPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_TEXT_BASE=0xFF800000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P1024RDB=y
-CONFIG_SYS_CUSTOM_LDSCRIPT=y
-CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_NAND_BOOT=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_TPL=y
-CONFIG_TPL_ENV_SUPPORT=y
-CONFIG_TPL_I2C_SUPPORT=y
-CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_TPL_NAND_SUPPORT=y
-CONFIG_TPL_SERIAL_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P1024RDB_SDCARD_defconfig b/configs/P1024RDB_SDCARD_defconfig
deleted file mode 100644
index 69a3718ec4..0000000000
--- a/configs/P1024RDB_SDCARD_defconfig
+++ /dev/null
@@ -1,71 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x0
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_TEXT_BASE=0xf8f81000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P1024RDB=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
-CONFIG_BOOTDELAY=10
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_MMC_BOOT=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P1024RDB_SPIFLASH_defconfig b/configs/P1024RDB_SPIFLASH_defconfig
deleted file mode 100644
index a09696cc63..0000000000
--- a/configs/P1024RDB_SPIFLASH_defconfig
+++ /dev/null
@@ -1,73 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_SPL_TEXT_BASE=0xf8f81000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P1024RDB=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
-CONFIG_BOOTDELAY=10
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_SPI_BOOT=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P1024RDB_defconfig b/configs/P1024RDB_defconfig
deleted file mode 100644
index 72665c4edf..0000000000
--- a/configs/P1024RDB_defconfig
+++ /dev/null
@@ -1,60 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P1024RDB=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P1025RDB_36BIT_defconfig b/configs/P1025RDB_36BIT_defconfig
deleted file mode 100644
index 8eaddb1290..0000000000
--- a/configs/P1025RDB_36BIT_defconfig
+++ /dev/null
@@ -1,63 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P1025RDB=y
-CONFIG_PHYS_64BIT=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P1025RDB_NAND_defconfig b/configs/P1025RDB_NAND_defconfig
deleted file mode 100644
index bbeb396f64..0000000000
--- a/configs/P1025RDB_NAND_defconfig
+++ /dev/null
@@ -1,80 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11001000
-CONFIG_ENV_SIZE=0x4000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_TPL_LIBCOMMON_SUPPORT=y
-CONFIG_TPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_TEXT_BASE=0xFF800000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P1025RDB=y
-CONFIG_SYS_CUSTOM_LDSCRIPT=y
-CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_NAND_BOOT=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_TPL=y
-CONFIG_TPL_ENV_SUPPORT=y
-CONFIG_TPL_I2C_SUPPORT=y
-CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_TPL_NAND_SUPPORT=y
-CONFIG_TPL_SERIAL_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P1025RDB_SDCARD_defconfig b/configs/P1025RDB_SDCARD_defconfig
deleted file mode 100644
index bc88a27479..0000000000
--- a/configs/P1025RDB_SDCARD_defconfig
+++ /dev/null
@@ -1,73 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x0
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_TEXT_BASE=0xf8f81000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P1025RDB=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
-CONFIG_BOOTDELAY=10
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_MMC_BOOT=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P1025RDB_SPIFLASH_defconfig b/configs/P1025RDB_SPIFLASH_defconfig
deleted file mode 100644
index 6dba8c5648..0000000000
--- a/configs/P1025RDB_SPIFLASH_defconfig
+++ /dev/null
@@ -1,76 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_SPL_TEXT_BASE=0xf8f81000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P1025RDB=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
-CONFIG_BOOTDELAY=10
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_SPI_BOOT=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P1025RDB_defconfig b/configs/P1025RDB_defconfig
deleted file mode 100644
index 92dc97ab08..0000000000
--- a/configs/P1025RDB_defconfig
+++ /dev/null
@@ -1,62 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P1025RDB=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig
deleted file mode 100644
index 3e6ea64ee3..0000000000
--- a/configs/P2020RDB-PC_36BIT_NAND_defconfig
+++ /dev/null
@@ -1,90 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11001000
-CONFIG_ENV_SIZE=0x4000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_TPL_LIBCOMMON_SUPPORT=y
-CONFIG_TPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_TEXT_BASE=0xFF800000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P2020RDB=y
-CONFIG_PHYS_64BIT=y
-CONFIG_SYS_CUSTOM_LDSCRIPT=y
-CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_NAND_BOOT=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_TPL=y
-CONFIG_TPL_ENV_SUPPORT=y
-CONFIG_TPL_I2C_SUPPORT=y
-CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_TPL_NAND_SUPPORT=y
-CONFIG_TPL_SERIAL_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=fef000000.nor"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)"
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc_36b"
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
diff --git a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
deleted file mode 100644
index 187cbee0d6..0000000000
--- a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
+++ /dev/null
@@ -1,85 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x0
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_TEXT_BASE=0xf8f81000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P2020RDB=y
-CONFIG_PHYS_64BIT=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
-CONFIG_BOOTDELAY=10
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_MMC_BOOT=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=fef000000.nor"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)"
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc_36b"
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
diff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
deleted file mode 100644
index 88c9224001..0000000000
--- a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
+++ /dev/null
@@ -1,87 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_SPL_TEXT_BASE=0xf8f81000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P2020RDB=y
-CONFIG_PHYS_64BIT=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
-CONFIG_BOOTDELAY=10
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_SPI_BOOT=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=fef000000.nor"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)"
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc_36b"
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
diff --git a/configs/P2020RDB-PC_36BIT_defconfig b/configs/P2020RDB-PC_36BIT_defconfig
deleted file mode 100644
index 88e24c30ba..0000000000
--- a/configs/P2020RDB-PC_36BIT_defconfig
+++ /dev/null
@@ -1,74 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P2020RDB=y
-CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
-CONFIG_PHYS_64BIT=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=fef000000.nor"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)"
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc_36b"
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_DM=y
-CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
diff --git a/configs/P2020RDB-PC_NAND_defconfig b/configs/P2020RDB-PC_NAND_defconfig
deleted file mode 100644
index dda34dd43e..0000000000
--- a/configs/P2020RDB-PC_NAND_defconfig
+++ /dev/null
@@ -1,89 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11001000
-CONFIG_ENV_SIZE=0x4000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_TPL_LIBCOMMON_SUPPORT=y
-CONFIG_TPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_TEXT_BASE=0xFF800000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P2020RDB=y
-CONFIG_SYS_CUSTOM_LDSCRIPT=y
-CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_NAND_BOOT=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_TPL=y
-CONFIG_TPL_ENV_SUPPORT=y
-CONFIG_TPL_I2C_SUPPORT=y
-CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_TPL_NAND_SUPPORT=y
-CONFIG_TPL_SERIAL_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=ef000000.nor"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=ef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)"
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc"
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
diff --git a/configs/P2020RDB-PC_SDCARD_defconfig b/configs/P2020RDB-PC_SDCARD_defconfig
deleted file mode 100644
index c2b6ad5f32..0000000000
--- a/configs/P2020RDB-PC_SDCARD_defconfig
+++ /dev/null
@@ -1,84 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x0
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_TEXT_BASE=0xf8f81000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P2020RDB=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
-CONFIG_BOOTDELAY=10
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_MMC_BOOT=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=ef000000.nor"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=ef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)"
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc"
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
diff --git a/configs/P2020RDB-PC_SPIFLASH_defconfig b/configs/P2020RDB-PC_SPIFLASH_defconfig
deleted file mode 100644
index 3ec208ee00..0000000000
--- a/configs/P2020RDB-PC_SPIFLASH_defconfig
+++ /dev/null
@@ -1,86 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_SPL_TEXT_BASE=0xf8f81000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P2020RDB=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
-CONFIG_BOOTDELAY=10
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_SPI_BOOT=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=ef000000.nor"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=ef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)"
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc"
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
diff --git a/configs/P2020RDB-PC_defconfig b/configs/P2020RDB-PC_defconfig
deleted file mode 100644
index 0f0a6ad810..0000000000
--- a/configs/P2020RDB-PC_defconfig
+++ /dev/null
@@ -1,73 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P2020RDB=y
-CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=ef000000.nor"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=ef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)"
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc"
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_DM=y
-CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
deleted file mode 100644
index 219e5d216b..0000000000
--- a/include/configs/p1_p2_rdb_pc.h
+++ /dev/null
@@ -1,881 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2010-2011 Freescale Semiconductor, Inc.
- * Copyright 2020 NXP
- */
-
-/*
- * QorIQ RDB boards configuration file
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <linux/stringify.h>
-
-#if defined(CONFIG_TARGET_P1020MBG)
-#define CONFIG_BOARDNAME "P1020MBG-PC"
-#define CONFIG_VSC7385_ENET
-#define CONFIG_SLIC
-#define __SW_BOOT_MASK 0x03
-#define __SW_BOOT_NOR 0xe4
-#define __SW_BOOT_SD 0x54
-#define CONFIG_SYS_L2_SIZE (256 << 10)
-#endif
-
-#if defined(CONFIG_TARGET_P1020UTM)
-#define CONFIG_BOARDNAME "P1020UTM-PC"
-#define __SW_BOOT_MASK 0x03
-#define __SW_BOOT_NOR 0xe0
-#define __SW_BOOT_SD 0x50
-#define CONFIG_SYS_L2_SIZE (256 << 10)
-#endif
-
-#if defined(CONFIG_TARGET_P1020RDB_PC)
-#define CONFIG_BOARDNAME "P1020RDB-PC"
-#define CONFIG_NAND_FSL_ELBC
-#define CONFIG_VSC7385_ENET
-#define CONFIG_SLIC
-#define __SW_BOOT_MASK 0x03
-#define __SW_BOOT_NOR 0x5c
-#define __SW_BOOT_SPI 0x1c
-#define __SW_BOOT_SD 0x9c
-#define __SW_BOOT_NAND 0xec
-#define __SW_BOOT_PCIE 0x6c
-#define CONFIG_SYS_L2_SIZE (256 << 10)
-#endif
-
-/*
- * P1020RDB-PD board has user selectable switches for evaluating different
- * frequency and boot options for the P1020 device. The table that
- * follow describe the available options. The front six binary number was in
- * accordance with SW3[1:6].
- * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off
- * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off
- * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off
- * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off
- * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off
- * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off
- * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off
- */
-#if defined(CONFIG_TARGET_P1020RDB_PD)
-#define CONFIG_BOARDNAME "P1020RDB-PD"
-#define CONFIG_NAND_FSL_ELBC
-#define CONFIG_VSC7385_ENET
-#define CONFIG_SLIC
-#define __SW_BOOT_MASK 0x03
-#define __SW_BOOT_NOR 0x64
-#define __SW_BOOT_SPI 0x34
-#define __SW_BOOT_SD 0x24
-#define __SW_BOOT_NAND 0x44
-#define __SW_BOOT_PCIE 0x74
-#define CONFIG_SYS_L2_SIZE (256 << 10)
-/*
- * Dynamic MTD Partition support with mtdparts
- */
-#endif
-
-#if defined(CONFIG_TARGET_P1021RDB)
-#define CONFIG_BOARDNAME "P1021RDB-PC"
-#define CONFIG_NAND_FSL_ELBC
-#define CONFIG_VSC7385_ENET
-#define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of
- addresses in the LBC */
-#define __SW_BOOT_MASK 0x03
-#define __SW_BOOT_NOR 0x5c
-#define __SW_BOOT_SPI 0x1c
-#define __SW_BOOT_SD 0x9c
-#define __SW_BOOT_NAND 0xec
-#define __SW_BOOT_PCIE 0x6c
-#define CONFIG_SYS_L2_SIZE (256 << 10)
-/*
- * Dynamic MTD Partition support with mtdparts
- */
-#endif
-
-#if defined(CONFIG_TARGET_P1024RDB)
-#define CONFIG_BOARDNAME "P1024RDB"
-#define CONFIG_NAND_FSL_ELBC
-#define CONFIG_SLIC
-#define __SW_BOOT_MASK 0xf3
-#define __SW_BOOT_NOR 0x00
-#define __SW_BOOT_SPI 0x08
-#define __SW_BOOT_SD 0x04
-#define __SW_BOOT_NAND 0x0c
-#define CONFIG_SYS_L2_SIZE (256 << 10)
-#endif
-
-#if defined(CONFIG_TARGET_P1025RDB)
-#define CONFIG_BOARDNAME "P1025RDB"
-#define CONFIG_NAND_FSL_ELBC
-#define CONFIG_SLIC
-
-#define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of
- addresses in the LBC */
-#define __SW_BOOT_MASK 0xf3
-#define __SW_BOOT_NOR 0x00
-#define __SW_BOOT_SPI 0x08
-#define __SW_BOOT_SD 0x04
-#define __SW_BOOT_NAND 0x0c
-#define CONFIG_SYS_L2_SIZE (256 << 10)
-#endif
-
-#if defined(CONFIG_TARGET_P2020RDB)
-#define CONFIG_BOARDNAME "P2020RDB-PC"
-#define CONFIG_NAND_FSL_ELBC
-#define CONFIG_VSC7385_ENET
-#define __SW_BOOT_MASK 0x03
-#define __SW_BOOT_NOR 0xc8
-#define __SW_BOOT_SPI 0x28
-#define __SW_BOOT_SD 0x68 /* or 0x18 */
-#define __SW_BOOT_NAND 0xe8
-#define __SW_BOOT_PCIE 0xa8
-#define CONFIG_SYS_L2_SIZE (512 << 10)
-/*
- * Dynamic MTD Partition support with mtdparts
- */
-#endif
-
-#ifdef CONFIG_SDCARD
-#define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
-#define CONFIG_SPL_PAD_TO 0x20000
-#define CONFIG_SPL_MAX_SIZE (128 * 1024)
-#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
-#define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
-#define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
-#define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10)
-#define CONFIG_SYS_MPC85XX_NO_RESETVEC
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SPL_COMMON_INIT_DDR
-#endif
-#endif
-
-#ifdef CONFIG_SPIFLASH
-#define CONFIG_SPL_SPI_FLASH_MINIMAL
-#define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
-#define CONFIG_SPL_PAD_TO 0x20000
-#define CONFIG_SPL_MAX_SIZE (128 * 1024)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10)
-#define CONFIG_SYS_MPC85XX_NO_RESETVEC
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SPL_COMMON_INIT_DDR
-#endif
-#endif
-
-#ifdef CONFIG_MTD_RAW_NAND
-#ifdef CONFIG_TPL_BUILD
-#define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_NAND_INIT
-#define CONFIG_SPL_COMMON_INIT_DDR
-#define CONFIG_SPL_MAX_SIZE (128 << 10)
-#define CONFIG_TPL_TEXT_BASE 0xf8f81000
-#define CONFIG_SYS_MPC85XX_NO_RESETVEC
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
-#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
-#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
-#elif defined(CONFIG_SPL_BUILD)
-#define CONFIG_SPL_INIT_MINIMAL
-#define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
-#define CONFIG_SPL_MAX_SIZE 4096
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
-#define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
-#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
-#endif /* not CONFIG_TPL_BUILD */
-
-#define CONFIG_SPL_PAD_TO 0x20000
-#define CONFIG_TPL_PAD_TO 0x20000
-#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
-#endif
-
-#ifndef CONFIG_RESET_VECTOR_ADDRESS
-#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
-#endif
-
-#ifndef CONFIG_SYS_MONITOR_BASE
-#ifdef CONFIG_TPL_BUILD
-#define CONFIG_SYS_MONITOR_BASE CONFIG_TPL_TEXT_BASE
-#elif defined(CONFIG_SPL_BUILD)
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
-#else
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-#endif
-#endif
-
-#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
-#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
-#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
-
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_SYS_SATA_MAX_DEVICE 2
-#define CONFIG_LBA48
-
-#if defined(CONFIG_TARGET_P2020RDB)
-#define CONFIG_SYS_CLK_FREQ 100000000
-#else
-#define CONFIG_SYS_CLK_FREQ 66666666
-#endif
-#define CONFIG_DDR_CLK_FREQ 66666666
-
-#define CONFIG_HWCONFIG
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_L2_CACHE
-#define CONFIG_BTB
-
-#define CONFIG_ENABLE_36BIT_PHYS
-
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_ADDR_MAP 1
-#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
-#endif
-
-#define CONFIG_SYS_CCSRBAR 0xffe00000
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
-
-/* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
- SPL code*/
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
-#endif
-
-/* DDR Setup */
-#define CONFIG_SYS_DDR_RAW_TIMING
-#define CONFIG_DDR_SPD
-#define CONFIG_SYS_SPD_BUS_NUM 1
-#define SPD_EEPROM_ADDRESS 0x52
-
-#if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
-#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G
-#define CONFIG_CHIP_SELECTS_PER_CTRL 2
-#else
-#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G
-#define CONFIG_CHIP_SELECTS_PER_CTRL 1
-#endif
-#define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-
-/* Default settings for DDR3 */
-#ifndef CONFIG_TARGET_P2020RDB
-#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
-#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
-#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
-#define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
-#define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
-#define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
-
-#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
-#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
-#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
-#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
-
-#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
-#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608
-#define CONFIG_SYS_DDR_SR_CNTR 0x00000000
-#define CONFIG_SYS_DDR_RCW_1 0x00000000
-#define CONFIG_SYS_DDR_RCW_2 0x00000000
-#define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
-#define CONFIG_SYS_DDR_CONTROL_2 0x04401050
-#define CONFIG_SYS_DDR_TIMING_4 0x00220001
-#define CONFIG_SYS_DDR_TIMING_5 0x03402400
-
-#define CONFIG_SYS_DDR_TIMING_3 0x00020000
-#define CONFIG_SYS_DDR_TIMING_0 0x00330004
-#define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846
-#define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF
-#define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
-#define CONFIG_SYS_DDR_MODE_1 0x40461520
-#define CONFIG_SYS_DDR_MODE_2 0x8000c000
-#define CONFIG_SYS_DDR_INTERVAL 0x0C300000
-#endif
-
-#undef CONFIG_CLOCKS_IN_MHZ
-
-/*
- * Memory map
- *
- * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
- * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3)
- * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
- * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable
- * (early boot only)
- * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0
- * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2
- * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3
- * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2
- * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
- * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable
- * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
- */
-
-/*
- * Local Bus Definitions
- */
-#if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
-#define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
-#define CONFIG_SYS_FLASH_BASE 0xec000000
-#elif defined(CONFIG_TARGET_P1020UTM)
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */
-#define CONFIG_SYS_FLASH_BASE 0xee000000
-#else
-#define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16M */
-#define CONFIG_SYS_FLASH_BASE 0xef000000
-#endif
-
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
-#else
-#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
-#endif
-
-#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
- | BR_PS_16 | BR_V)
-
-#define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
-
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
-#define CONFIG_SYS_FLASH_QUIET_TEST
-#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
-
-#undef CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
-/* Nand Flash */
-#ifdef CONFIG_NAND_FSL_ELBC
-#define CONFIG_SYS_NAND_BASE 0xff800000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
-#else
-#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
-#endif
-
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#if defined(CONFIG_TARGET_P1020RDB_PD)
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
-#else
-#define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
-#endif
-
-#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
- | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
- | BR_PS_8 /* Port Size = 8 bit */ \
- | BR_MS_FCM /* MSEL = FCM */ \
- | BR_V) /* valid */
-#if defined(CONFIG_TARGET_P1020RDB_PD)
-#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \
- | OR_FCM_PGS /* Large Page*/ \
- | OR_FCM_CSCT \
- | OR_FCM_CST \
- | OR_FCM_CHT \
- | OR_FCM_SCY_1 \
- | OR_FCM_TRLX \
- | OR_FCM_EHTR)
-#else
-#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \
- | OR_FCM_CSCT \
- | OR_FCM_CST \
- | OR_FCM_CHT \
- | OR_FCM_SCY_1 \
- | OR_FCM_TRLX \
- | OR_FCM_EHTR)
-#endif
-#endif /* CONFIG_NAND_FSL_ELBC */
-
-#define CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
-/* The assembler doesn't like typecast */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
- ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
- CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
-#else
-/* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
-#endif
-/* Size of used area in RAM */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */
-
-#define CONFIG_SYS_CPLD_BASE 0xffa00000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull
-#else
-#define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
-#endif
-/* CPLD config size: 1Mb */
-#define CONFIG_CPLD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \
- BR_PS_8 | BR_V)
-#define CONFIG_CPLD_OR_PRELIM (0xfff009f7)
-
-#define CONFIG_SYS_PMC_BASE 0xff980000
-#define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE
-#define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
- BR_PS_8 | BR_V)
-#define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
- OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
- OR_GPCM_EAD)
-
-#ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
-#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-#define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
-#define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
-#else
-#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
-#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
-#ifdef CONFIG_NAND_FSL_ELBC
-#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
-#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-#endif
-#endif
-#define CONFIG_SYS_BR3_PRELIM CONFIG_CPLD_BR_PRELIM /* CPLD Base Address */
-#define CONFIG_SYS_OR3_PRELIM CONFIG_CPLD_OR_PRELIM /* CPLD Options */
-
-/* Vsc7385 switch */
-#ifdef CONFIG_VSC7385_ENET
-#define CONFIG_SYS_VSC7385_BASE 0xffb00000
-
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull
-#else
-#define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE
-#endif
-
-#define CONFIG_SYS_VSC7385_BR_PRELIM \
- (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V)
-#define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \
- OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \
- OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
-
-#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_VSC7385_BR_PRELIM
-#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM
-
-/* The size of the VSC7385 firmware image */
-#define CONFIG_VSC7385_IMAGE_SIZE 8192
-#endif
-
-/*
- * Config the L2 Cache as L2 SRAM
-*/
-#if defined(CONFIG_SPL_BUILD)
-#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
-#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
-#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
-#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
-#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
-#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
-#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
-#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
-#if defined(CONFIG_TARGET_P2020RDB)
-#define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10)
-#else
-#define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10)
-#endif
-#elif defined(CONFIG_MTD_RAW_NAND)
-#ifdef CONFIG_TPL_BUILD
-#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
-#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
-#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
-#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
-#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
-#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
-#define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
-#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
-#else
-#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
-#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
-#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
-#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000)
-#define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
-#endif /* CONFIG_TPL_BUILD */
-#endif
-#endif
-
-/* Serial Port - controlled on board with jumper J8
- * open - index 2
- * shorted - index 1
- */
-#undef CONFIG_SERIAL_SOFTWARE_FIFO
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
-#define CONFIG_NS16550_MIN_FUNCTIONS
-#endif
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
-
-/* I2C */
-#ifndef CONFIG_DM_I2C
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-#define CONFIG_SYS_FSL_I2C2_SPEED 400000
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
-#else
-#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
-#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
-#endif
-
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
-#define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */
-
-/*
- * I2C2 EEPROM
- */
-#undef CONFIG_ID_EEPROM
-
-#define CONFIG_RTC_PT7C4338
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-#define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
-
-/* enable read and write access to EEPROM */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
-
-#if defined(CONFIG_PCI)
-/*
- * General PCI
- * Memory space is mapped 1-1, but I/O space must start from 0.
- */
-
-/* controller 2, direct to uli, tgtid 2, Base address 9000 */
-#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
-#else
-#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
-#endif
-#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
-#else
-#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
-#endif
-
-/* controller 1, Slot 2, tgtid 1, Base address a000 */
-#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
-#else
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
-#endif
-#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
-#else
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
-#endif
-
-#if !defined(CONFIG_DM_PCI)
-#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_SYS_PCIE2_NAME "PCIe SLOT"
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
-#else
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
-#endif
-#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
-
-#define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT"
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
-#else
-#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
-#endif
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
-#endif
-
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#endif /* CONFIG_PCI */
-
-#if defined(CONFIG_TSEC_ENET)
-#define CONFIG_TSEC1
-#define CONFIG_TSEC1_NAME "eTSEC1"
-#define CONFIG_TSEC2
-#define CONFIG_TSEC2_NAME "eTSEC2"
-#define CONFIG_TSEC3
-#define CONFIG_TSEC3_NAME "eTSEC3"
-
-#define TSEC1_PHY_ADDR 2
-#define TSEC2_PHY_ADDR 0
-#define TSEC3_PHY_ADDR 1
-
-#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-
-#define TSEC1_PHYIDX 0
-#define TSEC2_PHYIDX 0
-#define TSEC3_PHYIDX 0
-
-#define CONFIG_ETHPRIME "eTSEC1"
-
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#define CONFIG_HAS_ETH2
-#endif /* CONFIG_TSEC_ENET */
-
-#ifdef CONFIG_QE
-/* QE microcode/firmware address */
-#define CONFIG_SYS_QE_FW_ADDR 0xefec0000
-#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
-#endif /* CONFIG_QE */
-
-#ifdef CONFIG_TARGET_P1025RDB
-/*
- * QE UEC ethernet configuration
- */
-#define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120)
-
-#undef CONFIG_UEC_ETH
-#define CONFIG_PHY_MODE_NEED_CHANGE
-
-#define CONFIG_UEC_ETH1 /* ETH1 */
-#define CONFIG_HAS_ETH0
-
-#ifdef CONFIG_UEC_ETH1
-#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
-#define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */
-#define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */
-#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
-#define CONFIG_SYS_UEC1_PHY_ADDR 0x0 /* 0x0 for MII */
-#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
-#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
-#endif /* CONFIG_UEC_ETH1 */
-
-#define CONFIG_UEC_ETH5 /* ETH5 */
-#define CONFIG_HAS_ETH1
-
-#ifdef CONFIG_UEC_ETH5
-#define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */
-#define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE
-#define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */
-#define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH
-#define CONFIG_SYS_UEC5_PHY_ADDR 0x3 /* 0x3 for RMII */
-#define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
-#define CONFIG_SYS_UEC5_INTERFACE_SPEED 100
-#endif /* CONFIG_UEC_ETH5 */
-#endif /* CONFIG_TARGET_P1025RDB */
-
-/*
- * Environment
- */
-#if defined(CONFIG_SDCARD)
-#define CONFIG_FSL_FIXED_MMC_LOCATION
-#define CONFIG_SYS_MMC_ENV_DEV 0
-#elif defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
-#ifdef CONFIG_TPL_BUILD
-#define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
-#endif
-#elif defined(CONFIG_SYS_RAMBOOT)
-#define SPL_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
-#endif
-
-#define CONFIG_LOADS_ECHO /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
-
-/*
- * USB
- */
-#define CONFIG_HAS_FSL_DR_USB
-
-#if defined(CONFIG_HAS_FSL_DR_USB)
-#ifdef CONFIG_USB_EHCI_HCD
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_USB_EHCI_FSL
-#endif
-#endif
-
-#if defined(CONFIG_TARGET_P1020RDB_PD)
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-#endif
-
-#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
-#endif
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 64 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
-#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-#define CONFIG_HOSTNAME "unknown"
-#define CONFIG_ROOTPATH "/opt/nfsroot"
-#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
-
-/* default location for tftp and bootm */
-#define CONFIG_LOADADDR 1000000
-
-#ifdef __SW_BOOT_NOR
-#define __NOR_RST_CMD \
-norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \
-i2c mw 18 3 __SW_BOOT_MASK 1; reset
-#endif
-#ifdef __SW_BOOT_SPI
-#define __SPI_RST_CMD \
-spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \
-i2c mw 18 3 __SW_BOOT_MASK 1; reset
-#endif
-#ifdef __SW_BOOT_SD
-#define __SD_RST_CMD \
-sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \
-i2c mw 18 3 __SW_BOOT_MASK 1; reset
-#endif
-#ifdef __SW_BOOT_NAND
-#define __NAND_RST_CMD \
-nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \
-i2c mw 18 3 __SW_BOOT_MASK 1; reset
-#endif
-#ifdef __SW_BOOT_PCIE
-#define __PCIE_RST_CMD \
-pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \
-i2c mw 18 3 __SW_BOOT_MASK 1; reset
-#endif
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
-"netdev=eth0\0" \
-"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
-"loadaddr=1000000\0" \
-"bootfile=uImage\0" \
-"tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
- "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
-"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
-"consoledev=ttyS0\0" \
-"ramdiskaddr=2000000\0" \
-"ramdiskfile=rootfs.ext2.gz.uboot\0" \
-"fdtaddr=1e00000\0" \
-"bdev=sda1\0" \
-"jffs2nor=mtdblock3\0" \
-"norbootaddr=ef080000\0" \
-"norfdtaddr=ef040000\0" \
-"jffs2nand=mtdblock9\0" \
-"nandbootaddr=100000\0" \
-"nandfdtaddr=80000\0" \
-"ramdisk_size=120000\0" \
-"map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \
-"map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \
-__stringify(__NOR_RST_CMD)"\0" \
-__stringify(__SPI_RST_CMD)"\0" \
-__stringify(__SD_RST_CMD)"\0" \
-__stringify(__NAND_RST_CMD)"\0" \
-__stringify(__PCIE_RST_CMD)"\0"
-
-#define CONFIG_NFSBOOTCOMMAND \
-"setenv bootargs root=/dev/nfs rw " \
-"nfsroot=$serverip:$rootpath " \
-"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
-"console=$consoledev,$baudrate $othbootargs;" \
-"tftp $loadaddr $bootfile;" \
-"tftp $fdtaddr $fdtfile;" \
-"bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_HDBOOT \
-"setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
-"console=$consoledev,$baudrate $othbootargs;" \
-"usb start;" \
-"ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
-"ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
-"bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_USB_FAT_BOOT \
-"setenv bootargs root=/dev/ram rw " \
-"console=$consoledev,$baudrate $othbootargs " \
-"ramdisk_size=$ramdisk_size;" \
-"usb start;" \
-"fatload usb 0:2 $loadaddr $bootfile;" \
-"fatload usb 0:2 $fdtaddr $fdtfile;" \
-"fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
-"bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_USB_EXT2_BOOT \
-"setenv bootargs root=/dev/ram rw " \
-"console=$consoledev,$baudrate $othbootargs " \
-"ramdisk_size=$ramdisk_size;" \
-"usb start;" \
-"ext2load usb 0:4 $loadaddr $bootfile;" \
-"ext2load usb 0:4 $fdtaddr $fdtfile;" \
-"ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
-"bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_NORBOOT \
-"setenv bootargs root=/dev/$jffs2nor rw " \
-"console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
-"bootm $norbootaddr - $norfdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
-"setenv bootargs root=/dev/ram rw " \
-"console=$consoledev,$baudrate $othbootargs " \
-"ramdisk_size=$ramdisk_size;" \
-"tftp $ramdiskaddr $ramdiskfile;" \
-"tftp $loadaddr $bootfile;" \
-"tftp $fdtaddr $fdtfile;" \
-"bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
-
-#endif /* __CONFIG_H */
--
2.25.1
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 09/24] arm: Remove configs/P1022DS_36BIT_NAND_defconfig board
2020-05-27 16:46 [PATCH 00/24] spi: dm-conversion (part2) Jagan Teki
` (7 preceding siblings ...)
2020-05-27 16:46 ` [PATCH 08/24] arm: Remove configs/P1020MBG-PC_36BIT_SDCARD_defconfig board Jagan Teki
@ 2020-05-27 16:46 ` Jagan Teki
2020-05-28 5:37 ` Priyanka Jain
2020-05-27 16:46 ` [PATCH 10/24] arm: Remove configs/P2041RDB_NAND_defconfig board Jagan Teki
` (13 subsequent siblings)
22 siblings, 1 reply; 59+ messages in thread
From: Jagan Teki @ 2020-05-27 16:46 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_SPI by the deadline.
Remove it.
Patch-cc: Timur Tabi <timur@tabi.org>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
arch/powerpc/cpu/mpc85xx/Kconfig | 1 -
board/freescale/p1022ds/Kconfig | 12 -
board/freescale/p1022ds/MAINTAINERS | 13 -
board/freescale/p1022ds/Makefile | 25 -
board/freescale/p1022ds/README | 23 -
board/freescale/p1022ds/ddr.c | 106 ----
board/freescale/p1022ds/diu.c | 478 ------------------
board/freescale/p1022ds/law.c | 18 -
board/freescale/p1022ds/p1022ds.c | 364 --------------
board/freescale/p1022ds/spl.c | 131 -----
board/freescale/p1022ds/spl_minimal.c | 71 ---
board/freescale/p1022ds/tlb.c | 101 ----
configs/P1022DS_36BIT_NAND_defconfig | 80 ---
configs/P1022DS_36BIT_SDCARD_defconfig | 74 ---
configs/P1022DS_36BIT_SPIFLASH_defconfig | 76 ---
configs/P1022DS_36BIT_defconfig | 62 ---
configs/P1022DS_NAND_defconfig | 79 ---
configs/P1022DS_SDCARD_defconfig | 73 ---
configs/P1022DS_SPIFLASH_defconfig | 75 ---
configs/P1022DS_defconfig | 61 ---
include/configs/P1022DS.h | 593 -----------------------
21 files changed, 2516 deletions(-)
delete mode 100644 board/freescale/p1022ds/Kconfig
delete mode 100644 board/freescale/p1022ds/MAINTAINERS
delete mode 100644 board/freescale/p1022ds/Makefile
delete mode 100644 board/freescale/p1022ds/README
delete mode 100644 board/freescale/p1022ds/ddr.c
delete mode 100644 board/freescale/p1022ds/diu.c
delete mode 100644 board/freescale/p1022ds/law.c
delete mode 100644 board/freescale/p1022ds/p1022ds.c
delete mode 100644 board/freescale/p1022ds/spl.c
delete mode 100644 board/freescale/p1022ds/spl_minimal.c
delete mode 100644 board/freescale/p1022ds/tlb.c
delete mode 100644 configs/P1022DS_36BIT_NAND_defconfig
delete mode 100644 configs/P1022DS_36BIT_SDCARD_defconfig
delete mode 100644 configs/P1022DS_36BIT_SPIFLASH_defconfig
delete mode 100644 configs/P1022DS_36BIT_defconfig
delete mode 100644 configs/P1022DS_NAND_defconfig
delete mode 100644 configs/P1022DS_SDCARD_defconfig
delete mode 100644 configs/P1022DS_SPIFLASH_defconfig
delete mode 100644 configs/P1022DS_defconfig
delete mode 100644 include/configs/P1022DS.h
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index dbb991319b..331adbf712 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -1597,7 +1597,6 @@ source "board/freescale/mpc8555cds/Kconfig"
source "board/freescale/mpc8568mds/Kconfig"
source "board/freescale/mpc8569mds/Kconfig"
source "board/freescale/mpc8572ds/Kconfig"
-source "board/freescale/p1022ds/Kconfig"
source "board/freescale/p1023rdb/Kconfig"
source "board/freescale/p1_twr/Kconfig"
source "board/freescale/p2041rdb/Kconfig"
diff --git a/board/freescale/p1022ds/Kconfig b/board/freescale/p1022ds/Kconfig
deleted file mode 100644
index f1792de8e3..0000000000
--- a/board/freescale/p1022ds/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_P1022DS
-
-config SYS_BOARD
- default "p1022ds"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "P1022DS"
-
-endif
diff --git a/board/freescale/p1022ds/MAINTAINERS b/board/freescale/p1022ds/MAINTAINERS
deleted file mode 100644
index 62256c3703..0000000000
--- a/board/freescale/p1022ds/MAINTAINERS
+++ /dev/null
@@ -1,13 +0,0 @@
-P1022DS BOARD
-M: Timur Tabi <timur@tabi.org>
-S: Maintained
-F: board/freescale/p1022ds/
-F: include/configs/P1022DS.h
-F: configs/P1022DS_defconfig
-F: configs/P1022DS_36BIT_defconfig
-F: configs/P1022DS_36BIT_NAND_defconfig
-F: configs/P1022DS_36BIT_SDCARD_defconfig
-F: configs/P1022DS_36BIT_SPIFLASH_defconfig
-F: configs/P1022DS_NAND_defconfig
-F: configs/P1022DS_SDCARD_defconfig
-F: configs/P1022DS_SPIFLASH_defconfig
diff --git a/board/freescale/p1022ds/Makefile b/board/freescale/p1022ds/Makefile
deleted file mode 100644
index 699e5b5288..0000000000
--- a/board/freescale/p1022ds/Makefile
+++ /dev/null
@@ -1,25 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2010 Freescale Semiconductor, Inc.
-
-MINIMAL=
-
-ifdef CONFIG_SPL_BUILD
-ifdef CONFIG_SPL_INIT_MINIMAL
-MINIMAL=y
-endif
-endif
-
-ifdef MINIMAL
-obj-y += spl_minimal.o
-else
-ifdef CONFIG_SPL_BUILD
-obj-y += spl.o
-endif
-obj-y += p1022ds.o
-obj-y += ddr.o
-obj-$(CONFIG_FSL_DIU_FB) += diu.o
-endif
-
-obj-y += law.o
-obj-y += tlb.o
diff --git a/board/freescale/p1022ds/README b/board/freescale/p1022ds/README
deleted file mode 100644
index 04d9197074..0000000000
--- a/board/freescale/p1022ds/README
+++ /dev/null
@@ -1,23 +0,0 @@
-Overview
---------
-P1022ds is a Low End Dual core platform supporting the P1022 processor
-of QorIQ series. P1022 is an e500 based dual core SOC.
-
-
-Pin Multiplex(hwconfig setting)
--------------------------------
-Add the environment 'usb2', 'audclk' and 'tdm' to support pin multiplex
-via hwconfig, i.e:
-'setenv hwconfig usb2' to enable USB2 and disable eTsec2
-'setenv hwconfig tdm' to enable TDM and disable Audio
-'setenv hwconfig audclk:12' to enable Audio(codec clock sources is 12MHz)
- and disable TDM
-'setenv hwconfig 'usb2;tdm' to enable USB2 and TDM, disable eTsec2 and Audio
-'setenv hwconfig 'usb2;audclk:11' to enable USB2 and Audio(codec clock sources
- is 11MHz), disable eTsec2 and TDM
-
-Warning: TDM and AUDIO can not enable simultaneous !
-and AUDIO codec clock sources only setting as 11MHz or 12MHz !
-'setenv hwconfig 'audclk:12;tdm' --- error !
-'setenv hwconfig 'audclk:11;tdm' --- error !
-'setenv hwconfig 'audclk:10' --- error !
diff --git a/board/freescale/p1022ds/ddr.c b/board/freescale/p1022ds/ddr.c
deleted file mode 100644
index 70932115f4..0000000000
--- a/board/freescale/p1022ds/ddr.c
+++ /dev/null
@@ -1,106 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2010 Freescale Semiconductor, Inc.
- * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
- * Timur Tabi <timur@freescale.com>
- */
-
-#include <common.h>
-
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-
-struct board_specific_parameters {
- u32 n_ranks;
- u32 datarate_mhz_high;
- u32 clk_adjust; /* Range: 0-8 */
- u32 cpo; /* Range: 2-31 */
- u32 write_data_delay; /* Range: 0-6 */
- u32 force_2t;
-};
-
-/*
- * This table contains all valid speeds we want to override with board
- * specific parameters. datarate_mhz_high values need to be in ascending order
- * for each n_ranks group.
- */
-static const struct board_specific_parameters dimm0[] = {
- /*
- * memory controller 0
- * num| hi| clk| cpo|wrdata|2T
- * ranks| mhz|adjst| | delay|
- */
- {1, 549, 5, 31, 3, 0},
- {1, 850, 5, 31, 5, 0},
- {2, 549, 5, 31, 3, 0},
- {2, 850, 5, 31, 5, 0},
- {}
-};
-
-void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
- unsigned long ddr_freq;
- unsigned int i;
-
-
- if (ctrl_num) {
- printf("Wrong parameter for controller number %d", ctrl_num);
- return;
- }
- if (!pdimm->n_ranks)
- return;
-
- /* set odt_rd_cfg and odt_wr_cfg. */
- for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
- popts->cs_local_opts[i].odt_rd_cfg = 0;
- popts->cs_local_opts[i].odt_wr_cfg = 1;
- }
-
- pbsp = dimm0;
- /*
- * Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
- * freqency and n_banks specified in board_specific_parameters table.
- */
- ddr_freq = get_ddr_freq(0) / 1000000;
- while (pbsp->datarate_mhz_high) {
- if (pbsp->n_ranks == pdimm->n_ranks) {
- if (ddr_freq <= pbsp->datarate_mhz_high) {
- popts->clk_adjust = pbsp->clk_adjust;
- popts->cpo_override = pbsp->cpo;
- popts->write_data_delay =
- pbsp->write_data_delay;
- popts->twot_en = pbsp->force_2t;
- goto found;
- }
- pbsp_highest = pbsp;
- }
- pbsp++;
- }
-
- if (pbsp_highest) {
- printf("Error: board specific timing not found "
- "for data rate %lu MT/s!\n"
- "Trying to use the highest speed (%u) parameters\n",
- ddr_freq, pbsp_highest->datarate_mhz_high);
- popts->clk_adjust = pbsp->clk_adjust;
- popts->cpo_override = pbsp->cpo;
- popts->write_data_delay = pbsp->write_data_delay;
- popts->twot_en = pbsp->force_2t;
- } else {
- panic("DIMM is not supported by this board");
- }
-
-found:
- popts->half_strength_driver_enable = 1;
-
- /* Per AN4039, enable ZQ calibration. */
- popts->zq_en = 1;
-
- /*
- * For wake-up on ARP, we need auto self refresh enabled
- */
- popts->auto_self_refresh_en = 1;
- popts->sr_it = 0xb;
-}
diff --git a/board/freescale/p1022ds/diu.c b/board/freescale/p1022ds/diu.c
deleted file mode 100644
index 918b4b9f6a..0000000000
--- a/board/freescale/p1022ds/diu.c
+++ /dev/null
@@ -1,478 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2010-2011 Freescale Semiconductor, Inc.
- * Authors: Timur Tabi <timur@freescale.com>
- *
- * FSL DIU Framebuffer driver
- */
-
-#include <common.h>
-#include <clock_legacy.h>
-#include <command.h>
-#include <log.h>
-#include <linux/ctype.h>
-#include <asm/io.h>
-#include <stdio_dev.h>
-#include <video_fb.h>
-#include "../common/ngpixis.h"
-#include <fsl_diu_fb.h>
-
-/* The CTL register is called 'csr' in the ngpixis_t structure */
-#define PX_CTL_ALTACC 0x80
-
-#define PX_BRDCFG0_ELBC_SPI_MASK 0xc0
-#define PX_BRDCFG0_ELBC_SPI_ELBC 0x00
-#define PX_BRDCFG0_ELBC_SPI_NULL 0xc0
-#define PX_BRDCFG0_ELBC_DIU 0x02
-
-#define PX_BRDCFG1_DVIEN 0x80
-#define PX_BRDCFG1_DFPEN 0x40
-#define PX_BRDCFG1_BACKLIGHT 0x20
-
-#define PMUXCR_ELBCDIU_MASK 0xc0000000
-#define PMUXCR_ELBCDIU_NOR16 0x80000000
-#define PMUXCR_ELBCDIU_DIU 0x40000000
-
-/*
- * DIU Area Descriptor
- *
- * Note that we need to byte-swap the value before it's written to the AD
- * register. So even though the registers don't look like they're in the same
- * bit positions as they are on the MPC8610, the same value is written to the
- * AD register on the MPC8610 and on the P1022.
- */
-#define AD_BYTE_F 0x10000000
-#define AD_ALPHA_C_SHIFT 25
-#define AD_BLUE_C_SHIFT 23
-#define AD_GREEN_C_SHIFT 21
-#define AD_RED_C_SHIFT 19
-#define AD_PIXEL_S_SHIFT 16
-#define AD_COMP_3_SHIFT 12
-#define AD_COMP_2_SHIFT 8
-#define AD_COMP_1_SHIFT 4
-#define AD_COMP_0_SHIFT 0
-
-/*
- * Variables used by the DIU/LBC switching code. It's safe to makes these
- * global, because the DIU requires DDR, so we'll only run this code after
- * relocation.
- */
-static u8 px_brdcfg0;
-static u32 pmuxcr;
-static void *lbc_lcs0_ba;
-static void *lbc_lcs1_ba;
-static u32 old_br0, old_or0, old_br1, old_or1;
-static u32 new_br0, new_or0, new_br1, new_or1;
-
-void diu_set_pixel_clock(unsigned int pixclock)
-{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- unsigned long speed_ccb, temp;
- u32 pixval;
-
- speed_ccb = get_bus_freq(0);
- temp = 1000000000 / pixclock;
- temp *= 1000;
- pixval = speed_ccb / temp;
- debug("DIU pixval = %u\n", pixval);
-
- /* Modify PXCLK in GUTS CLKDVDR */
- temp = in_be32(&gur->clkdvdr) & 0x2000FFFF;
- out_be32(&gur->clkdvdr, temp); /* turn off clock */
- out_be32(&gur->clkdvdr, temp | 0x80000000 | ((pixval & 0x1F) << 16));
-}
-
-int platform_diu_init(unsigned int xres, unsigned int yres, const char *port)
-{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- const char *name;
- u32 pixel_format;
- u8 temp;
- phys_addr_t phys0, phys1; /* BR0/BR1 physical addresses */
-
- /*
- * Indirect mode requires both BR0 and BR1 to be set to "GPCM",
- * otherwise writes to these addresses won't actually appear on the
- * local bus, and so the PIXIS won't see them.
- *
- * In FCM mode, writes go to the NAND controller, which does not pass
- * them to the localbus directly. So we force BR0 and BR1 into GPCM
- * mode, since we don't care about what's behind the localbus any
- * more. However, we save those registers first, so that we can
- * restore them when necessary.
- */
- new_br0 = old_br0 = get_lbc_br(0);
- new_br1 = old_br1 = get_lbc_br(1);
- new_or0 = old_or0 = get_lbc_or(0);
- new_or1 = old_or1 = get_lbc_or(1);
-
- /*
- * Use the existing BRx/ORx values if it's already GPCM. Otherwise,
- * force the values to simple 32KB GPCM windows with the most
- * conservative timing.
- */
- if ((old_br0 & BR_MSEL) != BR_MS_GPCM) {
- new_br0 = (get_lbc_br(0) & BR_BA) | BR_V;
- new_or0 = OR_AM_32KB | 0xFF7;
- set_lbc_br(0, new_br0);
- set_lbc_or(0, new_or0);
- }
- if ((old_br1 & BR_MSEL) != BR_MS_GPCM) {
- new_br1 = (get_lbc_br(1) & BR_BA) | BR_V;
- new_or1 = OR_AM_32KB | 0xFF7;
- set_lbc_br(1, new_br1);
- set_lbc_or(1, new_or1);
- }
-
- /*
- * Determine the physical addresses for Chip Selects 0 and 1. The
- * BR0/BR1 registers contain the truncated physical addresses for the
- * chip selects, mapped via the localbus LAW. Since the BRx registers
- * only contain the lower 32 bits of the address, we have to determine
- * the upper 4 bits some other way. The proper way is to scan the LAW
- * table looking for a matching localbus address. Instead, we cheat.
- * We know that the upper bits are 0 for 32-bit addressing, or 0xF for
- * 36-bit addressing.
- */
-#ifdef CONFIG_PHYS_64BIT
- phys0 = 0xf00000000ULL | (old_br0 & old_or0 & BR_BA);
- phys1 = 0xf00000000ULL | (old_br1 & old_or1 & BR_BA);
-#else
- phys0 = old_br0 & old_or0 & BR_BA;
- phys1 = old_br1 & old_or1 & BR_BA;
-#endif
-
- /* Save the LBC LCS0 and LCS1 addresses for the DIU mux functions */
- lbc_lcs0_ba = map_physmem(phys0, 1, 0);
- lbc_lcs1_ba = map_physmem(phys1, 1, 0);
-
- pixel_format = cpu_to_le32(AD_BYTE_F | (3 << AD_ALPHA_C_SHIFT) |
- (0 << AD_BLUE_C_SHIFT) | (1 << AD_GREEN_C_SHIFT) |
- (2 << AD_RED_C_SHIFT) | (8 << AD_COMP_3_SHIFT) |
- (8 << AD_COMP_2_SHIFT) | (8 << AD_COMP_1_SHIFT) |
- (8 << AD_COMP_0_SHIFT) | (3 << AD_PIXEL_S_SHIFT));
-
- temp = in_8(&pixis->brdcfg1);
-
- if (strncmp(port, "lvds", 4) == 0) {
- /* Single link LVDS */
- temp &= ~PX_BRDCFG1_DVIEN;
- /*
- * LVDS also needs backlight enabled, otherwise the display
- * will be blank.
- */
- temp |= (PX_BRDCFG1_DFPEN | PX_BRDCFG1_BACKLIGHT);
- name = "Single-Link LVDS";
- } else { /* DVI */
- /* Enable the DVI port, disable the DFP and the backlight */
- temp &= ~(PX_BRDCFG1_DFPEN | PX_BRDCFG1_BACKLIGHT);
- temp |= PX_BRDCFG1_DVIEN;
- name = "DVI";
- }
-
- printf("DIU: Switching to %s monitor @ %ux%u\n", name, xres, yres);
- out_8(&pixis->brdcfg1, temp);
-
- /*
- * Enable PIXIS indirect access mode. This is a hack that allows us to
- * access PIXIS registers even when the LBC pins have been muxed to the
- * DIU.
- */
- setbits_8(&pixis->csr, PX_CTL_ALTACC);
-
- /*
- * Route the LAD pins to the DIU. This will disable access to the eLBC,
- * which means we won't be able to read/write any NOR flash addresses!
- */
- out_8(lbc_lcs0_ba, offsetof(ngpixis_t, brdcfg0));
- px_brdcfg0 = in_8(lbc_lcs1_ba);
- out_8(lbc_lcs1_ba, px_brdcfg0 | PX_BRDCFG0_ELBC_DIU);
- in_8(lbc_lcs1_ba);
-
- /* Set PMUXCR to switch the muxed pins from the LBC to the DIU */
- clrsetbits_be32(&gur->pmuxcr, PMUXCR_ELBCDIU_MASK, PMUXCR_ELBCDIU_DIU);
- pmuxcr = in_be32(&gur->pmuxcr);
-
- return fsl_diu_init(xres, yres, pixel_format, 0);
-}
-
-/*
- * set_mux_to_lbc - disable the DIU so that we can read/write to elbc
- *
- * On the Freescale P1022, the DIU video signal and the LBC address/data lines
- * share the same pins, which means that when the DIU is active (e.g. the
- * console is on the DVI display), NOR flash cannot be accessed. So we use the
- * weak accessor feature of the CFI flash code to temporarily switch the pin
- * mux from DIU to LBC whenever we want to read or write flash. This has a
- * significant performance penalty, but it's the only way to make it work.
- *
- * There are two muxes: one on the chip, and one on the board. The chip mux
- * controls whether the pins are used for the DIU or the LBC, and it is
- * set via PMUXCR. The board mux controls whether those signals go to
- * the video connector or the NOR flash chips, and it is set via the ngPIXIS.
- */
-static int set_mux_to_lbc(void)
-{
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
- /* Switch the muxes only if they're currently set to DIU mode */
- if ((in_be32(&gur->pmuxcr) & PMUXCR_ELBCDIU_MASK) !=
- PMUXCR_ELBCDIU_NOR16) {
- /*
- * In DIU mode, the PIXIS can only be accessed indirectly
- * since we can't read/write the LBC directly.
- */
- /* Set the board mux to LBC. This will disable the display. */
- out_8(lbc_lcs0_ba, offsetof(ngpixis_t, brdcfg0));
- out_8(lbc_lcs1_ba, px_brdcfg0);
- in_8(lbc_lcs1_ba);
-
- /* Disable indirect PIXIS mode */
- out_8(lbc_lcs0_ba, offsetof(ngpixis_t, csr));
- clrbits_8(lbc_lcs1_ba, PX_CTL_ALTACC);
-
- /* Set the chip mux to LBC mode, so that writes go to flash. */
- out_be32(&gur->pmuxcr, (pmuxcr & ~PMUXCR_ELBCDIU_MASK) |
- PMUXCR_ELBCDIU_NOR16);
- in_be32(&gur->pmuxcr);
-
- /* Restore the BR0 and BR1 settings */
- set_lbc_br(0, old_br0);
- set_lbc_or(0, old_or0);
- set_lbc_br(1, old_br1);
- set_lbc_or(1, old_or1);
-
- return 1;
- }
-
- return 0;
-}
-
-/*
- * set_mux_to_diu - re-enable the DIU muxing
- *
- * This function restores the chip and board muxing to point to the DIU.
- */
-static void set_mux_to_diu(void)
-{
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
- /* Set BR0 and BR1 to GPCM mode */
- set_lbc_br(0, new_br0);
- set_lbc_or(0, new_or0);
- set_lbc_br(1, new_br1);
- set_lbc_or(1, new_or1);
-
- /* Enable indirect PIXIS mode */
- setbits_8(&pixis->csr, PX_CTL_ALTACC);
-
- /* Set the board mux to DIU. This will enable the display. */
- out_8(lbc_lcs0_ba, offsetof(ngpixis_t, brdcfg0));
- out_8(lbc_lcs1_ba, px_brdcfg0 | PX_BRDCFG0_ELBC_DIU);
- in_8(lbc_lcs1_ba);
-
- /* Set the chip mux to DIU mode. */
- out_be32(&gur->pmuxcr, pmuxcr);
- in_be32(&gur->pmuxcr);
-}
-
-/*
- * pixis_read - board-specific function to read from the PIXIS
- *
- * This function overrides the generic pixis_read() function, so that it can
- * use PIXIS indirect mode if necessary.
- */
-u8 pixis_read(unsigned int reg)
-{
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
- /* Use indirect mode if the mux is currently set to DIU mode */
- if ((in_be32(&gur->pmuxcr) & PMUXCR_ELBCDIU_MASK) !=
- PMUXCR_ELBCDIU_NOR16) {
- out_8(lbc_lcs0_ba, reg);
- return in_8(lbc_lcs1_ba);
- } else {
- void *p = (void *)PIXIS_BASE;
-
- return in_8(p + reg);
- }
-}
-
-/*
- * pixis_write - board-specific function to write to the PIXIS
- *
- * This function overrides the generic pixis_write() function, so that it can
- * use PIXIS indirect mode if necessary.
- */
-void pixis_write(unsigned int reg, u8 value)
-{
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
- /* Use indirect mode if the mux is currently set to DIU mode */
- if ((in_be32(&gur->pmuxcr) & PMUXCR_ELBCDIU_MASK) !=
- PMUXCR_ELBCDIU_NOR16) {
- out_8(lbc_lcs0_ba, reg);
- out_8(lbc_lcs1_ba, value);
- /* Do a read-back to ensure the write completed */
- in_8(lbc_lcs1_ba);
- } else {
- void *p = (void *)PIXIS_BASE;
-
- out_8(p + reg, value);
- }
-}
-
-void pixis_bank_reset(void)
-{
- /*
- * For some reason, a PIXIS bank reset does not work if the PIXIS is
- * in indirect mode, so switch to direct mode first.
- */
- set_mux_to_lbc();
-
- out_8(&pixis->vctl, 0);
- out_8(&pixis->vctl, 1);
-
- while (1);
-}
-
-#ifdef CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
-
-void flash_write8(u8 value, void *addr)
-{
- int sw = set_mux_to_lbc();
-
- __raw_writeb(value, addr);
- if (sw) {
- /*
- * To ensure the post-write is completed to eLBC, software must
- * perform a dummy read from one valid address from eLBC space
- * before changing the eLBC_DIU from NOR mode to DIU mode.
- * set_mux_to_diu() includes a sync that will ensure the
- * __raw_readb() completes before it switches the mux.
- */
- __raw_readb(addr);
- set_mux_to_diu();
- }
-}
-
-void flash_write16(u16 value, void *addr)
-{
- int sw = set_mux_to_lbc();
-
- __raw_writew(value, addr);
- if (sw) {
- /*
- * To ensure the post-write is completed to eLBC, software must
- * perform a dummy read from one valid address from eLBC space
- * before changing the eLBC_DIU from NOR mode to DIU mode.
- * set_mux_to_diu() includes a sync that will ensure the
- * __raw_readb() completes before it switches the mux.
- */
- __raw_readb(addr);
- set_mux_to_diu();
- }
-}
-
-void flash_write32(u32 value, void *addr)
-{
- int sw = set_mux_to_lbc();
-
- __raw_writel(value, addr);
- if (sw) {
- /*
- * To ensure the post-write is completed to eLBC, software must
- * perform a dummy read from one valid address from eLBC space
- * before changing the eLBC_DIU from NOR mode to DIU mode.
- * set_mux_to_diu() includes a sync that will ensure the
- * __raw_readb() completes before it switches the mux.
- */
- __raw_readb(addr);
- set_mux_to_diu();
- }
-}
-
-void flash_write64(u64 value, void *addr)
-{
- int sw = set_mux_to_lbc();
- uint32_t *p = addr;
-
- /*
- * There is no __raw_writeq(), so do the write manually. We don't trust
- * the compiler, so we use inline assembly.
- */
- __asm__ __volatile__(
- "stw%U0%X0 %2,%0;\n"
- "stw%U1%X1 %3,%1;\n"
- : "=m" (*p), "=m" (*(p + 1))
- : "r" ((uint32_t) (value >> 32)), "r" ((uint32_t) (value)));
-
- if (sw) {
- /*
- * To ensure the post-write is completed to eLBC, software must
- * perform a dummy read from one valid address from eLBC space
- * before changing the eLBC_DIU from NOR mode to DIU mode. We
- * read addr+4 because we just wrote to addr+4, so that's how we
- * maintain execution order. set_mux_to_diu() includes a sync
- * that will ensure the __raw_readb() completes before it
- * switches the mux.
- */
- __raw_readb(addr + 4);
- set_mux_to_diu();
- }
-}
-
-u8 flash_read8(void *addr)
-{
- u8 ret;
-
- int sw = set_mux_to_lbc();
-
- ret = __raw_readb(addr);
- if (sw)
- set_mux_to_diu();
-
- return ret;
-}
-
-u16 flash_read16(void *addr)
-{
- u16 ret;
-
- int sw = set_mux_to_lbc();
-
- ret = __raw_readw(addr);
- if (sw)
- set_mux_to_diu();
-
- return ret;
-}
-
-u32 flash_read32(void *addr)
-{
- u32 ret;
-
- int sw = set_mux_to_lbc();
-
- ret = __raw_readl(addr);
- if (sw)
- set_mux_to_diu();
-
- return ret;
-}
-
-u64 flash_read64(void *addr)
-{
- u64 ret;
-
- int sw = set_mux_to_lbc();
-
- /* There is no __raw_readq(), so do the read manually */
- ret = *(volatile u64 *)addr;
- if (sw)
- set_mux_to_diu();
-
- return ret;
-}
-
-#endif
diff --git a/board/freescale/p1022ds/law.c b/board/freescale/p1022ds/law.c
deleted file mode 100644
index 079095d008..0000000000
--- a/board/freescale/p1022ds/law.c
+++ /dev/null
@@ -1,18 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2010 Freescale Semiconductor, Inc.
- * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
- * Timur Tabi <timur@freescale.com>
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-struct law_entry law_table[] = {
- SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
- SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
- SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_32K, LAW_TRGT_IF_LBC),
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/p1022ds/p1022ds.c b/board/freescale/p1022ds/p1022ds.c
deleted file mode 100644
index d10160d17a..0000000000
--- a/board/freescale/p1022ds/p1022ds.c
+++ /dev/null
@@ -1,364 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2010-2012 Freescale Semiconductor, Inc.
- * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
- * Timur Tabi <timur@freescale.com>
- */
-
-#include <common.h>
-#include <command.h>
-#include <env.h>
-#include <image.h>
-#include <init.h>
-#include <log.h>
-#include <net.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_pci.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/fsl_serdes.h>
-#include <asm/io.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <fsl_mdio.h>
-#include <tsec.h>
-#include <asm/fsl_law.h>
-#include <netdev.h>
-#include <i2c.h>
-#include <hwconfig.h>
-
-#include "../common/ngpixis.h"
-
-int board_early_init_f(void)
-{
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
- /* Set pmuxcr to allow both i2c1 and i2c2 */
- setbits_be32(&gur->pmuxcr, 0x1000);
-#ifdef CONFIG_SYS_RAMBOOT
- setbits_be32(&gur->pmuxcr,
- in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA);
-#endif
-
- /* Read back the register to synchronize the write. */
- in_be32(&gur->pmuxcr);
-
- /* Set the pin muxing to enable ETSEC2. */
- clrbits_be32(&gur->pmuxcr2, 0x001F8000);
-
- /* Enable the SPI */
- clrsetbits_8(&pixis->brdcfg0, PIXIS_ELBC_SPI_MASK, PIXIS_SPI);
-
- return 0;
-}
-
-int checkboard(void)
-{
- u8 sw;
-
- printf("Board: P1022DS Sys ID: 0x%02x, "
- "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
- in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
-
- sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
-
- switch ((sw & PIXIS_LBMAP_MASK) >> 6) {
- case 0:
- printf ("vBank: %u\n", ((sw & 0x30) >> 4));
- break;
- case 1:
- printf ("NAND\n");
- break;
- case 2:
- case 3:
- puts ("Promjet\n");
- break;
- }
-
- return 0;
-}
-
-#define CONFIG_TFP410_I2C_ADDR 0x38
-
-/* Masks for the SSI_TDM and AUDCLK bits of the ngPIXIS BRDCFG1 register. */
-#define CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK 0x0c
-#define CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK 0x03
-
-/* Route the I2C1 pins to the SSI port instead. */
-#define CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI 0x08
-
-/* Choose the 12.288Mhz codec reference clock */
-#define CONFIG_PIXIS_BRDCFG1_AUDCLK_12 0x02
-
-/* Choose the 11.2896Mhz codec reference clock */
-#define CONFIG_PIXIS_BRDCFG1_AUDCLK_11 0x01
-
-/* Connect to USB2 */
-#define CONFIG_PIXIS_BRDCFG0_USB2 0x10
-/* Connect to TFM bus */
-#define CONFIG_PIXIS_BRDCFG1_TDM 0x0c
-/* Connect to SPI */
-#define CONFIG_PIXIS_BRDCFG0_SPI 0x80
-
-int misc_init_r(void)
-{
- u8 temp;
- const char *audclk;
- size_t arglen;
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-
- /* For DVI, enable the TFP410 Encoder. */
-
- temp = 0xBF;
- if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0)
- return -1;
- if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0)
- return -1;
- debug("DVI Encoder Read: 0x%02x\n", temp);
-
- temp = 0x10;
- if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0)
- return -1;
- if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0)
- return -1;
- debug("DVI Encoder Read: 0x%02x\n",temp);
-
- /* Enable the USB2 in PMUXCR2 and FGPA */
- if (hwconfig("usb2")) {
- clrsetbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_ETSECUSB_MASK,
- MPC85xx_PMUXCR2_USB);
- setbits_8(&pixis->brdcfg0, CONFIG_PIXIS_BRDCFG0_USB2);
- }
-
- /* tdm and audio can not enable simultaneous*/
- if (hwconfig("tdm") && hwconfig("audclk")){
- printf("WARNING: TDM and AUDIO can not be enabled simultaneous !\n");
- return -1;
- }
-
- /* Enable the TDM in PMUXCR and FGPA */
- if (hwconfig("tdm")) {
- clrsetbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TDM_MASK,
- MPC85xx_PMUXCR_TDM);
- setbits_8(&pixis->brdcfg1, CONFIG_PIXIS_BRDCFG1_TDM);
- /* TDM need some configration option by SPI */
- clrsetbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SPI_MASK,
- MPC85xx_PMUXCR_SPI);
- setbits_8(&pixis->brdcfg0, CONFIG_PIXIS_BRDCFG0_SPI);
- }
-
- /*
- * Enable the reference clock for the WM8776 codec, and route the MUX
- * pins for SSI. The default is the 12.288 MHz clock
- */
-
- if (hwconfig("audclk")) {
- temp = in_8(&pixis->brdcfg1) & ~(CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK |
- CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK);
- temp |= CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI;
-
- audclk = hwconfig_arg("audclk", &arglen);
- /* Check the first two chars only */
- if (audclk && (strncmp(audclk, "11", 2) == 0))
- temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_11;
- else
- temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_12;
- setbits_8(&pixis->brdcfg1, temp);
- }
-
- return 0;
-}
-
-/*
- * A list of PCI and SATA slots
- */
-enum slot_id {
- SLOT_PCIE1 = 1,
- SLOT_PCIE2,
- SLOT_PCIE3,
- SLOT_PCIE4,
- SLOT_PCIE5,
- SLOT_SATA1,
- SLOT_SATA2
-};
-
-/*
- * This array maps the slot identifiers to their names on the P1022DS board.
- */
-static const char *slot_names[] = {
- [SLOT_PCIE1] = "Slot 1",
- [SLOT_PCIE2] = "Slot 2",
- [SLOT_PCIE3] = "Slot 3",
- [SLOT_PCIE4] = "Slot 4",
- [SLOT_PCIE5] = "Mini-PCIe",
- [SLOT_SATA1] = "SATA 1",
- [SLOT_SATA2] = "SATA 2",
-};
-
-/*
- * This array maps a given SERDES configuration and SERDES device to the PCI or
- * SATA slot that it connects to. This mapping is hard-coded in the FPGA.
- */
-static u8 serdes_dev_slot[][SATA2 + 1] = {
- [0x01] = { [PCIE3] = SLOT_PCIE4, [PCIE2] = SLOT_PCIE5 },
- [0x02] = { [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
- [0x09] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE4,
- [PCIE2] = SLOT_PCIE5 },
- [0x16] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2,
- [PCIE2] = SLOT_PCIE3,
- [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
- [0x17] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2,
- [PCIE2] = SLOT_PCIE3 },
- [0x1a] = { [PCIE1] = SLOT_PCIE1, [PCIE2] = SLOT_PCIE3,
- [PCIE2] = SLOT_PCIE3,
- [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
- [0x1c] = { [PCIE1] = SLOT_PCIE1,
- [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
- [0x1e] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE3 },
- [0x1f] = { [PCIE1] = SLOT_PCIE1 },
-};
-
-
-/*
- * Returns the name of the slot to which the PCIe or SATA controller is
- * connected
- */
-const char *board_serdes_name(enum srds_prtcl device)
-{
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
- u32 pordevsr = in_be32(&gur->pordevsr);
- unsigned int srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
- MPC85xx_PORDEVSR_IO_SEL_SHIFT;
- enum slot_id slot = serdes_dev_slot[srds_cfg][device];
- const char *name = slot_names[slot];
-
- if (name)
- return name;
- else
- return "Nothing";
-}
-
-#ifdef CONFIG_PCI
-void pci_init_board(void)
-{
- fsl_pcie_init_board(0);
-}
-#endif
-
-int board_early_init_r(void)
-{
- const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
- int flash_esel = find_tlb_idx((void *)flashbase, 1);
-
- /*
- * Remap Boot flash + PROMJET region to caching-inhibited
- * so that flash can be erased properly.
- */
-
- /* Flush d-cache and invalidate i-cache of any FLASH data */
- flush_dcache();
- invalidate_icache();
-
- if (flash_esel == -1) {
- /* very unlikely unless something is messed up */
- puts("Error: Could not find TLB for FLASH BASE\n");
- flash_esel = 2; /* give our best effort to continue */
- } else {
- /* invalidate existing TLB entry for flash + promjet */
- disable_tlb(flash_esel);
- }
-
- set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, flash_esel, BOOKE_PAGESZ_256M, 1);
-
- return 0;
-}
-
-/*
- * Initialize on-board and/or PCI Ethernet devices
- *
- * Returns:
- * <0, error
- * 0, no ethernet devices found
- * >0, number of ethernet devices initialized
- */
-int board_eth_init(bd_t *bis)
-{
- struct fsl_pq_mdio_info mdio_info;
- struct tsec_info_struct tsec_info[2];
- unsigned int num = 0;
-
-#ifdef CONFIG_TSEC1
- SET_STD_TSEC_INFO(tsec_info[num], 1);
- num++;
-#endif
-#ifdef CONFIG_TSEC2
- SET_STD_TSEC_INFO(tsec_info[num], 2);
- num++;
-#endif
-
- mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
- mdio_info.name = DEFAULT_MII_NAME;
- fsl_pq_mdio_init(bis, &mdio_info);
-
- return tsec_eth_init(bis, tsec_info, num) + pci_eth_init(bis);
-}
-
-#ifdef CONFIG_OF_BOARD_SETUP
-/**
- * ft_codec_setup - fix up the clock-frequency property of the codec node
- *
- * Update the clock-frequency property based on the value of the 'audclk'
- * hwconfig option. If audclk is not specified, then don't write anything
- * to the device tree, because it means that the codec clock is disabled.
- */
-static void ft_codec_setup(void *blob, const char *compatible)
-{
- const char *audclk;
- size_t arglen;
- u32 freq;
-
- audclk = hwconfig_arg("audclk", &arglen);
- if (audclk) {
- if (strncmp(audclk, "11", 2) == 0)
- freq = 11289600;
- else
- freq = 12288000;
-
- do_fixup_by_compat_u32(blob, compatible, "clock-frequency",
- freq, 1);
- }
-}
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
- phys_addr_t base;
- phys_size_t size;
-
- ft_cpu_setup(blob, bd);
-
- base = env_get_bootm_low();
- size = env_get_bootm_size();
-
- fdt_fixup_memory(blob, (u64)base, (u64)size);
-
-#ifdef CONFIG_HAS_FSL_DR_USB
- fsl_fdt_fixup_dr_usb(blob, bd);
-#endif
-
- FT_FSL_PCI_SETUP;
-
-#ifdef CONFIG_FSL_SGMII_RISER
- fsl_sgmii_riser_fdt_fixup(blob);
-#endif
-
- /* Update the WM8776 node's clock frequency property */
- ft_codec_setup(blob, "wlf,wm8776");
-
- return 0;
-}
-#endif
diff --git a/board/freescale/p1022ds/spl.c b/board/freescale/p1022ds/spl.c
deleted file mode 100644
index 39e1bee6f3..0000000000
--- a/board/freescale/p1022ds/spl.c
+++ /dev/null
@@ -1,131 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <clock_legacy.h>
-#include <console.h>
-#include <env.h>
-#include <env_internal.h>
-#include <init.h>
-#include <ns16550.h>
-#include <malloc.h>
-#include <mmc.h>
-#include <nand.h>
-#include <i2c.h>
-#include "../common/ngpixis.h"
-#include <fsl_esdhc.h>
-#include <spi_flash.h>
-#include "../common/spl.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static const u32 sysclk_tbl[] = {
- 66666000, 7499900, 83332500, 8999900,
- 99999000, 11111000, 12499800, 13333200
-};
-
-phys_size_t get_effective_memsize(void)
-{
- return CONFIG_SYS_L2_SIZE;
-}
-
-void board_init_f(ulong bootflag)
-{
- int px_spd;
- u32 plat_ratio, sys_clk, bus_clk;
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
- console_init_f();
-
- /* Set pmuxcr to allow both i2c1 and i2c2 */
- setbits_be32(&gur->pmuxcr, in_be32(&gur->pmuxcr) | 0x1000);
- setbits_be32(&gur->pmuxcr,
- in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA);
-
-#ifdef CONFIG_SPL_SPI_BOOT
- /* Enable the SPI */
- clrsetbits_8(&pixis->brdcfg0, PIXIS_ELBC_SPI_MASK, PIXIS_SPI);
-#endif
-
- /* Read back the register to synchronize the write. */
- in_be32(&gur->pmuxcr);
-
- /* initialize selected port with appropriate baud rate */
- px_spd = in_8((unsigned char *)(PIXIS_BASE + PIXIS_SPD));
- sys_clk = sysclk_tbl[px_spd & PIXIS_SPD_SYSCLK_MASK];
- plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
- bus_clk = sys_clk * plat_ratio / 2;
-
- NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
- bus_clk / 16 / CONFIG_BAUDRATE);
-#ifdef CONFIG_SPL_MMC_BOOT
- puts("\nSD boot...\n");
-#elif defined(CONFIG_SPL_SPI_BOOT)
- puts("\nSPI Flash boot...\n");
-#endif
-
- /* copy code to RAM and jump to it - this should not return */
- /* NOTE - code has to be copied out of NAND buffer before
- * other blocks can be read.
- */
- relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
- /* Pointer is writable since we allocated a register for it */
- gd = (gd_t *)CONFIG_SPL_GD_ADDR;
- bd_t *bd;
-
- memset(gd, 0, sizeof(gd_t));
- bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
- memset(bd, 0, sizeof(bd_t));
- gd->bd = bd;
- bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
- bd->bi_memsize = CONFIG_SYS_L2_SIZE;
-
- arch_cpu_init();
- get_clocks();
- mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
- CONFIG_SPL_RELOC_MALLOC_SIZE);
- gd->flags |= GD_FLG_FULL_MALLOC_INIT;
-#ifndef CONFIG_SPL_NAND_BOOT
- env_init();
-#endif
-#ifdef CONFIG_SPL_MMC_BOOT
- mmc_initialize(bd);
-#endif
- /* relocate environment function pointers etc. */
-#ifdef CONFIG_SPL_NAND_BOOT
- nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
- (uchar *)SPL_ENV_ADDR);
-
- gd->env_addr = (ulong)(SPL_ENV_ADDR);
- gd->env_valid = ENV_VALID;
-#else
- env_relocate();
-#endif
-
-#ifdef CONFIG_SYS_I2C
- i2c_init_all();
-#else
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-#endif
-
- dram_init();
-#ifdef CONFIG_SPL_NAND_BOOT
- puts("Tertiary program loader running in sram...");
-#else
- puts("Second program loader running in sram...\n");
-#endif
-
-#ifdef CONFIG_SPL_MMC_BOOT
- mmc_boot();
-#elif defined(CONFIG_SPL_SPI_BOOT)
- fsl_spi_boot();
-#elif defined(CONFIG_SPL_NAND_BOOT)
- nand_boot();
-#endif
-}
diff --git a/board/freescale/p1022ds/spl_minimal.c b/board/freescale/p1022ds/spl_minimal.c
deleted file mode 100644
index 31de26318d..0000000000
--- a/board/freescale/p1022ds/spl_minimal.c
+++ /dev/null
@@ -1,71 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2011 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <init.h>
-#include <ns16550.h>
-#include <asm/io.h>
-#include <nand.h>
-#include <asm/fsl_law.h>
-#include <fsl_ddr_sdram.h>
-
-
-const static u32 sysclk_tbl[] = {
- 66666000, 7499900, 83332500, 8999900,
- 99999000, 11111000, 12499800, 13333200
-};
-
-void board_init_f(ulong bootflag)
-{
- int px_spd;
- u32 plat_ratio, sys_clk, bus_clk;
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
-#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
- set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
- set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
-#endif
- /* for FPGA */
- set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
- set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
-
- /* initialize selected port with appropriate baud rate */
- px_spd = in_8((unsigned char *)(PIXIS_BASE + PIXIS_SPD));
- sys_clk = sysclk_tbl[px_spd & PIXIS_SPD_SYSCLK_MASK];
- plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
- bus_clk = sys_clk * plat_ratio / 2;
-
- NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
- bus_clk / 16 / CONFIG_BAUDRATE);
-
- puts("\nNAND boot... ");
-
- /* copy code to RAM and jump to it - this should not return */
- /* NOTE - code has to be copied out of NAND buffer before
- * other blocks can be read.
- */
- relocate_code(CONFIG_SPL_RELOC_STACK, 0,
- CONFIG_SPL_RELOC_TEXT_BASE);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
- puts("\nSecond program loader running in sram...");
- nand_boot();
-}
-
-void putc(char c)
-{
- if (c == '\n')
- NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
-
- NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
-}
-
-void puts(const char *str)
-{
- while (*str)
- putc(*str++);
-}
diff --git a/board/freescale/p1022ds/tlb.c b/board/freescale/p1022ds/tlb.c
deleted file mode 100644
index 194fbd5afc..0000000000
--- a/board/freescale/p1022ds/tlb.c
+++ /dev/null
@@ -1,101 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2010 Freescale Semiconductor, Inc.
- * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
- * Timur Tabi <timur@freescale.com>
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
- /* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
-
- /* TLB 1 */
- /* *I*** - Covers boot page */
- SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I,
- 0, 0, BOOKE_PAGESZ_4K, 1),
-
- /* *I*G* - CCSRBAR */
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 1, BOOKE_PAGESZ_1M, 1),
-
-#ifndef CONFIG_SPL_BUILD
- /* W**G* - Flash/promjet, localbus */
- /* This will be changed to *I*G* after relocation to RAM. */
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
- MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
- 0, 2, BOOKE_PAGESZ_256M, 1),
-
- /* *I*G* - PCI */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 3, BOOKE_PAGESZ_1G, 1),
-
- /* *I*G* - PCI */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000,
- CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 4, BOOKE_PAGESZ_256M, 1),
-
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000,
- CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 5, BOOKE_PAGESZ_256M, 1),
-
- /* *I*G* - PCI I/O */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 6, BOOKE_PAGESZ_256K, 1),
-#endif
-
- SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 7, BOOKE_PAGESZ_4K, 1),
-
-#if defined(CONFIG_SYS_RAMBOOT) || \
- (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
- /* **** - eSDHC/eSPI/NAND boot */
- SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
- 0, 8, BOOKE_PAGESZ_1G, 1),
- /* **** - eSDHC/eSPI/NAND boot - second 1GB of memory */
- SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
- CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
- 0, 9, BOOKE_PAGESZ_1G, 1),
-#endif
-
-#ifdef CONFIG_SYS_NAND_BASE
- /* *I*G - NAND */
- SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 10, BOOKE_PAGESZ_16K, 1),
-#endif
-
-#ifdef CONFIG_SYS_INIT_L2_ADDR
- /* *I*G - L2SRAM */
- SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
- 0, 11, BOOKE_PAGESZ_256K, 1)
-#endif
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/configs/P1022DS_36BIT_NAND_defconfig b/configs/P1022DS_36BIT_NAND_defconfig
deleted file mode 100644
index 2bfda3ed40..0000000000
--- a/configs/P1022DS_36BIT_NAND_defconfig
+++ /dev/null
@@ -1,80 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11001000
-CONFIG_ENV_SIZE=0x40000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_TPL_LIBCOMMON_SUPPORT=y
-CONFIG_TPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_TEXT_BASE=0xFF800000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P1022DS=y
-CONFIG_PHYS_64BIT=y
-CONFIG_SYS_CUSTOM_LDSCRIPT=y
-CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_NAND_BOOT=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_TPL=y
-CONFIG_TPL_ENV_SUPPORT=y
-CONFIG_TPL_I2C_SUPPORT=y
-CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_TPL_NAND_SUPPORT=y
-CONFIG_TPL_SERIAL_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_REGINFO=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:48m(ramdisk),14m(diagnostic),2m(dink),6m(kernel),58112k(fs),512k(dtb),768k(u-boot)"
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P1022DS_36BIT_SDCARD_defconfig b/configs/P1022DS_36BIT_SDCARD_defconfig
deleted file mode 100644
index 9cc214088c..0000000000
--- a/configs/P1022DS_36BIT_SDCARD_defconfig
+++ /dev/null
@@ -1,74 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x0
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_TEXT_BASE=0xf8f81000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P1022DS=y
-CONFIG_PHYS_64BIT=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_MMC_BOOT=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_REGINFO=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:48m(ramdisk),14m(diagnostic),2m(dink),6m(kernel),58112k(fs),512k(dtb),768k(u-boot)"
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P1022DS_36BIT_SPIFLASH_defconfig b/configs/P1022DS_36BIT_SPIFLASH_defconfig
deleted file mode 100644
index 80d3a88273..0000000000
--- a/configs/P1022DS_36BIT_SPIFLASH_defconfig
+++ /dev/null
@@ -1,76 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_SPL_TEXT_BASE=0xf8f81000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P1022DS=y
-CONFIG_PHYS_64BIT=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_SPI_BOOT=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_REGINFO=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:48m(ramdisk),14m(diagnostic),2m(dink),6m(kernel),58112k(fs),512k(dtb),768k(u-boot)"
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P1022DS_36BIT_defconfig b/configs/P1022DS_36BIT_defconfig
deleted file mode 100644
index 1048b53abb..0000000000
--- a/configs/P1022DS_36BIT_defconfig
+++ /dev/null
@@ -1,62 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P1022DS=y
-CONFIG_PHYS_64BIT=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_REGINFO=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:48m(ramdisk),14m(diagnostic),2m(dink),6m(kernel),58112k(fs),512k(dtb),768k(u-boot)"
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P1022DS_NAND_defconfig b/configs/P1022DS_NAND_defconfig
deleted file mode 100644
index 79754874b6..0000000000
--- a/configs/P1022DS_NAND_defconfig
+++ /dev/null
@@ -1,79 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11001000
-CONFIG_ENV_SIZE=0x40000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_TPL_LIBCOMMON_SUPPORT=y
-CONFIG_TPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_TEXT_BASE=0xFF800000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P1022DS=y
-CONFIG_SYS_CUSTOM_LDSCRIPT=y
-CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_NAND_BOOT=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_TPL=y
-CONFIG_TPL_ENV_SUPPORT=y
-CONFIG_TPL_I2C_SUPPORT=y
-CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_TPL_NAND_SUPPORT=y
-CONFIG_TPL_SERIAL_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_REGINFO=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=e8000000.nor"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=e8000000.nor:48m(ramdisk),14m(diagnostic),2m(dink),6m(kernel),58112k(fs),512k(dtb),768k(u-boot)"
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P1022DS_SDCARD_defconfig b/configs/P1022DS_SDCARD_defconfig
deleted file mode 100644
index 4e80b8844e..0000000000
--- a/configs/P1022DS_SDCARD_defconfig
+++ /dev/null
@@ -1,73 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x0
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_TEXT_BASE=0xf8f81000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P1022DS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_MMC_BOOT=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_REGINFO=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=e8000000.nor"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=e8000000.nor:48m(ramdisk),14m(diagnostic),2m(dink),6m(kernel),58112k(fs),512k(dtb),768k(u-boot)"
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P1022DS_SPIFLASH_defconfig b/configs/P1022DS_SPIFLASH_defconfig
deleted file mode 100644
index e55f05cf56..0000000000
--- a/configs/P1022DS_SPIFLASH_defconfig
+++ /dev/null
@@ -1,75 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_SPL_TEXT_BASE=0xf8f81000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P1022DS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_SPI_BOOT=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_REGINFO=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=e8000000.nor"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=e8000000.nor:48m(ramdisk),14m(diagnostic),2m(dink),6m(kernel),58112k(fs),512k(dtb),768k(u-boot)"
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P1022DS_defconfig b/configs/P1022DS_defconfig
deleted file mode 100644
index c611ce418d..0000000000
--- a/configs/P1022DS_defconfig
+++ /dev/null
@@ -1,61 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P1022DS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_REGINFO=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=e8000000.nor"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=e8000000.nor:48m(ramdisk),14m(diagnostic),2m(dink),6m(kernel),58112k(fs),512k(dtb),768k(u-boot)"
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h
deleted file mode 100644
index 2b761078bc..0000000000
--- a/include/configs/P1022DS.h
+++ /dev/null
@@ -1,593 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2010-2012 Freescale Semiconductor, Inc.
- * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
- * Timur Tabi <timur@freescale.com>
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <linux/stringify.h>
-
-#include "../board/freescale/common/ics307_clk.h"
-
-#ifdef CONFIG_SDCARD
-#define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
-#define CONFIG_SPL_PAD_TO 0x20000
-#define CONFIG_SPL_MAX_SIZE (128 * 1024)
-#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
-#define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
-#define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
-#define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10)
-#define CONFIG_SYS_MPC85XX_NO_RESETVEC
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SPL_COMMON_INIT_DDR
-#endif
-#endif
-
-#ifdef CONFIG_SPIFLASH
-#define CONFIG_SPL_SPI_FLASH_MINIMAL
-#define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
-#define CONFIG_SPL_PAD_TO 0x20000
-#define CONFIG_SPL_MAX_SIZE (128 * 1024)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10)
-#define CONFIG_SYS_MPC85XX_NO_RESETVEC
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SPL_COMMON_INIT_DDR
-#endif
-#endif
-
-#define CONFIG_NAND_FSL_ELBC
-#define CONFIG_SYS_NAND_MAX_ECCPOS 56
-#define CONFIG_SYS_NAND_MAX_OOBFREE 5
-
-#ifdef CONFIG_MTD_RAW_NAND
-#ifdef CONFIG_TPL_BUILD
-#define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_NAND_INIT
-#define CONFIG_SPL_COMMON_INIT_DDR
-#define CONFIG_SPL_MAX_SIZE (128 << 10)
-#define CONFIG_TPL_TEXT_BASE 0xf8f81000
-#define CONFIG_SYS_MPC85XX_NO_RESETVEC
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
-#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
-#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
-#elif defined(CONFIG_SPL_BUILD)
-#define CONFIG_SPL_INIT_MINIMAL
-#define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_MAX_SIZE 4096
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
-#define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
-#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
-#endif
-#define CONFIG_SPL_PAD_TO 0x20000
-#define CONFIG_TPL_PAD_TO 0x20000
-#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
-#endif
-
-/* High Level Configuration Options */
-
-#ifndef CONFIG_RESET_VECTOR_ADDRESS
-#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
-#endif
-
-#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
-#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
-#define CONFIG_PCIE3 /* PCIE controller 3 (ULI bridge) */
-#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
-#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
-
-#define CONFIG_ENABLE_36BIT_PHYS
-
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_ADDR_MAP
-#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
-#endif
-
-#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
-#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
-#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
-
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_L2_CACHE
-#define CONFIG_BTB
-
-#define CONFIG_SYS_CCSRBAR 0xffe00000
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
-
-/* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
- SPL code*/
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
-#endif
-
-/* DDR Setup */
-#define CONFIG_DDR_SPD
-#define CONFIG_VERY_BIG_RAM
-
-#ifdef CONFIG_DDR_ECC
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
-#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
-#endif
-
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
-
-/* I2C addresses of SPD EEPROMs */
-#define CONFIG_SYS_SPD_BUS_NUM 1
-#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
-
-/* These are used when DDR doesn't use SPD. */
-#define CONFIG_SYS_SDRAM_SIZE 2048
-#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G
-#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
-#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
-#define CONFIG_SYS_DDR_CS1_BNDS 0x0040007F
-#define CONFIG_SYS_DDR_CS1_CONFIG 0x80014202
-#define CONFIG_SYS_DDR_TIMING_3 0x00010000
-#define CONFIG_SYS_DDR_TIMING_0 0x40110104
-#define CONFIG_SYS_DDR_TIMING_1 0x5c5bd746
-#define CONFIG_SYS_DDR_TIMING_2 0x0fa8d4ca
-#define CONFIG_SYS_DDR_MODE_1 0x00441221
-#define CONFIG_SYS_DDR_MODE_2 0x00000000
-#define CONFIG_SYS_DDR_INTERVAL 0x0a280100
-#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
-#define CONFIG_SYS_DDR_CLK_CTRL 0x02800000
-#define CONFIG_SYS_DDR_CONTROL 0xc7000008
-#define CONFIG_SYS_DDR_CONTROL_2 0x24401041
-#define CONFIG_SYS_DDR_TIMING_4 0x00220001
-#define CONFIG_SYS_DDR_TIMING_5 0x02401400
-#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
-#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8675f608
-
-/*
- * Memory map
- *
- * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
- * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable
- * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable
- *
- * Localbus cacheable (TBD)
- * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
- *
- * Localbus non-cacheable
- * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable
- * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
- * 0xff80_0000 0xff80_7fff NAND 32K non-cacheable
- * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
- * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
- * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
- */
-
-/*
- * Local Bus Definitions
- */
-#define CONFIG_SYS_FLASH_BASE 0xe8000000 /* start of FLASH 128M */
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe8000000ull
-#else
-#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
-#endif
-
-#define CONFIG_FLASH_BR_PRELIM \
- (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
-#define CONFIG_FLASH_OR_PRELIM (OR_AM_128MB | 0xff7)
-
-#ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
-#define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
-#else
-#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
-#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
-#endif
-
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
-#define CONFIG_SYS_FLASH_QUIET_TEST
-#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_MAX_FLASH_SECT 1024
-
-#ifndef CONFIG_SYS_MONITOR_BASE
-#ifdef CONFIG_TPL_BUILD
-#define CONFIG_SYS_MONITOR_BASE CONFIG_TPL_TEXT_BASE
-#elif defined(CONFIG_SPL_BUILD)
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
-#else
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-#endif
-#endif
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
-/* Nand Flash */
-#if defined(CONFIG_NAND_FSL_ELBC)
-#define CONFIG_SYS_NAND_BASE 0xff800000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
-#else
-#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
-#endif
-
-#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024)
-#define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE
-
-/* NAND flash config */
-#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
- | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
- | BR_PS_8 /* Port Size = 8 bit */ \
- | BR_MS_FCM /* MSEL = FCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* length 256K */ \
- | OR_FCM_PGS /* Large Page*/ \
- | OR_FCM_CSCT \
- | OR_FCM_CST \
- | OR_FCM_CHT \
- | OR_FCM_SCY_1 \
- | OR_FCM_TRLX \
- | OR_FCM_EHTR)
-#ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
-#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-#else
-#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
-#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-#endif
-
-#endif /* CONFIG_NAND_FSL_ELBC */
-
-#define CONFIG_HWCONFIG
-
-#define CONFIG_FSL_NGPIXIS
-#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
-#ifdef CONFIG_PHYS_64BIT
-#define PIXIS_BASE_PHYS 0xfffdf0000ull
-#else
-#define PIXIS_BASE_PHYS PIXIS_BASE
-#endif
-
-#define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
-#define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | 0x6ff7)
-
-#define PIXIS_LBMAP_SWITCH 7
-#define PIXIS_LBMAP_MASK 0xF0
-#define PIXIS_LBMAP_ALTBANK 0x20
-#define PIXIS_SPD 0x07
-#define PIXIS_SPD_SYSCLK_MASK 0x07
-#define PIXIS_ELBC_SPI_MASK 0xc0
-#define PIXIS_SPI 0x80
-
-#define CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
-
-/*
- * Config the L2 Cache as L2 SRAM
-*/
-#if defined(CONFIG_SPL_BUILD)
-#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
-#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
-#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
-#define CONFIG_SYS_L2_SIZE (256 << 10)
-#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
-#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
-#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
-#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
-#define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10)
-#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
-#elif defined(CONFIG_MTD_RAW_NAND)
-#ifdef CONFIG_TPL_BUILD
-#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
-#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
-#define CONFIG_SYS_L2_SIZE (256 << 10)
-#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
-#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
-#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
-#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
-#define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
-#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
-#else
-#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
-#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
-#define CONFIG_SYS_L2_SIZE (256 << 10)
-#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
-#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000)
-#define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
-#endif
-#endif
-#endif
-
-/*
- * Serial Port
- */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
-#define CONFIG_NS16550_MIN_FUNCTIONS
-#endif
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
-
-/* Video */
-
-#ifdef CONFIG_FSL_DIU_FB
-#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000)
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_VIDEO_BMP_LOGO
-#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
-/*
- * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
- * disable empty flash sector detection, which is I/O-intensive.
- */
-#undef CONFIG_SYS_FLASH_EMPTY_INFO
-#endif
-
-#ifdef CONFIG_ATI
-#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT
-#define CONFIG_BIOSEMU
-#define CONFIG_ATI_RADEON_FB
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
-#endif
-
-/* I2C */
-#ifndef CONFIG_DM_I2C
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-#define CONFIG_SYS_FSL_I2C2_SPEED 400000
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
-#define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}}
-#endif
-#define CONFIG_SYS_I2C_FSL
-
-/*
- * I2C2 EEPROM
- */
-#define CONFIG_ID_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_BUS_NUM 1
-
-/*
- * General PCI
- * Memory space is mapped 1-1, but I/O space must start from 0.
- */
-
-/* controller 1, Slot 2, tgtid 1, Base address a000 */
-#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
-#else
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
-#endif
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
-#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
-#else
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
-#endif
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
-
-/* controller 2, direct to uli, tgtid 2, Base address 9000 */
-#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
-#else
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
-#endif
-#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
-#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
-#else
-#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
-#endif
-#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
-
-/* controller 3, Slot 1, tgtid 3, Base address b000 */
-#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
-#else
-#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
-#endif
-#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
-#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull
-#else
-#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
-#endif
-#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
-
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#endif
-
-/* SATA */
-#define CONFIG_FSL_SATA_V2
-
-#define CONFIG_SYS_SATA_MAX_DEVICE 2
-#define CONFIG_SATA1
-#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
-#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
-#define CONFIG_SATA2
-#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
-#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
-
-#ifdef CONFIG_FSL_SATA
-#define CONFIG_LBA48
-#endif
-
-#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
-#endif
-
-#ifdef CONFIG_TSEC_ENET
-
-#define CONFIG_TSECV2
-
-#define CONFIG_TSEC1 1
-#define CONFIG_TSEC1_NAME "eTSEC1"
-#define CONFIG_TSEC2 1
-#define CONFIG_TSEC2_NAME "eTSEC2"
-
-#define TSEC1_PHY_ADDR 1
-#define TSEC2_PHY_ADDR 2
-
-#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-
-#define TSEC1_PHYIDX 0
-#define TSEC2_PHYIDX 0
-
-#define CONFIG_ETHPRIME "eTSEC1"
-#endif
-
-/*
- * Dynamic MTD Partition support with mtdparts
- */
-
-/*
- * Environment
- */
-#if defined(CONFIG_SDCARD)
-#define CONFIG_FSL_FIXED_MMC_LOCATION
-#define CONFIG_SYS_MMC_ENV_DEV 0
-#elif defined(CONFIG_MTD_RAW_NAND)
-#ifdef CONFIG_TPL_BUILD
-#define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
-#endif
-#elif defined(CONFIG_SYS_RAMBOOT)
-#define SPL_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
-#endif
-
-#define CONFIG_LOADS_ECHO
-#define CONFIG_SYS_LOADS_BAUD_CHANGE
-
-/*
- * USB
- */
-#define CONFIG_HAS_FSL_DR_USB
-#ifdef CONFIG_HAS_FSL_DR_USB
-#ifdef CONFIG_USB_EHCI_HCD
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_USB_EHCI_FSL
-#endif
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 64 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
-#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-
-#define CONFIG_HOSTNAME "p1022ds"
-#define CONFIG_ROOTPATH "/opt/nfsroot"
-#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
-
-#define CONFIG_LOADADDR 1000000
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
- "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
- "tftpflash=tftpboot $loadaddr $uboot && " \
- "protect off $ubootaddr +$filesize && " \
- "erase $ubootaddr +$filesize && " \
- "cp.b $loadaddr $ubootaddr $filesize && " \
- "protect on $ubootaddr +$filesize && " \
- "cmp.b $loadaddr $ubootaddr $filesize\0" \
- "consoledev=ttyS0\0" \
- "ramdiskaddr=2000000\0" \
- "ramdiskfile=rootfs.ext2.gz.uboot\0" \
- "fdtaddr=1e00000\0" \
- "fdtfile=p1022ds.dtb\0" \
- "bdev=sda3\0" \
- "hwconfig=esdhc;audclk:12\0"
-
-#define CONFIG_HDBOOT \
- "setenv bootargs root=/dev/$bdev rw " \
- "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
-
-#endif
--
2.25.1
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 10/24] arm: Remove configs/P2041RDB_NAND_defconfig board
2020-05-27 16:46 [PATCH 00/24] spi: dm-conversion (part2) Jagan Teki
` (8 preceding siblings ...)
2020-05-27 16:46 ` [PATCH 09/24] arm: Remove configs/P1022DS_36BIT_NAND_defconfig board Jagan Teki
@ 2020-05-27 16:46 ` Jagan Teki
2020-05-28 5:43 ` Priyanka Jain
2020-05-27 16:46 ` [PATCH 11/24] arm: Remove configs/P3041DS_NAND_SECURE_BOOT_defconfig board Jagan Teki
` (12 subsequent siblings)
22 siblings, 1 reply; 59+ messages in thread
From: Jagan Teki @ 2020-05-27 16:46 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_SPI by the deadline.
Remove it.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
arch/powerpc/cpu/mpc85xx/Kconfig | 1 -
board/freescale/p2041rdb/Kconfig | 14 -
board/freescale/p2041rdb/MAINTAINERS | 11 -
board/freescale/p2041rdb/Makefile | 10 -
board/freescale/p2041rdb/README | 141 ------
board/freescale/p2041rdb/cpld.c | 157 ------
board/freescale/p2041rdb/cpld.h | 54 --
board/freescale/p2041rdb/ddr.c | 143 ------
board/freescale/p2041rdb/eth.c | 201 --------
board/freescale/p2041rdb/p2041rdb.c | 244 ---------
configs/P2041RDB_NAND_defconfig | 64 ---
configs/P2041RDB_SDCARD_defconfig | 63 ---
configs/P2041RDB_SECURE_BOOT_defconfig | 57 ---
configs/P2041RDB_SPIFLASH_defconfig | 64 ---
configs/P2041RDB_SRIO_PCIE_BOOT_defconfig | 50 --
configs/P2041RDB_defconfig | 62 ---
include/configs/P2041RDB.h | 585 ----------------------
17 files changed, 1921 deletions(-)
delete mode 100644 board/freescale/p2041rdb/Kconfig
delete mode 100644 board/freescale/p2041rdb/MAINTAINERS
delete mode 100644 board/freescale/p2041rdb/Makefile
delete mode 100644 board/freescale/p2041rdb/README
delete mode 100644 board/freescale/p2041rdb/cpld.c
delete mode 100644 board/freescale/p2041rdb/cpld.h
delete mode 100644 board/freescale/p2041rdb/ddr.c
delete mode 100644 board/freescale/p2041rdb/eth.c
delete mode 100644 board/freescale/p2041rdb/p2041rdb.c
delete mode 100644 configs/P2041RDB_NAND_defconfig
delete mode 100644 configs/P2041RDB_SDCARD_defconfig
delete mode 100644 configs/P2041RDB_SECURE_BOOT_defconfig
delete mode 100644 configs/P2041RDB_SPIFLASH_defconfig
delete mode 100644 configs/P2041RDB_SRIO_PCIE_BOOT_defconfig
delete mode 100644 configs/P2041RDB_defconfig
delete mode 100644 include/configs/P2041RDB.h
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 331adbf712..a776aa5e64 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -1599,7 +1599,6 @@ source "board/freescale/mpc8569mds/Kconfig"
source "board/freescale/mpc8572ds/Kconfig"
source "board/freescale/p1023rdb/Kconfig"
source "board/freescale/p1_twr/Kconfig"
-source "board/freescale/p2041rdb/Kconfig"
source "board/freescale/qemu-ppce500/Kconfig"
source "board/freescale/t102xqds/Kconfig"
source "board/freescale/t102xrdb/Kconfig"
diff --git a/board/freescale/p2041rdb/Kconfig b/board/freescale/p2041rdb/Kconfig
deleted file mode 100644
index 7e187dde72..0000000000
--- a/board/freescale/p2041rdb/Kconfig
+++ /dev/null
@@ -1,14 +0,0 @@
-if TARGET_P2041RDB
-
-config SYS_BOARD
- default "p2041rdb"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "P2041RDB"
-
-source "board/freescale/common/Kconfig"
-
-endif
diff --git a/board/freescale/p2041rdb/MAINTAINERS b/board/freescale/p2041rdb/MAINTAINERS
deleted file mode 100644
index d93cb0bebb..0000000000
--- a/board/freescale/p2041rdb/MAINTAINERS
+++ /dev/null
@@ -1,11 +0,0 @@
-P2041RDB BOARD
-#M: -
-S: Maintained
-F: board/freescale/p2041rdb/
-F: include/configs/P2041RDB.h
-F: configs/P2041RDB_defconfig
-F: configs/P2041RDB_NAND_defconfig
-F: configs/P2041RDB_SDCARD_defconfig
-F: configs/P2041RDB_SECURE_BOOT_defconfig
-F: configs/P2041RDB_SPIFLASH_defconfig
-F: configs/P2041RDB_SRIO_PCIE_BOOT_defconfig
diff --git a/board/freescale/p2041rdb/Makefile b/board/freescale/p2041rdb/Makefile
deleted file mode 100644
index ebd0982b5d..0000000000
--- a/board/freescale/p2041rdb/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2011 Freescale Semiconductor, Inc.
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-
-obj-y += p2041rdb.o
-obj-y += cpld.o
-obj-y += ddr.o
-obj-y += eth.o
diff --git a/board/freescale/p2041rdb/README b/board/freescale/p2041rdb/README
deleted file mode 100644
index 79f77e4961..0000000000
--- a/board/freescale/p2041rdb/README
+++ /dev/null
@@ -1,141 +0,0 @@
-Overview
-=========
-The P2041 Processor combines four Power Architecture processor cores
-with high-performance datapath acceleration architecture(DPAA), CoreNet
-fabric infrastructure, as well as network and peripheral bus interfaces
-required for networking, telecom/datacom, wireless infrastructure, and
-military/aerospace applications.
-
-P2041RDB board is a quad core platform supporting the P2041 processor
-of QorIQ DPAA series.
-
-Boot from NOR flash
-===================
-1. Build image
- make P2041RDB_config
- make all
-
-2. Program image
- => tftp 1000000 u-boot.bin
- => protect off all
- => erase eff40000 efffffff
- => cp.b 1000000 eff40000 c0000
-
-3. Program RCW
- => tftp 1000000 rcw.bin
- => protect off all
- => erase e8000000 e801ffff
- => cp.b 1000000 e8000000 50
-
-4. Program FMAN Firmware ucode
- => tftp 1000000 ucode.bin
- => protect off all
- => erase eff00000 eff3ffff
- => cp.b 1000000 eff00000 2000
-
-5. Change DIP-switch
- SW1[1-5] = 10110
- Note: 1 stands for 'on', 0 stands for 'off'
-
-Boot from SDCard
-===================
-1. Build image
- make P2041RDB_SDCARD_config
- make all
-
-2. Generate PBL imge
- Use PE tool to produce a image used to be programed to
- SDCard which contains RCW and U-Boot image.
-
-3. Program the PBL image to SDCard
- => tftp 1000000 pbl_sd.bin
- => mmcinfo
- => mmc write 1000000 8 672
-
-4. Program FMAN Firmware ucode
- => tftp 1000000 ucode.bin
- => mmc write 1000000 690 10
-
-5. Change DIP-switch
- SW1[1-5] = 01100
- Note: 1 stands for 'on', 0 stands for 'off'
-
-Boot from SPI flash
-===================
-1. Build image
- make P2041RDB_SPIFLASH_config
- make all
-
-2. Generate PBL imge
- Use PE tool to produce a image used to be programed to
- SPI flash which contains RCW and U-Boot image.
-
-3. Program the PBL image to SPI flash
- => tftp 1000000 pbl_spi.bin
- => spi probe 0
- => sf erase 0 100000
- => sf write 1000000 0 $filesize
-
-4. Program FMAN Firmware ucode
- => tftp 1000000 ucode.bin
- => sf erase 110000 10000
- => sf write 1000000 110000 $filesize
-
-5. Change DIP-switch
- SW1[1-5] = 10100
- Note: 1 stands for 'on', 0 stands for 'off'
-
-Device tree support and how to enable it for different configs
---------------------------------------------------------------
-Device tree support is available for p2041rdb for below mentioned boot,
-1. NOR Boot
-2. NAND Boot
-3. SD Boot
-4. SPIFLASH Boot
-
-To enable device tree support for other boot, below configs need to be
-enabled in relative defconfig file,
-1. CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" (Change default device tree name if required)
-2. CONFIG_OF_CONTROL
-3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at
- CONFIG_RESET_VECTOR_ADDRESS - 0xffc
-
-If device tree support is enabled in defconfig, use 'u-boot-with-dtb.bin'
-instead of u-boot.bin for all boot.
-
-CPLD command
-============
-The CPLD is used to control the power sequence and some serdes lane
-mux function.
-
-cpld reset - hard reset to default bank
-cpld reset altbank - reset to alternate bank
-cpld lane_mux <lane> <mux_value> - set multiplexed lane pin
- lane 6: 0 -> slot1 (Default)
- 1 -> SGMII
- lane a: 0 -> slot2 (Default)
- 1 -> AURORA
- lane c: 0 -> slot2 (Default)
- 1 -> SATA0
- lane d: 0 -> slot2 (Default)
- 1 -> SATA1
-
-Using the Device Tree Source File
-=================================
-To create the DTB (Device Tree Binary) image file, use a command
-similar to this:
- dtc -O dtb -b 0 -p 1024 p2041rdb.dts > p2041rdb.dtb
-
-Or use the following command:
- {linux-2.6}/make p2041rdb.dtb ARCH=powerpc
-
-then the dtb file will be generated under the following directory:
- {linux-2.6}/arch/powerpc/boot/p2041rdb.dtb
-
-Booting Linux
-=============
-Place a linux uImage in the TFTP disk area.
- tftp 1000000 uImage
- tftp 2000000 rootfs.ext2.gz.uboot
- tftp 3000000 p2041rdb.dtb
- bootm 1000000 2000000 3000000
diff --git a/board/freescale/p2041rdb/cpld.c b/board/freescale/p2041rdb/cpld.c
deleted file mode 100644
index b042fe3bcb..0000000000
--- a/board/freescale/p2041rdb/cpld.c
+++ /dev/null
@@ -1,157 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/**
- * Copyright 2011 Freescale Semiconductor
- * Author: Mingkai Hu <Mingkai.hu@freescale.com>
- *
- * This file provides support for the board-specific CPLD used on some Freescale
- * reference boards.
- *
- * The following macros need to be defined:
- *
- * CPLD_BASE - The virtual address of the base of the CPLD register map
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/io.h>
-
-#include "cpld.h"
-
-static u8 __cpld_read(unsigned int reg)
-{
- void *p = (void *)CPLD_BASE;
-
- return in_8(p + reg);
-}
-u8 cpld_read(unsigned int reg) __attribute__((weak, alias("__cpld_read")));
-
-static void __cpld_write(unsigned int reg, u8 value)
-{
- void *p = (void *)CPLD_BASE;
-
- out_8(p + reg, value);
-}
-void cpld_write(unsigned int reg, u8 value)
- __attribute__((weak, alias("__cpld_write")));
-
-/*
- * Reset the board. This honors the por_cfg registers.
- */
-void __cpld_reset(void)
-{
- CPLD_WRITE(system_rst, 1);
-}
-void cpld_reset(void) __attribute__((weak, alias("__cpld_reset")));
-
-/**
- * Set the boot bank to the alternate bank
- */
-void __cpld_set_altbank(void)
-{
- u8 reg5 = CPLD_READ(sw_ctl_on);
-
- CPLD_WRITE(sw_ctl_on, reg5 | CPLD_SWITCH_BANK_ENABLE);
- CPLD_WRITE(fbank_sel, 1);
- CPLD_WRITE(system_rst, 1);
-}
-void cpld_set_altbank(void)
- __attribute__((weak, alias("__cpld_set_altbank")));
-
-/**
- * Set the boot bank to the default bank
- */
-void __cpld_set_defbank(void)
-{
- CPLD_WRITE(system_rst_default, 1);
-}
-void cpld_set_defbank(void)
- __attribute__((weak, alias("__cpld_set_defbank")));
-
-#ifdef DEBUG
-static void cpld_dump_regs(void)
-{
- printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver));
- printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub));
- printf("pcba_ver = 0x%02x\n", CPLD_READ(pcba_ver));
- printf("system_rst = 0x%02x\n", CPLD_READ(system_rst));
- printf("sw_ctl_on = 0x%02x\n", CPLD_READ(sw_ctl_on));
- printf("por_cfg = 0x%02x\n", CPLD_READ(por_cfg));
- printf("switch_strobe = 0x%02x\n", CPLD_READ(switch_strobe));
- printf("jtag_sel = 0x%02x\n", CPLD_READ(jtag_sel));
- printf("sdbank1_clk = 0x%02x\n", CPLD_READ(sdbank1_clk));
- printf("sdbank2_clk = 0x%02x\n", CPLD_READ(sdbank2_clk));
- printf("fbank_sel = 0x%02x\n", CPLD_READ(fbank_sel));
- printf("serdes_mux = 0x%02x\n", CPLD_READ(serdes_mux));
- printf("SW[2] = 0x%02x\n", in_8(&CPLD_SW(2)));
- putc('\n');
-}
-#endif
-
-int cpld_cmd(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
-{
- int rc = 0;
-
- if (argc <= 1)
- return cmd_usage(cmdtp);
-
- if (strcmp(argv[1], "reset") == 0) {
- if (strcmp(argv[2], "altbank") == 0)
- cpld_set_altbank();
- else
- cpld_set_defbank();
- } else if (strcmp(argv[1], "lane_mux") == 0) {
- u32 lane = simple_strtoul(argv[2], NULL, 16);
- u8 val = (u8)simple_strtoul(argv[3], NULL, 16);
- u8 reg = CPLD_READ(serdes_mux);
-
- switch (lane) {
- case 0x6:
- reg &= ~SERDES_MUX_LANE_6_MASK;
- reg |= val << SERDES_MUX_LANE_6_SHIFT;
- break;
- case 0xa:
- reg &= ~SERDES_MUX_LANE_A_MASK;
- reg |= val << SERDES_MUX_LANE_A_SHIFT;
- break;
- case 0xc:
- reg &= ~SERDES_MUX_LANE_C_MASK;
- reg |= val << SERDES_MUX_LANE_C_SHIFT;
- break;
- case 0xd:
- reg &= ~SERDES_MUX_LANE_D_MASK;
- reg |= val << SERDES_MUX_LANE_D_SHIFT;
- break;
- default:
- printf("Invalid value\n");
- break;
- }
-
- CPLD_WRITE(serdes_mux, reg);
-#ifdef DEBUG
- } else if (strcmp(argv[1], "dump") == 0) {
- cpld_dump_regs();
-#endif
- } else
- rc = cmd_usage(cmdtp);
-
- return rc;
-}
-
-U_BOOT_CMD(
- cpld_cmd, CONFIG_SYS_MAXARGS, 1, cpld_cmd,
- "Reset the board or pin mulexing selection using the CPLD sequencer",
- "reset - hard reset to default bank\n"
- "cpld_cmd reset altbank - reset to alternate bank\n"
- "cpld_cmd lane_mux <lane> <mux_value> - set multiplexed lane pin\n"
- " lane 6: 0 -> slot1\n"
- " 1 -> SGMII (Default)\n"
- " lane a: 0 -> slot2\n"
- " 1 -> AURORA (Default)\n"
- " lane c: 0 -> slot2\n"
- " 1 -> SATA0 (Default)\n"
- " lane d: 0 -> slot2\n"
- " 1 -> SATA1 (Default)\n"
-#ifdef DEBUG
- "cpld_cmd dump - display the CPLD registers\n"
-#endif
- );
diff --git a/board/freescale/p2041rdb/cpld.h b/board/freescale/p2041rdb/cpld.h
deleted file mode 100644
index 8c90c1ccf3..0000000000
--- a/board/freescale/p2041rdb/cpld.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/**
- * Copyright 2011 Freescale Semiconductor
- * Author: Mingkai Hu <Mingkai.hu@freescale.com>
- *
- * This file provides support for the ngPIXIS, a board-specific FPGA used on
- * some Freescale reference boards.
- */
-
-/*
- * CPLD register set. Feel free to add board-specific #ifdefs where necessary.
- */
-typedef struct cpld_data {
- u8 cpld_ver; /* 0x0 - CPLD Major Revision Register */
- u8 cpld_ver_sub; /* 0x1 - CPLD Minor Revision Register */
- u8 pcba_ver; /* 0x2 - PCBA Revision Register */
- u8 system_rst; /* 0x3 - system reset register */
- u8 res0; /* 0x4 - not used */
- u8 sw_ctl_on; /* 0x5 - Switch Control Enable Register */
- u8 por_cfg; /* 0x6 - POR Control Register */
- u8 switch_strobe; /* 0x7 - Multiplexed pin Select Register */
- u8 jtag_sel; /* 0x8 - JTAG or AURORA Selection */
- u8 sdbank1_clk; /* 0x9 - SerDes Bank1 Reference clock */
- u8 sdbank2_clk; /* 0xa - SerDes Bank2 Reference clock */
- u8 fbank_sel; /* 0xb - Flash bank selection */
- u8 serdes_mux; /* 0xc - Multiplexed pin Select Register */
- u8 sw[1]; /* 0xd - SW2 Status */
- u8 system_rst_default; /* 0xe - system reset to default register */
- u8 sysclk_sw1; /* 0xf - sysclk configuration register */
-} __attribute__ ((packed)) cpld_data_t;
-
-#define SERDES_MUX_LANE_6_MASK 0x2
-#define SERDES_MUX_LANE_6_SHIFT 1
-#define SERDES_MUX_LANE_A_MASK 0x1
-#define SERDES_MUX_LANE_A_SHIFT 0
-#define SERDES_MUX_LANE_C_MASK 0x4
-#define SERDES_MUX_LANE_C_SHIFT 2
-#define SERDES_MUX_LANE_D_MASK 0x8
-#define SERDES_MUX_LANE_D_SHIFT 3
-#define CPLD_SWITCH_BANK_ENABLE 0x40
-#define CPLD_SYSCLK_83 0x1 /* system clock 83.3MHz */
-#define CPLD_SYSCLK_100 0x2 /* system clock 100MHz */
-
-/* Pointer to the CPLD register set */
-#define cpld ((cpld_data_t *)CPLD_BASE)
-
-/* The CPLD SW register that corresponds to board switch X, where x >= 1 */
-#define CPLD_SW(x) (cpld->sw[(x) - 2])
-
-u8 cpld_read(unsigned int reg);
-void cpld_write(unsigned int reg, u8 value);
-
-#define CPLD_READ(reg) cpld_read(offsetof(cpld_data_t, reg))
-#define CPLD_WRITE(reg, value) cpld_write(offsetof(cpld_data_t, reg), value)
diff --git a/board/freescale/p2041rdb/ddr.c b/board/freescale/p2041rdb/ddr.c
deleted file mode 100644
index 7a06c7af3d..0000000000
--- a/board/freescale/p2041rdb/ddr.c
+++ /dev/null
@@ -1,143 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright 2011 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <hwconfig.h>
-#include <init.h>
-#include <log.h>
-#include <asm/mmu.h>
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-#include <asm/fsl_law.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-struct board_specific_parameters {
- u32 n_ranks;
- u32 datarate_mhz_high;
- u32 clk_adjust;
- u32 wrlvl_start;
- u32 cpo;
- u32 write_data_delay;
- u32 force_2t;
-};
-
-/*
- * This table contains all valid speeds we want to override with board
- * specific parameters. datarate_mhz_high values need to be in ascending order
- * for each n_ranks group.
- *
- * ranges for parameters:
- * wr_data_delay = 0-6
- * clk adjust = 0-8
- * cpo 2-0x1E (30)
- */
-static const struct board_specific_parameters dimm0[] = {
- /*
- * memory controller 0
- * num| hi| clk| wrlvl | cpo |wrdata|2T
- * ranks| mhz|adjst| start | delay|
- */
- {2, 750, 3, 5, 0xff, 2, 0},
- {2, 1250, 4, 6, 0xff, 2, 0},
- {2, 1350, 5, 7, 0xff, 2, 0},
- {2, 1666, 5, 8, 0xff, 2, 0},
- {}
-};
-
-void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
- ulong ddr_freq;
-
- if (ctrl_num) {
- printf("Wrong parameter for controller number %d", ctrl_num);
- return;
- }
- if (!pdimm->n_ranks)
- return;
-
- pbsp = dimm0;
-
- /*
- * Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
- * freqency and n_banks specified in board_specific_parameters table.
- */
- ddr_freq = get_ddr_freq(0) / 1000000;
- while (pbsp->datarate_mhz_high) {
- if (pbsp->n_ranks == pdimm->n_ranks) {
- if (ddr_freq <= pbsp->datarate_mhz_high) {
- popts->cpo_override = pbsp->cpo;
- popts->write_data_delay =
- pbsp->write_data_delay;
- popts->clk_adjust = pbsp->clk_adjust;
- popts->wrlvl_start = pbsp->wrlvl_start;
- popts->twot_en = pbsp->force_2t;
- goto found;
- }
- pbsp_highest = pbsp;
- }
- pbsp++;
- }
-
- if (pbsp_highest) {
- printf("Error: board specific timing not found "
- "for data rate %lu MT/s!\n"
- "Trying to use the highest speed (%u) parameters\n",
- ddr_freq, pbsp_highest->datarate_mhz_high);
- popts->cpo_override = pbsp_highest->cpo;
- popts->write_data_delay = pbsp_highest->write_data_delay;
- popts->clk_adjust = pbsp_highest->clk_adjust;
- popts->wrlvl_start = pbsp_highest->wrlvl_start;
- popts->twot_en = pbsp_highest->force_2t;
- } else {
- panic("DIMM is not supported by this board");
- }
-
-found:
- /*
- * Factors to consider for half-strength driver enable:
- * - number of DIMMs installed
- */
- popts->half_strength_driver_enable = 0;
- /* Write leveling override */
- popts->wrlvl_override = 1;
- popts->wrlvl_sample = 0xf;
-
- /* Rtt and Rtt_WR override */
- popts->rtt_override = 0;
-
- /* Enable ZQ calibration */
- popts->zq_en = 1;
-
- /* DHC_EN =1, ODT = 60 Ohm */
- popts->ddr_cdr1 = DDR_CDR1_DHC_EN;
-}
-
-int dram_init(void)
-{
- phys_size_t dram_size = 0;
-
- puts("Initializing....");
-
- if (fsl_use_spd()) {
- puts("using SPD\n");
- dram_size = fsl_ddr_sdram();
- } else {
- puts("no SPD and fixed parameters\n");
- return -ENXIO;
- }
-
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
-
- debug(" DDR: ");
- gd->ram_size = dram_size;
-
- return 0;
-}
diff --git a/board/freescale/p2041rdb/eth.c b/board/freescale/p2041rdb/eth.c
deleted file mode 100644
index 32c68f2a71..0000000000
--- a/board/freescale/p2041rdb/eth.c
+++ /dev/null
@@ -1,201 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2011 Freescale Semiconductor, Inc.
- * Author: Mingkai Hu <Mingkai.hu@freescale.com>
- */
-
-/*
- * The RGMII PHYs are provided by the two on-board PHY. The SGMII PHYs
- * are provided by the three on-board PHY or by the standard Freescale
- * four-port SGMII riser card. We need to change the phy-handle in the
- * kernel dts file to point to the correct PHY according to serdes mux
- * and serdes protocol selection.
- */
-
-#include <common.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/fsl_serdes.h>
-#include <fm_eth.h>
-#include <fsl_mdio.h>
-#include <malloc.h>
-#include <fsl_dtsec.h>
-
-#include "cpld.h"
-#include "../common/fman.h"
-
-#ifdef CONFIG_FMAN_ENET
-/*
- * Mapping of all 18 SERDES lanes to board slots. A value of '0' here means
- * that the mapping must be determined dynamically, or that the lane maps to
- * something other than a board slot
- */
-static u8 lane_to_slot[] = {
- 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 2, 2, 2, 2, 0, 0, 0, 0
-};
-
-static int riser_phy_addr[] = {
- CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR,
- CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR,
- CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR,
- CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR,
-};
-
-/*
- * Initialize the lane_to_slot[] array.
- *
- * On the P2040RDB board the mapping is controlled by CPLD register.
- */
-static void initialize_lane_to_slot(void)
-{
- u8 mux = CPLD_READ(serdes_mux);
-
- lane_to_slot[6] = (mux & SERDES_MUX_LANE_6_MASK) ? 0 : 1;
- lane_to_slot[10] = (mux & SERDES_MUX_LANE_A_MASK) ? 0 : 2;
- lane_to_slot[12] = (mux & SERDES_MUX_LANE_C_MASK) ? 0 : 2;
- lane_to_slot[13] = (mux & SERDES_MUX_LANE_D_MASK) ? 0 : 2;
-}
-
-/*
- * Given the following ...
- *
- * 1) A pointer to an Fman Ethernet node (as identified by the 'compat'
- * compatible string and 'addr' physical address)
- *
- * 2) An Fman port
- *
- * ... update the phy-handle property of the Ethernet node to point to the
- * right PHY. This assumes that we already know the PHY for each port.
- *
- * The offset of the Fman Ethernet node is also passed in for convenience, but
- * it is not used, and we recalculate the offset anyway.
- *
- * Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC.
- * Inside the Fman, "ports" are things that connect to MACs. We only call them
- * ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs
- * and ports are the same thing.
- *
- */
-void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
- enum fm_port port, int offset)
-{
- phy_interface_t intf = fm_info_get_enet_if(port);
- char phy[16];
-
- /* The RGMII PHY is identified by the MAC connected to it */
- if (intf == PHY_INTERFACE_MODE_RGMII) {
- sprintf(phy, "phy_rgmii_%u", port == FM1_DTSEC5 ? 0 : 1);
- fdt_set_phy_handle(fdt, compat, addr, phy);
- }
-
- /* The SGMII PHY is identified by the MAC connected to it */
- if (intf == PHY_INTERFACE_MODE_SGMII) {
- int lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + port);
- u8 slot;
- if (lane < 0)
- return;
- slot = lane_to_slot[lane];
- if (slot) {
- sprintf(phy, "phy_sgmii_%x",
- CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR
- + (port - FM1_DTSEC1));
- fdt_set_phy_handle(fdt, compat, addr, phy);
- } else {
- sprintf(phy, "phy_sgmii_%x",
- CONFIG_SYS_FM1_DTSEC1_PHY_ADDR
- + (port - FM1_DTSEC1));
- fdt_set_phy_handle(fdt, compat, addr, phy);
- }
- }
-
- if (intf == PHY_INTERFACE_MODE_XGMII) {
- /* XAUI */
- int lane = serdes_get_first_lane(XAUI_FM1);
- if (lane >= 0) {
- /* The XAUI PHY is identified by the slot */
- sprintf(phy, "phy_xgmii_%u", lane_to_slot[lane]);
- fdt_set_phy_handle(fdt, compat, addr, phy);
- }
- }
-}
-#endif /* #ifdef CONFIG_FMAN_ENET */
-
-int board_eth_init(bd_t *bis)
-{
-#ifdef CONFIG_FMAN_ENET
- struct fsl_pq_mdio_info dtsec_mdio_info;
- struct tgec_mdio_info tgec_mdio_info;
- unsigned int i, slot;
- int lane;
-
- printf("Initializing Fman\n");
-
- initialize_lane_to_slot();
-
- dtsec_mdio_info.regs =
- (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
- dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
-
- /* Register the real 1G MDIO bus */
- fsl_pq_mdio_init(bis, &dtsec_mdio_info);
-
- tgec_mdio_info.regs =
- (struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
- tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
-
- /* Register the real 10G MDIO bus */
- fm_tgec_mdio_init(bis, &tgec_mdio_info);
-
- /*
- * Program the three on-board SGMII PHY addresses. If the SGMII Riser
- * card used, we'll override the PHY address later. For any DTSEC that
- * is RGMII, we'll also override its PHY address later. We assume that
- * DTSEC4 and DTSEC5 are used for RGMII.
- */
- fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR);
-
- for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
- int idx = i - FM1_DTSEC1;
-
- switch (fm_info_get_enet_if(i)) {
- case PHY_INTERFACE_MODE_SGMII:
- lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
- if (lane < 0)
- break;
- slot = lane_to_slot[lane];
- if (slot)
- fm_info_set_phy_address(i, riser_phy_addr[i]);
- break;
- case PHY_INTERFACE_MODE_RGMII:
- /* Only DTSEC4 and DTSEC5 can be routed to RGMII */
- fm_info_set_phy_address(i, i == FM1_DTSEC5 ?
- CONFIG_SYS_FM1_DTSEC5_PHY_ADDR :
- CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
- break;
- default:
- printf("Fman1: DTSEC%u set to unknown interface %i\n",
- idx + 1, fm_info_get_enet_if(i));
- break;
- }
-
- fm_info_set_mdio(i,
- miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
- }
-
- lane = serdes_get_first_lane(XAUI_FM1);
- if (lane >= 0) {
- slot = lane_to_slot[lane];
- if (slot)
- fm_info_set_phy_address(FM1_10GEC1,
- CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
- }
-
- fm_info_set_mdio(FM1_10GEC1,
- miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME));
- cpu_eth_init(bis);
-#endif
-
- return pci_eth_init(bis);
-}
diff --git a/board/freescale/p2041rdb/p2041rdb.c b/board/freescale/p2041rdb/p2041rdb.c
deleted file mode 100644
index 076e63a357..0000000000
--- a/board/freescale/p2041rdb/p2041rdb.c
+++ /dev/null
@@ -1,244 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2011,2012 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <env.h>
-#include <fdt_support.h>
-#include <image.h>
-#include <init.h>
-#include <netdev.h>
-#include <linux/compiler.h>
-#include <asm/mmu.h>
-#include <asm/processor.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_law.h>
-#include <asm/fsl_serdes.h>
-#include <asm/fsl_liodn.h>
-#include <fm_eth.h>
-
-extern void pci_of_setup(void *blob, bd_t *bd);
-
-#include "cpld.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
- u8 sw;
- struct cpu_type *cpu = gd->arch.cpu;
- unsigned int i;
-
- printf("Board: %sRDB, ", cpu->name);
- printf("CPLD version: %d.%d ", CPLD_READ(cpld_ver),
- CPLD_READ(cpld_ver_sub));
-
- sw = CPLD_READ(fbank_sel);
- printf("vBank: %d\n", sw & 0x1);
-
- /*
- * Display the actual SERDES reference clocks as configured by the
- * dip switches on the board. Note that the SWx registers could
- * technically be set to force the reference clocks to match the
- * values that the SERDES expects (or vice versa). For now, however,
- * we just display both values and hope the user notices when they
- * don't match.
- */
- puts("SERDES Reference Clocks: ");
- sw = in_8(&CPLD_SW(2)) >> 2;
- for (i = 0; i < 2; i++) {
- static const char * const freq[][3] = {{"0", "100", "125"},
- {"100", "156.25", "125"}
- };
- unsigned int clock = (sw >> (2 * i)) & 3;
-
- printf("Bank%u=%sMhz ", i+1, freq[i][clock]);
- }
- puts("\n");
-
- return 0;
-}
-
-int board_early_init_f(void)
-{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-
- /* board only uses the DDR_MCK0/1, so disable the DDR_MCK2/3 */
- setbits_be32(&gur->ddrclkdr, 0x000f000f);
-
- return 0;
-}
-
-#define CPLD_LANE_A_SEL 0x1
-#define CPLD_LANE_G_SEL 0x2
-#define CPLD_LANE_C_SEL 0x4
-#define CPLD_LANE_D_SEL 0x8
-
-void board_config_lanes_mux(void)
-{
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
- int srds_prtcl = (in_be32(&gur->rcwsr[4]) &
- FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
-
- u8 mux = 0;
- switch (srds_prtcl) {
- case 0x2:
- case 0x5:
- case 0x9:
- case 0xa:
- case 0xf:
- break;
- case 0x8:
- mux |= CPLD_LANE_C_SEL | CPLD_LANE_D_SEL;
- break;
- case 0x14:
- mux |= CPLD_LANE_A_SEL;
- break;
- case 0x17:
- mux |= CPLD_LANE_G_SEL;
- break;
- case 0x16:
- case 0x19:
- case 0x1a:
- mux |= CPLD_LANE_G_SEL | CPLD_LANE_C_SEL | CPLD_LANE_D_SEL;
- break;
- case 0x1c:
- mux |= CPLD_LANE_G_SEL | CPLD_LANE_A_SEL;
- break;
- default:
- printf("Fman:Unsupported SerDes Protocol 0x%02x\n", srds_prtcl);
- break;
- }
- CPLD_WRITE(serdes_mux, mux);
-}
-
-int board_early_init_r(void)
-{
- const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
- int flash_esel = find_tlb_idx((void *)flashbase, 1);
-
- /*
- * Remap Boot flash + PROMJET region to caching-inhibited
- * so that flash can be erased properly.
- */
-
- /* Flush d-cache and invalidate i-cache of any FLASH data */
- flush_dcache();
- invalidate_icache();
-
- if (flash_esel == -1) {
- /* very unlikely unless something is messed up */
- puts("Error: Could not find TLB for FLASH BASE\n");
- flash_esel = 2; /* give our best effort to continue */
- } else {
- /* invalidate existing TLB entry for flash + promjet */
- disable_tlb(flash_esel);
- }
-
- set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, flash_esel, BOOKE_PAGESZ_256M, 1);
-
- board_config_lanes_mux();
-
- return 0;
-}
-
-unsigned long get_board_sys_clk(unsigned long dummy)
-{
- u8 sysclk_conf = CPLD_READ(sysclk_sw1);
-
- switch (sysclk_conf & 0x7) {
- case CPLD_SYSCLK_83:
- return 83333333;
- case CPLD_SYSCLK_100:
- return 100000000;
- default:
- return 66666666;
- }
-}
-
-#define NUM_SRDS_BANKS 2
-
-int misc_init_r(void)
-{
- serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
- u32 actual[NUM_SRDS_BANKS];
- unsigned int i;
- u8 sw;
- static const int freq[][3] = {
- {0, SRDS_PLLCR0_RFCK_SEL_100, SRDS_PLLCR0_RFCK_SEL_125},
- {SRDS_PLLCR0_RFCK_SEL_100, SRDS_PLLCR0_RFCK_SEL_156_25,
- SRDS_PLLCR0_RFCK_SEL_125}
- };
-
- sw = in_8(&CPLD_SW(2)) >> 2;
- for (i = 0; i < NUM_SRDS_BANKS; i++) {
- unsigned int clock = (sw >> (2 * i)) & 3;
- if (clock == 0x3) {
- printf("Warning: SDREFCLK%u switch setting of '11' is "
- "unsupported\n", i + 1);
- break;
- }
- if (i == 0 && clock == 0)
- puts("Warning: SDREFCLK1 switch setting of"
- "'00' is unsupported\n");
- else
- actual[i] = freq[i][clock];
-
- /*
- * PC board uses a different CPLD with PB board, this CPLD
- * has cpld_ver_sub = 1, and pcba_ver = 5. But CPLD on PB
- * board has cpld_ver_sub = 0, and pcba_ver = 4.
- */
- if ((i == 1) && (CPLD_READ(cpld_ver_sub) == 1) &&
- (CPLD_READ(pcba_ver) == 5)) {
- /* PC board bank2 frequency */
- actual[i] = freq[i-1][clock];
- }
- }
-
- for (i = 0; i < NUM_SRDS_BANKS; i++) {
- u32 expected = in_be32(®s->bank[i].pllcr0);
- expected &= SRDS_PLLCR0_RFCK_SEL_MASK;
- if (expected != actual[i]) {
- printf("Warning: SERDES bank %u expects reference clock"
- " %sMHz, but actual is %sMHz\n", i + 1,
- serdes_clock_to_string(expected),
- serdes_clock_to_string(actual[i]));
- }
- }
-
- return 0;
-}
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
- phys_addr_t base;
- phys_size_t size;
-
- ft_cpu_setup(blob, bd);
-
- base = env_get_bootm_low();
- size = env_get_bootm_size();
-
- fdt_fixup_memory(blob, (u64)base, (u64)size);
-
-#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
- fsl_fdt_fixup_dr_usb(blob, bd);
-#endif
-
-#ifdef CONFIG_PCI
- pci_of_setup(blob, bd);
-#endif
-
- fdt_fixup_liodn(blob);
-#ifdef CONFIG_SYS_DPAA_FMAN
- fdt_fixup_fman_ethernet(blob);
-#endif
-
- return 0;
-}
diff --git a/configs/P2041RDB_NAND_defconfig b/configs/P2041RDB_NAND_defconfig
deleted file mode 100644
index 13b20dd1c6..0000000000
--- a/configs/P2041RDB_NAND_defconfig
+++ /dev/null
@@ -1,64 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFFF40000
-CONFIG_ENV_SIZE=0x20000
-CONFIG_ENV_OFFSET=0xE0000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P2041RDB=y
-CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="p2041rdb"
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
diff --git a/configs/P2041RDB_SDCARD_defconfig b/configs/P2041RDB_SDCARD_defconfig
deleted file mode 100644
index d99c15342d..0000000000
--- a/configs/P2041RDB_SDCARD_defconfig
+++ /dev/null
@@ -1,63 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0xCF400
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P2041RDB=y
-CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="p2041rdb"
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
diff --git a/configs/P2041RDB_SECURE_BOOT_defconfig b/configs/P2041RDB_SECURE_BOOT_defconfig
deleted file mode 100644
index af33f9de2b..0000000000
--- a/configs/P2041RDB_SECURE_BOOT_defconfig
+++ /dev/null
@@ -1,57 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P2041RDB=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P2041RDB_SPIFLASH_defconfig b/configs/P2041RDB_SPIFLASH_defconfig
deleted file mode 100644
index 78a2a97064..0000000000
--- a/configs/P2041RDB_SPIFLASH_defconfig
+++ /dev/null
@@ -1,64 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P2041RDB=y
-CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="p2041rdb"
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
diff --git a/configs/P2041RDB_SRIO_PCIE_BOOT_defconfig b/configs/P2041RDB_SRIO_PCIE_BOOT_defconfig
deleted file mode 100644
index dd5f2a4fc0..0000000000
--- a/configs/P2041RDB_SRIO_PCIE_BOOT_defconfig
+++ /dev/null
@@ -1,50 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P2041RDB=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_GREPENV=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_IS_IN_REMOTE=y
-CONFIG_ENV_ADDR=0xFFE20000
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_REMOTE=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P2041RDB_defconfig b/configs/P2041RDB_defconfig
deleted file mode 100644
index 0b9625e91e..0000000000
--- a/configs/P2041RDB_defconfig
+++ /dev/null
@@ -1,62 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P2041RDB=y
-CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="p2041rdb"
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
deleted file mode 100644
index 59404cbaf9..0000000000
--- a/include/configs/P2041RDB.h
+++ /dev/null
@@ -1,585 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2011-2012 Freescale Semiconductor, Inc.
- * Copyright 2020 NXP
- */
-
-/*
- * P2041 RDB board configuration file
- * Also supports P2040 RDB
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#ifdef CONFIG_RAMBOOT_PBL
-#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
-#define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg
-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p2041rdb.cfg
-#endif
-
-#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
-/* Set 1M boot space */
-#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
-#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
- (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
-#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
-#endif
-
-/* High Level Configuration Options */
-#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
-
-#ifndef CONFIG_RESET_VECTOR_ADDRESS
-#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
-#endif
-
-#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
-#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
-#define CONFIG_PCIE1 /* PCIE controller 1 */
-#define CONFIG_PCIE2 /* PCIE controller 2 */
-#define CONFIG_PCIE3 /* PCIE controller 3 */
-#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
-
-#define CONFIG_SYS_SRIO
-#define CONFIG_SRIO1 /* SRIO port 1 */
-#define CONFIG_SRIO2 /* SRIO port 2 */
-#define CONFIG_SRIO_PCIE_BOOT_MASTER
-#define CONFIG_SYS_DPAA_RMAN /* RMan */
-
-#define CONFIG_ENV_OVERWRITE
-
-#if defined(CONFIG_SPIFLASH)
-#elif defined(CONFIG_SDCARD)
- #define CONFIG_FSL_FIXED_MMC_LOCATION
- #define CONFIG_SYS_MMC_ENV_DEV 0
-#endif
-
-#ifndef __ASSEMBLY__
-unsigned long get_board_sys_clk(unsigned long dummy);
-#include <linux/stringify.h>
-#endif
-#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
-
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_SYS_CACHE_STASHING
-#define CONFIG_BACKSIDE_L2_CACHE
-#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
-#define CONFIG_BTB /* toggle branch predition */
-
-#define CONFIG_ENABLE_36BIT_PHYS
-
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_ADDR_MAP
-#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
-#endif
-
-#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
-
-/*
- * Config the L3 Cache as L3 SRAM
- */
-#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \
- CONFIG_RAMBOOT_TEXT_BASE)
-#else
-#define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
-#endif
-#define CONFIG_SYS_L3_SIZE (1024 << 10)
-#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
-
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_DCSRBAR 0xf0000000
-#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
-#endif
-
-/* EEPROM */
-#define CONFIG_ID_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#define CONFIG_SYS_EEPROM_BUS_NUM 0
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-
-/*
- * DDR Setup
- */
-#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
-
-#define CONFIG_DDR_SPD
-
-#define CONFIG_SYS_SPD_BUS_NUM 0
-#define SPD_EEPROM_ADDRESS 0x52
-#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
-
-/*
- * Local Bus Definitions
- */
-
-/* Set the local bus clock 1/8 of platform clock */
-#define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
-
-/*
- * This board doesn't have a promjet connector.
- * However, it uses commone corenet board LAW and TLB.
- * It is necessary to use the same start address with proper offset.
- */
-#define CONFIG_SYS_FLASH_BASE 0xe0000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
-#else
-#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
-#endif
-
-#define CONFIG_SYS_FLASH_BR_PRELIM \
- (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \
- BR_PS_16 | BR_V)
-#define CONFIG_SYS_FLASH_OR_PRELIM \
- ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
- | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
-
-#define CONFIG_FSL_CPLD
-#define CPLD_BASE 0xffdf0000 /* CPLD registers */
-#ifdef CONFIG_PHYS_64BIT
-#define CPLD_BASE_PHYS 0xfffdf0000ull
-#else
-#define CPLD_BASE_PHYS CPLD_BASE
-#endif
-
-#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V)
-#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
-
-#define PIXIS_LBMAP_SWITCH 7
-#define PIXIS_LBMAP_MASK 0xf0
-#define PIXIS_LBMAP_SHIFT 4
-#define PIXIS_LBMAP_ALTBANK 0x40
-
-#define CONFIG_SYS_FLASH_QUIET_TEST
-#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Write Timeout (ms) */
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-
-#if defined(CONFIG_RAMBOOT_PBL)
-#define CONFIG_SYS_RAMBOOT
-#endif
-
-#define CONFIG_NAND_FSL_ELBC
-/* Nand Flash */
-#ifdef CONFIG_NAND_FSL_ELBC
-#define CONFIG_SYS_NAND_BASE 0xffa00000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
-#else
-#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
-#endif
-
-#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
-
-/* NAND flash config */
-#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
- | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
- | BR_PS_8 /* Port Size = 8 bit */ \
- | BR_MS_FCM /* MSEL = FCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
- | OR_FCM_PGS /* Large Page*/ \
- | OR_FCM_CSCT \
- | OR_FCM_CST \
- | OR_FCM_CHT \
- | OR_FCM_SCY_1 \
- | OR_FCM_TRLX \
- | OR_FCM_EHTR)
-
-#ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
-#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
-#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
-#else
-#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
-#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
-#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
-#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-#endif
-#else
-#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
-#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
-#endif /* CONFIG_NAND_FSL_ELBC */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
-
-#define CONFIG_HWCONFIG
-
-/* define to use L1 as initial stack */
-#define CONFIG_L1_INIT_RAM
-#define CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
-/* The assembler doesn't like typecast */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
- ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
- CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
-#else
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
-#endif
-#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
-
-/* Serial Port - controlled on board with jumper J8
- * open - index 2
- * shorted - index 1
- */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
-#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
-#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
-
-/* I2C */
-#ifndef CONFIG_DM_I2C
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
-#define CONFIG_SYS_FSL_I2C2_SPEED 400000
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
-#else
-#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
-#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
-#endif
-#define CONFIG_SYS_I2C_FSL
-
-
-/*
- * RapidIO
- */
-#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
-#else
-#define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
-#endif
-#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
-
-#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
-#else
-#define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
-#endif
-#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
-
-/*
- * for slave u-boot IMAGE instored in master memory space,
- * PHYS must be aligned based on the SIZE
- */
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
-/*
- * for slave UCODE and ENV instored in master memory space,
- * PHYS must be aligned based on the SIZE
- */
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
-
-/* slave core release by master*/
-#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
-#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
-
-/*
- * SRIO_PCIE_BOOT - SLAVE
- */
-#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
-#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
-#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
- (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
-#endif
-
-/*
- * eSPI - Enhanced SPI
- */
-
-/*
- * General PCI
- * Memory space is mapped 1-1, but I/O space must start from 0.
- */
-
-/* controller 1, direct to uli, tgtid 3, Base address 20000 */
-#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
-#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
-
-/* controller 2, Slot 2, tgtid 2, Base address 201000 */
-#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
-#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
-#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
-
-/* controller 3, Slot 1, tgtid 1, Base address 202000 */
-#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
-#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
-#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
-
-/* Qman/Bman */
-#define CONFIG_SYS_BMAN_NUM_PORTALS 10
-#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
-#else
-#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
-#endif
-#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
-#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
-#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
-#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
-#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
- CONFIG_SYS_BMAN_CENA_SIZE)
-#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
-#define CONFIG_SYS_QMAN_NUM_PORTALS 10
-#define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
-#else
-#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
-#endif
-#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
-#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
-#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
-#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
-#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
- CONFIG_SYS_QMAN_CENA_SIZE)
-#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
-
-#define CONFIG_SYS_DPAA_FMAN
-#define CONFIG_SYS_DPAA_PME
-/* Default address of microcode for the Linux Fman driver */
-#if defined(CONFIG_SPIFLASH)
-/*
- * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
- * env, so we got 0x110000.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
-#elif defined(CONFIG_SDCARD)
-/*
- * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
- * about 825KB (1650 blocks), Env is stored after the image, and the env size is
- * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
-#elif defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
-#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
-/*
- * Slave has no ucode locally, it can fetch this from remote. When implementing
- * in two corenet boards, slave's ucode could be stored in master's memory
- * space, the address can be mapped from slave TLB->slave LAW->
- * slave SRIO or PCIE outbound window->master inbound window->
- * master LAW->the ucode address in master's memory space.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
-#else
-#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
-#endif
-#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
-#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
-
-#ifdef CONFIG_PCI
-#if !defined(CONFIG_DM_PCI)
-#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
-#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
-#endif
-
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#endif /* CONFIG_PCI */
-
-/* SATA */
-#define CONFIG_FSL_SATA_V2
-
-#ifdef CONFIG_FSL_SATA_V2
-#define CONFIG_SYS_SATA_MAX_DEVICE 2
-#define CONFIG_SATA1
-#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
-#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
-#define CONFIG_SATA2
-#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
-#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
-
-#define CONFIG_LBA48
-#endif
-
-#ifdef CONFIG_FMAN_ENET
-#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2
-#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3
-#define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x4
-#define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1
-#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x0
-
-#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
-#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
-#define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
-#define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
-
-#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0
-
-#define CONFIG_SYS_TBIPA_VALUE 8
-#define CONFIG_ETHPRIME "FM1 at DTSEC1"
-#endif
-
-/*
- * Environment
- */
-#define CONFIG_LOADS_ECHO /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
-
-/*
- * Command line configuration.
- */
-
-/*
-* USB
-*/
-#define CONFIG_HAS_FSL_DR_USB
-#define CONFIG_HAS_FSL_MPH_USB
-
-#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
-#define CONFIG_USB_EHCI_FSL
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#endif
-
-#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
-#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 64 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */
-#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-#define CONFIG_ROOTPATH "/opt/nfsroot"
-#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_UBOOTPATH u-boot.bin
-
-/* default location for tftp and bootm */
-#define CONFIG_LOADADDR 1000000
-
-#define __USB_PHY_TYPE utmi
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
- "bank_intlv=cs0_cs1\0" \
- "netdev=eth0\0" \
- "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
- "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
- "tftpflash=tftpboot $loadaddr $uboot && " \
- "protect off $ubootaddr +$filesize && " \
- "erase $ubootaddr +$filesize && " \
- "cp.b $loadaddr $ubootaddr $filesize && " \
- "protect on $ubootaddr +$filesize && " \
- "cmp.b $loadaddr $ubootaddr $filesize\0" \
- "consoledev=ttyS0\0" \
- "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
- "usb_dr_mode=host\0" \
- "ramdiskaddr=2000000\0" \
- "ramdiskfile=p2041rdb/ramdisk.uboot\0" \
- "fdtaddr=1e00000\0" \
- "fdtfile=p2041rdb/p2041rdb.dtb\0" \
- "bdev=sda3\0"
-
-#define CONFIG_HDBOOT \
- "setenv bootargs root=/dev/$bdev rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
-
-#include <asm/fsl_secure_boot.h>
-
-#endif /* __CONFIG_H */
--
2.25.1
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 11/24] arm: Remove configs/P3041DS_NAND_SECURE_BOOT_defconfig board
2020-05-27 16:46 [PATCH 00/24] spi: dm-conversion (part2) Jagan Teki
` (9 preceding siblings ...)
2020-05-27 16:46 ` [PATCH 10/24] arm: Remove configs/P2041RDB_NAND_defconfig board Jagan Teki
@ 2020-05-27 16:46 ` Jagan Teki
2020-05-28 7:09 ` Priyanka Jain
2020-05-27 16:46 ` [PATCH 12/24] arm: Remove configs/T1023RDB_NAND_defconfig board Jagan Teki
` (11 subsequent siblings)
22 siblings, 1 reply; 59+ messages in thread
From: Jagan Teki @ 2020-05-27 16:46 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_SPI by the deadline.
Remove it.
Patch-cc: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
arch/powerpc/cpu/mpc85xx/Kconfig | 1 -
board/freescale/corenet_ds/Kconfig | 59 --
board/freescale/corenet_ds/MAINTAINERS | 37 -
board/freescale/corenet_ds/Makefile | 16 -
board/freescale/corenet_ds/corenet_ds.c | 215 ------
board/freescale/corenet_ds/corenet_ds.h | 12 -
board/freescale/corenet_ds/ddr.c | 286 --------
board/freescale/corenet_ds/eth_hydra.c | 520 -------------
board/freescale/corenet_ds/eth_p4080.c | 483 ------------
board/freescale/corenet_ds/eth_superhydra.c | 771 --------------------
board/freescale/corenet_ds/p3041ds_ddr.c | 11 -
board/freescale/corenet_ds/p4080ds_ddr.c | 347 ---------
board/freescale/corenet_ds/p5020ds_ddr.c | 15 -
board/freescale/corenet_ds/p5040ds_ddr.c | 15 -
board/freescale/corenet_ds/pbi.cfg | 33 -
board/freescale/corenet_ds/rcw_p2041rdb.cfg | 11 -
board/freescale/corenet_ds/rcw_p3041ds.cfg | 11 -
board/freescale/corenet_ds/rcw_p4080ds.cfg | 11 -
board/freescale/corenet_ds/rcw_p5020ds.cfg | 11 -
board/freescale/corenet_ds/rcw_p5040ds.cfg | 11 -
configs/P3041DS_NAND_SECURE_BOOT_defconfig | 59 --
configs/P3041DS_NAND_defconfig | 64 --
configs/P3041DS_SDCARD_defconfig | 63 --
configs/P3041DS_SECURE_BOOT_defconfig | 57 --
configs/P3041DS_SPIFLASH_defconfig | 64 --
configs/P3041DS_SRIO_PCIE_BOOT_defconfig | 50 --
configs/P3041DS_defconfig | 62 --
configs/P4080DS_SDCARD_defconfig | 62 --
configs/P4080DS_SECURE_BOOT_defconfig | 56 --
configs/P4080DS_SPIFLASH_defconfig | 63 --
configs/P4080DS_SRIO_PCIE_BOOT_defconfig | 48 --
configs/P4080DS_defconfig | 61 --
configs/P5020DS_NAND_SECURE_BOOT_defconfig | 60 --
configs/P5020DS_NAND_defconfig | 57 --
configs/P5020DS_SDCARD_defconfig | 55 --
configs/P5020DS_SECURE_BOOT_defconfig | 57 --
configs/P5020DS_SPIFLASH_defconfig | 56 --
configs/P5020DS_SRIO_PCIE_BOOT_defconfig | 50 --
configs/P5020DS_defconfig | 54 --
configs/P5040DS_NAND_SECURE_BOOT_defconfig | 60 --
configs/P5040DS_NAND_defconfig | 65 --
configs/P5040DS_SDCARD_defconfig | 63 --
configs/P5040DS_SECURE_BOOT_defconfig | 57 --
configs/P5040DS_SPIFLASH_defconfig | 64 --
configs/P5040DS_defconfig | 62 --
include/configs/P3041DS.h | 24 -
include/configs/P4080DS.h | 23 -
include/configs/P5020DS.h | 25 -
include/configs/P5040DS.h | 19 -
49 files changed, 4436 deletions(-)
delete mode 100644 board/freescale/corenet_ds/Kconfig
delete mode 100644 board/freescale/corenet_ds/MAINTAINERS
delete mode 100644 board/freescale/corenet_ds/Makefile
delete mode 100644 board/freescale/corenet_ds/corenet_ds.c
delete mode 100644 board/freescale/corenet_ds/corenet_ds.h
delete mode 100644 board/freescale/corenet_ds/ddr.c
delete mode 100644 board/freescale/corenet_ds/eth_hydra.c
delete mode 100644 board/freescale/corenet_ds/eth_p4080.c
delete mode 100644 board/freescale/corenet_ds/eth_superhydra.c
delete mode 100644 board/freescale/corenet_ds/p3041ds_ddr.c
delete mode 100644 board/freescale/corenet_ds/p4080ds_ddr.c
delete mode 100644 board/freescale/corenet_ds/p5020ds_ddr.c
delete mode 100644 board/freescale/corenet_ds/p5040ds_ddr.c
delete mode 100644 board/freescale/corenet_ds/pbi.cfg
delete mode 100644 board/freescale/corenet_ds/rcw_p2041rdb.cfg
delete mode 100644 board/freescale/corenet_ds/rcw_p3041ds.cfg
delete mode 100644 board/freescale/corenet_ds/rcw_p4080ds.cfg
delete mode 100644 board/freescale/corenet_ds/rcw_p5020ds.cfg
delete mode 100644 board/freescale/corenet_ds/rcw_p5040ds.cfg
delete mode 100644 configs/P3041DS_NAND_SECURE_BOOT_defconfig
delete mode 100644 configs/P3041DS_NAND_defconfig
delete mode 100644 configs/P3041DS_SDCARD_defconfig
delete mode 100644 configs/P3041DS_SECURE_BOOT_defconfig
delete mode 100644 configs/P3041DS_SPIFLASH_defconfig
delete mode 100644 configs/P3041DS_SRIO_PCIE_BOOT_defconfig
delete mode 100644 configs/P3041DS_defconfig
delete mode 100644 configs/P4080DS_SDCARD_defconfig
delete mode 100644 configs/P4080DS_SECURE_BOOT_defconfig
delete mode 100644 configs/P4080DS_SPIFLASH_defconfig
delete mode 100644 configs/P4080DS_SRIO_PCIE_BOOT_defconfig
delete mode 100644 configs/P4080DS_defconfig
delete mode 100644 configs/P5020DS_NAND_SECURE_BOOT_defconfig
delete mode 100644 configs/P5020DS_NAND_defconfig
delete mode 100644 configs/P5020DS_SDCARD_defconfig
delete mode 100644 configs/P5020DS_SECURE_BOOT_defconfig
delete mode 100644 configs/P5020DS_SPIFLASH_defconfig
delete mode 100644 configs/P5020DS_SRIO_PCIE_BOOT_defconfig
delete mode 100644 configs/P5020DS_defconfig
delete mode 100644 configs/P5040DS_NAND_SECURE_BOOT_defconfig
delete mode 100644 configs/P5040DS_NAND_defconfig
delete mode 100644 configs/P5040DS_SDCARD_defconfig
delete mode 100644 configs/P5040DS_SECURE_BOOT_defconfig
delete mode 100644 configs/P5040DS_SPIFLASH_defconfig
delete mode 100644 configs/P5040DS_defconfig
delete mode 100644 include/configs/P3041DS.h
delete mode 100644 include/configs/P4080DS.h
delete mode 100644 include/configs/P5020DS.h
delete mode 100644 include/configs/P5040DS.h
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index a776aa5e64..1511691974 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -1589,7 +1589,6 @@ config SYS_FSL_LBC_CLK_DIV
Defines divider of platform clock(clock input to
eLBC controller).
-source "board/freescale/corenet_ds/Kconfig"
source "board/freescale/mpc8541cds/Kconfig"
source "board/freescale/mpc8544ds/Kconfig"
source "board/freescale/mpc8548cds/Kconfig"
diff --git a/board/freescale/corenet_ds/Kconfig b/board/freescale/corenet_ds/Kconfig
deleted file mode 100644
index 98b1adde62..0000000000
--- a/board/freescale/corenet_ds/Kconfig
+++ /dev/null
@@ -1,59 +0,0 @@
-if TARGET_P3041DS
-
-config SYS_BOARD
- default "corenet_ds"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "P3041DS"
-
-source "board/freescale/common/Kconfig"
-
-endif
-
-if TARGET_P4080DS
-
-config SYS_BOARD
- default "corenet_ds"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "P4080DS"
-
-source "board/freescale/common/Kconfig"
-
-endif
-
-if TARGET_P5020DS
-
-config SYS_BOARD
- default "corenet_ds"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "P5020DS"
-
-source "board/freescale/common/Kconfig"
-
-endif
-
-if TARGET_P5040DS
-
-config SYS_BOARD
- default "corenet_ds"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "P5040DS"
-
-source "board/freescale/common/Kconfig"
-
-endif
diff --git a/board/freescale/corenet_ds/MAINTAINERS b/board/freescale/corenet_ds/MAINTAINERS
deleted file mode 100644
index 708e812e8e..0000000000
--- a/board/freescale/corenet_ds/MAINTAINERS
+++ /dev/null
@@ -1,37 +0,0 @@
-CORENET_DS BOARD
-#M: -
-S: Maintained
-F: board/freescale/corenet_ds/
-F: include/configs/P3041DS.h
-F: configs/P3041DS_defconfig
-F: configs/P3041DS_NAND_defconfig
-F: configs/P3041DS_SDCARD_defconfig
-F: configs/P3041DS_SECURE_BOOT_defconfig
-F: configs/P3041DS_SPIFLASH_defconfig
-F: configs/P3041DS_SRIO_PCIE_BOOT_defconfig
-F: include/configs/P4080DS.h
-F: configs/P4080DS_defconfig
-F: configs/P4080DS_SDCARD_defconfig
-F: configs/P4080DS_SECURE_BOOT_defconfig
-F: configs/P4080DS_SPIFLASH_defconfig
-F: configs/P4080DS_SRIO_PCIE_BOOT_defconfig
-F: include/configs/P5020DS.h
-F: configs/P5020DS_defconfig
-F: configs/P5020DS_NAND_defconfig
-F: configs/P5020DS_SDCARD_defconfig
-F: configs/P5020DS_SECURE_BOOT_defconfig
-F: configs/P5020DS_SPIFLASH_defconfig
-F: configs/P5020DS_SRIO_PCIE_BOOT_defconfig
-F: include/configs/P5040DS.h
-F: configs/P5040DS_defconfig
-F: configs/P5040DS_NAND_defconfig
-F: configs/P5040DS_SDCARD_defconfig
-F: configs/P5040DS_SPIFLASH_defconfig
-F: configs/P5040DS_SECURE_BOOT_defconfig
-
-CORENET_DS_SECURE_BOOT BOARD
-M: Ruchika Gupta <ruchika.gupta@nxp.com>
-S: Maintained
-F: configs/P3041DS_NAND_SECURE_BOOT_defconfig
-F: configs/P5020DS_NAND_SECURE_BOOT_defconfig
-F: configs/P5040DS_NAND_SECURE_BOOT_defconfig
diff --git a/board/freescale/corenet_ds/Makefile b/board/freescale/corenet_ds/Makefile
deleted file mode 100644
index 98322b2747..0000000000
--- a/board/freescale/corenet_ds/Makefile
+++ /dev/null
@@ -1,16 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2007-2009 Freescale Semiconductor, Inc.
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-
-obj-y += corenet_ds.o
-obj-y += ddr.o
-obj-$(CONFIG_TARGET_P3041DS) += eth_hydra.o
-obj-$(CONFIG_TARGET_P4080DS) += eth_p4080.o
-obj-$(CONFIG_TARGET_P5020DS) += eth_hydra.o
-obj-$(CONFIG_TARGET_P5040DS) += eth_superhydra.o
-obj-$(CONFIG_TARGET_P3041DS) += p3041ds_ddr.o
-obj-$(CONFIG_TARGET_P4080DS) += p4080ds_ddr.o
-obj-$(CONFIG_TARGET_P5020DS) += p5020ds_ddr.o
-obj-$(CONFIG_TARGET_P5040DS) += p5040ds_ddr.o
diff --git a/board/freescale/corenet_ds/corenet_ds.c b/board/freescale/corenet_ds/corenet_ds.c
deleted file mode 100644
index f0c7bed68f..0000000000
--- a/board/freescale/corenet_ds/corenet_ds.c
+++ /dev/null
@@ -1,215 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2009-2011 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <env.h>
-#include <fdt_support.h>
-#include <image.h>
-#include <init.h>
-#include <netdev.h>
-#include <linux/compiler.h>
-#include <asm/mmu.h>
-#include <asm/processor.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_law.h>
-#include <asm/fsl_serdes.h>
-#include <asm/fsl_liodn.h>
-#include <fm_eth.h>
-
-#include "../common/ngpixis.h"
-#include "corenet_ds.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard (void)
-{
- u8 sw;
- struct cpu_type *cpu = gd->arch.cpu;
-#if defined(CONFIG_TARGET_P3041DS) || defined(CONFIG_TARGET_P5020DS) || \
- defined(CONFIG_TARGET_P5040DS)
- unsigned int i;
-#endif
- static const char * const freq[] = {"100", "125", "156.25", "212.5" };
-
- printf("Board: %sDS, ", cpu->name);
- printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
- in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
-
- sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
- sw = (sw & PIXIS_LBMAP_MASK) >> PIXIS_LBMAP_SHIFT;
-
- if (sw < 0x8)
- printf("vBank: %d\n", sw);
- else if (sw == 0x8)
- puts("Promjet\n");
- else if (sw == 0x9)
- puts("NAND\n");
- else
- printf("invalid setting of SW%u\n", PIXIS_LBMAP_SWITCH);
-
- /* Display the actual SERDES reference clocks as configured by the
- * dip switches on the board. Note that the SWx registers could
- * technically be set to force the reference clocks to match the
- * values that the SERDES expects (or vice versa). For now, however,
- * we just display both values and hope the user notices when they
- * don't match.
- */
- puts("SERDES Reference Clocks: ");
-#if defined(CONFIG_TARGET_P3041DS) || defined(CONFIG_TARGET_P5020DS) || \
- defined(CONFIG_TARGET_P5040DS)
- sw = in_8(&PIXIS_SW(5));
- for (i = 0; i < 3; i++) {
- unsigned int clock = (sw >> (6 - (2 * i))) & 3;
-
- printf("Bank%u=%sMhz ", i+1, freq[clock]);
- }
-#ifdef CONFIG_TARGET_P5040DS
- /* On P5040DS, SW11[7:8] determines the Bank 4 frequency */
- sw = in_8(&PIXIS_SW(9));
- printf("Bank4=%sMhz ", freq[sw & 3]);
-#endif
- puts("\n");
-#else
- sw = in_8(&PIXIS_SW(3));
- /* SW3[2]: 0 = 100 Mhz, 1 = 125 MHz */
- /* SW3[3]: 0 = 125 Mhz, 1 = 156.25 MHz */
- /* SW3[4]: 0 = 125 Mhz, 1 = 156.25 MHz */
- printf("Bank1=%sMHz ", freq[!!(sw & 0x40)]);
- printf("Bank2=%sMHz ", freq[1 + !!(sw & 0x20)]);
- printf("Bank3=%sMHz\n", freq[1 + !!(sw & 0x10)]);
-#endif
-
- return 0;
-}
-
-int board_early_init_f(void)
-{
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-
- /*
- * P4080 DS board only uses the DDR1_MCK0/3 and DDR2_MCK0/3
- * disable the DDR1_MCK1/2/4/5 and DDR2_MCK1/2/4/5 to reduce
- * the noise introduced by these unterminated and unused clock pairs.
- */
- setbits_be32(&gur->ddrclkdr, 0x001B001B);
-
- return 0;
-}
-
-int board_early_init_r(void)
-{
- const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
- int flash_esel = find_tlb_idx((void *)flashbase, 1);
-
- /*
- * Remap Boot flash + PROMJET region to caching-inhibited
- * so that flash can be erased properly.
- */
-
- /* Flush d-cache and invalidate i-cache of any FLASH data */
- flush_dcache();
- invalidate_icache();
-
- if (flash_esel == -1) {
- /* very unlikely unless something is messed up */
- puts("Error: Could not find TLB for FLASH BASE\n");
- flash_esel = 2; /* give our best effort to continue */
- } else {
- /* invalidate existing TLB entry for flash + promjet */
- disable_tlb(flash_esel);
- }
-
- set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
- 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */
-
- return 0;
-}
-
-#define NUM_SRDS_BANKS 3
-
-int misc_init_r(void)
-{
- serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
- u32 actual[NUM_SRDS_BANKS];
- unsigned int i;
- u8 sw;
-
-#if defined(CONFIG_TARGET_P3041DS) || defined(CONFIG_TARGET_P5020DS) || \
- defined(CONFIG_TARGET_P5040DS)
- sw = in_8(&PIXIS_SW(5));
- for (i = 0; i < 3; i++) {
- unsigned int clock = (sw >> (6 - (2 * i))) & 3;
- switch (clock) {
- case 0:
- actual[i] = SRDS_PLLCR0_RFCK_SEL_100;
- break;
- case 1:
- actual[i] = SRDS_PLLCR0_RFCK_SEL_125;
- break;
- case 2:
- actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25;
- break;
- default:
- printf("Warning: SDREFCLK%u switch setting of '11' is "
- "unsupported\n", i + 1);
- break;
- }
- }
-#else
- /* Warn if the expected SERDES reference clocks don't match the
- * actual reference clocks. This needs to be done after calling
- * p4080_erratum_serdes8(), since that function may modify the clocks.
- */
- sw = in_8(&PIXIS_SW(3));
- actual[0] = (sw & 0x40) ?
- SRDS_PLLCR0_RFCK_SEL_125 : SRDS_PLLCR0_RFCK_SEL_100;
- actual[1] = (sw & 0x20) ?
- SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125;
- actual[2] = (sw & 0x10) ?
- SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125;
-#endif
-
- for (i = 0; i < NUM_SRDS_BANKS; i++) {
- u32 expected = srds_regs->bank[i].pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
- if (expected != actual[i]) {
- printf("Warning: SERDES bank %u expects reference clock"
- " %sMHz, but actual is %sMHz\n", i + 1,
- serdes_clock_to_string(expected),
- serdes_clock_to_string(actual[i]));
- }
- }
-
- return 0;
-}
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
- phys_addr_t base;
- phys_size_t size;
-
- ft_cpu_setup(blob, bd);
-
- base = env_get_bootm_low();
- size = env_get_bootm_size();
-
- fdt_fixup_memory(blob, (u64)base, (u64)size);
-
-#ifdef CONFIG_PCI
- pci_of_setup(blob, bd);
-#endif
-
- fdt_fixup_liodn(blob);
- fsl_fdt_fixup_dr_usb(blob, bd);
-
-#ifdef CONFIG_SYS_DPAA_FMAN
- fdt_fixup_fman_ethernet(blob);
- fdt_fixup_board_enet(blob);
-#endif
-
- return 0;
-}
diff --git a/board/freescale/corenet_ds/corenet_ds.h b/board/freescale/corenet_ds/corenet_ds.h
deleted file mode 100644
index 301f04442a..0000000000
--- a/board/freescale/corenet_ds/corenet_ds.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2011 Freescale Semiconductor, Inc.
- */
-
-#ifndef __CORENET_DS_H__
-#define __CORENET_DS_H__
-
-void fdt_fixup_board_enet(void *blob);
-void pci_of_setup(void *blob, bd_t *bd);
-
-#endif
diff --git a/board/freescale/corenet_ds/ddr.c b/board/freescale/corenet_ds/ddr.c
deleted file mode 100644
index 19f6e8700d..0000000000
--- a/board/freescale/corenet_ds/ddr.c
+++ /dev/null
@@ -1,286 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright 2009-2011 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <hwconfig.h>
-#include <init.h>
-#include <log.h>
-#include <vsprintf.h>
-#include <asm/mmu.h>
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-#include <asm/fsl_law.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-
-/*
- * Fixed sdram init -- doesn't use serial presence detect.
- */
-extern fixed_ddr_parm_t fixed_ddr_parm_0[];
-#if (CONFIG_SYS_NUM_DDR_CTLRS == 2)
-extern fixed_ddr_parm_t fixed_ddr_parm_1[];
-#endif
-
-phys_size_t fixed_sdram(void)
-{
- int i;
- char buf[32];
- fsl_ddr_cfg_regs_t ddr_cfg_regs;
- phys_size_t ddr_size;
- unsigned int lawbar1_target_id;
- ulong ddr_freq, ddr_freq_mhz;
-
- ddr_freq = get_ddr_freq(0);
- ddr_freq_mhz = ddr_freq / 1000000;
-
- printf("Configuring DDR for %s MT/s data rate\n",
- strmhz(buf, ddr_freq));
-
- for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
- if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) &&
- (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) {
- memcpy(&ddr_cfg_regs,
- fixed_ddr_parm_0[i].ddr_settings,
- sizeof(ddr_cfg_regs));
- break;
- }
- }
-
- if (fixed_ddr_parm_0[i].max_freq == 0)
- panic("Unsupported DDR data rate %s MT/s data rate\n",
- strmhz(buf, ddr_freq));
-
- ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
- ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN;
- fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
-
-#if (CONFIG_SYS_NUM_DDR_CTLRS == 2)
- memcpy(&ddr_cfg_regs,
- fixed_ddr_parm_1[i].ddr_settings,
- sizeof(ddr_cfg_regs));
- ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN;
- fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 1, 0);
-#endif
-
- /*
- * setup laws for DDR. If not interleaving, presuming half memory on
- * DDR1 and the other half on DDR2
- */
- if (fixed_ddr_parm_0[i].ddr_settings->cs[0].config & 0x20000000) {
- if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
- ddr_size,
- LAW_TRGT_IF_DDR_INTRLV) < 0) {
- printf("ERROR setting Local Access Windows for DDR\n");
- return 0;
- }
- } else {
-#if (CONFIG_SYS_NUM_DDR_CTLRS == 2)
- /* We require both controllers have identical DIMMs */
- lawbar1_target_id = LAW_TRGT_IF_DDR_1;
- if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
- ddr_size / 2,
- lawbar1_target_id) < 0) {
- printf("ERROR setting Local Access Windows for DDR\n");
- return 0;
- }
- lawbar1_target_id = LAW_TRGT_IF_DDR_2;
- if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE + ddr_size / 2,
- ddr_size / 2,
- lawbar1_target_id) < 0) {
- printf("ERROR setting Local Access Windows for DDR\n");
- return 0;
- }
-#else
- lawbar1_target_id = LAW_TRGT_IF_DDR_1;
- if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
- ddr_size,
- lawbar1_target_id) < 0) {
- printf("ERROR setting Local Access Windows for DDR\n");
- return 0;
- }
-#endif
- }
- return ddr_size;
-}
-
-struct board_specific_parameters {
- u32 n_ranks;
- u32 datarate_mhz_high;
- u32 clk_adjust;
- u32 wrlvl_start;
- u32 cpo;
- u32 write_data_delay;
- u32 force_2t;
-};
-
-/*
- * This table contains all valid speeds we want to override with board
- * specific parameters. datarate_mhz_high values need to be in ascending order
- * for each n_ranks group.
- */
-static const struct board_specific_parameters udimm0[] = {
- /*
- * memory controller 0
- * num| hi| clk| wrlvl | cpo |wrdata|2T
- * ranks| mhz|adjst| start | |delay |
- */
- {4, 850, 4, 6, 0xff, 2, 0},
- {4, 950, 5, 7, 0xff, 2, 0},
- {4, 1050, 5, 8, 0xff, 2, 0},
- {4, 1250, 5, 10, 0xff, 2, 0},
- {4, 1350, 5, 11, 0xff, 2, 0},
- {4, 1666, 5, 12, 0xff, 2, 0},
- {2, 850, 5, 6, 0xff, 2, 0},
- {2, 1050, 5, 7, 0xff, 2, 0},
- {2, 1250, 4, 6, 0xff, 2, 0},
- {2, 1350, 5, 7, 0xff, 2, 0},
- {2, 1666, 5, 8, 0xff, 2, 0},
- {1, 1250, 4, 6, 0xff, 2, 0},
- {1, 1335, 4, 7, 0xff, 2, 0},
- {1, 1666, 4, 8, 0xff, 2, 0},
- {}
-};
-
-/*
- * The two slots have slightly different timing. The center values are good
- * for both slots. We use identical speed tables for them. In future use, if
- * DIMMs have fewer center values that require two separated tables, copy the
- * udimm0 table to udimm1 and make changes to clk_adjust and wrlvl_start.
- */
-static const struct board_specific_parameters *udimms[] = {
- udimm0,
- udimm0,
-};
-
-static const struct board_specific_parameters rdimm0[] = {
- /*
- * memory controller 0
- * num| hi| clk| wrlvl | cpo |wrdata|2T
- * ranks| mhz|adjst| start | |delay |
- */
- {4, 850, 4, 6, 0xff, 2, 0},
- {4, 950, 5, 7, 0xff, 2, 0},
- {4, 1050, 5, 8, 0xff, 2, 0},
- {4, 1250, 5, 10, 0xff, 2, 0},
- {4, 1350, 5, 11, 0xff, 2, 0},
- {4, 1666, 5, 12, 0xff, 2, 0},
- {2, 850, 4, 6, 0xff, 2, 0},
- {2, 1050, 4, 7, 0xff, 2, 0},
- {2, 1666, 4, 8, 0xff, 2, 0},
- {1, 850, 4, 5, 0xff, 2, 0},
- {1, 950, 4, 7, 0xff, 2, 0},
- {1, 1666, 4, 8, 0xff, 2, 0},
- {}
-};
-
-/*
- * The two slots have slightly different timing. See comments above.
- */
-static const struct board_specific_parameters *rdimms[] = {
- rdimm0,
- rdimm0,
-};
-
-void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
- ulong ddr_freq;
-
- if (ctrl_num > 1) {
- printf("Wrong parameter for controller number %d", ctrl_num);
- return;
- }
- if (!pdimm->n_ranks)
- return;
-
- if (popts->registered_dimm_en)
- pbsp = rdimms[ctrl_num];
- else
- pbsp = udimms[ctrl_num];
-
-
- /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
- * freqency and n_banks specified in board_specific_parameters table.
- */
- ddr_freq = get_ddr_freq(0) / 1000000;
- while (pbsp->datarate_mhz_high) {
- if (pbsp->n_ranks == pdimm->n_ranks) {
- if (ddr_freq <= pbsp->datarate_mhz_high) {
- popts->cpo_override = pbsp->cpo;
- popts->write_data_delay =
- pbsp->write_data_delay;
- popts->clk_adjust = pbsp->clk_adjust;
- popts->wrlvl_start = pbsp->wrlvl_start;
- popts->twot_en = pbsp->force_2t;
- goto found;
- }
- pbsp_highest = pbsp;
- }
- pbsp++;
- }
-
- if (pbsp_highest) {
- printf("Error: board specific timing not found "
- "for data rate %lu MT/s!\n"
- "Trying to use the highest speed (%u) parameters\n",
- ddr_freq, pbsp_highest->datarate_mhz_high);
- popts->cpo_override = pbsp_highest->cpo;
- popts->write_data_delay = pbsp_highest->write_data_delay;
- popts->clk_adjust = pbsp_highest->clk_adjust;
- popts->wrlvl_start = pbsp_highest->wrlvl_start;
- popts->twot_en = pbsp_highest->force_2t;
- } else {
- panic("DIMM is not supported by this board");
- }
-found:
- /*
- * Factors to consider for half-strength driver enable:
- * - number of DIMMs installed
- */
- popts->half_strength_driver_enable = 0;
- /*
- * Write leveling override
- */
- popts->wrlvl_override = 1;
- popts->wrlvl_sample = 0xf;
-
- /*
- * Rtt and Rtt_WR override
- */
- popts->rtt_override = 0;
-
- /* Enable ZQ calibration */
- popts->zq_en = 1;
-
- /* DHC_EN =1, ODT = 60 Ohm */
- popts->ddr_cdr1 = DDR_CDR1_DHC_EN;
-}
-
-int dram_init(void)
-{
- phys_size_t dram_size;
-
- puts("Initializing....");
-
- if (fsl_use_spd()) {
- puts("using SPD\n");
- dram_size = fsl_ddr_sdram();
- } else {
- puts("using fixed parameters\n");
- dram_size = fixed_sdram();
- }
-
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
-
- debug(" DDR: ");
- gd->ram_size = dram_size;
-
- return 0;
-}
diff --git a/board/freescale/corenet_ds/eth_hydra.c b/board/freescale/corenet_ds/eth_hydra.c
deleted file mode 100644
index a17ca7ac60..0000000000
--- a/board/freescale/corenet_ds/eth_hydra.c
+++ /dev/null
@@ -1,520 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2009-2011 Freescale Semiconductor, Inc.
- * Author: Timur Tabi <timur@freescale.com>
- */
-
-/*
- * This file handles the board muxing between the Fman Ethernet MACs and
- * the RGMII/SGMII/XGMII PHYs on a Freescale P3041/P5020 "Hydra" reference
- * board. The RGMII PHYs are the two on-board 1Gb ports. The SGMII PHYs are
- * provided by the standard Freescale four-port SGMII riser card. The 10Gb
- * XGMII PHY is provided via the XAUI riser card. Since there is only one
- * Fman device on a P3041 and P5020, we only support one SGMII card and one
- * RGMII card.
- *
- * Muxing is handled via the PIXIS BRDCFG1 register. The EMI1 bits control
- * muxing among the RGMII PHYs and the SGMII PHYs. The value for RGMII is
- * always the same (0). The value for SGMII depends on which slot the riser is
- * inserted in. The EMI2 bits control muxing for the the XGMII. Like SGMII,
- * the value is based on which slot the XAUI is inserted in.
- *
- * The SERDES configuration is used to determine where the SGMII and XAUI cards
- * exist, and also which Fman MACs are routed to which PHYs. So for a given
- * Fman MAC, there is one and only PHY it connects to. MACs cannot be routed
- * to PHYs dynamically.
- *
- *
- * This file also updates the device tree in three ways:
- *
- * 1) The status of each virtual MDIO node that is referenced by an Ethernet
- * node is set to "okay".
- *
- * 2) The phy-handle property of each active Ethernet MAC node is set to the
- * appropriate PHY node.
- *
- * 3) The "mux value" for each virtual MDIO node is set to the correct value,
- * if necessary. Some virtual MDIO nodes do not have configurable mux
- * values, so those values are hard-coded in the DTS. On the HYDRA board,
- * the virtual MDIO node for the SGMII card needs to be updated.
- *
- * For all this to work, the device tree needs to have the following:
- *
- * 1) An alias for each PHY node that an Ethernet node could be routed to.
- *
- * 2) An alias for each real and virtual MDIO node that is disabled by default
- * and might need to be enabled, and also might need to have its mux-value
- * updated.
- */
-
-#include <common.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/fsl_serdes.h>
-#include <fm_eth.h>
-#include <fsl_mdio.h>
-#include <malloc.h>
-#include <fdt_support.h>
-#include <fsl_dtsec.h>
-
-#include "../common/ngpixis.h"
-#include "../common/fman.h"
-
-#ifdef CONFIG_FMAN_ENET
-
-#define BRDCFG1_EMI1_SEL_MASK 0x78
-#define BRDCFG1_EMI1_SEL_SLOT1 0x10
-#define BRDCFG1_EMI1_SEL_SLOT2 0x20
-#define BRDCFG1_EMI1_SEL_SLOT5 0x30
-#define BRDCFG1_EMI1_SEL_SLOT6 0x40
-#define BRDCFG1_EMI1_SEL_SLOT7 0x50
-#define BRDCFG1_EMI1_SEL_RGMII 0x00
-#define BRDCFG1_EMI1_EN 0x08
-#define BRDCFG1_EMI2_SEL_MASK 0x06
-#define BRDCFG1_EMI2_SEL_SLOT1 0x00
-#define BRDCFG1_EMI2_SEL_SLOT2 0x02
-
-#define BRDCFG2_REG_GPIO_SEL 0x20
-
-#define PHY_BASE_ADDR 0x00
-
-/*
- * BRDCFG1 mask and value for each MAC
- *
- * This array contains the BRDCFG1 values (in mask/val format) that route the
- * MDIO bus to a particular RGMII or SGMII PHY.
- */
-struct {
- u8 mask;
- u8 val;
-} mdio_mux[NUM_FM_PORTS];
-
-/*
- * Mapping of all 18 SERDES lanes to board slots. A value of '0' here means
- * that the mapping must be determined dynamically, or that the lane maps to
- * something other than a board slot
- */
-static u8 lane_to_slot[] = {
- 7, 7, 0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 2, 2, 1, 1, 0, 0
-};
-
-/*
- * Set the board muxing for a given MAC
- *
- * The MDIO layer calls this function every time it wants to talk to a PHY.
- */
-void hydra_mux_mdio(u8 mask, u8 val)
-{
- clrsetbits_8(&pixis->brdcfg1, mask, val);
-}
-
-struct hydra_mdio {
- u8 mask;
- u8 val;
- struct mii_dev *realbus;
-};
-
-static int hydra_mdio_read(struct mii_dev *bus, int addr, int devad,
- int regnum)
-{
- struct hydra_mdio *priv = bus->priv;
-
- hydra_mux_mdio(priv->mask, priv->val);
-
- return priv->realbus->read(priv->realbus, addr, devad, regnum);
-}
-
-static int hydra_mdio_write(struct mii_dev *bus, int addr, int devad,
- int regnum, u16 value)
-{
- struct hydra_mdio *priv = bus->priv;
-
- hydra_mux_mdio(priv->mask, priv->val);
-
- return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
-}
-
-static int hydra_mdio_reset(struct mii_dev *bus)
-{
- struct hydra_mdio *priv = bus->priv;
-
- return priv->realbus->reset(priv->realbus);
-}
-
-static void hydra_mdio_set_mux(char *name, u8 mask, u8 val)
-{
- struct mii_dev *bus = miiphy_get_dev_by_name(name);
- struct hydra_mdio *priv = bus->priv;
-
- priv->mask = mask;
- priv->val = val;
-}
-
-static int hydra_mdio_init(char *realbusname, char *fakebusname)
-{
- struct hydra_mdio *hmdio;
- struct mii_dev *bus = mdio_alloc();
-
- if (!bus) {
- printf("Failed to allocate Hydra MDIO bus\n");
- return -1;
- }
-
- hmdio = malloc(sizeof(*hmdio));
- if (!hmdio) {
- printf("Failed to allocate Hydra private data\n");
- free(bus);
- return -1;
- }
-
- bus->read = hydra_mdio_read;
- bus->write = hydra_mdio_write;
- bus->reset = hydra_mdio_reset;
- strcpy(bus->name, fakebusname);
-
- hmdio->realbus = miiphy_get_dev_by_name(realbusname);
-
- if (!hmdio->realbus) {
- printf("No bus with name %s\n", realbusname);
- free(bus);
- free(hmdio);
- return -1;
- }
-
- bus->priv = hmdio;
-
- return mdio_register(bus);
-}
-
-/*
- * Given an alias or a path for a node, set the mux value of that node.
- *
- * If 'alias' is not a valid alias, then it is treated as a full path to the
- * node. No error checking is performed.
- *
- * This function is normally called to set the fsl,hydra-mdio-muxval property
- * of a virtual MDIO node.
- */
-static void fdt_set_mdio_mux(void *fdt, const char *alias, u32 mux)
-{
- const char *path = fdt_get_alias(fdt, alias);
-
- if (!path)
- path = alias;
-
- do_fixup_by_path(fdt, path, "reg",
- &mux, sizeof(mux), 1);
- do_fixup_by_path(fdt, path, "fsl,hydra-mdio-muxval",
- &mux, sizeof(mux), 1);
-}
-
-/*
- * Given the following ...
- *
- * 1) A pointer to an Fman Ethernet node (as identified by the 'compat'
- * compatible string and 'addr' physical address)
- *
- * 2) An Fman port
- *
- * ... update the phy-handle property of the Ethernet node to point to the
- * right PHY. This assumes that we already know the PHY for each port. That
- * information is stored in mdio_mux[].
- *
- * The offset of the Fman Ethernet node is also passed in for convenience, but
- * it is not used, and we recalculate the offset anyway.
- *
- * Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC.
- * Inside the Fman, "ports" are things that connect to MACs. We only call them
- * ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs
- * and ports are the same thing.
- *
- * Note that this code would be cleaner if had a function called
- * fm_info_get_phy_address(), which returns a value from the fm1_dtsec_info[]
- * array. That's because all we're doing is figuring out the PHY address for
- * a given Fman MAC and writing it to the device tree. Well, we already did
- * the hard work to figure that out in board_eth_init(), so it's silly to
- * repeat that here.
- */
-void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
- enum fm_port port, int offset)
-{
- unsigned int mux = mdio_mux[port].val & mdio_mux[port].mask;
- char phy[16];
-
- if (port == FM1_10GEC1) {
- /* XAUI */
- int lane = serdes_get_first_lane(XAUI_FM1);
- if (lane >= 0) {
- /* The XAUI PHY is identified by the slot */
- sprintf(phy, "phy_xgmii_%u", lane_to_slot[lane]);
- fdt_set_phy_handle(fdt, compat, addr, phy);
- }
- return;
- }
-
- if (mux == (BRDCFG1_EMI1_SEL_RGMII | BRDCFG1_EMI1_EN)) {
- /* RGMII */
- /* The RGMII PHY is identified by the MAC connected to it */
- sprintf(phy, "phy_rgmii_%u", port == FM1_DTSEC4 ? 0 : 1);
- fdt_set_phy_handle(fdt, compat, addr, phy);
- return;
- }
-
- /* If it's not RGMII or XGMII, it must be SGMII */
- if (mux) {
- /* The SGMII PHY is identified by the MAC connected to it */
- sprintf(phy, "phy_sgmii_%x",
- CONFIG_SYS_FM1_DTSEC1_PHY_ADDR + (port - FM1_DTSEC1));
- fdt_set_phy_handle(fdt, compat, addr, phy);
- }
-}
-
-#define PIXIS_SW2_LANE_23_SEL 0x80
-#define PIXIS_SW2_LANE_45_SEL 0x40
-#define PIXIS_SW2_LANE_67_SEL_MASK 0x30
-#define PIXIS_SW2_LANE_67_SEL_5 0x00
-#define PIXIS_SW2_LANE_67_SEL_6 0x20
-#define PIXIS_SW2_LANE_67_SEL_7 0x10
-#define PIXIS_SW2_LANE_8_SEL 0x08
-#define PIXIS_SW2_LANE_1617_SEL 0x04
-
-/*
- * Initialize the lane_to_slot[] array.
- *
- * On the P4080DS "Expedition" board, the mapping of SERDES lanes to board
- * slots is hard-coded. On the Hydra board, however, the mapping is controlled
- * by board switch SW2, so the lane_to_slot[] array needs to be dynamically
- * initialized.
- */
-static void initialize_lane_to_slot(void)
-{
- u8 sw2 = in_8(&PIXIS_SW(2));
-
- lane_to_slot[2] = (sw2 & PIXIS_SW2_LANE_23_SEL) ? 7 : 4;
- lane_to_slot[3] = lane_to_slot[2];
-
- lane_to_slot[4] = (sw2 & PIXIS_SW2_LANE_45_SEL) ? 7 : 6;
- lane_to_slot[5] = lane_to_slot[4];
-
- switch (sw2 & PIXIS_SW2_LANE_67_SEL_MASK) {
- case PIXIS_SW2_LANE_67_SEL_5:
- lane_to_slot[6] = 5;
- break;
- case PIXIS_SW2_LANE_67_SEL_6:
- lane_to_slot[6] = 6;
- break;
- case PIXIS_SW2_LANE_67_SEL_7:
- lane_to_slot[6] = 7;
- break;
- }
- lane_to_slot[7] = lane_to_slot[6];
-
- lane_to_slot[8] = (sw2 & PIXIS_SW2_LANE_8_SEL) ? 3 : 0;
-
- lane_to_slot[16] = (sw2 & PIXIS_SW2_LANE_1617_SEL) ? 1 : 0;
- lane_to_slot[17] = lane_to_slot[16];
-}
-
-#endif /* #ifdef CONFIG_FMAN_ENET */
-
-/*
- * Configure the status for the virtual MDIO nodes
- *
- * Rather than create the virtual MDIO nodes from scratch for each active
- * virtual MDIO, we expect the DTS to have the nodes defined already, and we
- * only enable the ones that are actually active.
- *
- * We assume that the DTS already hard-codes the status for all the
- * virtual MDIO nodes to "disabled", so all we need to do is enable the
- * active ones.
- *
- * For SGMII, we also need to set the mux value in the node.
- */
-void fdt_fixup_board_enet(void *fdt)
-{
-#ifdef CONFIG_FMAN_ENET
- unsigned int i;
- int lane;
-
- for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
- int idx = i - FM1_DTSEC1;
-
- switch (fm_info_get_enet_if(i)) {
- case PHY_INTERFACE_MODE_SGMII:
- lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
- if (lane >= 0) {
- fdt_status_okay_by_alias(fdt, "emi1_sgmii");
- /* Also set the MUX value */
- fdt_set_mdio_mux(fdt, "emi1_sgmii",
- mdio_mux[i].val);
- }
- break;
- case PHY_INTERFACE_MODE_RGMII:
- fdt_status_okay_by_alias(fdt, "emi1_rgmii");
- break;
- default:
- break;
- }
- }
-
- lane = serdes_get_first_lane(XAUI_FM1);
- if (lane >= 0)
- fdt_status_okay_by_alias(fdt, "emi2_xgmii");
-#endif
-}
-
-int board_eth_init(bd_t *bis)
-{
-#ifdef CONFIG_FMAN_ENET
- struct fsl_pq_mdio_info dtsec_mdio_info;
- struct tgec_mdio_info tgec_mdio_info;
- unsigned int i, slot;
- int lane;
- struct mii_dev *bus;
-
- printf("Initializing Fman\n");
-
- initialize_lane_to_slot();
-
- /* We want to use the PIXIS to configure MUX routing, not GPIOs. */
- setbits_8(&pixis->brdcfg2, BRDCFG2_REG_GPIO_SEL);
-
- memset(mdio_mux, 0, sizeof(mdio_mux));
-
- dtsec_mdio_info.regs =
- (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
- dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
-
- /* Register the real 1G MDIO bus */
- fsl_pq_mdio_init(bis, &dtsec_mdio_info);
-
- tgec_mdio_info.regs =
- (struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
- tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
-
- /* Register the real 10G MDIO bus */
- fm_tgec_mdio_init(bis, &tgec_mdio_info);
-
- /* Register the three virtual MDIO front-ends */
- hydra_mdio_init(DEFAULT_FM_MDIO_NAME, "HYDRA_RGMII_MDIO");
- hydra_mdio_init(DEFAULT_FM_MDIO_NAME, "HYDRA_SGMII_MDIO");
-
- /*
- * Program the DTSEC PHY addresses assuming that they are all SGMII.
- * For any DTSEC that's RGMII, we'll override its PHY address later.
- * We assume that DTSEC5 is only used for RGMII.
- */
- fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
-
- for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
- int idx = i - FM1_DTSEC1;
-
- switch (fm_info_get_enet_if(i)) {
- case PHY_INTERFACE_MODE_SGMII:
- lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
- if (lane < 0)
- break;
- slot = lane_to_slot[lane];
- mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK;
- switch (slot) {
- case 1:
- /* Always DTSEC5 on Bank 3 */
- mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT1 |
- BRDCFG1_EMI1_EN;
- break;
- case 2:
- mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT2 |
- BRDCFG1_EMI1_EN;
- break;
- case 5:
- mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT5 |
- BRDCFG1_EMI1_EN;
- break;
- case 6:
- mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT6 |
- BRDCFG1_EMI1_EN;
- break;
- case 7:
- mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT7 |
- BRDCFG1_EMI1_EN;
- break;
- };
-
- hydra_mdio_set_mux("HYDRA_SGMII_MDIO",
- mdio_mux[i].mask, mdio_mux[i].val);
- fm_info_set_mdio(i,
- miiphy_get_dev_by_name("HYDRA_SGMII_MDIO"));
- break;
- case PHY_INTERFACE_MODE_RGMII:
- /*
- * If DTSEC4 is RGMII, then it's routed via via EC1 to
- * the first on-board RGMII port. If DTSEC5 is RGMII,
- * then it's routed via via EC2 to the second on-board
- * RGMII port. The other DTSECs cannot be routed to
- * RGMII.
- */
- fm_info_set_phy_address(i, i == FM1_DTSEC4 ? 0 : 1);
- mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK;
- mdio_mux[i].val = BRDCFG1_EMI1_SEL_RGMII |
- BRDCFG1_EMI1_EN;
- hydra_mdio_set_mux("HYDRA_RGMII_MDIO",
- mdio_mux[i].mask, mdio_mux[i].val);
- fm_info_set_mdio(i,
- miiphy_get_dev_by_name("HYDRA_RGMII_MDIO"));
- break;
- case PHY_INTERFACE_MODE_NONE:
- fm_info_set_phy_address(i, 0);
- break;
- default:
- printf("Fman1: DTSEC%u set to unknown interface %i\n",
- idx + 1, fm_info_get_enet_if(i));
- fm_info_set_phy_address(i, 0);
- break;
- }
- }
-
- bus = miiphy_get_dev_by_name("HYDRA_SGMII_MDIO");
- set_sgmii_phy(bus, FM1_DTSEC1, CONFIG_SYS_NUM_FM1_DTSEC, PHY_BASE_ADDR);
-
- /*
- * For 10G, we only support one XAUI card per Fman. If present, then we
- * force its routing and never touch those bits again, which removes the
- * need for Linux to do any muxing. This works because of the way
- * BRDCFG1 is defined, but it's a bit hackish.
- *
- * The PHY address for the XAUI card depends on which slot it's in. The
- * macros we use imply that the PHY address is based on which FM, but
- * that's not true. On the P4080DS, FM1 could only use XAUI in slot 5,
- * and FM2 could only use a XAUI in slot 4. On the Hydra board, we
- * check the actual slot and just use the macros as-is, even though
- * the P3041 and P5020 only have one Fman.
- */
- lane = serdes_get_first_lane(XAUI_FM1);
- if (lane >= 0) {
- slot = lane_to_slot[lane];
- if (slot == 1) {
- /* XAUI card is in slot 1 */
- clrsetbits_8(&pixis->brdcfg1, BRDCFG1_EMI2_SEL_MASK,
- BRDCFG1_EMI2_SEL_SLOT1);
- fm_info_set_phy_address(FM1_10GEC1,
- CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
- } else {
- /* XAUI card is in slot 2 */
- clrsetbits_8(&pixis->brdcfg1, BRDCFG1_EMI2_SEL_MASK,
- BRDCFG1_EMI2_SEL_SLOT2);
- fm_info_set_phy_address(FM1_10GEC1,
- CONFIG_SYS_FM2_10GEC1_PHY_ADDR);
- }
- }
-
- fm_info_set_mdio(FM1_10GEC1,
- miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME));
-
- cpu_eth_init(bis);
-#endif
-
- return pci_eth_init(bis);
-}
diff --git a/board/freescale/corenet_ds/eth_p4080.c b/board/freescale/corenet_ds/eth_p4080.c
deleted file mode 100644
index 801a6f44f0..0000000000
--- a/board/freescale/corenet_ds/eth_p4080.c
+++ /dev/null
@@ -1,483 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2009-2011 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <fdt_support.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/mmu.h>
-#include <asm/processor.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_law.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/fsl_serdes.h>
-#include <asm/fsl_portals.h>
-#include <asm/fsl_liodn.h>
-#include <malloc.h>
-#include <fm_eth.h>
-#include <fsl_mdio.h>
-#include <miiphy.h>
-#include <phy.h>
-#include <linux/delay.h>
-
-#include "../common/ngpixis.h"
-#include "../common/fman.h"
-#include <fsl_dtsec.h>
-
-#define EMI_NONE 0xffffffff
-#define EMI_MASK 0xf0000000
-#define EMI1_RGMII 0x0
-#define EMI1_SLOT3 0x80000000 /* bank1 EFGH */
-#define EMI1_SLOT4 0x40000000 /* bank2 ABCD */
-#define EMI1_SLOT5 0xc0000000 /* bank3 ABCD */
-#define EMI2_SLOT4 0x10000000 /* bank2 ABCD */
-#define EMI2_SLOT5 0x30000000 /* bank3 ABCD */
-#define EMI1_MASK 0xc0000000
-#define EMI2_MASK 0x30000000
-
-#define PHY_BASE_ADDR 0x00
-#define PHY_BASE_ADDR_SLOT5 0x10
-
-static int mdio_mux[NUM_FM_PORTS];
-
-static char *mdio_names[16] = {
- "P4080DS_MDIO0",
- "P4080DS_MDIO1",
- NULL,
- "P4080DS_MDIO3",
- "P4080DS_MDIO4",
- NULL, NULL, NULL,
- "P4080DS_MDIO8",
- NULL, NULL, NULL,
- "P4080DS_MDIO12",
- NULL, NULL, NULL,
-};
-
-/*
- * Mapping of all 18 SERDES lanes to board slots. A value of '0' here means
- * that the mapping must be determined dynamically, or that the lane maps to
- * something other than a board slot.
- */
-static u8 lane_to_slot[] = {
- 1, 1, 2, 2, 3, 3, 3, 3, 6, 6, 4, 4, 4, 4, 5, 5, 5, 5
-};
-
-static char *p4080ds_mdio_name_for_muxval(u32 muxval)
-{
- return mdio_names[(muxval & EMI_MASK) >> 28];
-}
-
-struct mii_dev *mii_dev_for_muxval(u32 muxval)
-{
- struct mii_dev *bus;
- char *name = p4080ds_mdio_name_for_muxval(muxval);
-
- if (!name) {
- printf("No bus for muxval %x\n", muxval);
- return NULL;
- }
-
- bus = miiphy_get_dev_by_name(name);
-
- if (!bus) {
- printf("No bus by name %s\n", name);
- return NULL;
- }
-
- return bus;
-}
-
-#if defined(CONFIG_SYS_P4080_ERRATUM_SERDES9) && defined(CONFIG_PHY_TERANETICS)
-int board_phy_config(struct phy_device *phydev)
-{
- if (phydev->drv->config)
- phydev->drv->config(phydev);
- if (phydev->drv->uid == PHY_UID_TN2020) {
- unsigned long timeout = 1 * 1000; /* 1 seconds */
- enum srds_prtcl device;
-
- /*
- * Wait for the XAUI to come out of reset. This is when it
- * starts transmitting alignment signals.
- */
- while (--timeout) {
- int reg = phy_read(phydev, MDIO_MMD_PHYXS, MDIO_CTRL1);
- if (reg < 0) {
- printf("TN2020: Error reading from PHY@"
- "address %u\n", phydev->addr);
- break;
- }
- /*
- * Note that we've never actually seen
- * MDIO_CTRL1_RESET set to 1.
- */
- if ((reg & MDIO_CTRL1_RESET) == 0)
- break;
- udelay(1000);
- }
-
- if (!timeout) {
- printf("TN2020: Timeout waiting for PHY at address %u "
- " to reset.\n", phydev->addr);
- }
-
- switch (phydev->addr) {
- case CONFIG_SYS_FM1_10GEC1_PHY_ADDR:
- device = XAUI_FM1;
- break;
- case CONFIG_SYS_FM2_10GEC1_PHY_ADDR:
- device = XAUI_FM2;
- break;
- default:
- device = NONE;
- }
-
- serdes_reset_rx(device);
- }
-
- return 0;
-}
-#endif
-
-struct p4080ds_mdio {
- u32 muxval;
- struct mii_dev *realbus;
-};
-
-static void p4080ds_mux_mdio(u32 muxval)
-{
- ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
- uint gpioval = in_be32(&pgpio->gpdat) & ~(EMI_MASK);
- gpioval |= muxval;
-
- out_be32(&pgpio->gpdat, gpioval);
-}
-
-static int p4080ds_mdio_read(struct mii_dev *bus, int addr, int devad,
- int regnum)
-{
- struct p4080ds_mdio *priv = bus->priv;
-
- p4080ds_mux_mdio(priv->muxval);
-
- return priv->realbus->read(priv->realbus, addr, devad, regnum);
-}
-
-static int p4080ds_mdio_write(struct mii_dev *bus, int addr, int devad,
- int regnum, u16 value)
-{
- struct p4080ds_mdio *priv = bus->priv;
-
- p4080ds_mux_mdio(priv->muxval);
-
- return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
-}
-
-static int p4080ds_mdio_reset(struct mii_dev *bus)
-{
- struct p4080ds_mdio *priv = bus->priv;
-
- return priv->realbus->reset(priv->realbus);
-}
-
-static int p4080ds_mdio_init(char *realbusname, u32 muxval)
-{
- struct p4080ds_mdio *pmdio;
- struct mii_dev *bus = mdio_alloc();
-
- if (!bus) {
- printf("Failed to allocate P4080DS MDIO bus\n");
- return -1;
- }
-
- pmdio = malloc(sizeof(*pmdio));
- if (!pmdio) {
- printf("Failed to allocate P4080DS private data\n");
- free(bus);
- return -1;
- }
-
- bus->read = p4080ds_mdio_read;
- bus->write = p4080ds_mdio_write;
- bus->reset = p4080ds_mdio_reset;
- sprintf(bus->name, p4080ds_mdio_name_for_muxval(muxval));
-
- pmdio->realbus = miiphy_get_dev_by_name(realbusname);
-
- if (!pmdio->realbus) {
- printf("No bus with name %s\n", realbusname);
- free(bus);
- free(pmdio);
- return -1;
- }
-
- pmdio->muxval = muxval;
- bus->priv = pmdio;
-
- return mdio_register(bus);
-}
-
-void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa,
- enum fm_port port, int offset)
-{
- if (mdio_mux[port] == EMI1_RGMII)
- fdt_set_phy_handle(blob, prop, pa, "phy_rgmii");
-
- if (mdio_mux[port] == EMI1_SLOT3) {
- int idx = port - FM2_DTSEC1 + 5;
- char phy[16];
-
- sprintf(phy, "phy%d_slot3", idx);
-
- fdt_set_phy_handle(blob, prop, pa, phy);
- }
-}
-
-void fdt_fixup_board_enet(void *fdt)
-{
- int i;
-
- /*
- * P4080DS can be configured in many different ways, supporting a number
- * of combinations of ethernet devices and phy types. In order to
- * have just one device tree for all of those configurations, we fix up
- * the tree here. By default, the device tree configures FM1 and FM2
- * for SGMII, and configures XAUI on both 10G interfaces. So we have
- * a number of different variables to track:
- *
- * 1) Whether the device is configured at all. Whichever devices are
- * not enabled should be disabled by setting the "status" property
- * to "disabled".
- * 2) What the PHY interface is. If this is an RGMII connection,
- * we should change the "phy-connection-type" property to
- * "rgmii"
- * 3) Which PHY is being used. Because the MDIO buses are muxed,
- * we need to redirect the "phy-handle" property to point at the
- * PHY on the right slot/bus.
- */
-
- /* We've got six MDIO nodes that may or may not need to exist */
- fdt_status_disabled_by_alias(fdt, "emi1_slot3");
- fdt_status_disabled_by_alias(fdt, "emi1_slot4");
- fdt_status_disabled_by_alias(fdt, "emi1_slot5");
- fdt_status_disabled_by_alias(fdt, "emi2_slot4");
- fdt_status_disabled_by_alias(fdt, "emi2_slot5");
-
- for (i = 0; i < NUM_FM_PORTS; i++) {
- switch (mdio_mux[i]) {
- case EMI1_SLOT3:
- fdt_status_okay_by_alias(fdt, "emi1_slot3");
- break;
- case EMI1_SLOT4:
- fdt_status_okay_by_alias(fdt, "emi1_slot4");
- break;
- case EMI1_SLOT5:
- fdt_status_okay_by_alias(fdt, "emi1_slot5");
- break;
- case EMI2_SLOT4:
- fdt_status_okay_by_alias(fdt, "emi2_slot4");
- break;
- case EMI2_SLOT5:
- fdt_status_okay_by_alias(fdt, "emi2_slot5");
- break;
- }
- }
-}
-
-int board_eth_init(bd_t *bis)
-{
-#ifdef CONFIG_FMAN_ENET
- ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
- int i;
- struct fsl_pq_mdio_info dtsec_mdio_info;
- struct tgec_mdio_info tgec_mdio_info;
- struct mii_dev *bus;
-
- /* Initialize the mdio_mux array so we can recognize empty elements */
- for (i = 0; i < NUM_FM_PORTS; i++)
- mdio_mux[i] = EMI_NONE;
-
- /* The first 4 GPIOs are outputs to control MDIO bus muxing */
- out_be32(&pgpio->gpdir, EMI_MASK);
-
- dtsec_mdio_info.regs =
- (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
- dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
-
- /* Register the 1G MDIO bus */
- fsl_pq_mdio_init(bis, &dtsec_mdio_info);
-
- tgec_mdio_info.regs =
- (struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
- tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
-
- /* Register the 10G MDIO bus */
- fm_tgec_mdio_init(bis, &tgec_mdio_info);
-
- /* Register the 6 muxing front-ends to the MDIO buses */
- p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII);
- p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
- p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
- p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
- p4080ds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2_SLOT4);
- p4080ds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2_SLOT5);
-
- fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
- fm_info_set_phy_address(FM1_10GEC1, CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
-
-#if (CONFIG_SYS_NUM_FMAN == 2)
- fm_info_set_phy_address(FM2_DTSEC1, CONFIG_SYS_FM2_DTSEC1_PHY_ADDR);
- fm_info_set_phy_address(FM2_DTSEC2, CONFIG_SYS_FM2_DTSEC2_PHY_ADDR);
- fm_info_set_phy_address(FM2_DTSEC3, CONFIG_SYS_FM2_DTSEC3_PHY_ADDR);
- fm_info_set_phy_address(FM2_DTSEC4, CONFIG_SYS_FM2_DTSEC4_PHY_ADDR);
- fm_info_set_phy_address(FM2_10GEC1, CONFIG_SYS_FM2_10GEC1_PHY_ADDR);
-#endif
-
- for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
- int idx = i - FM1_DTSEC1, lane, slot;
- switch (fm_info_get_enet_if(i)) {
- case PHY_INTERFACE_MODE_SGMII:
- lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
- if (lane < 0)
- break;
- slot = lane_to_slot[lane];
- switch (slot) {
- case 3:
- mdio_mux[i] = EMI1_SLOT3;
- fm_info_set_mdio(i,
- mii_dev_for_muxval(mdio_mux[i]));
- break;
- case 4:
- mdio_mux[i] = EMI1_SLOT4;
- fm_info_set_mdio(i,
- mii_dev_for_muxval(mdio_mux[i]));
- break;
- case 5:
- mdio_mux[i] = EMI1_SLOT5;
- fm_info_set_mdio(i,
- mii_dev_for_muxval(mdio_mux[i]));
- break;
- };
- break;
- case PHY_INTERFACE_MODE_RGMII:
- fm_info_set_phy_address(i, 0);
- mdio_mux[i] = EMI1_RGMII;
- fm_info_set_mdio(i,
- mii_dev_for_muxval(mdio_mux[i]));
- break;
- default:
- break;
- }
- }
- bus = mii_dev_for_muxval(EMI1_SLOT5);
- set_sgmii_phy(bus, FM1_DTSEC1,
- CONFIG_SYS_NUM_FM1_DTSEC, PHY_BASE_ADDR_SLOT5);
-
- for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
- int idx = i - FM1_10GEC1, lane, slot;
- switch (fm_info_get_enet_if(i)) {
- case PHY_INTERFACE_MODE_XGMII:
- lane = serdes_get_first_lane(XAUI_FM1 + idx);
- if (lane < 0)
- break;
- slot = lane_to_slot[lane];
- switch (slot) {
- case 4:
- mdio_mux[i] = EMI2_SLOT4;
- fm_info_set_mdio(i,
- mii_dev_for_muxval(mdio_mux[i]));
- break;
- case 5:
- mdio_mux[i] = EMI2_SLOT5;
- fm_info_set_mdio(i,
- mii_dev_for_muxval(mdio_mux[i]));
- break;
- };
- break;
- default:
- break;
- }
- }
-
-#if (CONFIG_SYS_NUM_FMAN == 2)
- for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
- int idx = i - FM2_DTSEC1, lane, slot;
- switch (fm_info_get_enet_if(i)) {
- case PHY_INTERFACE_MODE_SGMII:
- lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx);
- if (lane < 0)
- break;
- slot = lane_to_slot[lane];
- switch (slot) {
- case 3:
- mdio_mux[i] = EMI1_SLOT3;
- fm_info_set_mdio(i,
- mii_dev_for_muxval(mdio_mux[i]));
- break;
- case 4:
- mdio_mux[i] = EMI1_SLOT4;
- fm_info_set_mdio(i,
- mii_dev_for_muxval(mdio_mux[i]));
- break;
- case 5:
- mdio_mux[i] = EMI1_SLOT5;
- fm_info_set_mdio(i,
- mii_dev_for_muxval(mdio_mux[i]));
- break;
- };
- break;
- case PHY_INTERFACE_MODE_RGMII:
- fm_info_set_phy_address(i, 0);
- mdio_mux[i] = EMI1_RGMII;
- fm_info_set_mdio(i,
- mii_dev_for_muxval(mdio_mux[i]));
- break;
- default:
- break;
- }
- }
-
- bus = mii_dev_for_muxval(EMI1_SLOT3);
- set_sgmii_phy(bus, FM2_DTSEC1, CONFIG_SYS_NUM_FM2_DTSEC, PHY_BASE_ADDR);
- bus = mii_dev_for_muxval(EMI1_SLOT4);
- set_sgmii_phy(bus, FM2_DTSEC1, CONFIG_SYS_NUM_FM2_DTSEC, PHY_BASE_ADDR);
-
- for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) {
- int idx = i - FM2_10GEC1, lane, slot;
- switch (fm_info_get_enet_if(i)) {
- case PHY_INTERFACE_MODE_XGMII:
- lane = serdes_get_first_lane(XAUI_FM2 + idx);
- if (lane < 0)
- break;
- slot = lane_to_slot[lane];
- switch (slot) {
- case 4:
- mdio_mux[i] = EMI2_SLOT4;
- fm_info_set_mdio(i,
- mii_dev_for_muxval(mdio_mux[i]));
- break;
- case 5:
- mdio_mux[i] = EMI2_SLOT5;
- fm_info_set_mdio(i,
- mii_dev_for_muxval(mdio_mux[i]));
- break;
- };
- break;
- default:
- break;
- }
- }
-#endif
-
- cpu_eth_init(bis);
-#endif /* CONFIG_FMAN_ENET */
-
- return pci_eth_init(bis);
-}
diff --git a/board/freescale/corenet_ds/eth_superhydra.c b/board/freescale/corenet_ds/eth_superhydra.c
deleted file mode 100644
index 8ca220b840..0000000000
--- a/board/freescale/corenet_ds/eth_superhydra.c
+++ /dev/null
@@ -1,771 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2009-2011 Freescale Semiconductor, Inc.
- * Author: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
- */
-
-/*
- * This file handles the board muxing between the Fman Ethernet MACs and
- * the RGMII/SGMII/XGMII PHYs on a Freescale P5040 "Super Hydra" reference
- * board. The RGMII PHYs are the two on-board 1Gb ports. The SGMII PHYs are
- * provided by the standard Freescale four-port SGMII riser card. The 10Gb
- * XGMII PHYs are provided via the XAUI riser card. The P5040 has 2 FMans
- * and 5 1G interfaces and 10G interface per FMan. Based on the options in
- * the RCW, we could have upto 3 SGMII cards and 1 XAUI card at a time.
- *
- * Muxing is handled via the PIXIS BRDCFG1 register. The EMI1 bits control
- * muxing among the RGMII PHYs and the SGMII PHYs. The value for RGMII is
- * always the same (0). The value for SGMII depends on which slot the riser is
- * inserted in. The EMI2 bits control muxing for the the XGMII. Like SGMII,
- * the value is based on which slot the XAUI is inserted in.
- *
- * The SERDES configuration is used to determine where the SGMII and XAUI cards
- * exist, and also which Fman's MACs are routed to which PHYs. So for a given
- * Fman MAC, there is one and only PHY it connects to. MACs cannot be routed
- * to PHYs dynamically.
- *
- *
- * This file also updates the device tree in three ways:
- *
- * 1) The status of each virtual MDIO node that is referenced by an Ethernet
- * node is set to "okay".
- *
- * 2) The phy-handle property of each active Ethernet MAC node is set to the
- * appropriate PHY node.
- *
- * 3) The "mux value" for each virtual MDIO node is set to the correct value,
- * if necessary. Some virtual MDIO nodes do not have configurable mux
- * values, so those values are hard-coded in the DTS. On the HYDRA board,
- * the virtual MDIO node for the SGMII card needs to be updated.
- *
- * For all this to work, the device tree needs to have the following:
- *
- * 1) An alias for each PHY node that an Ethernet node could be routed to.
- *
- * 2) An alias for each real and virtual MDIO node that is disabled by default
- * and might need to be enabled, and also might need to have its mux-value
- * updated.
- */
-
-#include <common.h>
-#include <log.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/fsl_serdes.h>
-#include <fm_eth.h>
-#include <fsl_mdio.h>
-#include <malloc.h>
-#include <fdt_support.h>
-#include <fsl_dtsec.h>
-
-#include "../common/ngpixis.h"
-#include "../common/fman.h"
-
-#ifdef CONFIG_FMAN_ENET
-
-#define BRDCFG1_EMI1_SEL_MASK 0x70
-#define BRDCFG1_EMI1_SEL_SLOT1 0x10
-#define BRDCFG1_EMI1_SEL_SLOT2 0x20
-#define BRDCFG1_EMI1_SEL_SLOT5 0x30
-#define BRDCFG1_EMI1_SEL_SLOT6 0x40
-#define BRDCFG1_EMI1_SEL_SLOT7 0x50
-#define BRDCFG1_EMI1_SEL_SLOT3 0x60
-#define BRDCFG1_EMI1_SEL_RGMII 0x00
-#define BRDCFG1_EMI1_EN 0x08
-#define BRDCFG1_EMI2_SEL_MASK 0x06
-#define BRDCFG1_EMI2_SEL_SLOT1 0x00
-#define BRDCFG1_EMI2_SEL_SLOT2 0x02
-
-#define BRDCFG2_REG_GPIO_SEL 0x20
-
-/* SGMII */
-#define PHY_BASE_ADDR 0x00
-#define REGNUM 0x00
-#define PORT_NUM_FM1 0x04
-#define PORT_NUM_FM2 0x02
-
-/*
- * BRDCFG1 mask and value for each MAC
- *
- * This array contains the BRDCFG1 values (in mask/val format) that route the
- * MDIO bus to a particular RGMII or SGMII PHY.
- */
-static struct {
- u8 mask;
- u8 val;
-} mdio_mux[NUM_FM_PORTS];
-
-/*
- * Mapping of all 18 SERDES lanes to board slots. A value of '0' here means
- * that the mapping must be determined dynamically, or that the lane maps to
- * something other than a board slot
- */
-static u8 lane_to_slot[] = {
- 7, 7, 0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 2, 2, 1, 1, 0, 0, 0, 0
-};
-
-/*
- * Set the board muxing for a given MAC
- *
- * The MDIO layer calls this function every time it wants to talk to a PHY.
- */
-void super_hydra_mux_mdio(u8 mask, u8 val)
-{
- clrsetbits_8(&pixis->brdcfg1, mask, val);
-}
-
-struct super_hydra_mdio {
- u8 mask;
- u8 val;
- struct mii_dev *realbus;
-};
-
-static int super_hydra_mdio_read(struct mii_dev *bus, int addr, int devad,
- int regnum)
-{
- struct super_hydra_mdio *priv = bus->priv;
-
- super_hydra_mux_mdio(priv->mask, priv->val);
-
- return priv->realbus->read(priv->realbus, addr, devad, regnum);
-}
-
-static int super_hydra_mdio_write(struct mii_dev *bus, int addr, int devad,
- int regnum, u16 value)
-{
- struct super_hydra_mdio *priv = bus->priv;
-
- super_hydra_mux_mdio(priv->mask, priv->val);
-
- return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
-}
-
-static int super_hydra_mdio_reset(struct mii_dev *bus)
-{
- struct super_hydra_mdio *priv = bus->priv;
-
- return priv->realbus->reset(priv->realbus);
-}
-
-static void super_hydra_mdio_set_mux(char *name, u8 mask, u8 val)
-{
- struct mii_dev *bus = miiphy_get_dev_by_name(name);
- struct super_hydra_mdio *priv = bus->priv;
-
- priv->mask = mask;
- priv->val = val;
-}
-
-static int super_hydra_mdio_init(char *realbusname, char *fakebusname)
-{
- struct super_hydra_mdio *hmdio;
- struct mii_dev *bus = mdio_alloc();
-
- if (!bus) {
- printf("Failed to allocate Hydra MDIO bus\n");
- return -1;
- }
-
- hmdio = malloc(sizeof(*hmdio));
- if (!hmdio) {
- printf("Failed to allocate Hydra private data\n");
- free(bus);
- return -1;
- }
-
- bus->read = super_hydra_mdio_read;
- bus->write = super_hydra_mdio_write;
- bus->reset = super_hydra_mdio_reset;
- strcpy(bus->name, fakebusname);
-
- hmdio->realbus = miiphy_get_dev_by_name(realbusname);
-
- if (!hmdio->realbus) {
- printf("No bus with name %s\n", realbusname);
- free(bus);
- free(hmdio);
- return -1;
- }
-
- bus->priv = hmdio;
-
- return mdio_register(bus);
-}
-
-/*
- * Given the following ...
- *
- * 1) A pointer to an Fman Ethernet node (as identified by the 'compat'
- * compatible string and 'addr' physical address)
- *
- * 2) An Fman port
- *
- * ... update the phy-handle property of the Ethernet node to point to the
- * right PHY. This assumes that we already know the PHY for each port. That
- * information is stored in mdio_mux[].
- *
- * The offset of the Fman Ethernet node is also passed in for convenience, but
- * it is not used.
- *
- * Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC.
- * Inside the Fman, "ports" are things that connect to MACs. We only call them
- * ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs
- * and ports are the same thing.
- */
-void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
- enum fm_port port, int offset)
-{
- enum srds_prtcl device;
- int lane, slot, phy;
- char alias[32];
-
- /* RGMII and XGMII are already mapped correctly in the DTS */
-
- if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
- device = serdes_device_from_fm_port(port);
- lane = serdes_get_first_lane(device);
- slot = lane_to_slot[lane];
- phy = fm_info_get_phy_address(port);
-
- sprintf(alias, "phy_sgmii_slot%u_%x", slot, phy);
- fdt_set_phy_handle(fdt, compat, addr, alias);
- }
-}
-
-#define PIXIS_SW2_LANE_23_SEL 0x80
-#define PIXIS_SW2_LANE_45_SEL 0x40
-#define PIXIS_SW2_LANE_67_SEL_MASK 0x30
-#define PIXIS_SW2_LANE_67_SEL_5 0x00
-#define PIXIS_SW2_LANE_67_SEL_6 0x20
-#define PIXIS_SW2_LANE_67_SEL_7 0x10
-#define PIXIS_SW2_LANE_8_SEL 0x08
-#define PIXIS_SW2_LANE_1617_SEL 0x04
-#define PIXIS_SW11_LANE_9_SEL 0x04
-/*
- * Initialize the lane_to_slot[] array.
- *
- * On the P4080DS "Expedition" board, the mapping of SERDES lanes to board
- * slots is hard-coded. On the Hydra board, however, the mapping is controlled
- * by board switch SW2, so the lane_to_slot[] array needs to be dynamically
- * initialized.
- */
-static void initialize_lane_to_slot(void)
-{
- u8 sw2 = in_8(&PIXIS_SW(2));
- /* SW11 appears in the programming model as SW9 */
- u8 sw11 = in_8(&PIXIS_SW(9));
-
- lane_to_slot[2] = (sw2 & PIXIS_SW2_LANE_23_SEL) ? 7 : 4;
- lane_to_slot[3] = lane_to_slot[2];
-
- lane_to_slot[4] = (sw2 & PIXIS_SW2_LANE_45_SEL) ? 7 : 6;
- lane_to_slot[5] = lane_to_slot[4];
-
- switch (sw2 & PIXIS_SW2_LANE_67_SEL_MASK) {
- case PIXIS_SW2_LANE_67_SEL_5:
- lane_to_slot[6] = 5;
- break;
- case PIXIS_SW2_LANE_67_SEL_6:
- lane_to_slot[6] = 6;
- break;
- case PIXIS_SW2_LANE_67_SEL_7:
- lane_to_slot[6] = 7;
- break;
- }
- lane_to_slot[7] = lane_to_slot[6];
-
- lane_to_slot[8] = (sw2 & PIXIS_SW2_LANE_8_SEL) ? 3 : 0;
- lane_to_slot[9] = (sw11 & PIXIS_SW11_LANE_9_SEL) ? 0 : 3;
-
- lane_to_slot[16] = (sw2 & PIXIS_SW2_LANE_1617_SEL) ? 1 : 0;
- lane_to_slot[17] = lane_to_slot[16];
-}
-
-#endif /* #ifdef CONFIG_FMAN_ENET */
-
-/*
- * Configure the status for the virtual MDIO nodes
- *
- * Rather than create the virtual MDIO nodes from scratch for each active
- * virtual MDIO, we expect the DTS to have the nodes defined already, and we
- * only enable the ones that are actually active.
- *
- * We assume that the DTS already hard-codes the status for all the
- * virtual MDIO nodes to "disabled", so all we need to do is enable the
- * active ones.
- */
-void fdt_fixup_board_enet(void *fdt)
-{
-#ifdef CONFIG_FMAN_ENET
- enum fm_port i;
- int lane, slot;
-
- for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
- int idx = i - FM1_DTSEC1;
-
- switch (fm_info_get_enet_if(i)) {
- case PHY_INTERFACE_MODE_SGMII:
- lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
- if (lane >= 0) {
- char alias[32];
-
- slot = lane_to_slot[lane];
- sprintf(alias, "hydra_sg_slot%u", slot);
- fdt_status_okay_by_alias(fdt, alias);
- debug("Enabled MDIO node %s (slot %i)\n",
- alias, slot);
- }
- break;
- case PHY_INTERFACE_MODE_RGMII:
- fdt_status_okay_by_alias(fdt, "hydra_rg");
- debug("Enabled MDIO node hydra_rg\n");
- break;
- default:
- break;
- }
- }
-
- lane = serdes_get_first_lane(XAUI_FM1);
- if (lane >= 0) {
- char alias[32];
-
- slot = lane_to_slot[lane];
- sprintf(alias, "hydra_xg_slot%u", slot);
- fdt_status_okay_by_alias(fdt, alias);
- debug("Enabled MDIO node %s (slot %i)\n", alias, slot);
- }
-
-#if CONFIG_SYS_NUM_FMAN == 2
- for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
- int idx = i - FM2_DTSEC1;
-
- switch (fm_info_get_enet_if(i)) {
- case PHY_INTERFACE_MODE_SGMII:
- lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx);
- if (lane >= 0) {
- char alias[32];
-
- slot = lane_to_slot[lane];
- sprintf(alias, "hydra_sg_slot%u", slot);
- fdt_status_okay_by_alias(fdt, alias);
- debug("Enabled MDIO node %s (slot %i)\n",
- alias, slot);
- }
- break;
- case PHY_INTERFACE_MODE_RGMII:
- fdt_status_okay_by_alias(fdt, "hydra_rg");
- debug("Enabled MDIO node hydra_rg\n");
- break;
- default:
- break;
- }
- }
-
- lane = serdes_get_first_lane(XAUI_FM2);
- if (lane >= 0) {
- char alias[32];
-
- slot = lane_to_slot[lane];
- sprintf(alias, "hydra_xg_slot%u", slot);
- fdt_status_okay_by_alias(fdt, alias);
- debug("Enabled MDIO node %s (slot %i)\n", alias, slot);
- }
-#endif /* CONFIG_SYS_NUM_FMAN == 2 */
-#endif /* CONFIG_FMAN_ENET */
-}
-
-/*
- * Mapping of SerDes Protocol to MDIO MUX value and PHY address.
- *
- * Fman 1:
- * DTSEC1 | DTSEC2 | DTSEC3 | DTSEC4
- * Mux Phy | Mux Phy | Mux Phy | Mux Phy
- * Value Addr | Value Addr | Value Addr | Value Addr
- * 0x00 2 1c | 2 1d | 2 1e | 2 1f
- * 0x01 | | 6 1c |
- * 0x02 | | 3 1c | 3 1d
- * 0x03 2 1c | 2 1d | 2 1e | 2 1f
- * 0x04 2 1c | 2 1d | 2 1e | 2 1f
- * 0x05 | | 3 1c | 3 1d
- * 0x06 2 1c | 2 1d | 2 1e | 2 1f
- * 0x07 | | 6 1c |
- * 0x11 2 1c | 2 1d | 2 1e | 2 1f
- * 0x2a 2 | | 2 1e | 2 1f
- * 0x34 6 1c | 6 1d | 4 1e | 4 1f
- * 0x35 | | 3 1c | 3 1d
- * 0x36 6 1c | 6 1d | 4 1e | 4 1f
- * | | |
- * Fman 2: | | |
- * DTSEC1 | DTSEC2 | DTSEC3 | DTSEC4
- * EMI1 | EMI1 | EMI1 | EMI1
- * Mux Phy | Mux Phy | Mux Phy | Mux Phy
- * Value Addr | Value Addr | Value Addr | Value Addr
- * 0x00 | | 6 1c | 6 1d
- * 0x01 | | |
- * 0x02 | | 6 1c | 6 1d
- * 0x03 3 1c | 3 1d | 6 1c | 6 1d
- * 0x04 3 1c | 3 1d | 6 1c | 6 1d
- * 0x05 | | 6 1c | 6 1d
- * 0x06 | | 6 1c | 6 1d
- * 0x07 | | |
- * 0x11 | | |
- * 0x2a | | |
- * 0x34 | | |
- * 0x35 | | |
- * 0x36 | | |
- */
-
-int board_eth_init(bd_t *bis)
-{
-#ifdef CONFIG_FMAN_ENET
- struct fsl_pq_mdio_info dtsec_mdio_info;
- struct tgec_mdio_info tgec_mdio_info;
- unsigned int i, slot;
- int lane;
- struct mii_dev *bus;
- int qsgmii;
- int phy_real_addr;
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- int srds_prtcl = (in_be32(&gur->rcwsr[4]) &
- FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
-
- printf("Initializing Fman\n");
-
- initialize_lane_to_slot();
-
- /* We want to use the PIXIS to configure MUX routing, not GPIOs. */
- setbits_8(&pixis->brdcfg2, BRDCFG2_REG_GPIO_SEL);
-
- memset(mdio_mux, 0, sizeof(mdio_mux));
-
- dtsec_mdio_info.regs =
- (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
- dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
-
- /* Register the real 1G MDIO bus */
- fsl_pq_mdio_init(bis, &dtsec_mdio_info);
-
- tgec_mdio_info.regs =
- (struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
- tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
-
- /* Register the real 10G MDIO bus */
- fm_tgec_mdio_init(bis, &tgec_mdio_info);
-
- /* Register the three virtual MDIO front-ends */
- super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME,
- "SUPER_HYDRA_RGMII_MDIO");
- super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME,
- "SUPER_HYDRA_FM1_SGMII_MDIO");
- super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME,
- "SUPER_HYDRA_FM2_SGMII_MDIO");
- super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME,
- "SUPER_HYDRA_FM3_SGMII_MDIO");
- super_hydra_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME,
- "SUPER_HYDRA_FM1_TGEC_MDIO");
- super_hydra_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME,
- "SUPER_HYDRA_FM2_TGEC_MDIO");
-
- /*
- * Program the DTSEC PHY addresses assuming that they are all SGMII.
- * For any DTSEC that's RGMII, we'll override its PHY address later.
- * We assume that DTSEC5 is only used for RGMII.
- */
- fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
- fm_info_set_phy_address(FM1_10GEC1, CONFIG_SYS_FM2_10GEC1_PHY_ADDR);
-
-#if (CONFIG_SYS_NUM_FMAN == 2)
- fm_info_set_phy_address(FM2_DTSEC1, CONFIG_SYS_FM2_DTSEC1_PHY_ADDR);
- fm_info_set_phy_address(FM2_DTSEC2, CONFIG_SYS_FM2_DTSEC2_PHY_ADDR);
- fm_info_set_phy_address(FM2_DTSEC3, CONFIG_SYS_FM2_DTSEC1_PHY_ADDR);
- fm_info_set_phy_address(FM2_DTSEC4, CONFIG_SYS_FM2_DTSEC2_PHY_ADDR);
- fm_info_set_phy_address(FM2_10GEC1, CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
-#endif
-
- switch (srds_prtcl) {
- case 0:
- case 3:
- case 4:
- case 6:
- case 0x11:
- case 0x2a:
- case 0x34:
- case 0x36:
- fm_info_set_phy_address(FM1_DTSEC3,
- CONFIG_SYS_FM1_DTSEC3_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC4,
- CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
- break;
- case 1:
- case 2:
- case 5:
- case 7:
- case 0x35:
- fm_info_set_phy_address(FM1_DTSEC3,
- CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC4,
- CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
- break;
- default:
- printf("Fman: Unsupport SerDes Protocol 0x%02x\n", srds_prtcl);
- break;
- }
-
- for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
- int idx = i - FM1_DTSEC1;
-
- switch (fm_info_get_enet_if(i)) {
- case PHY_INTERFACE_MODE_SGMII:
- lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
- if (lane < 0)
- break;
- slot = lane_to_slot[lane];
- mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK;
- debug("FM1 at DTSEC%u expects SGMII in slot %u\n",
- idx + 1, slot);
- switch (slot) {
- case 1:
- mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT1 |
- BRDCFG1_EMI1_EN;
- break;
- case 2:
- mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT2 |
- BRDCFG1_EMI1_EN;
- break;
- case 3:
- mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT3 |
- BRDCFG1_EMI1_EN;
- break;
- case 5:
- mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT5 |
- BRDCFG1_EMI1_EN;
- break;
- case 6:
- mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT6 |
- BRDCFG1_EMI1_EN;
- break;
- case 7:
- mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT7 |
- BRDCFG1_EMI1_EN;
- break;
- };
-
- super_hydra_mdio_set_mux("SUPER_HYDRA_FM1_SGMII_MDIO",
- mdio_mux[i].mask, mdio_mux[i].val);
- fm_info_set_mdio(i,
- miiphy_get_dev_by_name("SUPER_HYDRA_FM1_SGMII_MDIO"));
- break;
- case PHY_INTERFACE_MODE_RGMII:
- /*
- * FM1 DTSEC5 is routed via EC1 to the first on-board
- * RGMII port. FM2 DTSEC5 is routed via EC2 to the
- * second on-board RGMII port. The other DTSECs cannot
- * be routed to RGMII.
- */
- debug("FM1 at DTSEC%u is RGMII@address %u\n",
- idx + 1, 0);
- fm_info_set_phy_address(i, 0);
- mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK;
- mdio_mux[i].val = BRDCFG1_EMI1_SEL_RGMII |
- BRDCFG1_EMI1_EN;
- super_hydra_mdio_set_mux("SUPER_HYDRA_RGMII_MDIO",
- mdio_mux[i].mask, mdio_mux[i].val);
- fm_info_set_mdio(i,
- miiphy_get_dev_by_name("SUPER_HYDRA_RGMII_MDIO"));
- break;
- case PHY_INTERFACE_MODE_NONE:
- fm_info_set_phy_address(i, 0);
- break;
- default:
- printf("Fman1: DTSEC%u set to unknown interface %i\n",
- idx + 1, fm_info_get_enet_if(i));
- fm_info_set_phy_address(i, 0);
- break;
- }
- }
-
- bus = miiphy_get_dev_by_name("SUPER_HYDRA_FM1_SGMII_MDIO");
- qsgmii = is_qsgmii_riser_card(bus, PHY_BASE_ADDR, PORT_NUM_FM1, REGNUM);
-
- if (qsgmii) {
- for (i = FM1_DTSEC1; i < FM1_DTSEC1 + PORT_NUM_FM1; i++) {
- if (fm_info_get_enet_if(i) ==
- PHY_INTERFACE_MODE_SGMII) {
- phy_real_addr = PHY_BASE_ADDR + i - FM1_DTSEC1;
- fm_info_set_phy_address(i, phy_real_addr);
- }
- }
- switch (srds_prtcl) {
- case 0x00:
- case 0x03:
- case 0x04:
- case 0x06:
- case 0x11:
- case 0x2a:
- case 0x34:
- case 0x36:
- fm_info_set_phy_address(FM1_DTSEC3, PHY_BASE_ADDR + 2);
- fm_info_set_phy_address(FM1_DTSEC4, PHY_BASE_ADDR + 3);
- break;
- case 0x01:
- case 0x02:
- case 0x05:
- case 0x07:
- case 0x35:
- fm_info_set_phy_address(FM1_DTSEC3, PHY_BASE_ADDR + 0);
- fm_info_set_phy_address(FM1_DTSEC4, PHY_BASE_ADDR + 1);
- break;
- default:
- break;
- }
- }
-
- /*
- * For 10G, we only support one XAUI card per Fman. If present, then we
- * force its routing and never touch those bits again, which removes the
- * need for Linux to do any muxing. This works because of the way
- * BRDCFG1 is defined, but it's a bit hackish.
- *
- * The PHY address for the XAUI card depends on which slot it's in. The
- * macros we use imply that the PHY address is based on which FM, but
- * that's not true. On the P4080DS, FM1 could only use XAUI in slot 5,
- * and FM2 could only use a XAUI in slot 4. On the Hydra board, we
- * check the actual slot and just use the macros as-is, even though
- * the P3041 and P5020 only have one Fman.
- */
- lane = serdes_get_first_lane(XAUI_FM1);
- if (lane >= 0) {
- debug("FM1 at TGEC1 expects XAUI in slot %u\n", lane_to_slot[lane]);
- mdio_mux[i].mask = BRDCFG1_EMI2_SEL_MASK;
- mdio_mux[i].val = BRDCFG1_EMI2_SEL_SLOT2;
- super_hydra_mdio_set_mux("SUPER_HYDRA_FM1_TGEC_MDIO",
- mdio_mux[i].mask, mdio_mux[i].val);
- }
-
- fm_info_set_mdio(FM1_10GEC1,
- miiphy_get_dev_by_name("SUPER_HYDRA_FM1_TGEC_MDIO"));
-
-#if (CONFIG_SYS_NUM_FMAN == 2)
- for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
- int idx = i - FM2_DTSEC1;
-
- switch (fm_info_get_enet_if(i)) {
- case PHY_INTERFACE_MODE_SGMII:
- lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx);
- if (lane < 0)
- break;
- slot = lane_to_slot[lane];
- mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK;
- debug("FM2 at DTSEC%u expects SGMII in slot %u\n",
- idx + 1, slot);
- switch (slot) {
- case 1:
- mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT1 |
- BRDCFG1_EMI1_EN;
- break;
- case 2:
- mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT2 |
- BRDCFG1_EMI1_EN;
- break;
- case 3:
- mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT3 |
- BRDCFG1_EMI1_EN;
- break;
- case 5:
- mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT5 |
- BRDCFG1_EMI1_EN;
- break;
- case 6:
- mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT6 |
- BRDCFG1_EMI1_EN;
- break;
- case 7:
- mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT7 |
- BRDCFG1_EMI1_EN;
- break;
- };
-
- if (i == FM2_DTSEC1 || i == FM2_DTSEC2) {
- super_hydra_mdio_set_mux(
- "SUPER_HYDRA_FM3_SGMII_MDIO",
- mdio_mux[i].mask,
- mdio_mux[i].val);
- fm_info_set_mdio(i, miiphy_get_dev_by_name(
- "SUPER_HYDRA_FM3_SGMII_MDIO"));
- } else {
- super_hydra_mdio_set_mux(
- "SUPER_HYDRA_FM2_SGMII_MDIO",
- mdio_mux[i].mask,
- mdio_mux[i].val);
- fm_info_set_mdio(i, miiphy_get_dev_by_name(
- "SUPER_HYDRA_FM2_SGMII_MDIO"));
- }
-
- break;
- case PHY_INTERFACE_MODE_RGMII:
- /*
- * FM1 DTSEC5 is routed via EC1 to the first on-board
- * RGMII port. FM2 DTSEC5 is routed via EC2 to the
- * second on-board RGMII port. The other DTSECs cannot
- * be routed to RGMII.
- */
- debug("FM2 at DTSEC%u is RGMII@address %u\n",
- idx + 1, 1);
- fm_info_set_phy_address(i, 1);
- mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK;
- mdio_mux[i].val = BRDCFG1_EMI1_SEL_RGMII |
- BRDCFG1_EMI1_EN;
- super_hydra_mdio_set_mux("SUPER_HYDRA_RGMII_MDIO",
- mdio_mux[i].mask, mdio_mux[i].val);
- fm_info_set_mdio(i,
- miiphy_get_dev_by_name("SUPER_HYDRA_RGMII_MDIO"));
- break;
- case PHY_INTERFACE_MODE_NONE:
- fm_info_set_phy_address(i, 0);
- break;
- default:
- printf("Fman2: DTSEC%u set to unknown interface %i\n",
- idx + 1, fm_info_get_enet_if(i));
- fm_info_set_phy_address(i, 0);
- break;
- }
- }
-
- bus = miiphy_get_dev_by_name("SUPER_HYDRA_FM2_SGMII_MDIO");
- set_sgmii_phy(bus, FM2_DTSEC3, PORT_NUM_FM2, PHY_BASE_ADDR);
- bus = miiphy_get_dev_by_name("SUPER_HYDRA_FM3_SGMII_MDIO");
- set_sgmii_phy(bus, FM2_DTSEC1, PORT_NUM_FM2, PHY_BASE_ADDR);
-
- /*
- * For 10G, we only support one XAUI card per Fman. If present, then we
- * force its routing and never touch those bits again, which removes the
- * need for Linux to do any muxing. This works because of the way
- * BRDCFG1 is defined, but it's a bit hackish.
- *
- * The PHY address for the XAUI card depends on which slot it's in. The
- * macros we use imply that the PHY address is based on which FM, but
- * that's not true. On the P4080DS, FM1 could only use XAUI in slot 5,
- * and FM2 could only use a XAUI in slot 4. On the Hydra board, we
- * check the actual slot and just use the macros as-is, even though
- * the P3041 and P5020 only have one Fman.
- */
- lane = serdes_get_first_lane(XAUI_FM2);
- if (lane >= 0) {
- debug("FM2 at TGEC1 expects XAUI in slot %u\n", lane_to_slot[lane]);
- mdio_mux[i].mask = BRDCFG1_EMI2_SEL_MASK;
- mdio_mux[i].val = BRDCFG1_EMI2_SEL_SLOT1;
- super_hydra_mdio_set_mux("SUPER_HYDRA_FM2_TGEC_MDIO",
- mdio_mux[i].mask, mdio_mux[i].val);
- }
-
- fm_info_set_mdio(FM2_10GEC1,
- miiphy_get_dev_by_name("SUPER_HYDRA_FM2_TGEC_MDIO"));
-
-#endif
-
- cpu_eth_init(bis);
-#endif
-
- return pci_eth_init(bis);
-}
diff --git a/board/freescale/corenet_ds/p3041ds_ddr.c b/board/freescale/corenet_ds/p3041ds_ddr.c
deleted file mode 100644
index c62d85ccc0..0000000000
--- a/board/freescale/corenet_ds/p3041ds_ddr.c
+++ /dev/null
@@ -1,11 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright 2009-2010 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <fsl_ddr_sdram.h>
-
-fixed_ddr_parm_t fixed_ddr_parm_0[] = {
- {0, 0, NULL}
-};
diff --git a/board/freescale/corenet_ds/p4080ds_ddr.c b/board/freescale/corenet_ds/p4080ds_ddr.c
deleted file mode 100644
index 3469064562..0000000000
--- a/board/freescale/corenet_ds/p4080ds_ddr.c
+++ /dev/null
@@ -1,347 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright 2009-2011 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <fsl_ddr_sdram.h>
-
-#define CONFIG_SYS_DDR_TIMING_3_1200 0x01030000
-#define CONFIG_SYS_DDR_TIMING_0_1200 0xCC550104
-#define CONFIG_SYS_DDR_TIMING_1_1200 0x868FAA45
-#define CONFIG_SYS_DDR_TIMING_2_1200 0x0FB8A912
-#define CONFIG_SYS_DDR_MODE_1_1200 0x00441A40
-#define CONFIG_SYS_DDR_MODE_2_1200 0x00100000
-#define CONFIG_SYS_DDR_INTERVAL_1200 0x12480100
-#define CONFIG_SYS_DDR_CLK_CTRL_1200 0x02800000
-
-#define CONFIG_SYS_DDR_TIMING_3_1000 0x00020000
-#define CONFIG_SYS_DDR_TIMING_0_1000 0xCC440104
-#define CONFIG_SYS_DDR_TIMING_1_1000 0x727DF944
-#define CONFIG_SYS_DDR_TIMING_2_1000 0x0FB088CF
-#define CONFIG_SYS_DDR_MODE_1_1000 0x00441830
-#define CONFIG_SYS_DDR_MODE_2_1000 0x00080000
-#define CONFIG_SYS_DDR_INTERVAL_1000 0x0F3C0100
-#define CONFIG_SYS_DDR_CLK_CTRL_1000 0x02800000
-
-#define CONFIG_SYS_DDR_TIMING_3_900 0x00020000
-#define CONFIG_SYS_DDR_TIMING_0_900 0xCC440104
-#define CONFIG_SYS_DDR_TIMING_1_900 0x616ba844
-#define CONFIG_SYS_DDR_TIMING_2_900 0x0fb088ce
-#define CONFIG_SYS_DDR_MODE_1_900 0x00441620
-#define CONFIG_SYS_DDR_MODE_2_900 0x00080000
-#define CONFIG_SYS_DDR_INTERVAL_900 0x0db60100
-#define CONFIG_SYS_DDR_CLK_CTRL_900 0x02800000
-
-#define CONFIG_SYS_DDR_TIMING_3_800 0x00020000
-#define CONFIG_SYS_DDR_TIMING_0_800 0xcc330104
-#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b4744
-#define CONFIG_SYS_DDR_TIMING_2_800 0x0fa888cc
-#define CONFIG_SYS_DDR_MODE_1_800 0x00441420
-#define CONFIG_SYS_DDR_MODE_2_800 0x00000000
-#define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100
-#define CONFIG_SYS_DDR_CLK_CTRL_800 0x02800000
-
-#define CONFIG_SYS_DDR_CS0_BNDS 0x000000FF
-#define CONFIG_SYS_DDR_CS1_BNDS 0x00000000
-#define CONFIG_SYS_DDR_CS2_BNDS 0x000000FF
-#define CONFIG_SYS_DDR_CS3_BNDS 0x000000FF
-#define CONFIG_SYS_DDR2_CS0_BNDS 0x000000FF
-#define CONFIG_SYS_DDR2_CS1_BNDS 0x00000000
-#define CONFIG_SYS_DDR2_CS2_BNDS 0x000000FF
-#define CONFIG_SYS_DDR2_CS3_BNDS 0x000000FF
-#define CONFIG_SYS_DDR_CS0_CONFIG 0xA0044202
-#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
-#define CONFIG_SYS_DDR_CS1_CONFIG 0x80004202
-#define CONFIG_SYS_DDR_CS2_CONFIG 0x00000000
-#define CONFIG_SYS_DDR_CS3_CONFIG 0x00000000
-#define CONFIG_SYS_DDR2_CS0_CONFIG 0x80044202
-#define CONFIG_SYS_DDR2_CS1_CONFIG 0x80004202
-#define CONFIG_SYS_DDR2_CS2_CONFIG 0x00000000
-#define CONFIG_SYS_DDR2_CS3_CONFIG 0x00000000
-#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
-#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
-#define CONFIG_SYS_DDR_CS1_CONFIG 0x80004202
-#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
-#define CONFIG_SYS_DDR_TIMING_4 0x00000001
-#define CONFIG_SYS_DDR_TIMING_5 0x02401400
-#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
-#define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600
-#define CONFIG_SYS_DDR_WRLVL_CNTL 0x8675F607
-#define CONFIG_SYS_DDR_SDRAM_CFG 0xE7044000
-#define CONFIG_SYS_DDR_SDRAM_CFG2 0x24401031
-#define CONFIG_SYS_DDR_RCW_1 0x00000000
-#define CONFIG_SYS_DDR_RCW_2 0x00000000
-#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
-
-fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
- .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
- .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
- .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
- .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
- .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
- .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
- .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
- .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
- .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
- .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
- .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
- .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
- .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
- .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
- .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
- .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
- .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
- .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
- .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
- .ddr_data_init = CONFIG_MEM_INIT_VALUE,
- .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
- .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
- .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
- .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
- .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
- .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
- .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
- .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
- .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
-};
-
-fsl_ddr_cfg_regs_t ddr_cfg_regs_800_2nd = {
- .cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS,
- .cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS,
- .cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS,
- .cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS,
- .cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG,
- .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
- .cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG,
- .cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG,
- .cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG,
- .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
- .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
- .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
- .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
- .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
- .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
- .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
- .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
- .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
- .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
- .ddr_data_init = CONFIG_MEM_INIT_VALUE,
- .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
- .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
- .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
- .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
- .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
- .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
- .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
- .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
- .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
-};
-
-fsl_ddr_cfg_regs_t ddr_cfg_regs_900 = {
- .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
- .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
- .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
- .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
- .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
- .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
- .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
- .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
- .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
- .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_900,
- .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_900,
- .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_900,
- .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_900,
- .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
- .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
- .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_900,
- .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_900,
- .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
- .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_900,
- .ddr_data_init = CONFIG_MEM_INIT_VALUE,
- .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_900,
- .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
- .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
- .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
- .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
- .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
- .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
- .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
- .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
-};
-
-fsl_ddr_cfg_regs_t ddr_cfg_regs_900_2nd = {
- .cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS,
- .cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS,
- .cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS,
- .cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS,
- .cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG,
- .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
- .cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG,
- .cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG,
- .cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG,
- .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_900,
- .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_900,
- .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_900,
- .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_900,
- .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
- .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
- .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_900,
- .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_900,
- .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
- .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_900,
- .ddr_data_init = CONFIG_MEM_INIT_VALUE,
- .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_900,
- .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
- .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
- .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
- .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
- .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
- .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
- .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
- .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
-};
-
-fsl_ddr_cfg_regs_t ddr_cfg_regs_1000 = {
- .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
- .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
- .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
- .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
- .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
- .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
- .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
- .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
- .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
- .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1000,
- .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1000,
- .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1000,
- .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1000,
- .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
- .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
- .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1000,
- .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1000,
- .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
- .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1000,
- .ddr_data_init = CONFIG_MEM_INIT_VALUE,
- .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1000,
- .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
- .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
- .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
- .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
- .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
- .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
- .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
- .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
-};
-
-fsl_ddr_cfg_regs_t ddr_cfg_regs_1000_2nd = {
- .cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS,
- .cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS,
- .cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS,
- .cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS,
- .cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG,
- .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
- .cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG,
- .cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG,
- .cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG,
- .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1000,
- .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1000,
- .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1000,
- .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1000,
- .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
- .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
- .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1000,
- .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1000,
- .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
- .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1000,
- .ddr_data_init = CONFIG_MEM_INIT_VALUE,
- .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1000,
- .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
- .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
- .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
- .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
- .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
- .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
- .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
- .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
-};
-
-fsl_ddr_cfg_regs_t ddr_cfg_regs_1200 = {
- .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
- .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
- .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
- .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
- .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
- .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
- .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
- .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
- .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
- .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1200,
- .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1200,
- .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1200,
- .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1200,
- .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
- .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
- .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1200,
- .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1200,
- .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
- .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1200,
- .ddr_data_init = CONFIG_MEM_INIT_VALUE,
- .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1200,
- .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
- .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
- .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
- .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
- .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
- .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
- .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
- .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
-};
-
-fsl_ddr_cfg_regs_t ddr_cfg_regs_1200_2nd = {
- .cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS,
- .cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS,
- .cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS,
- .cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS,
- .cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG,
- .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
- .cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG,
- .cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG,
- .cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG,
- .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1200,
- .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1200,
- .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1200,
- .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1200,
- .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
- .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
- .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1200,
- .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1200,
- .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
- .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1200,
- .ddr_data_init = CONFIG_MEM_INIT_VALUE,
- .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1200,
- .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
- .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
- .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
- .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
- .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
- .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
- .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
- .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
-};
-
-fixed_ddr_parm_t fixed_ddr_parm_0[] = {
- {750, 850, &ddr_cfg_regs_800},
- {850, 950, &ddr_cfg_regs_900},
- {950, 1050, &ddr_cfg_regs_1000},
- {1050, 1250, &ddr_cfg_regs_1200},
- {0, 0, NULL}
-};
-
-fixed_ddr_parm_t fixed_ddr_parm_1[] = {
- {750, 850, &ddr_cfg_regs_800_2nd},
- {850, 950, &ddr_cfg_regs_900_2nd},
- {950, 1050, &ddr_cfg_regs_1000_2nd},
- {1050, 1250, &ddr_cfg_regs_1200_2nd},
- {0, 0, NULL}
-};
diff --git a/board/freescale/corenet_ds/p5020ds_ddr.c b/board/freescale/corenet_ds/p5020ds_ddr.c
deleted file mode 100644
index 112733be78..0000000000
--- a/board/freescale/corenet_ds/p5020ds_ddr.c
+++ /dev/null
@@ -1,15 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright 2009-2010 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <fsl_ddr_sdram.h>
-
-fixed_ddr_parm_t fixed_ddr_parm_0[] = {
- {0, 0, NULL}
-};
-
-fixed_ddr_parm_t fixed_ddr_parm_1[] = {
- {0, 0, NULL}
-};
diff --git a/board/freescale/corenet_ds/p5040ds_ddr.c b/board/freescale/corenet_ds/p5040ds_ddr.c
deleted file mode 100644
index 112733be78..0000000000
--- a/board/freescale/corenet_ds/p5040ds_ddr.c
+++ /dev/null
@@ -1,15 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright 2009-2010 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <fsl_ddr_sdram.h>
-
-fixed_ddr_parm_t fixed_ddr_parm_0[] = {
- {0, 0, NULL}
-};
-
-fixed_ddr_parm_t fixed_ddr_parm_1[] = {
- {0, 0, NULL}
-};
diff --git a/board/freescale/corenet_ds/pbi.cfg b/board/freescale/corenet_ds/pbi.cfg
deleted file mode 100644
index 75dfc32162..0000000000
--- a/board/freescale/corenet_ds/pbi.cfg
+++ /dev/null
@@ -1,33 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2012 Freescale Semiconductor, Inc.
-# Refer doc/README.pblimage for more details about how-to configure
-# and create PBL boot image
-#
-
-#PBI commands
-#Initialize CPC1 as 1MB SRAM
-09010000 00200400
-09138000 00000000
-091380c0 00000100
-09010100 00000000
-09010104 fff0000b
-09010f00 08000000
-09010000 80000000
-#Configure LAW for CPC1
-09000d00 00000000
-09000d04 fff00000
-09000d08 81000013
-09000010 00000000
-09000014 ff000000
-09000018 81000000
-#Initialize eSPI controller, default configuration is slow for eSPI to
-#load data, this configuration comes from u-boot eSPI driver.
-09110000 80000403
-09110020 2d170008
-09110024 00100008
-09110028 00100008
-0911002c 00100008
-#Flush PBL data
-09138000 00000000
-091380c0 00000000
diff --git a/board/freescale/corenet_ds/rcw_p2041rdb.cfg b/board/freescale/corenet_ds/rcw_p2041rdb.cfg
deleted file mode 100644
index 8df19dd3fe..0000000000
--- a/board/freescale/corenet_ds/rcw_p2041rdb.cfg
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Default RCW for P2041RDB.
-#
-
-#PBL preamble and RCW header
-aa55aa55 010e0100
-#64 bytes RCW data
-12600000 00000000 241C0000 00000000
-649FA0C1 C3C02000 58000000 40000000
-00000000 00000000 00000000 D0030F07
-00000000 00000000 00000000 00000000
diff --git a/board/freescale/corenet_ds/rcw_p3041ds.cfg b/board/freescale/corenet_ds/rcw_p3041ds.cfg
deleted file mode 100644
index 8813156219..0000000000
--- a/board/freescale/corenet_ds/rcw_p3041ds.cfg
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Default RCW for P3041DS.
-#
-
-#PBL preamble and RCW header
-aa55aa55 010e0100
-#64 bytes RCW data
-12600000 00000000 241C0000 00000000
-D8984A01 03002000 58000000 41000000
-00000000 00000000 00000000 10070000
-00000000 00000000 00000000 00000000
diff --git a/board/freescale/corenet_ds/rcw_p4080ds.cfg b/board/freescale/corenet_ds/rcw_p4080ds.cfg
deleted file mode 100644
index 6a26339599..0000000000
--- a/board/freescale/corenet_ds/rcw_p4080ds.cfg
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Default RCW for P4080DS.
-#
-
-#PBL preamble and RCW header
-aa55aa55 010e0100
-#64 bytes RCW data
-105a0000 00000000 1e1e181e 0000cccc
-58400000 3c3c2000 58000000 e1000000
-00000000 00000000 00000000 008b6000
-00000000 00000000 00000000 00000000
diff --git a/board/freescale/corenet_ds/rcw_p5020ds.cfg b/board/freescale/corenet_ds/rcw_p5020ds.cfg
deleted file mode 100644
index b09e409bbf..0000000000
--- a/board/freescale/corenet_ds/rcw_p5020ds.cfg
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Default RCW for P5020DS.
-#
-
-#PBL preamble and RCW header
-aa55aa55 010e0100
-#64 bytes RCW data
-0C540000 00000000 1E120000 00000000
-D8984A01 03002000 58000000 41000000
-00000000 00000000 00000000 10070000
-00000000 00000000 00000000 00000000
diff --git a/board/freescale/corenet_ds/rcw_p5040ds.cfg b/board/freescale/corenet_ds/rcw_p5040ds.cfg
deleted file mode 100644
index 82fa7417d9..0000000000
--- a/board/freescale/corenet_ds/rcw_p5040ds.cfg
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Default RCW for P5040DS.
-#
-
-#PBL preamble and RCW header
-aa55aa55 010e0100
-#64 bytes RCW data
-0c580000 00000000 22121200 00000000
-089c4400 00283000 58000000 61000000
-00000000 00000000 00000000 10070000
-00000000 00000000 00000000 00000000
diff --git a/configs/P3041DS_NAND_SECURE_BOOT_defconfig b/configs/P3041DS_NAND_SECURE_BOOT_defconfig
deleted file mode 100644
index 8ab25373c9..0000000000
--- a/configs/P3041DS_NAND_SECURE_BOOT_defconfig
+++ /dev/null
@@ -1,59 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFFF40000
-CONFIG_ENV_SIZE=0x20000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P3041DS=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P3041DS_NAND_defconfig b/configs/P3041DS_NAND_defconfig
deleted file mode 100644
index 55613ccacd..0000000000
--- a/configs/P3041DS_NAND_defconfig
+++ /dev/null
@@ -1,64 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFFF40000
-CONFIG_ENV_SIZE=0x20000
-CONFIG_ENV_OFFSET=0xE0000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P3041DS=y
-CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="p3041ds"
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
diff --git a/configs/P3041DS_SDCARD_defconfig b/configs/P3041DS_SDCARD_defconfig
deleted file mode 100644
index b52068d050..0000000000
--- a/configs/P3041DS_SDCARD_defconfig
+++ /dev/null
@@ -1,63 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0xCF400
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P3041DS=y
-CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="p3041ds"
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
diff --git a/configs/P3041DS_SECURE_BOOT_defconfig b/configs/P3041DS_SECURE_BOOT_defconfig
deleted file mode 100644
index d6cabebeb7..0000000000
--- a/configs/P3041DS_SECURE_BOOT_defconfig
+++ /dev/null
@@ -1,57 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P3041DS=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P3041DS_SPIFLASH_defconfig b/configs/P3041DS_SPIFLASH_defconfig
deleted file mode 100644
index 3af52b90e8..0000000000
--- a/configs/P3041DS_SPIFLASH_defconfig
+++ /dev/null
@@ -1,64 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P3041DS=y
-CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="p3041ds"
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
diff --git a/configs/P3041DS_SRIO_PCIE_BOOT_defconfig b/configs/P3041DS_SRIO_PCIE_BOOT_defconfig
deleted file mode 100644
index c34311b2f9..0000000000
--- a/configs/P3041DS_SRIO_PCIE_BOOT_defconfig
+++ /dev/null
@@ -1,50 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P3041DS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_GREPENV=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_IS_IN_REMOTE=y
-CONFIG_ENV_ADDR=0xFFE20000
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_REMOTE=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P3041DS_defconfig b/configs/P3041DS_defconfig
deleted file mode 100644
index cc3234c6b1..0000000000
--- a/configs/P3041DS_defconfig
+++ /dev/null
@@ -1,62 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P3041DS=y
-CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="p3041ds"
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
diff --git a/configs/P4080DS_SDCARD_defconfig b/configs/P4080DS_SDCARD_defconfig
deleted file mode 100644
index 18ad56ac8d..0000000000
--- a/configs/P4080DS_SDCARD_defconfig
+++ /dev/null
@@ -1,62 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0xCF400
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P4080DS=y
-CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="p4080ds"
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
diff --git a/configs/P4080DS_SECURE_BOOT_defconfig b/configs/P4080DS_SECURE_BOOT_defconfig
deleted file mode 100644
index 22a6ebe89c..0000000000
--- a/configs/P4080DS_SECURE_BOOT_defconfig
+++ /dev/null
@@ -1,56 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P4080DS=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P4080DS_SPIFLASH_defconfig b/configs/P4080DS_SPIFLASH_defconfig
deleted file mode 100644
index 81a513bec9..0000000000
--- a/configs/P4080DS_SPIFLASH_defconfig
+++ /dev/null
@@ -1,63 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P4080DS=y
-CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="p4080ds"
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
diff --git a/configs/P4080DS_SRIO_PCIE_BOOT_defconfig b/configs/P4080DS_SRIO_PCIE_BOOT_defconfig
deleted file mode 100644
index a740bc4a7b..0000000000
--- a/configs/P4080DS_SRIO_PCIE_BOOT_defconfig
+++ /dev/null
@@ -1,48 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P4080DS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_IS_IN_REMOTE=y
-CONFIG_ENV_ADDR=0xFFE20000
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_REMOTE=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P4080DS_defconfig b/configs/P4080DS_defconfig
deleted file mode 100644
index 52db2e06c7..0000000000
--- a/configs/P4080DS_defconfig
+++ /dev/null
@@ -1,61 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P4080DS=y
-CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="p4080ds"
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
diff --git a/configs/P5020DS_NAND_SECURE_BOOT_defconfig b/configs/P5020DS_NAND_SECURE_BOOT_defconfig
deleted file mode 100644
index 52efa92009..0000000000
--- a/configs/P5020DS_NAND_SECURE_BOOT_defconfig
+++ /dev/null
@@ -1,60 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFFF40000
-CONFIG_ENV_SIZE=0x20000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P5020DS=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P5020DS_NAND_defconfig b/configs/P5020DS_NAND_defconfig
deleted file mode 100644
index baf7d835bc..0000000000
--- a/configs/P5020DS_NAND_defconfig
+++ /dev/null
@@ -1,57 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFFF40000
-CONFIG_ENV_SIZE=0x20000
-CONFIG_ENV_OFFSET=0xE0000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P5020DS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P5020DS_SDCARD_defconfig b/configs/P5020DS_SDCARD_defconfig
deleted file mode 100644
index c5b424145c..0000000000
--- a/configs/P5020DS_SDCARD_defconfig
+++ /dev/null
@@ -1,55 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0xCF400
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P5020DS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P5020DS_SECURE_BOOT_defconfig b/configs/P5020DS_SECURE_BOOT_defconfig
deleted file mode 100644
index c08f9fffa6..0000000000
--- a/configs/P5020DS_SECURE_BOOT_defconfig
+++ /dev/null
@@ -1,57 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P5020DS=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P5020DS_SPIFLASH_defconfig b/configs/P5020DS_SPIFLASH_defconfig
deleted file mode 100644
index 03d7a16a6d..0000000000
--- a/configs/P5020DS_SPIFLASH_defconfig
+++ /dev/null
@@ -1,56 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P5020DS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P5020DS_SRIO_PCIE_BOOT_defconfig b/configs/P5020DS_SRIO_PCIE_BOOT_defconfig
deleted file mode 100644
index 7569364252..0000000000
--- a/configs/P5020DS_SRIO_PCIE_BOOT_defconfig
+++ /dev/null
@@ -1,50 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P5020DS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_GREPENV=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_IS_IN_REMOTE=y
-CONFIG_ENV_ADDR=0xFFE20000
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_REMOTE=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P5020DS_defconfig b/configs/P5020DS_defconfig
deleted file mode 100644
index a1b410c7b6..0000000000
--- a/configs/P5020DS_defconfig
+++ /dev/null
@@ -1,54 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P5020DS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P5040DS_NAND_SECURE_BOOT_defconfig b/configs/P5040DS_NAND_SECURE_BOOT_defconfig
deleted file mode 100644
index beab855eae..0000000000
--- a/configs/P5040DS_NAND_SECURE_BOOT_defconfig
+++ /dev/null
@@ -1,60 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFFF40000
-CONFIG_ENV_SIZE=0x20000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P5040DS=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P5040DS_NAND_defconfig b/configs/P5040DS_NAND_defconfig
deleted file mode 100644
index efffb706fb..0000000000
--- a/configs/P5040DS_NAND_defconfig
+++ /dev/null
@@ -1,65 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFFF40000
-CONFIG_ENV_SIZE=0x20000
-CONFIG_ENV_OFFSET=0xE0000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P5040DS=y
-CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="p5040ds"
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
diff --git a/configs/P5040DS_SDCARD_defconfig b/configs/P5040DS_SDCARD_defconfig
deleted file mode 100644
index fdd39acbaf..0000000000
--- a/configs/P5040DS_SDCARD_defconfig
+++ /dev/null
@@ -1,63 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0xCF400
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P5040DS=y
-CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="p5040ds"
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
diff --git a/configs/P5040DS_SECURE_BOOT_defconfig b/configs/P5040DS_SECURE_BOOT_defconfig
deleted file mode 100644
index 5d48206dc8..0000000000
--- a/configs/P5040DS_SECURE_BOOT_defconfig
+++ /dev/null
@@ -1,57 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P5040DS=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P5040DS_SPIFLASH_defconfig b/configs/P5040DS_SPIFLASH_defconfig
deleted file mode 100644
index 3f4642f4e0..0000000000
--- a/configs/P5040DS_SPIFLASH_defconfig
+++ /dev/null
@@ -1,64 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P5040DS=y
-CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="p5040ds"
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
diff --git a/configs/P5040DS_defconfig b/configs/P5040DS_defconfig
deleted file mode 100644
index d2a2e02dcd..0000000000
--- a/configs/P5040DS_defconfig
+++ /dev/null
@@ -1,62 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P5040DS=y
-CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="p5040ds"
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
diff --git a/include/configs/P3041DS.h b/include/configs/P3041DS.h
deleted file mode 100644
index 2f6cc5d8e1..0000000000
--- a/include/configs/P3041DS.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2010-2011 Freescale Semiconductor, Inc.
- */
-
-/*
- * P3041 DS board configuration file
- *
- */
-#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */
-
-#define CONFIG_NAND_FSL_ELBC
-#define CONFIG_FSL_SATA_V2
-#define CONFIG_PCIE3
-#define CONFIG_PCIE4
-#define CONFIG_SYS_DPAA_RMAN
-
-#define CONFIG_SYS_SRIO
-#define CONFIG_SRIO1 /* SRIO port 1 */
-#define CONFIG_SRIO2 /* SRIO port 2 */
-#define CONFIG_SRIO_PCIE_BOOT_MASTER
-#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
-
-#include "corenet_ds.h"
diff --git a/include/configs/P4080DS.h b/include/configs/P4080DS.h
deleted file mode 100644
index ed88b41844..0000000000
--- a/include/configs/P4080DS.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2009-2011 Freescale Semiconductor, Inc.
- */
-
-/*
- * P4080 DS board configuration file
- * Also supports P4040 DS
- */
-#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */
-
-#define CONFIG_PCIE3
-
-#define CONFIG_SYS_SATA_MAX_DEVICE 2
-#define CONFIG_LBA48
-
-#define CONFIG_SYS_SRIO
-#define CONFIG_SRIO1 /* SRIO port 1 */
-#define CONFIG_SRIO2 /* SRIO port 2 */
-#define CONFIG_SRIO_PCIE_BOOT_MASTER
-#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 ref clk freq */
-
-#include "corenet_ds.h"
diff --git a/include/configs/P5020DS.h b/include/configs/P5020DS.h
deleted file mode 100644
index 873d39a10c..0000000000
--- a/include/configs/P5020DS.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2009-2011 Freescale Semiconductor, Inc.
- */
-
-/*
- * P5020 DS board configuration file
- * Also supports P5010 DS
- */
-#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */
-
-#define CONFIG_NAND_FSL_ELBC
-#define CONFIG_FSL_SATA_V2
-#define CONFIG_PCIE3
-#define CONFIG_PCIE4
-#define CONFIG_SYS_FSL_RAID_ENGINE
-#define CONFIG_SYS_DPAA_RMAN
-
-#define CONFIG_SYS_SRIO
-#define CONFIG_SRIO1 /* SRIO port 1 */
-#define CONFIG_SRIO2 /* SRIO port 2 */
-#define CONFIG_SRIO_PCIE_BOOT_MASTER
-#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
-
-#include "corenet_ds.h"
diff --git a/include/configs/P5040DS.h b/include/configs/P5040DS.h
deleted file mode 100644
index 12666d6ee6..0000000000
--- a/include/configs/P5040DS.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2009-2011 Freescale Semiconductor, Inc.
- */
-
-/*
- * P5040 DS board configuration file
- *
- */
-#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */
-
-#define CONFIG_NAND_FSL_ELBC
-#define CONFIG_PCIE3
-#define CONFIG_FSL_SATA_V2
-#define CONFIG_SYS_FSL_RAID_ENGINE
-
-#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
-
-#include "corenet_ds.h"
--
2.25.1
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 12/24] arm: Remove configs/T1023RDB_NAND_defconfig board
2020-05-27 16:46 [PATCH 00/24] spi: dm-conversion (part2) Jagan Teki
` (10 preceding siblings ...)
2020-05-27 16:46 ` [PATCH 11/24] arm: Remove configs/P3041DS_NAND_SECURE_BOOT_defconfig board Jagan Teki
@ 2020-05-27 16:46 ` Jagan Teki
2020-05-28 7:08 ` Priyanka Jain
2020-05-27 16:46 ` [PATCH 13/24] arm: Remove configs/T1024QDS_DDR4_SECURE_BOOT_defconfig board Jagan Teki
` (10 subsequent siblings)
22 siblings, 1 reply; 59+ messages in thread
From: Jagan Teki @ 2020-05-27 16:46 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_SPI by the deadline.
Remove it.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
arch/powerpc/cpu/mpc85xx/Kconfig | 1 -
board/freescale/t102xrdb/Kconfig | 14 -
board/freescale/t102xrdb/MAINTAINERS | 15 -
board/freescale/t102xrdb/Makefile | 17 -
board/freescale/t102xrdb/README | 340 ---------
board/freescale/t102xrdb/cpld.c | 102 ---
board/freescale/t102xrdb/cpld.h | 48 --
board/freescale/t102xrdb/ddr.c | 257 -------
board/freescale/t102xrdb/eth_t102xrdb.c | 146 ----
board/freescale/t102xrdb/law.c | 31 -
board/freescale/t102xrdb/pci.c | 25 -
board/freescale/t102xrdb/spl.c | 143 ----
board/freescale/t102xrdb/t1023_nand_rcw.cfg | 8 -
board/freescale/t102xrdb/t1023_sd_rcw.cfg | 8 -
board/freescale/t102xrdb/t1023_spi_rcw.cfg | 8 -
board/freescale/t102xrdb/t1024_nand_rcw.cfg | 8 -
board/freescale/t102xrdb/t1024_pbi.cfg | 26 -
board/freescale/t102xrdb/t1024_sd_rcw.cfg | 8 -
board/freescale/t102xrdb/t1024_spi_rcw.cfg | 8 -
board/freescale/t102xrdb/t102xrdb.c | 394 -----------
board/freescale/t102xrdb/t102xrdb.h | 15 -
board/freescale/t102xrdb/tlb.c | 116 ----
configs/T1023RDB_NAND_defconfig | 77 ---
configs/T1023RDB_SDCARD_defconfig | 74 --
configs/T1023RDB_SECURE_BOOT_defconfig | 64 --
configs/T1023RDB_SPIFLASH_defconfig | 77 ---
configs/T1023RDB_defconfig | 61 --
configs/T1024RDB_NAND_defconfig | 86 ---
configs/T1024RDB_SDCARD_defconfig | 83 ---
configs/T1024RDB_SECURE_BOOT_defconfig | 66 --
configs/T1024RDB_SPIFLASH_defconfig | 86 ---
configs/T1024RDB_defconfig | 71 --
include/configs/T102xRDB.h | 721 --------------------
33 files changed, 3204 deletions(-)
delete mode 100644 board/freescale/t102xrdb/Kconfig
delete mode 100644 board/freescale/t102xrdb/MAINTAINERS
delete mode 100644 board/freescale/t102xrdb/Makefile
delete mode 100644 board/freescale/t102xrdb/README
delete mode 100644 board/freescale/t102xrdb/cpld.c
delete mode 100644 board/freescale/t102xrdb/cpld.h
delete mode 100644 board/freescale/t102xrdb/ddr.c
delete mode 100644 board/freescale/t102xrdb/eth_t102xrdb.c
delete mode 100644 board/freescale/t102xrdb/law.c
delete mode 100644 board/freescale/t102xrdb/pci.c
delete mode 100644 board/freescale/t102xrdb/spl.c
delete mode 100644 board/freescale/t102xrdb/t1023_nand_rcw.cfg
delete mode 100644 board/freescale/t102xrdb/t1023_sd_rcw.cfg
delete mode 100644 board/freescale/t102xrdb/t1023_spi_rcw.cfg
delete mode 100644 board/freescale/t102xrdb/t1024_nand_rcw.cfg
delete mode 100644 board/freescale/t102xrdb/t1024_pbi.cfg
delete mode 100644 board/freescale/t102xrdb/t1024_sd_rcw.cfg
delete mode 100644 board/freescale/t102xrdb/t1024_spi_rcw.cfg
delete mode 100644 board/freescale/t102xrdb/t102xrdb.c
delete mode 100644 board/freescale/t102xrdb/t102xrdb.h
delete mode 100644 board/freescale/t102xrdb/tlb.c
delete mode 100644 configs/T1023RDB_NAND_defconfig
delete mode 100644 configs/T1023RDB_SDCARD_defconfig
delete mode 100644 configs/T1023RDB_SECURE_BOOT_defconfig
delete mode 100644 configs/T1023RDB_SPIFLASH_defconfig
delete mode 100644 configs/T1023RDB_defconfig
delete mode 100644 configs/T1024RDB_NAND_defconfig
delete mode 100644 configs/T1024RDB_SDCARD_defconfig
delete mode 100644 configs/T1024RDB_SECURE_BOOT_defconfig
delete mode 100644 configs/T1024RDB_SPIFLASH_defconfig
delete mode 100644 configs/T1024RDB_defconfig
delete mode 100644 include/configs/T102xRDB.h
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 1511691974..deffa831dc 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -1600,7 +1600,6 @@ source "board/freescale/p1023rdb/Kconfig"
source "board/freescale/p1_twr/Kconfig"
source "board/freescale/qemu-ppce500/Kconfig"
source "board/freescale/t102xqds/Kconfig"
-source "board/freescale/t102xrdb/Kconfig"
source "board/freescale/t1040qds/Kconfig"
source "board/freescale/t104xrdb/Kconfig"
source "board/freescale/t208xqds/Kconfig"
diff --git a/board/freescale/t102xrdb/Kconfig b/board/freescale/t102xrdb/Kconfig
deleted file mode 100644
index 6deeb248a3..0000000000
--- a/board/freescale/t102xrdb/Kconfig
+++ /dev/null
@@ -1,14 +0,0 @@
-if TARGET_T1023RDB || TARGET_T1024RDB
-
-config SYS_BOARD
- default "t102xrdb"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "T102xRDB"
-
-source "board/freescale/common/Kconfig"
-
-endif
diff --git a/board/freescale/t102xrdb/MAINTAINERS b/board/freescale/t102xrdb/MAINTAINERS
deleted file mode 100644
index 6c24f7785c..0000000000
--- a/board/freescale/t102xrdb/MAINTAINERS
+++ /dev/null
@@ -1,15 +0,0 @@
-T102XRDB BOARD
-#M: Shengzhou Liu <Shengzhou.Liu@freescale.com>
-S: Orphan (since 2018-05)
-F: board/freescale/t102xrdb/
-F: include/configs/T102xRDB.h
-F: configs/T1024RDB_defconfig
-F: configs/T1024RDB_NAND_defconfig
-F: configs/T1024RDB_SDCARD_defconfig
-F: configs/T1024RDB_SPIFLASH_defconfig
-F: configs/T1024RDB_SECURE_BOOT_defconfig
-F: configs/T1023RDB_defconfig
-F: configs/T1023RDB_NAND_defconfig
-F: configs/T1023RDB_SDCARD_defconfig
-F: configs/T1023RDB_SPIFLASH_defconfig
-F: configs/T1023RDB_SECURE_BOOT_defconfig
diff --git a/board/freescale/t102xrdb/Makefile b/board/freescale/t102xrdb/Makefile
deleted file mode 100644
index ddeb44f36e..0000000000
--- a/board/freescale/t102xrdb/Makefile
+++ /dev/null
@@ -1,17 +0,0 @@
-#
-# Copyright 2014 Freescale Semiconductor, Inc.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-ifdef CONFIG_SPL_BUILD
-obj-y += spl.o
-else
-obj-y += t102xrdb.o
-obj-$(CONFIG_TARGET_T1024RDB) += cpld.o
-obj-y += eth_t102xrdb.o
-obj-$(CONFIG_PCI) += pci.o
-endif
-obj-y += ddr.o
-obj-y += law.o
-obj-y += tlb.o
diff --git a/board/freescale/t102xrdb/README b/board/freescale/t102xrdb/README
deleted file mode 100644
index dde3f8ca37..0000000000
--- a/board/freescale/t102xrdb/README
+++ /dev/null
@@ -1,340 +0,0 @@
-T1024 SoC Overview
-------------------
-The T1024/T1023 dual core and T1014/T1013 single core QorIQ communication processor
-combines two or one 64-bit Power Architecture e5500 core respectively with high
-performance datapath acceleration logic, and network peripheral bus interfaces
-required for networking and telecommunications. This processor can be used in
-applications such as enterprise WLAN access points, routers, switches, firewall
-and other packet processing intensive small enterprise and branch office appliances,
-and general-purpose embedded computing. Its high level of integration offers
-significant performance benefits and greatly helps to simplify board design.
-
-
-The T1024 SoC includes the following function and features:
-- two e5500 cores, each with a private 256 KB L2 cache
- - Up to 1.4 GHz with 64-bit ISA support (Power Architecture v2.06-compliant)
- - Three levels of instructions: User, supervisor, and hypervisor
- - Independent boot and reset
- - Secure boot capability
-- 256 KB shared L3 CoreNet platform cache (CPC)
-- Interconnect CoreNet platform
- - CoreNet coherency manager supporting coherent and noncoherent transactions
- with prioritization and bandwidth allocation amongst CoreNet endpoints
- - 150 Gbps coherent read bandwidth
-- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support
-- Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions:
- - Packet parsing, classification, and distribution
- - Queue management for scheduling, packet sequencing, and congestion management
- - Cryptography Acceleration (SEC 5.x)
- - IEEE 1588 support
- - Hardware buffer management for buffer allocation and deallocation
- - MACSEC on DPAA-based Ethernet ports
-- Ethernet interfaces
- - Four 1 Gbps Ethernet controllers
-- Parallel Ethernet interfaces
- - Two RGMII interfaces
-- High speed peripheral interfaces
- - Three PCI Express 2.0 controllers/ports running at up to 5 GHz
- - One SATA controller supporting 1.5 and 3.0 Gb/s operation
- - One QSGMII interface
- - Four SGMII interface supporting 1000 Mbps
- - Three SGMII interfaces supporting up to 2500 Mbps
- - 10GbE XFI or 10Base-KR interface
-- Additional peripheral interfaces
- - Two USB 2.0 controllers with integrated PHY
- - SD/eSDHC/eMMC
- - eSPI controller
- - Four I2C controllers
- - Four UARTs
- - Four GPIO controllers
- - Integrated flash controller (IFC)
- - LCD interface (DIU) with 12 bit dual data rate
-- Multicore programmable interrupt controller (PIC)
-- Two 8-channel DMA engines
-- Single source clocking implementation
-- Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
-- QUICC Engine block
- - 32-bit RISC controller for flexible support of the communications peripherals
- - Serial DMA channel for receive and transmit on all serial channels
- - Two universal communication controllers, supporting TDM, HDLC, and UART
-
-T1023 Personality
-------------------
-T1023 is a reduced personality of T1024 without QUICC Engine, DIU, and
-unavailable deep sleep. Rest of the blocks are almost same as T1024.
-Differences between T1024 and T1023
-Feature T1024 T1023
-QUICC Engine: yes no
-DIU: yes no
-Deep Sleep: yes no
-I2C controller: 4 3
-DDR: 64-bit 32-bit
-IFC: 32-bit 28-bit
-Package: 23x23 19x19
-
-
-T1024RDB board Overview
------------------------
- - Ethernet
- - Two on-board 10M/100M/1G bps RGMII ethernet ports
- - One on-board 10G bps Base-T port.
- - DDR Memory
- - Supports 64-bit 4GB DDR3L DIMM
- - PCIe
- - One on-board PCIe slot.
- - Two on-board PCIe Mini-PCIe connectors.
- - IFC/Local Bus
- - NOR: 128MB 16-bit NOR Flash
- - NAND: 1GB 8-bit NAND flash
- - CPLD: for system controlling with programable header on-board
- - USB
- - Supports two USB 2.0 ports with integrated PHYs
- - Two type A ports with 5V at 1.5A per port.
- - SDHC
- - one SD connector supporting 1.8V/3.3V via J53.
- - SPI
- - On-board 64MB SPI flash
- - Other
- - Two Serial ports
- - Four I2C ports
-
-
-T1023RDB board Overview
------------------------
-- T1023 SoC integrating two 64-bit e5500 cores up to 1.4GHz
-- CoreNet fabric supporting coherent and noncoherent transactions with
- prioritization and bandwidth allocation
-- SDRAM memory: 2GB Micron MT40A512M8HX unbuffered 32-bit DDR4 w/o ECC
-- Accelerator: DPAA components consist of FMan, BMan, QMan, DCE and SEC
-- Ethernet interfaces:
- - one 1G RGMII port on-board(RTL8211FS PHY)
- - one 1G SGMII port on-board(RTL8211FS PHY)
- - one 2.5G SGMII port on-board(AQR105 PHY)
-- PCIe: Two Mini-PCIe connectors on-board.
-- SerDes: 4 lanes up to 10.3125GHz
-- NOR: 128MB S29GL01GS110TFIV10 Spansion NOR Flash
-- NAND: 512MB S34MS04G200BFI000 Spansion NAND Flash
-- eSPI: 64MB S25FL512SAGMFI010 Spansion SPI flash.
-- USB: one Type-A USB 2.0 port with internal PHY
-- eSDHC: support SD/MMC and eMMC card
-- 256Kbit M24256 I2C EEPROM
-- RTC: Real-time clock DS1339U on I2C bus
-- UART: one serial port on-board with RJ45 connector
-- Debugging: JTAG/COP for T1023 debugging
-
-
-Memory map on T1024RDB
-----------------------
-Start Address End Address Description Size
-0xF_FFDF_0000 0xF_FFDF_0FFF IFC - CPLD 4KB
-0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB
-0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB
-0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB
-0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB
-0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB
-0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB
-0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB
-0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB
-0xF_0000_0000 0xF_003F_FFFF DCSR 4MB
-0xC_2000_0000 0xC_2FFF_FFFF PCI Express 3 Mem Space 256MB
-0xC_1000_0000 0xC_1FFF_FFFF PCI Express 2 Mem Space 256MB
-0xC_0000_0000 0xC_0FFF_FFFF PCI Express 1 Mem Space 256MB
-0x0_0000_0000 0x0_ffff_ffff DDR 4GB
-
-
-128MB NOR Flash Memory Layout
------------------------------
-Start Address End Address Definition Max size
-0xEFF40000 0xEFFFFFFF U-Boot (current bank) 768KB
-0xEFF20000 0xEFF3FFFF U-Boot env (current bank) 128KB
-0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB
-0xEFE00000 0xEFE3FFFF QE firmware (current bank) 256KB
-0xED300000 0xEFDFFFFF rootfs (alt bank) 44MB
-0xED000000 0xED2FFFFF Guest image #3 (alternate bank) 3MB
-0xECD00000 0xECFFFFFF Guest image #2 (alternate bank) 3MB
-0xECA00000 0xECCFFFFF Guest image #1 (alternate bank) 3MB
-0xEC900000 0xEC9FFFFF HV config device tree(alt bank) 1MB
-0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB
-0xEC700000 0xEC7FFFFF HV.uImage (alternate bank) 1MB
-0xEC020000 0xEC6FFFFF Linux.uImage (alt bank) ~7MB
-0xEC000000 0xEC01FFFF RCW (alt bank) 128KB
-0xEBF40000 0xEBFFFFFF U-Boot (alt bank) 768KB
-0xEBF20000 0xEBF3FFFF U-Boot env (alt bank) 128KB
-0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB
-0xEBE00000 0xEBE3FFFF QE firmware (alt bank) 256KB
-0xE9300000 0xEBDFFFFF rootfs (current bank) 44MB
-0xE9000000 0xE92FFFFF Guest image #3 (current bank) 3MB
-0xE8D00000 0xE8FFFFFF Guest image #2 (current bank) 3MB
-0xE8A00000 0xE8CFFFFF Guest image #1 (current bank) 3MB
-0xE8900000 0xE89FFFFF HV config device tree(cur bank) 1MB
-0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 1MB
-0xE8700000 0xE87FFFFF HV.uImage (current bank) 1MB
-0xE8020000 0xE86FFFFF Linux.uImage (current bank) ~7MB
-0xE8000000 0xE801FFFF RCW (current bank) 128KB
-
-
-T1024/T1023 Clock frequency
----------------------------
-BIN Core DDR Platform FMan
-Bin1: 1400MHz 1600MT/s 400MHz 700MHz
-Bin2: 1200MHz 1600MT/s 400MHz 600MHz
-Bin3: 1000MHz 1600MT/s 400MHz 500MHz
-
-
-Software configurations and board settings
-------------------------------------------
-1. NOR boot:
- a. build NOR boot image
- $ make T1024RDB_defconfig
- $ make
- b. program u-boot.bin image to NOR flash
- => tftp 1000000 u-boot.bin
- => pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize
- on T1024RDB:
- set SW1[1:8] = '00010011', SW2[1] = '1', SW3[4] = '0' for NOR boot
- on T1023RDB:
- set SW1[1:8] = '00010111', SW2[1] = '1', SW3[4] = '0' for NOR boot
-
- Switching between default bank0 and alternate bank4 on NOR flash
- To change boot source to vbank4:
- on T1024RDB:
- via software: run command 'cpld reset altbank' in U-Boot.
- via DIP-switch: set SW3[5:7] = '100'
- on T1023RDB:
- via software: run command 'switch bank4' in U-Boot.
- via DIP-switch: set SW3[5:7] = '100'
-
- To change boot source to vbank0:
- on T1024RDB:
- via software: run command 'cpld reset' in U-Boot.
- via DIP-Switch: set SW3[5:7] = '000'
- on T1023RDB:
- via software: run command 'switch bank0' in U-Boot.
- via DIP-switch: set SW3[5:7] = '000'
-
-2. NAND Boot:
- a. build PBL image for NAND boot
- $ make T1024RDB_NAND_defconfig
- $ make
- b. program u-boot-with-spl-pbl.bin to NAND flash
- => tftp 1000000 u-boot-with-spl-pbl.bin
- => nand erase 0 $filesize
- => nand write 1000000 0 $filesize
- set SW1[1:8] = '10000010', SW2[1] = '1', SW3[4] = '1' for NAND boot
-
-3. SPI Boot:
- a. build PBL image for SPI boot
- $ make T1024RDB_SPIFLASH_defconfig
- $ make
- b. program u-boot-with-spl-pbl.bin to SPI flash
- => tftp 1000000 u-boot-with-spl-pbl.bin
- => sf probe 0
- => sf erase 0 100000
- => sf write 1000000 0 $filesize
- => tftp 1000000 fsl_fman_ucode_t1024_xx.bin
- => sf erase 100000 100000
- => sf write 1000000 110000 20000
- set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot
-
-4. SD Boot:
- a. build PBL image for SD boot
- $ make T1024RDB_SDCARD_defconfig
- $ make
- b. program u-boot-with-spl-pbl.bin to SD/MMC card
- => tftp 1000000 u-boot-with-spl-pbl.bin
- => mmc write 1000000 8 0x7f0
- => tftp 1000000 fsl_fman_ucode_t1024_xx.bin
- => mmc write 1000000 0x820 80
- set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot
-
- SW3[3] = '1' for SD card(or 'switch sd' by software)
- SW3[3] = '0' for eMMC (or 'switch emmc' by software)
-
-
-device tree support and how to enable it for different configs
---------------------------------------------------------------
-device tree support is available for t1024rdb for below mentioned boot,
-1. nor boot
-2. nand boot
-3. sd boot
-4. spiflash boot
-
-to enable device tree support for other boot, below configs need to be
-enabled in relative defconfig file,
-1. config_default_device_tree="t1024rdb" (change default device tree name if required)
-2. config_of_control
-3. config_mpc85xx_have_reset_vector if reset vector is located at
- config_reset_vector_address - 0xffc
-
-if device tree support is enabled in defconfig,
-1. use 'u-boot-with-dtb.bin' for nor boot.
-2. use 'u-boot-with-spl-pbl.bin' for other boot.
-
-2-stage NAND/SPI/SD boot loader
--------------------------------
-PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM.
-SPL further initializes DDR using SPD and environment variables
-and copy U-Boot(768 KB) from NAND/SPI/SD device to DDR.
-Finally SPL transers control to U-Boot for futher booting.
-
-SPL has following features:
- - Executes within 256K
- - No relocation required
-
-Run time view of SPL framework
--------------------------------------------------
-|Area | Address |
--------------------------------------------------
-|SecureBoot header | 0xFFFC0000 (32KB) |
--------------------------------------------------
-|GD, BD | 0xFFFC8000 (4KB) |
--------------------------------------------------
-|ENV | 0xFFFC9000 (8KB) |
--------------------------------------------------
-|HEAP | 0xFFFCB000 (30KB) |
--------------------------------------------------
-|STACK | 0xFFFD8000 (22KB) |
--------------------------------------------------
-|U-Boot SPL | 0xFFFD8000 (160KB) |
--------------------------------------------------
-
-NAND Flash memory Map on T1024RDB
--------------------------------------------------------------
-Start End Definition Size
-0x000000 0x0FFFFF U-Boot 1MB(2 block)
-0x100000 0x17FFFF U-Boot env 512KB(1 block)
-0x180000 0x1FFFFF FMAN Ucode 512KB(1 block)
-0x200000 0x27FFFF QE Firmware 512KB(1 block)
-
-
-NAND Flash memory Map on T1023RDB
-----------------------------------------------------
-Start End Definition Size
-0x000000 0x0FFFFF U-Boot 1MB
-0x100000 0x15FFFF U-Boot env 8KB
-0x160000 0x17FFFF FMAN Ucode 128KB
-
-
-SD Card memory Map on T102xRDB
-----------------------------------------------------
-Block #blocks Definition Size
-0x008 2048 U-Boot img 1MB
-0x800 0016 U-Boot env 8KB
-0x820 0256 FMAN Ucode 128KB
-0x920 0256 QE Firmware 128KB(only T1024RDB)
-
-
-64MB SPI Flash memory Map on T102xRDB
-----------------------------------------------------
-Start End Definition Size
-0x000000 0x0FFFFF U-Boot img 1MB
-0x100000 0x101FFF U-Boot env 8KB
-0x110000 0x12FFFF FMAN Ucode 128KB
-0x130000 0x14FFFF QE Firmware 128KB(only T1024RDB)
-0x300000 0x3FFFFF device tree 128KB
-0x400000 0x9FFFFF Linux kernel 6MB
-0xa00000 0x3FFFFFF rootfs 54MB
-
-
-For more details, please refer to T1024RDB/T1023RDB User Guide
-and Freescale QorIQ SDK Infocenter document.
diff --git a/board/freescale/t102xrdb/cpld.c b/board/freescale/t102xrdb/cpld.c
deleted file mode 100644
index 47c3b1627e..0000000000
--- a/board/freescale/t102xrdb/cpld.c
+++ /dev/null
@@ -1,102 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/**
- * Copyright 2014 Freescale Semiconductor
- *
- * Freescale T1024RDB board-specific CPLD controlling supports.
- *
- * The following macros need to be defined:
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/io.h>
-#include "cpld.h"
-
-u8 cpld_read(unsigned int reg)
-{
- void *p = (void *)CONFIG_SYS_CPLD_BASE;
-
- return in_8(p + reg);
-}
-
-void cpld_write(unsigned int reg, u8 value)
-{
- void *p = (void *)CONFIG_SYS_CPLD_BASE;
-
- out_8(p + reg, value);
-}
-
-/**
- * Set the boot bank to the alternate bank
- */
-void cpld_set_altbank(void)
-{
- u8 reg = CPLD_READ(flash_csr);
-
- reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_ALTBANK;
-
- CPLD_WRITE(flash_csr, reg);
- CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET);
-}
-
-/**
- * Set the boot bank to the default bank
- */
-void cpld_set_defbank(void)
-{
- u8 reg = CPLD_READ(flash_csr);
-
- reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_DFLTBANK;
-
- CPLD_WRITE(flash_csr, reg);
- CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET);
-}
-
-static void cpld_dump_regs(void)
-{
- printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver));
- printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub));
- printf("hw_ver = 0x%02x\n", CPLD_READ(hw_ver));
- printf("sw_ver = 0x%02x\n", CPLD_READ(sw_ver));
- printf("reset_ctl1 = 0x%02x\n", CPLD_READ(reset_ctl1));
- printf("reset_ctl2 = 0x%02x\n", CPLD_READ(reset_ctl2));
- printf("int_status = 0x%02x\n", CPLD_READ(int_status));
- printf("flash_csr = 0x%02x\n", CPLD_READ(flash_csr));
- printf("fan_ctl_status = 0x%02x\n", CPLD_READ(fan_ctl_status));
- printf("led_ctl_status = 0x%02x\n", CPLD_READ(led_ctl_status));
- printf("sfp_ctl_status = 0x%02x\n", CPLD_READ(sfp_ctl_status));
- printf("misc_ctl_status = 0x%02x\n", CPLD_READ(misc_ctl_status));
- printf("boot_override = 0x%02x\n", CPLD_READ(boot_override));
- printf("boot_config1 = 0x%02x\n", CPLD_READ(boot_config1));
- printf("boot_config2 = 0x%02x\n", CPLD_READ(boot_config2));
- putc('\n');
-}
-
-int do_cpld(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
-{
- int rc = 0;
-
- if (argc <= 1)
- return cmd_usage(cmdtp);
-
- if (strcmp(argv[1], "reset") == 0) {
- if (strcmp(argv[2], "altbank") == 0)
- cpld_set_altbank();
- else
- cpld_set_defbank();
- } else if (strcmp(argv[1], "dump") == 0) {
- cpld_dump_regs();
- } else {
- rc = cmd_usage(cmdtp);
- }
-
- return rc;
-}
-
-U_BOOT_CMD(
- cpld, CONFIG_SYS_MAXARGS, 1, do_cpld,
- "Reset the board or alternate bank",
- "reset - hard reset to default bank\n"
- "cpld reset altbank - reset to alternate bank\n"
- "cpld dump - display the CPLD registers\n"
- );
diff --git a/board/freescale/t102xrdb/cpld.h b/board/freescale/t102xrdb/cpld.h
deleted file mode 100644
index c05f536806..0000000000
--- a/board/freescale/t102xrdb/cpld.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/**
- * Copyright 2014 Freescale Semiconductor
- *
- */
-
-struct cpld_data {
- u8 cpld_ver; /* 0x00 - CPLD Major Revision Register */
- u8 cpld_ver_sub; /* 0x01 - CPLD Minor Revision Register */
- u8 hw_ver; /* 0x02 - Hardware Revision Register */
- u8 sw_ver; /* 0x03 - Software Revision register */
- u8 res0[12]; /* 0x04 - 0x0F - not used */
- u8 reset_ctl1; /* 0x10 - Reset control Register1 */
- u8 reset_ctl2; /* 0x11 - Reset control Register2 */
- u8 int_status; /* 0x12 - Interrupt status Register */
- u8 flash_csr; /* 0x13 - Flash control and status register */
- u8 fan_ctl_status; /* 0x14 - Fan control and status register */
- u8 led_ctl_status; /* 0x15 - LED control and status register */
- u8 sfp_ctl_status; /* 0x16 - SFP control and status register */
- u8 misc_ctl_status; /* 0x17 - Miscellanies ctrl & status register*/
- u8 boot_override; /* 0x18 - Boot override register */
- u8 boot_config1; /* 0x19 - Boot config override register*/
- u8 boot_config2; /* 0x1A - Boot config override register*/
-} cpld_data_t;
-
-
-/* Pointer to the CPLD register set */
-
-u8 cpld_read(unsigned int reg);
-void cpld_write(unsigned int reg, u8 value);
-
-#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg))
-#define CPLD_WRITE(reg, value)\
- cpld_write(offsetof(struct cpld_data, reg), value)
-
-/* CPLD on IFC */
-#define CPLD_LBMAP_MASK 0x3F
-#define CPLD_BANK_SEL_MASK 0x07
-#define CPLD_BANK_OVERRIDE 0x40
-#define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */
-#define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK 0 */
-#define CPLD_LBMAP_RESET 0xFF
-#define CPLD_LBMAP_SHIFT 0x03
-#define CPLD_BOOT_SEL 0x80
-
-#define CPLD_PCIE_SGMII_MUX 0x80
-#define CPLD_OVERRIDE_BOOT_EN 0x01
-#define CPLD_OVERRIDE_MUX_EN 0x02 /* PCIE/2.5G-SGMII mux override enable */
diff --git a/board/freescale/t102xrdb/ddr.c b/board/freescale/t102xrdb/ddr.c
deleted file mode 100644
index 3640a47957..0000000000
--- a/board/freescale/t102xrdb/ddr.c
+++ /dev/null
@@ -1,257 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <hwconfig.h>
-#include <init.h>
-#include <log.h>
-#include <asm/mmu.h>
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-#include <asm/fsl_law.h>
-#include <asm/mpc85xx_gpio.h>
-#include <linux/delay.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-struct board_specific_parameters {
- u32 n_ranks;
- u32 datarate_mhz_high;
- u32 rank_gb;
- u32 clk_adjust;
- u32 wrlvl_start;
- u32 wrlvl_ctl_2;
- u32 wrlvl_ctl_3;
-};
-
-/*
- * datarate_mhz_high values need to be in ascending order
- */
-static const struct board_specific_parameters udimm0[] = {
- /*
- * memory controller 0
- * num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
- * ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
- */
- {2, 833, 0, 8, 6, 0x06060607, 0x08080807,},
- {2, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09,},
- {2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,},
- {1, 833, 0, 8, 6, 0x06060607, 0x08080807,},
- {1, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09,},
- {1, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,},
- {}
-};
-
-static const struct board_specific_parameters *udimms[] = {
- udimm0,
-};
-
-void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
- ulong ddr_freq;
- struct cpu_type *cpu = gd->arch.cpu;
-
- if (ctrl_num > 1) {
- printf("Not supported controller number %d\n", ctrl_num);
- return;
- }
- if (!pdimm->n_ranks)
- return;
-
- pbsp = udimms[0];
-
- /* Get clk_adjust according to the board ddr freqency and n_banks
- * specified in board_specific_parameters table.
- */
- ddr_freq = get_ddr_freq(0) / 1000000;
- while (pbsp->datarate_mhz_high) {
- if (pbsp->n_ranks == pdimm->n_ranks &&
- (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
- if (ddr_freq <= pbsp->datarate_mhz_high) {
- popts->clk_adjust = pbsp->clk_adjust;
- popts->wrlvl_start = pbsp->wrlvl_start;
- popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
- popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
- goto found;
- }
- pbsp_highest = pbsp;
- }
- pbsp++;
- }
-
- if (pbsp_highest) {
- printf("Error: board specific timing not found\n");
- printf("for data rate %lu MT/s\n", ddr_freq);
- printf("Trying to use the highest speed (%u) parameters\n",
- pbsp_highest->datarate_mhz_high);
- popts->clk_adjust = pbsp_highest->clk_adjust;
- popts->wrlvl_start = pbsp_highest->wrlvl_start;
- popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
- popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
- } else {
- panic("DIMM is not supported by this board");
- }
-found:
- debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
- pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);
- debug("\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, ",
- pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2);
- debug("wrlvl_ctrl_3 0x%x\n", pbsp->wrlvl_ctl_3);
-
- /*
- * Factors to consider for half-strength driver enable:
- * - number of DIMMs installed
- */
- popts->half_strength_driver_enable = 0;
- /*
- * Write leveling override
- */
- popts->wrlvl_override = 1;
- popts->wrlvl_sample = 0xf;
-
- /*
- * rtt and rtt_wr override
- */
- popts->rtt_override = 0;
-
- /* Enable ZQ calibration */
- popts->zq_en = 1;
-
- /* DHC_EN =1, ODT = 75 Ohm */
- popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_OFF);
- popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_OFF);
-
- /* T1023 supports max DDR bus 32bit width, T1024 supports DDR 64bit,
- * force DDR bus width to 32bit for T1023
- */
- if (cpu->soc_ver == SVR_T1023)
- popts->data_bus_width = DDR_DATA_BUS_WIDTH_32;
-
-#ifdef CONFIG_FORCE_DDR_DATA_BUS_WIDTH_32
- /* for DDR bus 32bit test on T1024 */
- popts->data_bus_width = DDR_DATA_BUS_WIDTH_32;
-#endif
-
-#ifdef CONFIG_TARGET_T1023RDB
- popts->wrlvl_ctl_2 = 0x07070606;
- popts->half_strength_driver_enable = 1;
- popts->cpo_sample = 0x43;
-#elif defined(CONFIG_TARGET_T1024RDB)
- /* optimize cpo for erratum A-009942 */
- popts->cpo_sample = 0x52;
-#endif
-}
-
-#ifdef CONFIG_SYS_DDR_RAW_TIMING
-/* 2GB discrete DDR4 MT40A512M8HX on T1023RDB */
-dimm_params_t ddr_raw_timing = {
- .n_ranks = 1,
- .rank_density = 0x80000000,
- .capacity = 0x80000000,
- .primary_sdram_width = 32,
- .ec_sdram_width = 8,
- .registered_dimm = 0,
- .mirrored_dimm = 0,
- .n_row_addr = 15,
- .n_col_addr = 10,
- .bank_addr_bits = 2,
- .bank_group_bits = 2,
- .edc_config = 0,
- .burst_lengths_bitmask = 0x0c,
- .tckmin_x_ps = 938,
- .tckmax_ps = 1500,
- .caslat_x = 0x000DFA00,
- .taa_ps = 13500,
- .trcd_ps = 13500,
- .trp_ps = 13500,
- .tras_ps = 33000,
- .trc_ps = 46500,
- .trfc1_ps = 260000,
- .trfc2_ps = 160000,
- .trfc4_ps = 110000,
- .tfaw_ps = 25000,
- .trrds_ps = 3700,
- .trrdl_ps = 5300,
- .tccdl_ps = 5355,
- .refresh_rate_ps = 7800000,
- .dq_mapping[0] = 0x0,
- .dq_mapping[1] = 0x0,
- .dq_mapping[2] = 0x0,
- .dq_mapping[3] = 0x0,
- .dq_mapping[4] = 0x0,
- .dq_mapping[5] = 0x0,
- .dq_mapping[6] = 0x0,
- .dq_mapping[7] = 0x0,
- .dq_mapping[8] = 0x0,
- .dq_mapping[9] = 0x0,
- .dq_mapping[10] = 0x0,
- .dq_mapping[11] = 0x0,
- .dq_mapping[12] = 0x0,
- .dq_mapping[13] = 0x0,
- .dq_mapping[14] = 0x0,
- .dq_mapping[15] = 0x0,
- .dq_mapping[16] = 0x0,
- .dq_mapping[17] = 0x0,
- .dq_mapping_ors = 1,
-};
-
-int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
- unsigned int controller_number,
- unsigned int dimm_number)
-{
- const char dimm_model[] = "Fixed DDR4 on board";
-
- if (((controller_number == 0) && (dimm_number == 0)) ||
- ((controller_number == 1) && (dimm_number == 0))) {
- memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
- memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
- memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
- }
-
- return 0;
-}
-#endif
-
-#if defined(CONFIG_DEEP_SLEEP)
-void board_mem_sleep_setup(void)
-{
- void __iomem *cpld_base = (void *)CONFIG_SYS_CPLD_BASE;
-
- /* does not provide HW signals for power management */
- clrbits_8(cpld_base + 0x17, 0x40);
- /* Disable MCKE isolation */
- gpio_set_value(2, 0);
- udelay(1);
-}
-#endif
-
-int dram_init(void)
-{
- phys_size_t dram_size;
-
-#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
-#ifndef CONFIG_SYS_DDR_RAW_TIMING
- puts("Initializing....using SPD\n");
-#endif
- dram_size = fsl_ddr_sdram();
-#else
- /* DDR has been initialised by first stage boot loader */
- dram_size = fsl_ddr_sdram_size();
-#endif
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
-
-#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
- fsl_dp_resume();
-#endif
-
- gd->ram_size = dram_size;
-
- return 0;
-}
diff --git a/board/freescale/t102xrdb/eth_t102xrdb.c b/board/freescale/t102xrdb/eth_t102xrdb.c
deleted file mode 100644
index dbf25a237d..0000000000
--- a/board/freescale/t102xrdb/eth_t102xrdb.c
+++ /dev/null
@@ -1,146 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- *
- * Shengzhou Liu <Shengzhou.Liu@freescale.com>
- */
-
-#include <common.h>
-#include <command.h>
-#include <fdt_support.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/mmu.h>
-#include <asm/processor.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_law.h>
-#include <asm/fsl_serdes.h>
-#include <asm/fsl_portals.h>
-#include <asm/fsl_liodn.h>
-#include <malloc.h>
-#include <fm_eth.h>
-#include <fsl_mdio.h>
-#include <miiphy.h>
-#include <phy.h>
-#include <fsl_dtsec.h>
-#include <asm/fsl_serdes.h>
-#include "../common/fman.h"
-
-int board_eth_init(bd_t *bis)
-{
-#if defined(CONFIG_FMAN_ENET)
- int i, interface;
- struct memac_mdio_info dtsec_mdio_info;
- struct memac_mdio_info tgec_mdio_info;
- struct mii_dev *dev;
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- u32 srds_s1;
-
- srds_s1 = in_be32(&gur->rcwsr[4]) &
- FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
- srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
-
- dtsec_mdio_info.regs =
- (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
-
- dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
-
- /* Register the 1G MDIO bus */
- fm_memac_mdio_init(bis, &dtsec_mdio_info);
-
- tgec_mdio_info.regs =
- (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
- tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
-
- /* Register the 10G MDIO bus */
- fm_memac_mdio_init(bis, &tgec_mdio_info);
-
- /* Set the on-board RGMII PHY address */
- fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY1_ADDR);
-
- switch (srds_s1) {
-#ifdef CONFIG_TARGET_T1024RDB
- case 0x95:
- /* set the on-board RGMII2 PHY */
- fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR);
-
- /* set 10G XFI with Aquantia AQR105 PHY */
- fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
- break;
-#endif
- case 0x6a:
- case 0x6b:
- case 0x77:
- case 0x135:
- /* set the on-board 2.5G SGMII AQR105 PHY */
- fm_info_set_phy_address(FM1_DTSEC3, SGMII_AQR_PHY_ADDR);
-#ifdef CONFIG_TARGET_T1023RDB
- /* set the on-board 1G SGMII RTL8211F PHY */
- fm_info_set_phy_address(FM1_DTSEC1, SGMII_RTK_PHY_ADDR);
-#endif
- break;
- default:
- printf("SerDes protocol 0x%x is not supported on T102xRDB\n",
- srds_s1);
- break;
- }
-
- for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
- interface = fm_info_get_enet_if(i);
- switch (interface) {
- case PHY_INTERFACE_MODE_RGMII:
- dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
- fm_info_set_mdio(i, dev);
- break;
- case PHY_INTERFACE_MODE_SGMII:
-#if defined(CONFIG_TARGET_T1023RDB)
- dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
-#elif defined(CONFIG_TARGET_T1024RDB)
- dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
-#endif
- fm_info_set_mdio(i, dev);
- break;
- case PHY_INTERFACE_MODE_SGMII_2500:
- dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
- fm_info_set_mdio(i, dev);
- break;
- default:
- break;
- }
- }
-
- for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
- switch (fm_info_get_enet_if(i)) {
- case PHY_INTERFACE_MODE_XGMII:
- dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
- fm_info_set_mdio(i, dev);
- break;
- default:
- break;
- }
- }
-
- cpu_eth_init(bis);
-#endif /* CONFIG_FMAN_ENET */
-
- return pci_eth_init(bis);
-}
-
-void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
- enum fm_port port, int offset)
-{
-#if defined(CONFIG_TARGET_T1024RDB)
- if (((fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) ||
- (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII)) &&
- (port == FM1_DTSEC3)) {
- fdt_set_phy_handle(fdt, compat, addr, "sg_2500_aqr105_phy4");
- fdt_setprop_string(fdt, offset, "phy-connection-type",
- "sgmii-2500");
- fdt_status_disabled_by_alias(fdt, "xg_aqr105_phy3");
- }
-#endif
-}
-
-void fdt_fixup_board_enet(void *fdt)
-{
-}
diff --git a/board/freescale/t102xrdb/law.c b/board/freescale/t102xrdb/law.c
deleted file mode 100644
index 04a4239797..0000000000
--- a/board/freescale/t102xrdb/law.c
+++ /dev/null
@@ -1,31 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-struct law_entry law_table[] = {
-#ifdef CONFIG_MTD_NOR_FLASH
- SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
-#endif
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
- SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
-#endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
- SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
-#endif
-#ifdef CONFIG_SYS_CPLD_BASE_PHYS
- SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
-#endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
- SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
-#endif
-#ifdef CONFIG_SYS_NAND_BASE_PHYS
- SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
-#endif
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/t102xrdb/pci.c b/board/freescale/t102xrdb/pci.c
deleted file mode 100644
index bd0e29744c..0000000000
--- a/board/freescale/t102xrdb/pci.c
+++ /dev/null
@@ -1,25 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2007-2014 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <init.h>
-#include <pci.h>
-#include <asm/fsl_pci.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <asm/fsl_serdes.h>
-
-#if !defined(CONFIG_DM_PCI)
-void pci_init_board(void)
-{
- fsl_pcie_init_board(0);
-}
-
-void pci_of_setup(void *blob, bd_t *bd)
-{
- FT_FSL_PCI_SETUP;
-}
-#endif
diff --git a/board/freescale/t102xrdb/spl.c b/board/freescale/t102xrdb/spl.c
deleted file mode 100644
index aed0721c0d..0000000000
--- a/board/freescale/t102xrdb/spl.c
+++ /dev/null
@@ -1,143 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/* Copyright 2014 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <clock_legacy.h>
-#include <console.h>
-#include <env_internal.h>
-#include <init.h>
-#include <malloc.h>
-#include <ns16550.h>
-#include <nand.h>
-#include <i2c.h>
-#include <mmc.h>
-#include <fsl_esdhc.h>
-#include <spi_flash.h>
-#include "../common/sleep.h"
-#include "../common/spl.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-phys_size_t get_effective_memsize(void)
-{
- return CONFIG_SYS_L3_SIZE;
-}
-
-unsigned long get_board_sys_clk(void)
-{
- return CONFIG_SYS_CLK_FREQ;
-}
-
-unsigned long get_board_ddr_clk(void)
-{
- return CONFIG_DDR_CLK_FREQ;
-}
-
-#if defined(CONFIG_SPL_MMC_BOOT)
-#define GPIO1_SD_SEL 0x00020000
-int board_mmc_getcd(struct mmc *mmc)
-{
- ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
- u32 val = in_be32(&pgpio->gpdat);
-
- /* GPIO1_14, 0: eMMC, 1: SD */
- val &= GPIO1_SD_SEL;
-
- return val ? -1 : 1;
-}
-
-int board_mmc_getwp(struct mmc *mmc)
-{
- ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
- u32 val = in_be32(&pgpio->gpdat);
-
- val &= GPIO1_SD_SEL;
-
- return val ? -1 : 0;
-}
-#endif
-
-void board_init_f(ulong bootflag)
-{
- u32 plat_ratio, sys_clk, ccb_clk;
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
- /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
- memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
-
- /* Update GD pointer */
- gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
-
- console_init_f();
-
-#ifdef CONFIG_DEEP_SLEEP
- /* disable the console if boot from deep sleep */
- if (is_warm_boot())
- fsl_dp_disable_console();
-#endif
-
- /* initialize selected port with appropriate baud rate */
- sys_clk = get_board_sys_clk();
- plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
- ccb_clk = sys_clk * plat_ratio / 2;
-
- NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
- ccb_clk / 16 / CONFIG_BAUDRATE);
-
-#if defined(CONFIG_SPL_MMC_BOOT)
- puts("\nSD boot...\n");
-#elif defined(CONFIG_SPL_SPI_BOOT)
- puts("\nSPI boot...\n");
-#elif defined(CONFIG_SPL_NAND_BOOT)
- puts("\nNAND boot...\n");
-#endif
-
- relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
- bd_t *bd;
-
- bd = (bd_t *)(gd + sizeof(gd_t));
- memset(bd, 0, sizeof(bd_t));
- gd->bd = bd;
- bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
- bd->bi_memsize = CONFIG_SYS_L3_SIZE;
-
- arch_cpu_init();
- get_clocks();
- mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
- CONFIG_SPL_RELOC_MALLOC_SIZE);
- gd->flags |= GD_FLG_FULL_MALLOC_INIT;
-
-#ifdef CONFIG_SPL_NAND_BOOT
- nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
- (uchar *)SPL_ENV_ADDR);
-#endif
-#ifdef CONFIG_SPL_MMC_BOOT
- mmc_initialize(bd);
- mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
- (uchar *)SPL_ENV_ADDR);
-#endif
-#ifdef CONFIG_SPL_SPI_BOOT
- fsl_spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
- (uchar *)SPL_ENV_ADDR);
-#endif
-
- gd->env_addr = (ulong)(SPL_ENV_ADDR);
- gd->env_valid = ENV_VALID;
-
- i2c_init_all();
-
- dram_init();
-
-#ifdef CONFIG_SPL_MMC_BOOT
- mmc_boot();
-#elif defined(CONFIG_SPL_SPI_BOOT)
- fsl_spi_boot();
-#elif defined(CONFIG_SPL_NAND_BOOT)
- nand_boot();
-#endif
-}
diff --git a/board/freescale/t102xrdb/t1023_nand_rcw.cfg b/board/freescale/t102xrdb/t1023_nand_rcw.cfg
deleted file mode 100644
index f8f72826b1..0000000000
--- a/board/freescale/t102xrdb/t1023_nand_rcw.cfg
+++ /dev/null
@@ -1,8 +0,0 @@
-#PBL preamble and RCW header for T1023RDB
-aa55aa55 010e0100
-#SerDes Protocol: 0x77
-#Default Core=1200MHz, DDR=1600MT/s with single source clock
-0810000c 00000000 00000000 00000000
-3b800003 00000012 e8104000 21000000
-00000000 00000000 00000000 00022800
-00000130 04020200 00000000 00000006
diff --git a/board/freescale/t102xrdb/t1023_sd_rcw.cfg b/board/freescale/t102xrdb/t1023_sd_rcw.cfg
deleted file mode 100644
index dbf8fba553..0000000000
--- a/board/freescale/t102xrdb/t1023_sd_rcw.cfg
+++ /dev/null
@@ -1,8 +0,0 @@
-#PBL preamble and RCW header for T1023RDB
-aa55aa55 010e0100
-#SerDes Protocol: 0x77
-#Default Core=1200MHz, DDR=1600MT/s with single source clock
-0810000c 00000000 00000000 00000000
-3b800003 00000012 68104000 21000000
-00000000 00000000 00000000 00022800
-00000130 04020200 00000000 00000006
diff --git a/board/freescale/t102xrdb/t1023_spi_rcw.cfg b/board/freescale/t102xrdb/t1023_spi_rcw.cfg
deleted file mode 100644
index 5edcdb50ea..0000000000
--- a/board/freescale/t102xrdb/t1023_spi_rcw.cfg
+++ /dev/null
@@ -1,8 +0,0 @@
-#PBL preamble and RCW header for T1023RDB
-aa55aa55 010e0100
-#SerDes Protocol: 0x77
-#Default Core=1200MHz, DDR=1600MT/s with single source clock
-0810000c 00000000 00000000 00000000
-3b800003 00000012 58104000 21000000
-00000000 00000000 00000000 00022800
-00000130 04020200 00000000 00000006
diff --git a/board/freescale/t102xrdb/t1024_nand_rcw.cfg b/board/freescale/t102xrdb/t1024_nand_rcw.cfg
deleted file mode 100644
index cd6f906396..0000000000
--- a/board/freescale/t102xrdb/t1024_nand_rcw.cfg
+++ /dev/null
@@ -1,8 +0,0 @@
-#PBL preamble and RCW header for T1024RDB
-aa55aa55 010e0100
-#SerDes Protocol: 0x95
-#Core/DDR: 1400Mhz/1600MT/s with single source clock
-0810000c 00000000 00000000 00000000
-4a800003 80000012 ec027000 21000000
-00000000 00000000 00000000 00030810
-00000000 0b005a08 00000000 00000006
diff --git a/board/freescale/t102xrdb/t1024_pbi.cfg b/board/freescale/t102xrdb/t1024_pbi.cfg
deleted file mode 100644
index 98efca25a2..0000000000
--- a/board/freescale/t102xrdb/t1024_pbi.cfg
+++ /dev/null
@@ -1,26 +0,0 @@
-#PBI commands
-#Initialize CPC1
-09010000 00200400
-09138000 00000000
-091380c0 00000100
-#Configure CPC1 as 256KB SRAM
-09010100 00000000
-09010104 fffc0007
-09010f00 081e000d
-09010000 80000000
-#Configure LAW for CPC1
-09000cd0 00000000
-09000cd4 fffc0000
-09000cd8 81000011
-#Configure alternate space
-09000010 00000000
-09000014 ff000000
-09000018 81000000
-#Configure SPI controller
-09110000 80000403
-09110020 2d170008
-09110024 00100008
-09110028 00100008
-0911002c 00100008
-#Flush PBL data
-091380c0 000FFFFF
diff --git a/board/freescale/t102xrdb/t1024_sd_rcw.cfg b/board/freescale/t102xrdb/t1024_sd_rcw.cfg
deleted file mode 100644
index 05b3f37763..0000000000
--- a/board/freescale/t102xrdb/t1024_sd_rcw.cfg
+++ /dev/null
@@ -1,8 +0,0 @@
-#PBL preamble and RCW header for T1024RDB
-aa55aa55 010e0100
-#SerDes Protocol: 0x95
-#Core/DDR: 1400Mhz/1600MT/s with single source clock
-0810000c 00000000 00000000 00000000
-4a800003 80000012 6c027000 21000000
-00000000 00000000 00000000 00030810
-00000000 0b005a08 00000000 00000006
diff --git a/board/freescale/t102xrdb/t1024_spi_rcw.cfg b/board/freescale/t102xrdb/t1024_spi_rcw.cfg
deleted file mode 100644
index 8b695b4ab7..0000000000
--- a/board/freescale/t102xrdb/t1024_spi_rcw.cfg
+++ /dev/null
@@ -1,8 +0,0 @@
-#PBL preamble and RCW header for T1024RDB
-aa55aa55 010e0100
-#SerDes Protocol: 0x95
-#Core/DDR: 1400Mhz/1600MT/s with single source clock
-0810000c 00000000 00000000 00000000
-4a800003 80000012 5c027000 21000000
-00000000 00000000 00000000 00030810
-00000000 0b005a08 00000000 00000006
diff --git a/board/freescale/t102xrdb/t102xrdb.c b/board/freescale/t102xrdb/t102xrdb.c
deleted file mode 100644
index 754fcb0ad5..0000000000
--- a/board/freescale/t102xrdb/t102xrdb.c
+++ /dev/null
@@ -1,394 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2020 NXP
- */
-
-#include <common.h>
-#include <command.h>
-#include <env.h>
-#include <fdt_support.h>
-#include <i2c.h>
-#include <image.h>
-#include <init.h>
-#include <netdev.h>
-#include <linux/compiler.h>
-#include <asm/mmu.h>
-#include <asm/processor.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_law.h>
-#include <asm/fsl_serdes.h>
-#include <asm/fsl_liodn.h>
-#include <fm_eth.h>
-#include "t102xrdb.h"
-#ifdef CONFIG_TARGET_T1024RDB
-#include "cpld.h"
-#elif defined(CONFIG_TARGET_T1023RDB)
-#include <i2c.h>
-#include <mmc.h>
-#endif
-#include "../common/sleep.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_TARGET_T1023RDB
-enum {
- GPIO1_SD_SEL = 0x00020000, /* GPIO1_14, 0: eMMC, 1:SD/MMC */
- GPIO1_EMMC_SEL,
- GPIO3_GET_VERSION, /* GPIO3_4/5, 00:RevB, 01: RevC */
- GPIO3_BRD_VER_MASK = 0x0c000000,
- GPIO3_OFFSET = 0x2000,
- I2C_GET_BANK,
- I2C_SET_BANK0,
- I2C_SET_BANK4,
-};
-#endif
-
-int checkboard(void)
-{
- struct cpu_type *cpu = gd->arch.cpu;
- static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"};
- ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- u32 srds_s1;
-
- srds_s1 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
- srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
-
- printf("Board: %sRDB, ", cpu->name);
-#if defined(CONFIG_TARGET_T1024RDB)
- printf("Board rev: 0x%02x CPLD ver: 0x%02x, ",
- CPLD_READ(hw_ver), CPLD_READ(sw_ver));
-#elif defined(CONFIG_TARGET_T1023RDB)
- printf("Rev%c, ", t1023rdb_ctrl(GPIO3_GET_VERSION) + 'B');
-#endif
- printf("boot from ");
-
-#ifdef CONFIG_SDCARD
- puts("SD/MMC\n");
-#elif CONFIG_SPIFLASH
- puts("SPI\n");
-#elif defined(CONFIG_TARGET_T1024RDB)
- u8 reg;
-
- reg = CPLD_READ(flash_csr);
-
- if (reg & CPLD_BOOT_SEL) {
- puts("NAND\n");
- } else {
- reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
- printf("NOR vBank%d\n", reg);
- }
-#elif defined(CONFIG_TARGET_T1023RDB)
-#ifdef CONFIG_MTD_RAW_NAND
- puts("NAND\n");
-#else
- printf("NOR vBank%d\n", t1023rdb_ctrl(I2C_GET_BANK));
-#endif
-#endif
-
- puts("SERDES Reference Clocks:\n");
- if (srds_s1 == 0x95)
- printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]);
- else
- printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[0], freq[1]);
-
- return 0;
-}
-
-#ifdef CONFIG_TARGET_T1024RDB
-static void board_mux_lane(void)
-{
- ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- u32 srds_prtcl_s1;
- u8 reg = CPLD_READ(misc_ctl_status);
-
- srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
- FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
- srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
-
- if (srds_prtcl_s1 == 0x95) {
- /* Route Lane B to PCIE */
- CPLD_WRITE(misc_ctl_status, reg & ~CPLD_PCIE_SGMII_MUX);
- } else {
- /* Route Lane B to SGMII */
- CPLD_WRITE(misc_ctl_status, reg | CPLD_PCIE_SGMII_MUX);
- }
- CPLD_WRITE(boot_override, CPLD_OVERRIDE_MUX_EN);
-}
-#endif
-
-int board_early_init_f(void)
-{
-#if defined(CONFIG_DEEP_SLEEP)
- if (is_warm_boot())
- fsl_dp_disable_console();
-#endif
-
- return 0;
-}
-
-int board_early_init_r(void)
-{
-#ifdef CONFIG_SYS_FLASH_BASE
- const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
- int flash_esel = find_tlb_idx((void *)flashbase, 1);
- /*
- * Remap Boot flash region to caching-inhibited
- * so that flash can be erased properly.
- */
-
- /* Flush d-cache and invalidate i-cache of any FLASH data */
- flush_dcache();
- invalidate_icache();
- if (flash_esel == -1) {
- /* very unlikely unless something is messed up */
- puts("Error: Could not find TLB for FLASH BASE\n");
- flash_esel = 2; /* give our best effort to continue */
- } else {
- /* invalidate existing TLB entry for flash + promjet */
- disable_tlb(flash_esel);
- }
-
- set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, flash_esel, BOOKE_PAGESZ_256M, 1);
-#endif
-
-#ifdef CONFIG_TARGET_T1024RDB
- board_mux_lane();
-#endif
-
- return 0;
-}
-
-unsigned long get_board_sys_clk(void)
-{
- return CONFIG_SYS_CLK_FREQ;
-}
-
-unsigned long get_board_ddr_clk(void)
-{
- return CONFIG_DDR_CLK_FREQ;
-}
-
-#ifdef CONFIG_TARGET_T1024RDB
-void board_reset(void)
-{
- CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET);
-}
-#endif
-
-int misc_init_r(void)
-{
- return 0;
-}
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
- phys_addr_t base;
- phys_size_t size;
-
- ft_cpu_setup(blob, bd);
-
- base = env_get_bootm_low();
- size = env_get_bootm_size();
-
- fdt_fixup_memory(blob, (u64)base, (u64)size);
-
-#ifdef CONFIG_PCI
- pci_of_setup(blob, bd);
-#endif
-
- fdt_fixup_liodn(blob);
- fsl_fdt_fixup_dr_usb(blob, bd);
-
-#ifdef CONFIG_SYS_DPAA_FMAN
- fdt_fixup_fman_ethernet(blob);
- fdt_fixup_board_enet(blob);
-#endif
-
-#ifdef CONFIG_TARGET_T1023RDB
- if (t1023rdb_ctrl(GPIO3_GET_VERSION) > 0)
- fdt_enable_nor(blob);
-#endif
-
- return 0;
-}
-
-#ifdef CONFIG_TARGET_T1023RDB
-/* Enable NOR flash for RevC */
-static void fdt_enable_nor(void *blob)
-{
- int nodeoff = fdt_node_offset_by_compatible(blob, 0, "cfi-flash");
-
- if (nodeoff >= 0)
- fdt_status_okay(blob, nodeoff);
- else
- printf("WARNING unable to set status for NOR\n");
-}
-
-int board_mmc_getcd(struct mmc *mmc)
-{
- ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
- u32 val = in_be32(&pgpio->gpdat);
-
- /* GPIO1_14, 0: eMMC, 1: SD/MMC */
- val &= GPIO1_SD_SEL;
-
- return val ? -1 : 1;
-}
-
-int board_mmc_getwp(struct mmc *mmc)
-{
- ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
- u32 val = in_be32(&pgpio->gpdat);
-
- val &= GPIO1_SD_SEL;
-
- return val ? -1 : 0;
-}
-
-static u32 t1023rdb_ctrl(u32 ctrl_type)
-{
- ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
- ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- u32 val;
- u8 tmp;
- int bus_num = I2C_PCA6408_BUS_NUM;
-
-#ifdef CONFIG_DM_I2C
- struct udevice *dev;
- int ret;
-
- ret = i2c_get_chip_for_busnum(bus_num, I2C_PCA6408_ADDR,
- 1, &dev);
- if (ret) {
- printf("%s: Cannot find udev for a bus %d\n", __func__,
- bus_num);
- return ret;
- }
- switch (ctrl_type) {
- case GPIO1_SD_SEL:
- val = in_be32(&pgpio->gpdat);
- val |= GPIO1_SD_SEL;
- out_be32(&pgpio->gpdat, val);
- setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL);
- break;
- case GPIO1_EMMC_SEL:
- val = in_be32(&pgpio->gpdat);
- val &= ~GPIO1_SD_SEL;
- out_be32(&pgpio->gpdat, val);
- setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL);
- break;
- case GPIO3_GET_VERSION:
- pgpio = (ccsr_gpio_t *)(CONFIG_SYS_MPC85xx_GPIO_ADDR
- + GPIO3_OFFSET);
- val = in_be32(&pgpio->gpdat);
- val = ((val & GPIO3_BRD_VER_MASK) >> 26) & 0x3;
- if (val == 0x3) /* GPIO3_4/5 not used on RevB */
- val = 0;
- return val;
- case I2C_GET_BANK:
- dm_i2c_read(dev, 0, &tmp, 1);
- tmp &= 0x7;
- tmp = ((tmp & 1) << 2) | (tmp & 2) | ((tmp & 4) >> 2);
- return tmp;
- case I2C_SET_BANK0:
- tmp = 0x0;
- dm_i2c_write(dev, 1, &tmp, 1);
- tmp = 0xf8;
- dm_i2c_write(dev, 3, &tmp, 1);
- /* asserting HRESET_REQ */
- out_be32(&gur->rstcr, 0x2);
- break;
- case I2C_SET_BANK4:
- tmp = 0x1;
- dm_i2c_write(dev, 1, &tmp, 1);
- tmp = 0xf8;
- dm_i2c_write(dev, 3, &tmp, 1);
- out_be32(&gur->rstcr, 0x2);
- break;
- default:
- break;
- }
-#else
- u32 orig_bus;
-
- orig_bus = i2c_get_bus_num();
-
- switch (ctrl_type) {
- case GPIO1_SD_SEL:
- val = in_be32(&pgpio->gpdat);
- val |= GPIO1_SD_SEL;
- out_be32(&pgpio->gpdat, val);
- setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL);
- break;
- case GPIO1_EMMC_SEL:
- val = in_be32(&pgpio->gpdat);
- val &= ~GPIO1_SD_SEL;
- out_be32(&pgpio->gpdat, val);
- setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL);
- break;
- case GPIO3_GET_VERSION:
- pgpio = (ccsr_gpio_t *)(CONFIG_SYS_MPC85xx_GPIO_ADDR
- + GPIO3_OFFSET);
- val = in_be32(&pgpio->gpdat);
- val = ((val & GPIO3_BRD_VER_MASK) >> 26) & 0x3;
- if (val == 0x3) /* GPIO3_4/5 not used on RevB */
- val = 0;
- return val;
- case I2C_GET_BANK:
- i2c_set_bus_num(bus_num);
- i2c_read(I2C_PCA6408_ADDR, 0, 1, &tmp, 1);
- tmp &= 0x7;
- tmp = ((tmp & 1) << 2) | (tmp & 2) | ((tmp & 4) >> 2);
- i2c_set_bus_num(orig_bus);
- return tmp;
- case I2C_SET_BANK0:
- i2c_set_bus_num(bus_num);
- tmp = 0x0;
- i2c_write(I2C_PCA6408_ADDR, 1, 1, &tmp, 1);
- tmp = 0xf8;
- i2c_write(I2C_PCA6408_ADDR, 3, 1, &tmp, 1);
- /* asserting HRESET_REQ */
- out_be32(&gur->rstcr, 0x2);
- break;
- case I2C_SET_BANK4:
- i2c_set_bus_num(bus_num);
- tmp = 0x1;
- i2c_write(I2C_PCA6408_ADDR, 1, 1, &tmp, 1);
- tmp = 0xf8;
- i2c_write(I2C_PCA6408_ADDR, 3, 1, &tmp, 1);
- out_be32(&gur->rstcr, 0x2);
- break;
- default:
- break;
- }
-#endif
- return 0;
-}
-
-static int switch_cmd(struct cmd_tbl *cmdtp, int flag, int argc,
- char *const argv[])
-{
- if (argc < 2)
- return CMD_RET_USAGE;
- if (!strcmp(argv[1], "bank0"))
- t1023rdb_ctrl(I2C_SET_BANK0);
- else if (!strcmp(argv[1], "bank4") || !strcmp(argv[1], "altbank"))
- t1023rdb_ctrl(I2C_SET_BANK4);
- else if (!strcmp(argv[1], "sd"))
- t1023rdb_ctrl(GPIO1_SD_SEL);
- else if (!strcmp(argv[1], "emmc"))
- t1023rdb_ctrl(GPIO1_EMMC_SEL);
- else
- return CMD_RET_USAGE;
- return 0;
-}
-
-U_BOOT_CMD(
- switch, 2, 0, switch_cmd,
- "for bank0/bank4/sd/emmc switch control in runtime",
- "command (e.g. switch bank4)"
-);
-#endif
diff --git a/board/freescale/t102xrdb/t102xrdb.h b/board/freescale/t102xrdb/t102xrdb.h
deleted file mode 100644
index 5d46014823..0000000000
--- a/board/freescale/t102xrdb/t102xrdb.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- */
-
-#ifndef __T1024_RDB_H__
-#define __T1024_RDB_H__
-
-void fdt_fixup_board_enet(void *blob);
-void pci_of_setup(void *blob, bd_t *bd);
-#ifdef CONFIG_TARGET_T1023RDB
-static u32 t1023rdb_ctrl(u32 ctrl_type);
-static void fdt_enable_nor(void *blob);
-#endif
-#endif
diff --git a/board/freescale/t102xrdb/tlb.c b/board/freescale/t102xrdb/tlb.c
deleted file mode 100644
index 97080eb95e..0000000000
--- a/board/freescale/t102xrdb/tlb.c
+++ /dev/null
@@ -1,116 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
- /* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
-
- /* TLB 1 */
- /* *I*** - Covers boot page */
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
- /*
- * *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the
- * SRAM is at 0xfffc0000, it covered the 0xfffff000.
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_256K, 1),
-#else
- SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_4K, 1),
-#endif
-
- /* *I*G* - CCSRBAR */
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 1, BOOKE_PAGESZ_16M, 1),
-
- /* *I*G* - Flash, localbus */
- /* This will be changed to *I*G* after relocation to RAM. */
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
- MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
- 0, 2, BOOKE_PAGESZ_256M, 1),
-
-#ifndef CONFIG_SPL_BUILD
- /* *I*G* - PCI */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 3, BOOKE_PAGESZ_1G, 1),
-
- /* *I*G* - PCI I/O */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 4, BOOKE_PAGESZ_256K, 1),
-
- /* Bman/Qman */
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
- SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 5, BOOKE_PAGESZ_16M, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
- CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 6, BOOKE_PAGESZ_16M, 1),
-#endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
- SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 7, BOOKE_PAGESZ_16M, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
- CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 8, BOOKE_PAGESZ_16M, 1),
-#endif
-#endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
- SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 9, BOOKE_PAGESZ_4M, 1),
-#endif
-#ifdef CONFIG_SYS_NAND_BASE
- SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 10, BOOKE_PAGESZ_64K, 1),
-#endif
-#ifdef CONFIG_SYS_CPLD_BASE
- SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 11, BOOKE_PAGESZ_256K, 1),
-#endif
-
-#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
- SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
- 0, 12, BOOKE_PAGESZ_1G, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
- CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
- 0, 13, BOOKE_PAGESZ_1G, 1)
-#endif
- /* entry 14 and 15 has been used hard coded, they will be disabled
- * in cpu_init_f, so if needed more, will use entry 16 later.
- */
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/configs/T1023RDB_NAND_defconfig b/configs/T1023RDB_NAND_defconfig
deleted file mode 100644
index 75604383c6..0000000000
--- a/configs/T1023RDB_NAND_defconfig
+++ /dev/null
@@ -1,77 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x30001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x140000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T1023RDB=y
-CONFIG_SYS_CUSTOM_LDSCRIPT=y
-CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_NAND_BOOT=y
-CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_SYS_ALT_MEMTEST=y
-CONFIG_SYS_MEMTEST_START=0x00200000
-CONFIG_SYS_MEMTEST_END=0x00400000
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.1"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_AQUANTIA=y
-CONFIG_PHY_REALTEK=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T1023RDB_SDCARD_defconfig b/configs/T1023RDB_SDCARD_defconfig
deleted file mode 100644
index 4471c83f3f..0000000000
--- a/configs/T1023RDB_SDCARD_defconfig
+++ /dev/null
@@ -1,74 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x30001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T1023RDB=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_MMC_BOOT=y
-CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_SYS_ALT_MEMTEST=y
-CONFIG_SYS_MEMTEST_START=0x00200000
-CONFIG_SYS_MEMTEST_END=0x00400000
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.1"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_AQUANTIA=y
-CONFIG_PHY_REALTEK=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T1023RDB_SECURE_BOOT_defconfig b/configs/T1023RDB_SECURE_BOOT_defconfig
deleted file mode 100644
index 34fe6e5e52..0000000000
--- a/configs/T1023RDB_SECURE_BOOT_defconfig
+++ /dev/null
@@ -1,64 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T1023RDB=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_SYS_ALT_MEMTEST=y
-CONFIG_SYS_MEMTEST_START=0x00200000
-CONFIG_SYS_MEMTEST_END=0x00400000
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.1"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_AQUANTIA=y
-CONFIG_PHY_REALTEK=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T1023RDB_SPIFLASH_defconfig b/configs/T1023RDB_SPIFLASH_defconfig
deleted file mode 100644
index 599aeec688..0000000000
--- a/configs/T1023RDB_SPIFLASH_defconfig
+++ /dev/null
@@ -1,77 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x30001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T1023RDB=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_SPI_BOOT=y
-CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_SYS_ALT_MEMTEST=y
-CONFIG_SYS_MEMTEST_START=0x00200000
-CONFIG_SYS_MEMTEST_END=0x00400000
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.1"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_ADDR=0xFFFC9000
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_AQUANTIA=y
-CONFIG_PHY_REALTEK=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T1023RDB_defconfig b/configs/T1023RDB_defconfig
deleted file mode 100644
index 62cc129a31..0000000000
--- a/configs/T1023RDB_defconfig
+++ /dev/null
@@ -1,61 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T1023RDB=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_SYS_ALT_MEMTEST=y
-CONFIG_SYS_MEMTEST_START=0x00200000
-CONFIG_SYS_MEMTEST_END=0x00400000
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.1"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_AQUANTIA=y
-CONFIG_PHY_REALTEK=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig
deleted file mode 100644
index 9b116548a7..0000000000
--- a/configs/T1024RDB_NAND_defconfig
+++ /dev/null
@@ -1,86 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x30001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T1024RDB=y
-CONFIG_SYS_CUSTOM_LDSCRIPT=y
-CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL"
-CONFIG_BOOTDELAY=10
-CONFIG_SILENT_CONSOLE=y
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_NAND_BOOT=y
-CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_SYS_ALT_MEMTEST=y
-CONFIG_SYS_MEMTEST_START=0x00200000
-CONFIG_SYS_MEMTEST_END=0x00400000
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.1"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="t1024rdb"
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_SYS_FSL_DDR3=y
-CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_AQUANTIA=y
-CONFIG_PHY_REALTEK=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
-CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
diff --git a/configs/T1024RDB_SDCARD_defconfig b/configs/T1024RDB_SDCARD_defconfig
deleted file mode 100644
index 5e087fe2f3..0000000000
--- a/configs/T1024RDB_SDCARD_defconfig
+++ /dev/null
@@ -1,83 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x30001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T1024RDB=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD"
-CONFIG_BOOTDELAY=10
-CONFIG_SILENT_CONSOLE=y
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_MMC_BOOT=y
-CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_SYS_ALT_MEMTEST=y
-CONFIG_SYS_MEMTEST_START=0x00200000
-CONFIG_SYS_MEMTEST_END=0x00400000
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.1"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="t1024rdb"
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_SYS_FSL_DDR3=y
-CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_AQUANTIA=y
-CONFIG_PHY_REALTEK=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
-CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
diff --git a/configs/T1024RDB_SECURE_BOOT_defconfig b/configs/T1024RDB_SECURE_BOOT_defconfig
deleted file mode 100644
index f23f021143..0000000000
--- a/configs/T1024RDB_SECURE_BOOT_defconfig
+++ /dev/null
@@ -1,66 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T1024RDB=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_SILENT_CONSOLE=y
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_SYS_ALT_MEMTEST=y
-CONFIG_SYS_MEMTEST_START=0x00200000
-CONFIG_SYS_MEMTEST_END=0x00400000
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.1"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_SYS_FSL_DDR3=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_AQUANTIA=y
-CONFIG_PHY_REALTEK=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T1024RDB_SPIFLASH_defconfig b/configs/T1024RDB_SPIFLASH_defconfig
deleted file mode 100644
index 39b4537e71..0000000000
--- a/configs/T1024RDB_SPIFLASH_defconfig
+++ /dev/null
@@ -1,86 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x30001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T1024RDB=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH"
-CONFIG_BOOTDELAY=10
-CONFIG_SILENT_CONSOLE=y
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_SPI_BOOT=y
-CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_SYS_ALT_MEMTEST=y
-CONFIG_SYS_MEMTEST_START=0x00200000
-CONFIG_SYS_MEMTEST_END=0x00400000
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.1"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="t1024rdb"
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_ADDR=0xFFFC9000
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_SYS_FSL_DDR3=y
-CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_AQUANTIA=y
-CONFIG_PHY_REALTEK=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
-CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
diff --git a/configs/T1024RDB_defconfig b/configs/T1024RDB_defconfig
deleted file mode 100644
index 8ff2fe3f0c..0000000000
--- a/configs/T1024RDB_defconfig
+++ /dev/null
@@ -1,71 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T1024RDB=y
-CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_SILENT_CONSOLE=y
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_SYS_ALT_MEMTEST=y
-CONFIG_SYS_MEMTEST_START=0x00200000
-CONFIG_SYS_MEMTEST_END=0x00400000
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.1"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="t1024rdb"
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_SYS_FSL_DDR3=y
-CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_AQUANTIA=y
-CONFIG_PHY_REALTEK=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h
deleted file mode 100644
index f5d9657444..0000000000
--- a/include/configs/T102xRDB.h
+++ /dev/null
@@ -1,721 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2020 NXP
- */
-
-/*
- * T1024/T1023 RDB board configuration file
- */
-
-#ifndef __T1024RDB_H
-#define __T1024RDB_H
-
-#include <linux/stringify.h>
-
-/* High Level Configuration Options */
-#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
-#define CONFIG_ENABLE_36BIT_PHYS
-
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_ADDR_MAP 1
-#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
-#endif
-
-#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
-#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
-
-#define CONFIG_ENV_OVERWRITE
-
-/* support deep sleep */
-#ifdef CONFIG_ARCH_T1024
-#define CONFIG_DEEP_SLEEP
-#endif
-
-#ifdef CONFIG_RAMBOOT_PBL
-#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg
-#define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_PAD_TO 0x40000
-#define CONFIG_SPL_MAX_SIZE 0x28000
-#define RESET_VECTOR_OFFSET 0x27FFC
-#define BOOT_PAGE_OFFSET 0x27000
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SPL_SKIP_RELOCATE
-#define CONFIG_SPL_COMMON_INIT_DDR
-#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
-#endif
-
-#ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
-#define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
-#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
-#if defined(CONFIG_TARGET_T1024RDB)
-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_nand_rcw.cfg
-#elif defined(CONFIG_TARGET_T1023RDB)
-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_nand_rcw.cfg
-#endif
-#endif
-
-#ifdef CONFIG_SPIFLASH
-#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
-#define CONFIG_SPL_SPI_FLASH_MINIMAL
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_SYS_MPC85XX_NO_RESETVEC
-#endif
-#if defined(CONFIG_TARGET_T1024RDB)
-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_spi_rcw.cfg
-#elif defined(CONFIG_TARGET_T1023RDB)
-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_spi_rcw.cfg
-#endif
-#endif
-
-#ifdef CONFIG_SDCARD
-#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
-#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
-#define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000)
-#define CONFIG_SYS_MMC_U_BOOT_START (0x30000000)
-#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_SYS_MPC85XX_NO_RESETVEC
-#endif
-#if defined(CONFIG_TARGET_T1024RDB)
-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_sd_rcw.cfg
-#elif defined(CONFIG_TARGET_T1023RDB)
-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_sd_rcw.cfg
-#endif
-#endif
-
-#endif /* CONFIG_RAMBOOT_PBL */
-
-#ifndef CONFIG_RESET_VECTOR_ADDRESS
-#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
-#endif
-
-/* PCIe Boot - Master */
-#define CONFIG_SRIO_PCIE_BOOT_MASTER
-/*
- * for slave u-boot IMAGE instored in master memory space,
- * PHYS must be aligned based on the SIZE
- */
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
-#else
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
-#endif
-/*
- * for slave UCODE and ENV instored in master memory space,
- * PHYS must be aligned based on the SIZE
- */
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
-#else
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000
-#endif
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
-/* slave core release by master*/
-#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
-#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
-
-/* PCIe Boot - Slave */
-#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
-#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
-#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
- (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
-/* Set 1M boot space for PCIe boot */
-#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
-#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
- (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
-#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
-#endif
-
-#if defined(CONFIG_SPIFLASH)
-#elif defined(CONFIG_SDCARD)
-#define CONFIG_SYS_MMC_ENV_DEV 0
-#endif
-
-#ifndef __ASSEMBLY__
-unsigned long get_board_sys_clk(void);
-unsigned long get_board_ddr_clk(void);
-#endif
-
-#define CONFIG_SYS_CLK_FREQ 100000000
-#define CONFIG_DDR_CLK_FREQ 100000000
-
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_SYS_CACHE_STASHING
-#define CONFIG_BACKSIDE_L2_CACHE
-#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
-#define CONFIG_BTB /* toggle branch predition */
-#define CONFIG_DDR_ECC
-#ifdef CONFIG_DDR_ECC
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
-#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
-#endif
-
-/*
- * Config the L3 Cache as L3 SRAM
- */
-#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
-#define CONFIG_SYS_L3_SIZE (256 << 10)
-#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
-#define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
-#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
-#define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
-#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
-
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_DCSRBAR 0xf0000000
-#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
-#endif
-
-/* EEPROM */
-#define CONFIG_ID_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#define CONFIG_SYS_EEPROM_BUS_NUM 0
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
-
-/*
- * DDR Setup
- */
-#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
-#if defined(CONFIG_TARGET_T1024RDB)
-#define CONFIG_DDR_SPD
-#define CONFIG_SYS_SPD_BUS_NUM 0
-#define SPD_EEPROM_ADDRESS 0x51
-#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
-#elif defined(CONFIG_TARGET_T1023RDB)
-#define CONFIG_SYS_DDR_RAW_TIMING
-#define CONFIG_SYS_SDRAM_SIZE 2048
-#endif
-
-/*
- * IFC Definitions
- */
-#define CONFIG_SYS_FLASH_BASE 0xe8000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
-#else
-#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
-#endif
-
-#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
-#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
- CSPR_PORT_SIZE_16 | \
- CSPR_MSEL_NOR | \
- CSPR_V)
-#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
-
-/* NOR Flash Timing Params */
-#if defined(CONFIG_TARGET_T1024RDB)
-#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
-#elif defined(CONFIG_TARGET_T1023RDB)
-#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(0) | \
- CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN)
-#endif
-#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
- FTIM0_NOR_TEADC(0x5) | \
- FTIM0_NOR_TEAHC(0x5))
-#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
- FTIM1_NOR_TRAD_NOR(0x1A) |\
- FTIM1_NOR_TSEQRAD_NOR(0x13))
-#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
- FTIM2_NOR_TCH(0x4) | \
- FTIM2_NOR_TWPH(0x0E) | \
- FTIM2_NOR_TWP(0x1c))
-#define CONFIG_SYS_NOR_FTIM3 0x0
-
-#define CONFIG_SYS_FLASH_QUIET_TEST
-#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
-
-#ifdef CONFIG_TARGET_T1024RDB
-/* CPLD on IFC */
-#define CONFIG_SYS_CPLD_BASE 0xffdf0000
-#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
-#define CONFIG_SYS_CSPR2_EXT (0xf)
-#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
- | CSPR_PORT_SIZE_8 \
- | CSPR_MSEL_GPCM \
- | CSPR_V)
-#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
-#define CONFIG_SYS_CSOR2 0x0
-
-/* CPLD Timing parameters for IFC CS2 */
-#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
- FTIM0_GPCM_TEADC(0x0e) | \
- FTIM0_GPCM_TEAHC(0x0e))
-#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
- FTIM1_GPCM_TRAD(0x1f))
-#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
- FTIM2_GPCM_TCH(0x8) | \
- FTIM2_GPCM_TWP(0x1f))
-#define CONFIG_SYS_CS2_FTIM3 0x0
-#endif
-
-/* NAND Flash on IFC */
-#define CONFIG_NAND_FSL_IFC
-#define CONFIG_SYS_NAND_BASE 0xff800000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
-#else
-#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
-#endif
-#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
-#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
- | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
- | CSPR_MSEL_NAND /* MSEL = NAND */ \
- | CSPR_V)
-#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
-
-#if defined(CONFIG_TARGET_T1024RDB)
-#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
- | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
- | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
- | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
- | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
- | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
- | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
-#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
-#elif defined(CONFIG_TARGET_T1023RDB)
-#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
- | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
- | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
- | CSOR_NAND_RAL_3 /* RAL 3Bytes */ \
- | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
- | CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \
- | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
-#endif
-
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-/* ONFI NAND Flash mode0 Timing Params */
-#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
- FTIM0_NAND_TWP(0x18) | \
- FTIM0_NAND_TWCHT(0x07) | \
- FTIM0_NAND_TWH(0x0a))
-#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
- FTIM1_NAND_TWBE(0x39) | \
- FTIM1_NAND_TRR(0x0e) | \
- FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
- FTIM2_NAND_TREH(0x0a) | \
- FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3 0x0
-
-#define CONFIG_SYS_NAND_DDR_LAW 11
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-
-#if defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
-#else
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
-#endif
-
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
-#else
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#endif
-
-#if defined(CONFIG_RAMBOOT_PBL)
-#define CONFIG_SYS_RAMBOOT
-#endif
-
-#define CONFIG_HWCONFIG
-
-/* define to use L1 as initial stack */
-#define CONFIG_L1_INIT_RAM
-#define CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
-/* The assembler doesn't like typecast */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
- ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
- CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
-#else
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
-#endif
-#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
-
-/* Serial Port */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
-#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
-#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
-
-/* Video */
-#undef CONFIG_FSL_DIU_FB /* RDB doesn't support DIU */
-#ifdef CONFIG_FSL_DIU_FB
-#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_VIDEO_BMP_LOGO
-#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
-/*
- * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
- * disable empty flash sector detection, which is I/O-intensive.
- */
-#undef CONFIG_SYS_FLASH_EMPTY_INFO
-#endif
-
-/* I2C */
-#ifndef CONFIG_DM_I2C
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
-#else
-#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
-#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
-#endif
-
-#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
-#define I2C_PCA6408_BUS_NUM 1
-#define I2C_PCA6408_ADDR 0x20
-
-/* I2C bus multiplexer */
-#define I2C_MUX_CH_DEFAULT 0x8
-
-/*
- * RTC configuration
- */
-#define RTC
-#define CONFIG_RTC_DS1337 1
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-
-/*
- * eSPI - Enhanced SPI
- */
-
-/*
- * General PCIe
- * Memory space is mapped 1-1, but I/O space must start from 0.
- */
-#define CONFIG_PCIE1 /* PCIE controller 1 */
-#define CONFIG_PCIE2 /* PCIE controller 2 */
-#define CONFIG_PCIE3 /* PCIE controller 3 */
-#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
-
-#ifdef CONFIG_PCI
-/* controller 1, direct to uli, tgtid 3, Base address 20000 */
-#ifdef CONFIG_PCIE1
-#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
-#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
-#endif
-
-/* controller 2, Slot 2, tgtid 2, Base address 201000 */
-#ifdef CONFIG_PCIE2
-#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
-#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
-#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
-#endif
-
-/* controller 3, Slot 1, tgtid 1, Base address 202000 */
-#ifdef CONFIG_PCIE3
-#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
-#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
-#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
-#endif
-
-#if !defined(CONFIG_DM_PCI)
-#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
-#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#endif
-
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#endif /* CONFIG_PCI */
-
-/*
- * USB
- */
-#define CONFIG_HAS_FSL_DR_USB
-
-#ifdef CONFIG_HAS_FSL_DR_USB
-#define CONFIG_USB_EHCI_FSL
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#endif
-
-/*
- * SDHC
- */
-#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
-#endif
-
-/* Qman/Bman */
-#ifndef CONFIG_NOBQFMAN
-#define CONFIG_SYS_BMAN_NUM_PORTALS 10
-#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
-#else
-#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
-#endif
-#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
-#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
-#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
-#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
-#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
- CONFIG_SYS_BMAN_CENA_SIZE)
-#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
-#define CONFIG_SYS_QMAN_NUM_PORTALS 10
-#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
-#else
-#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
-#endif
-#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
-#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
-#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
-#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
-#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
- CONFIG_SYS_QMAN_CENA_SIZE)
-#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
-
-#define CONFIG_SYS_DPAA_FMAN
-
-/* Default address of microcode for the Linux FMan driver */
-#if defined(CONFIG_SPIFLASH)
-/*
- * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
- * env, so we got 0x110000.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
-#define CONFIG_SYS_QE_FW_ADDR 0x130000
-#elif defined(CONFIG_SDCARD)
-/*
- * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
- * about 1MB (2048 blocks), Env is stored after the image, and the env size is
- * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
- */
-#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
-#define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
-#elif defined(CONFIG_MTD_RAW_NAND)
-#if defined(CONFIG_TARGET_T1024RDB)
-#define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
-#define CONFIG_SYS_QE_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
-#elif defined(CONFIG_TARGET_T1023RDB)
-#define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
-#define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
-#endif
-#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
-/*
- * Slave has no ucode locally, it can fetch this from remote. When implementing
- * in two corenet boards, slave's ucode could be stored in master's memory
- * space, the address can be mapped from slave TLB->slave LAW->
- * slave SRIO or PCIE outbound window->master inbound window->
- * master LAW->the ucode address in master's memory space.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
-#else
-#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
-#define CONFIG_SYS_QE_FW_ADDR 0xEFE00000
-#endif
-#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
-#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
-#endif /* CONFIG_NOBQFMAN */
-
-#ifdef CONFIG_SYS_DPAA_FMAN
-#if defined(CONFIG_TARGET_T1024RDB)
-#define RGMII_PHY1_ADDR 0x2
-#define RGMII_PHY2_ADDR 0x6
-#define SGMII_AQR_PHY_ADDR 0x2
-#define FM1_10GEC1_PHY_ADDR 0x1
-#elif defined(CONFIG_TARGET_T1023RDB)
-#define RGMII_PHY1_ADDR 0x1
-#define SGMII_RTK_PHY_ADDR 0x3
-#define SGMII_AQR_PHY_ADDR 0x2
-#endif
-#endif
-
-#ifdef CONFIG_FMAN_ENET
-#define CONFIG_ETHPRIME "FM1 at DTSEC4"
-#endif
-
-/*
- * Dynamic MTD Partition support with mtdparts
- */
-
-/*
- * Environment
- */
-#define CONFIG_LOADS_ECHO /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 64 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
-#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-#define CONFIG_ROOTPATH "/opt/nfsroot"
-#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
-#define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */
-#define __USB_PHY_TYPE utmi
-
-#ifdef CONFIG_ARCH_T1024
-#define CONFIG_BOARDNAME t1024rdb
-#define BANK_INTLV cs0_cs1
-#else
-#define CONFIG_BOARDNAME t1023rdb
-#define BANK_INTLV null
-#endif
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
- "bank_intlv=" __stringify(BANK_INTLV) "\0" \
- "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
- "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \
- "fdtfile=" __stringify(CONFIG_BOARDNAME) "/" \
- __stringify(CONFIG_BOARDNAME) ".dtb\0" \
- "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
- "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
- "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
- "netdev=eth0\0" \
- "tftpflash=tftpboot $loadaddr $uboot && " \
- "protect off $ubootaddr +$filesize && " \
- "erase $ubootaddr +$filesize && " \
- "cp.b $loadaddr $ubootaddr $filesize && " \
- "protect on $ubootaddr +$filesize && " \
- "cmp.b $loadaddr $ubootaddr $filesize\0" \
- "consoledev=ttyS0\0" \
- "ramdiskaddr=2000000\0" \
- "fdtaddr=1e00000\0" \
- "bdev=sda3\0"
-
-#define CONFIG_LINUX \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "setenv ramdiskaddr 0x02000000;" \
- "setenv fdtaddr 0x00c00000;" \
- "setenv loadaddr 0x1000000;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND CONFIG_LINUX
-
-#include <asm/fsl_secure_boot.h>
-
-#endif /* __T1024RDB_H */
--
2.25.1
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 13/24] arm: Remove configs/T1024QDS_DDR4_SECURE_BOOT_defconfig board
2020-05-27 16:46 [PATCH 00/24] spi: dm-conversion (part2) Jagan Teki
` (11 preceding siblings ...)
2020-05-27 16:46 ` [PATCH 12/24] arm: Remove configs/T1023RDB_NAND_defconfig board Jagan Teki
@ 2020-05-27 16:46 ` Jagan Teki
2020-05-28 7:10 ` Priyanka Jain
2020-05-27 16:46 ` [PATCH 14/24] arm: Remove configs/T1040D4RDB_NAND_defconfig board Jagan Teki
` (9 subsequent siblings)
22 siblings, 1 reply; 59+ messages in thread
From: Jagan Teki @ 2020-05-27 16:46 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_SPI by the deadline.
Remove it.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
arch/powerpc/cpu/mpc85xx/Kconfig | 1 -
board/freescale/t102xqds/Kconfig | 14 -
board/freescale/t102xqds/MAINTAINERS | 12 -
board/freescale/t102xqds/Makefile | 15 -
board/freescale/t102xqds/README | 328 ---------
board/freescale/t102xqds/ddr.c | 195 -----
board/freescale/t102xqds/eth_t102xqds.c | 445 ------------
board/freescale/t102xqds/law.c | 31 -
board/freescale/t102xqds/pci.c | 23 -
board/freescale/t102xqds/spl.c | 156 ----
board/freescale/t102xqds/t1024_nand_rcw.cfg | 10 -
board/freescale/t102xqds/t1024_pbi.cfg | 26 -
board/freescale/t102xqds/t1024_sd_rcw.cfg | 10 -
board/freescale/t102xqds/t1024_spi_rcw.cfg | 10 -
board/freescale/t102xqds/t102xqds.c | 497 -------------
board/freescale/t102xqds/t102xqds.h | 14 -
board/freescale/t102xqds/t102xqds_qixis.h | 63 --
board/freescale/t102xqds/tlb.c | 116 ---
configs/T1024QDS_DDR4_SECURE_BOOT_defconfig | 69 --
configs/T1024QDS_DDR4_defconfig | 64 --
configs/T1024QDS_NAND_defconfig | 83 ---
configs/T1024QDS_SDCARD_defconfig | 80 ---
configs/T1024QDS_SECURE_BOOT_defconfig | 70 --
configs/T1024QDS_SPIFLASH_defconfig | 83 ---
configs/T1024QDS_defconfig | 67 --
include/configs/T102xQDS.h | 756 --------------------
26 files changed, 3238 deletions(-)
delete mode 100644 board/freescale/t102xqds/Kconfig
delete mode 100644 board/freescale/t102xqds/MAINTAINERS
delete mode 100644 board/freescale/t102xqds/Makefile
delete mode 100644 board/freescale/t102xqds/README
delete mode 100644 board/freescale/t102xqds/ddr.c
delete mode 100644 board/freescale/t102xqds/eth_t102xqds.c
delete mode 100644 board/freescale/t102xqds/law.c
delete mode 100644 board/freescale/t102xqds/pci.c
delete mode 100644 board/freescale/t102xqds/spl.c
delete mode 100644 board/freescale/t102xqds/t1024_nand_rcw.cfg
delete mode 100644 board/freescale/t102xqds/t1024_pbi.cfg
delete mode 100644 board/freescale/t102xqds/t1024_sd_rcw.cfg
delete mode 100644 board/freescale/t102xqds/t1024_spi_rcw.cfg
delete mode 100644 board/freescale/t102xqds/t102xqds.c
delete mode 100644 board/freescale/t102xqds/t102xqds.h
delete mode 100644 board/freescale/t102xqds/t102xqds_qixis.h
delete mode 100644 board/freescale/t102xqds/tlb.c
delete mode 100644 configs/T1024QDS_DDR4_SECURE_BOOT_defconfig
delete mode 100644 configs/T1024QDS_DDR4_defconfig
delete mode 100644 configs/T1024QDS_NAND_defconfig
delete mode 100644 configs/T1024QDS_SDCARD_defconfig
delete mode 100644 configs/T1024QDS_SECURE_BOOT_defconfig
delete mode 100644 configs/T1024QDS_SPIFLASH_defconfig
delete mode 100644 configs/T1024QDS_defconfig
delete mode 100644 include/configs/T102xQDS.h
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index deffa831dc..96ec6360c4 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -1599,7 +1599,6 @@ source "board/freescale/mpc8572ds/Kconfig"
source "board/freescale/p1023rdb/Kconfig"
source "board/freescale/p1_twr/Kconfig"
source "board/freescale/qemu-ppce500/Kconfig"
-source "board/freescale/t102xqds/Kconfig"
source "board/freescale/t1040qds/Kconfig"
source "board/freescale/t104xrdb/Kconfig"
source "board/freescale/t208xqds/Kconfig"
diff --git a/board/freescale/t102xqds/Kconfig b/board/freescale/t102xqds/Kconfig
deleted file mode 100644
index 87818a8d3a..0000000000
--- a/board/freescale/t102xqds/Kconfig
+++ /dev/null
@@ -1,14 +0,0 @@
-if TARGET_T1024QDS
-
-config SYS_BOARD
- default "t102xqds"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "T102xQDS"
-
-source "board/freescale/common/Kconfig"
-
-endif
diff --git a/board/freescale/t102xqds/MAINTAINERS b/board/freescale/t102xqds/MAINTAINERS
deleted file mode 100644
index 7e30e5f84b..0000000000
--- a/board/freescale/t102xqds/MAINTAINERS
+++ /dev/null
@@ -1,12 +0,0 @@
-T102XQDS BOARD
-#M: Shengzhou Liu <Shengzhou.Liu@freescale.com>
-S: Orphan (since 2018-05)
-F: board/freescale/t102xqds/
-F: include/configs/T102xQDS.h
-F: configs/T1024QDS_defconfig
-F: configs/T1024QDS_NAND_defconfig
-F: configs/T1024QDS_SDCARD_defconfig
-F: configs/T1024QDS_SPIFLASH_defconfig
-F: configs/T1024QDS_DDR4_defconfig
-F: configs/T1024QDS_SECURE_BOOT_defconfig
-F: configs/T1024QDS_DDR4_SECURE_BOOT_defconfig
diff --git a/board/freescale/t102xqds/Makefile b/board/freescale/t102xqds/Makefile
deleted file mode 100644
index ae872b46c3..0000000000
--- a/board/freescale/t102xqds/Makefile
+++ /dev/null
@@ -1,15 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2014 Freescale Semiconductor, Inc.
-
-ifdef CONFIG_SPL_BUILD
-obj-y += spl.o
-else
-obj-y += t102xqds.o
-obj-y += eth_t102xqds.o
-obj-$(CONFIG_PCI) += pci.o
-obj-$(CONFIG_FSL_DIU_FB) += ../t1040qds/diu.o
-endif
-obj-y += ddr.o
-obj-y += law.o
-obj-y += tlb.o
diff --git a/board/freescale/t102xqds/README b/board/freescale/t102xqds/README
deleted file mode 100644
index c00e3bafbe..0000000000
--- a/board/freescale/t102xqds/README
+++ /dev/null
@@ -1,328 +0,0 @@
-T1024 SoC Overview
-------------------
-The T1024/T1023 dual core and T1014/T1013 single core QorIQ communication processor
-combines two or one 64-bit Power Architecture e5500 core respectively with high
-performance datapath acceleration logic, and network peripheral bus interfaces
-required for networking and telecommunications. This processor can be used in
-applications such as enterprise WLAN access points, routers, switches, firewall
-and other packet processing intensive small enterprise and branch office appliances,
-and general-purpose embedded computing. Its high level of integration offers
-significant performance benefits and greatly helps to simplify board design.
-
-
-The T1024 SoC includes the following function and features:
-- two e5500 cores, each with a private 256 KB L2 cache
- - Up to 1.4 GHz with 64-bit ISA support (Power Architecture v2.06-compliant)
- - Three levels of instructions: User, supervisor, and hypervisor
- - Independent boot and reset
- - Secure boot capability
-- 256 KB shared L3 CoreNet platform cache (CPC)
-- Interconnect CoreNet platform
- - CoreNet coherency manager supporting coherent and noncoherent transactions
- with prioritization and bandwidth allocation amongst CoreNet endpoints
- - 150 Gbps coherent read bandwidth
-- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support
-- Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions:
- - Packet parsing, classification, and distribution
- - Queue management for scheduling, packet sequencing, and congestion management
- - Cryptography Acceleration (SEC 5.x)
- - IEEE 1588 support
- - Hardware buffer management for buffer allocation and deallocation
- - MACSEC on DPAA-based Ethernet ports
-- Ethernet interfaces
- - Four 1 Gbps Ethernet controllers
-- Parallel Ethernet interfaces
- - Two RGMII interfaces
-- High speed peripheral interfaces
- - Three PCI Express 2.0 controllers/ports running at up to 5 GHz
- - One SATA controller supporting 1.5 and 3.0 Gb/s operation
- - One QSGMII interface
- - Four SGMII interface supporting 1000 Mbps
- - Three SGMII interfaces supporting up to 2500 Mbps
- - 10GbE XFI or 10Base-KR interface
-- Additional peripheral interfaces
- - Two USB 2.0 controllers with integrated PHY
- - SD/eSDHC/eMMC
- - eSPI controller
- - Four I2C controllers
- - Four UARTs
- - Four GPIO controllers
- - Integrated flash controller (IFC)
- - LCD interface (DIU) with 12 bit dual data rate
-- Multicore programmable interrupt controller (PIC)
-- Two 8-channel DMA engines
-- Single source clocking implementation
-- Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
-- QUICC Engine block
- - 32-bit RISC controller for flexible support of the communications peripherals
- - Serial DMA channel for receive and transmit on all serial channels
- - Two universal communication controllers, supporting TDM, HDLC, and UART
-
-T1023 Personality
-------------------
-T1023 is a reduced personality of T1024 without QUICC Engine, DIU, and
-unavailable deep sleep. Rest of the blocks are almost same as T1024.
-Differences between T1024 and T1023
-Feature T1024 T1023
-QUICC Engine: yes no
-DIU: yes no
-Deep Sleep: yes no
-I2C controller: 4 3
-DDR: 64-bit 32-bit
-IFC: 32-bit 28-bit
-
-
-T1024QDS board Overview
------------------------
-- SERDES Connections
- 4 lanes supporting the following:
- - PCI Express: supports Gen 1 and Gen 2
- - SGMII 1G and SGMII 2.5G
- - QSGMII
- - XFI
- - SATA 2.0
- - High-speed multiplexers route the SerDes traffic to appropriate slots or connectors.
- - Aurora debug with dedicated connectors.
-- DDR Controller
- - Supports up to 1600 MTPS data-rate.
- - Supports one DDR4 or DDR3L module using DDR4 to DDR3L adapter card.
- - Supports Single-, dual- or quad-rank DIMMs
- - DDR power supplies 1.35V (DDR3L)/1.20V (DDR4) to all devices with automatic tracking of VTT.
-- IFC/Local Bus
- - NAND Flash: 8-bit, async, up to 2GB
- - NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB
- - NOR devices support 8 virtual banks
- - Socketed to allow alternate devices
- - GASIC: Simple (minimal) target within QIXIS FPGA
- - PromJET rapid memory download support
- - IFC Debug/Development card
-- Ethernet
- - Two on-board RGMII 10M/100M/1G ethernet ports.
- - One QSGMII interface
- - Four SGMII interface supporting 1Gbps
- - Three SGMII interfaces supporting 2.5Gbps
- - one 10Gbps XFI or 10Base-KR interface
-- QIXIS System Logic FPGA
- - Manages system power and reset sequencing.
- - Manages the configurations of DUT, board, and clock for dynamic shmoo.
- - Collects V-I-T data in background for code/power profiling.
- - Supports legacy TMT test features (POSt, IRS, SYSCLK-synchronous assertion).
- - General fault monitoring and logging.
- - Powered from ATX 'standby' power supply that allows continuous operation while rest of the system is off.
-- Clocks
- - System and DDR clock (SYSCLK, DDRCLK).
- - Switch selectable to one of 16 common settings in the interval of 64 MHz-166 MHz.
- - Software programmable in 1 MHz increments from 1-200 MHz.
- - SERDES clocks
- - Provides clocks to SerDes blocks and slots.
- - 100 MHz, 125 MHz and 156.25 MHz options.
- - Spread-spectrum option for 100 MHz.
-- Power Supplies
- - Dedicated PMBus regulator for VDD and VDDC.
- - Adjustable from 0.7V to 1.3V at 35A
- - VDD can be disabled independanty from VDDC for ?deep sleep?.
- - DDR3L/DDR4 power supply for GVDD: 1.35 or 1.20V at up to 22A.
- - VTT/MVREF automatically track operating voltage.
- - Dedicated 2.5V VPP supply.
- - Dedicated regulators/filters for AVDD supplies.
- - Dedicated regulators for other supplies, for example OVDD, CVDD, DVDD, LVDD, POVDD, and EVDD.
-- Video
- - DIU supports video up to 1280x1024x32 bpp.
- - Chrontel CH7201 for HDMI connection.
- - TI DS90C387R for direct LCD connection.
- - Raw (not encoded) video connector for testing or other encoders.
-- USB
- - Supports two USB 2.0 ports with integrated PHYs.
- - Two type A ports with 5V at 1.5A per port.
- - Second port can be converted to OTG mini-AB.
-- SDHC
- For T1024QDS, the SDHC port connects directly to an adapter card slot that has the following features:
- - upport for optional clock feedback paths.
- - Support for optional high-speed voltage translation direction controls.
- - Support for SD slots for: SD, SDHC (1x, 4x, 8x) and MMC.
- - Support for eMMC memory devices.
-- SPI
- -On-board support of 3 different devices and sizes.
-- Other IO
- - Two Serial ports
- - ProfiBus port
- - Four I2C ports
-
-
-Memory map on T1024QDS
-----------------------
-Start Address End Address Description Size
-0xF_FFDF_0000 0xF_FFDF_0FFF IFC - FPGA 4KB
-0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB
-0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB
-0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB
-0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB
-0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB
-0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB
-0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB
-0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB
-0xF_E000_0000 0xF_E7FF_FFFF Promjet 128MB
-0xF_0000_0000 0xF_003F_FFFF DCSR 4MB
-0xC_2000_0000 0xC_2FFF_FFFF PCI Express 3 Mem Space 256MB
-0xC_1000_0000 0xC_1FFF_FFFF PCI Express 2 Mem Space 256MB
-0xC_0000_0000 0xC_0FFF_FFFF PCI Express 1 Mem Space 256MB
-0x0_0000_0000 0x0_ffff_ffff DDR 4GB
-
-
-128MB NOR Flash memory Map
---------------------------
-Start Address End Address Definition Max size
-0xEFF40000 0xEFFFFFFF U-Boot (current bank) 768KB
-0xEFF20000 0xEFF3FFFF U-Boot env (current bank) 128KB
-0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB
-0xEFE00000 0xEFE3FFFF QE firmware (current bank) 256KB
-0xED300000 0xEFEFFFFF rootfs (alt bank) 44MB
-0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB
-0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB
-0xEC000000 0xEC01FFFF RCW (alt bank) 128KB
-0xEBF40000 0xEBFFFFFF U-Boot (alt bank) 768KB
-0xEBF20000 0xEBF3FFFF U-Boot env (alt bank) 128KB
-0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB
-0xEBE00000 0xEBE3FFFF QE firmware (alt bank) 256KB
-0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB
-0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 1MB
-0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB
-0xE8000000 0xE801FFFF RCW (current bank) 128KB
-
-
-SerDes clock vs DIP-switch settings
------------------------------------
-SRDS_PRTCL_S1 SD1_REF_CLK1 SD1_REF_CLK2 SW4[1:4]
-0x6F 100MHz 125MHz 1101
-0xD6 100MHz 100MHz 1111
-0x99 156.25MHz 100MHz 1011
-
-
-T1024 Clock frequency
-----------------------
-BIN Core DDR Platform FMan
-Bin1: 1400MHz 1600MT/s 400MHz 700MHz
-Bin2: 1200MHz 1600MT/s 400MHz 600MHz
-Bin3: 1000MHz 1600MT/s 400MHz 500MHz
-
-
-
-Software configurations and board settings
-------------------------------------------
-1. NOR boot:
- a. build NOR boot image
- $ make T1024QDS_defconfig (For DDR3L, by default)
- or make T1024QDS_D4_defconfig (For DDR4)
- $ make
- b. program u-boot.bin image to NOR flash
- => tftp 1000000 u-boot.bin
- => pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize
- set SW1[1:8] = '00010011', SW2[1] = '1', SW6[1:4] = '0000' for NOR boot
-
- Switching between default bank0 and alternate bank4 on NOR flash
- To change boot source to vbank4:
- via software: run command 'qixis_reset altbank' in U-Boot.
- via DIP-switch: set SW6[1:4] = '0100'
-
- To change boot source to vbank0:
- via software: run command 'qixis_reset' in U-Boot.
- via DIP-Switch: set SW6[1:4] = '0000'
-
-2. NAND Boot:
- a. build PBL image for NAND boot
- $ make T1024QDS_NAND_defconfig
- $ make
- b. program u-boot-with-spl-pbl.bin to NAND flash
- => tftp 1000000 u-boot-with-spl-pbl.bin
- => nand erase 0 $filesize
- => nand write 1000000 0 $filesize
- set SW1[1:8] = '10000010', SW2[1] = '0' and SW6[1:4] = '1001' for NAND boot
-
-3. SPI Boot:
- a. build PBL image for SPI boot
- $ make T1024QDS_SPIFLASH_defconfig
- $ make
- b. program u-boot-with-spl-pbl.bin to SPI flash
- => tftp 1000000 u-boot-with-spl-pbl.bin
- => sf probe 0
- => sf erase 0 f0000
- => sf write 1000000 0 $filesize
- set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot
-
-4. SD Boot:
- a. build PBL image for SD boot
- $ make T1024QDS_SDCARD_defconfig
- $ make
- b. program u-boot-with-spl-pbl.bin to SD/MMC card
- => tftp 1000000 u-boot-with-spl-pbl.bin
- => mmc write 1000000 8 0x800
- => tftp 1000000 fsl_fman_ucode_t1024_xx.bin
- => mmc write 1000000 0x820 80
- set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot
-
-
-DIU/QE-TDM/SDXC settings
--------------------
-a) For TDM Riser: set pin_mux=tdm in hwconfig
-b) For UCC(ProfiBus): set pin_mux=ucc in hwconfig
-c) For HDMI(DVI): set pin_mux=hdmi in hwconfig
-d) For LCD(DFP): set pin_mux=lcd in hwconfig
-e) For SDXC: set adaptor=sdxc in hwconfig
-
-2-stage NAND/SPI/SD boot loader
--------------------------------
-PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM.
-SPL further initializes DDR using SPD and environment variables
-and copy U-Boot(768 KB) from NAND/SPI/SD device to DDR.
-Finally SPL transers control to U-Boot for futher booting.
-
-SPL has following features:
- - Executes within 256K
- - No relocation required
-
-Run time view of SPL framework
--------------------------------------------------
-|Area | Address |
--------------------------------------------------
-|SecureBoot header | 0xFFFC0000 (32KB) |
--------------------------------------------------
-|GD, BD | 0xFFFC8000 (4KB) |
--------------------------------------------------
-|ENV | 0xFFFC9000 (8KB) |
--------------------------------------------------
-|HEAP | 0xFFFCB000 (30KB) |
--------------------------------------------------
-|STACK | 0xFFFD8000 (22KB) |
--------------------------------------------------
-|U-Boot SPL | 0xFFFD8000 (160KB) |
--------------------------------------------------
-
-NAND Flash memory Map on T1024QDS
--------------------------------------------------------------
-Start End Definition Size
-0x000000 0x0FFFFF U-Boot 1MB
-0x100000 0x15FFFF U-Boot env 8KB
-0x160000 0x17FFFF FMAN Ucode 128KB
-0x180000 0x19FFFF QE Firmware 128KB
-
-
-SD Card memory Map on T1024QDS
-----------------------------------------------------
-Block #blocks Definition Size
-0x008 2048 U-Boot img 1MB
-0x800 0016 U-Boot env 8KB
-0x820 0256 FMAN Ucode 128KB
-0x920 0256 QE Firmware 128KB
-
-
-SPI Flash memory Map on T1024QDS
-----------------------------------------------------
-Start End Definition Size
-0x000000 0x0FFFFF U-Boot img 1MB
-0x100000 0x101FFF U-Boot env 8KB
-0x110000 0x12FFFF FMAN Ucode 128KB
-0x130000 0x14FFFF QE Firmware 128KB
-
-
-For more details, please refer to T1024QDS Reference Manual and access
-website www.freescale.com and Freescale QorIQ SDK Infocenter document.
diff --git a/board/freescale/t102xqds/ddr.c b/board/freescale/t102xqds/ddr.c
deleted file mode 100644
index c27cecd5aa..0000000000
--- a/board/freescale/t102xqds/ddr.c
+++ /dev/null
@@ -1,195 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <hwconfig.h>
-#include <init.h>
-#include <log.h>
-#include <asm/mmu.h>
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-#include <asm/fsl_law.h>
-#include <asm/mpc85xx_gpio.h>
-#include <linux/delay.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-struct board_specific_parameters {
- u32 n_ranks;
- u32 datarate_mhz_high;
- u32 rank_gb;
- u32 clk_adjust;
- u32 wrlvl_start;
- u32 wrlvl_ctl_2;
- u32 wrlvl_ctl_3;
-};
-
-/*
- * datarate_mhz_high values need to be in ascending order
- */
-static const struct board_specific_parameters udimm0[] = {
- /*
- * memory controller 0
- * num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
- * ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
- */
-#if defined(CONFIG_SYS_FSL_DDR4)
- {2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,},
- {2, 1900, 0, 8, 6, 0x08080A0C, 0x0D0E0F0A,},
- {1, 1666, 0, 8, 6, 0x0708090B, 0x0C0D0E09,},
- {1, 1900, 0, 8, 6, 0x08080A0C, 0x0D0E0F0A,},
- {1, 2200, 0, 8, 7, 0x08090A0D, 0x0F0F100C,},
-#elif defined(CONFIG_SYS_FSL_DDR3)
- {2, 833, 0, 8, 6, 0x06060607, 0x08080807,},
- {2, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09,},
- {2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,},
- {1, 833, 0, 8, 6, 0x06060607, 0x08080807,},
- {1, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09,},
- {1, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,},
-#else
-#error DDR type not defined
-#endif
- {}
-};
-
-static const struct board_specific_parameters *udimms[] = {
- udimm0,
-};
-
-void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
- ulong ddr_freq;
- struct cpu_type *cpu = gd->arch.cpu;
-
- if (ctrl_num > 2) {
- printf("Not supported controller number %d\n", ctrl_num);
- return;
- }
- if (!pdimm->n_ranks)
- return;
-
- pbsp = udimms[0];
-
- /* Get clk_adjust according to the board ddr freqency and n_banks
- * specified in board_specific_parameters table.
- */
- ddr_freq = get_ddr_freq(0) / 1000000;
- while (pbsp->datarate_mhz_high) {
- if (pbsp->n_ranks == pdimm->n_ranks &&
- (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
- if (ddr_freq <= pbsp->datarate_mhz_high) {
- popts->clk_adjust = pbsp->clk_adjust;
- popts->wrlvl_start = pbsp->wrlvl_start;
- popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
- popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
- goto found;
- }
- pbsp_highest = pbsp;
- }
- pbsp++;
- }
-
- if (pbsp_highest) {
- printf("Error: board specific timing not found\n");
- printf("for data rate %lu MT/s\n", ddr_freq);
- printf("Trying to use the highest speed (%u) parameters\n",
- pbsp_highest->datarate_mhz_high);
- popts->clk_adjust = pbsp_highest->clk_adjust;
- popts->wrlvl_start = pbsp_highest->wrlvl_start;
- popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
- popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
- } else {
- panic("DIMM is not supported by this board");
- }
-found:
- debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
- pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);
- debug("\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, ",
- pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2);
- debug("wrlvl_ctrl_3 0x%x\n", pbsp->wrlvl_ctl_3);
-
- /*
- * Factors to consider for half-strength driver enable:
- * - number of DIMMs installed
- */
- popts->half_strength_driver_enable = 1;
- /*
- * Write leveling override
- */
- popts->wrlvl_override = 1;
- popts->wrlvl_sample = 0xf;
-
- /*
- * rtt and rtt_wr override
- */
- popts->rtt_override = 0;
-
- /* Enable ZQ calibration */
- popts->zq_en = 1;
-
- /* DHC_EN =1, ODT = 75 Ohm */
-#ifdef CONFIG_SYS_FSL_DDR4
- popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
- popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
- DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */
-#else
- popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
- popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
-
- /* optimize cpo for erratum A-009942 */
- popts->cpo_sample = 0x5f;
-#endif
-
- /* T1023 supports max DDR bus 32bit width, T1024 supports DDR 64bit,
- * set DDR bus width to 32bit for T1023
- */
- if (cpu->soc_ver == SVR_T1023)
- popts->data_bus_width = DDR_DATA_BUS_WIDTH_32;
-
-#ifdef CONFIG_FORCE_DDR_DATA_BUS_WIDTH_32
- /* for DDR bus 32bit test on T1024 */
- popts->data_bus_width = DDR_DATA_BUS_WIDTH_32;
-#endif
-}
-
-#if defined(CONFIG_DEEP_SLEEP)
-void board_mem_sleep_setup(void)
-{
- void __iomem *qixis_base = (void *)QIXIS_BASE;
-
- /* does not provide HW signals for power management */
- clrbits_8(qixis_base + 0x21, 0x2);
- /* Disable MCKE isolation */
- gpio_set_value(2, 0);
- udelay(1);
-}
-#endif
-
-int dram_init(void)
-{
- phys_size_t dram_size;
-
-#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
- puts("Initializing....using SPD\n");
- dram_size = fsl_ddr_sdram();
-#else
- /* DDR has been initialised by first stage boot loader */
- dram_size = fsl_ddr_sdram_size();
-#endif
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
-
-#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
- fsl_dp_resume();
-#endif
-
- gd->ram_size = dram_size;
-
- return 0;
-}
diff --git a/board/freescale/t102xqds/eth_t102xqds.c b/board/freescale/t102xqds/eth_t102xqds.c
deleted file mode 100644
index 49ea21a83a..0000000000
--- a/board/freescale/t102xqds/eth_t102xqds.c
+++ /dev/null
@@ -1,445 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- *
- * Shengzhou Liu <Shengzhou.Liu@freescale.com>
- */
-
-#include <common.h>
-#include <command.h>
-#include <fdt_support.h>
-#include <log.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/mmu.h>
-#include <asm/processor.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_law.h>
-#include <asm/fsl_serdes.h>
-#include <asm/fsl_portals.h>
-#include <asm/fsl_liodn.h>
-#include <malloc.h>
-#include <fm_eth.h>
-#include <fsl_mdio.h>
-#include <miiphy.h>
-#include <phy.h>
-#include <fsl_dtsec.h>
-#include <asm/fsl_serdes.h>
-#include "../common/qixis.h"
-#include "../common/fman.h"
-#include "t102xqds_qixis.h"
-
-#define EMI_NONE 0xFFFFFFFF
-#define EMI1_RGMII1 0
-#define EMI1_RGMII2 1
-#define EMI1_SLOT1 2
-#define EMI1_SLOT2 3
-#define EMI1_SLOT3 4
-#define EMI1_SLOT4 5
-#define EMI1_SLOT5 6
-#define EMI2 7
-
-static int mdio_mux[NUM_FM_PORTS];
-
-static const char * const mdio_names[] = {
- "T1024QDS_MDIO_RGMII1",
- "T1024QDS_MDIO_RGMII2",
- "T1024QDS_MDIO_SLOT1",
- "T1024QDS_MDIO_SLOT2",
- "T1024QDS_MDIO_SLOT3",
- "T1024QDS_MDIO_SLOT4",
- "T1024QDS_MDIO_SLOT5",
- "T1024QDS_MDIO_10GC",
- "NULL",
-};
-
-/* Map SerDes1 4 lanes to default slot, will be initialized dynamically */
-static u8 lane_to_slot[] = {2, 3, 4, 5};
-
-static const char *t1024qds_mdio_name_for_muxval(u8 muxval)
-{
- return mdio_names[muxval];
-}
-
-struct mii_dev *mii_dev_for_muxval(u8 muxval)
-{
- struct mii_dev *bus;
- const char *name;
-
- if (muxval > EMI2)
- return NULL;
-
- name = t1024qds_mdio_name_for_muxval(muxval);
-
- if (!name) {
- printf("No bus for muxval %x\n", muxval);
- return NULL;
- }
-
- bus = miiphy_get_dev_by_name(name);
-
- if (!bus) {
- printf("No bus by name %s\n", name);
- return NULL;
- }
-
- return bus;
-}
-
-struct t1024qds_mdio {
- u8 muxval;
- struct mii_dev *realbus;
-};
-
-static void t1024qds_mux_mdio(u8 muxval)
-{
- u8 brdcfg4;
-
- if (muxval < 7) {
- brdcfg4 = QIXIS_READ(brdcfg[4]);
- brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
- brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
- QIXIS_WRITE(brdcfg[4], brdcfg4);
- }
-}
-
-static int t1024qds_mdio_read(struct mii_dev *bus, int addr, int devad,
- int regnum)
-{
- struct t1024qds_mdio *priv = bus->priv;
-
- t1024qds_mux_mdio(priv->muxval);
-
- return priv->realbus->read(priv->realbus, addr, devad, regnum);
-}
-
-static int t1024qds_mdio_write(struct mii_dev *bus, int addr, int devad,
- int regnum, u16 value)
-{
- struct t1024qds_mdio *priv = bus->priv;
-
- t1024qds_mux_mdio(priv->muxval);
-
- return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
-}
-
-static int t1024qds_mdio_reset(struct mii_dev *bus)
-{
- struct t1024qds_mdio *priv = bus->priv;
-
- return priv->realbus->reset(priv->realbus);
-}
-
-static int t1024qds_mdio_init(char *realbusname, u8 muxval)
-{
- struct t1024qds_mdio *pmdio;
- struct mii_dev *bus = mdio_alloc();
-
- if (!bus) {
- printf("Failed to allocate t1024qds MDIO bus\n");
- return -1;
- }
-
- pmdio = malloc(sizeof(*pmdio));
- if (!pmdio) {
- printf("Failed to allocate t1024qds private data\n");
- free(bus);
- return -1;
- }
-
- bus->read = t1024qds_mdio_read;
- bus->write = t1024qds_mdio_write;
- bus->reset = t1024qds_mdio_reset;
- strcpy(bus->name, t1024qds_mdio_name_for_muxval(muxval));
-
- pmdio->realbus = miiphy_get_dev_by_name(realbusname);
-
- if (!pmdio->realbus) {
- printf("No bus with name %s\n", realbusname);
- free(bus);
- free(pmdio);
- return -1;
- }
-
- pmdio->muxval = muxval;
- bus->priv = pmdio;
- return mdio_register(bus);
-}
-
-void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
- enum fm_port port, int offset)
-{
- struct fixed_link f_link;
-
- if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_RGMII) {
- if (port == FM1_DTSEC3) {
- fdt_set_phy_handle(fdt, compat, addr, "rgmii_phy2");
- fdt_setprop_string(fdt, offset, "phy-connection-type",
- "rgmii");
- fdt_status_okay_by_alias(fdt, "emi1_rgmii1");
- }
- } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
- if (port == FM1_DTSEC1) {
- fdt_set_phy_handle(fdt, compat, addr,
- "sgmii_vsc8234_phy_s5");
- } else if (port == FM1_DTSEC2) {
- fdt_set_phy_handle(fdt, compat, addr,
- "sgmii_vsc8234_phy_s4");
- }
- } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) {
- if (port == FM1_DTSEC3) {
- fdt_set_phy_handle(fdt, compat, addr,
- "sgmii_aqr105_phy_s3");
- }
- } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) {
- switch (port) {
- case FM1_DTSEC1:
- fdt_set_phy_handle(fdt, compat, addr, "qsgmii_phy_p1");
- break;
- case FM1_DTSEC2:
- fdt_set_phy_handle(fdt, compat, addr, "qsgmii_phy_p2");
- break;
- case FM1_DTSEC3:
- fdt_set_phy_handle(fdt, compat, addr, "qsgmii_phy_p3");
- break;
- case FM1_DTSEC4:
- fdt_set_phy_handle(fdt, compat, addr, "qsgmii_phy_p4");
- break;
- default:
- break;
- }
- fdt_delprop(fdt, offset, "phy-connection-type");
- fdt_setprop_string(fdt, offset, "phy-connection-type",
- "qsgmii");
- fdt_status_okay_by_alias(fdt, "emi1_slot2");
- } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) {
- /* XFI interface */
- f_link.phy_id = port;
- f_link.duplex = 1;
- f_link.link_speed = 10000;
- f_link.pause = 0;
- f_link.asym_pause = 0;
- /* no PHY for XFI */
- fdt_delprop(fdt, offset, "phy-handle");
- fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));
- fdt_setprop_string(fdt, offset, "phy-connection-type", "xgmii");
- }
-}
-
-void fdt_fixup_board_enet(void *fdt)
-{
-}
-
-/*
- * This function reads RCW to check if Serdes1{A:D} is configured
- * to slot 1/2/3/4/5 and update the lane_to_slot[] array accordingly
- */
-static void initialize_lane_to_slot(void)
-{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- u32 srds_s1 = in_be32(&gur->rcwsr[4]) &
- FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
-
- srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
-
- switch (srds_s1) {
- case 0x46:
- case 0x47:
- lane_to_slot[1] = 2;
- break;
- default:
- break;
- }
-}
-
-int board_eth_init(bd_t *bis)
-{
-#if defined(CONFIG_FMAN_ENET)
- int i, idx, lane, slot, interface;
- struct memac_mdio_info dtsec_mdio_info;
- struct memac_mdio_info tgec_mdio_info;
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- u32 srds_s1;
-
- srds_s1 = in_be32(&gur->rcwsr[4]) &
- FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
- srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
-
- initialize_lane_to_slot();
-
- /* Initialize the mdio_mux array so we can recognize empty elements */
- for (i = 0; i < NUM_FM_PORTS; i++)
- mdio_mux[i] = EMI_NONE;
-
- dtsec_mdio_info.regs =
- (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
-
- dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
-
- /* Register the 1G MDIO bus */
- fm_memac_mdio_init(bis, &dtsec_mdio_info);
-
- tgec_mdio_info.regs =
- (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
- tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
-
- /* Register the 10G MDIO bus */
- fm_memac_mdio_init(bis, &tgec_mdio_info);
-
- /* Register the muxing front-ends to the MDIO buses */
- t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
- t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);
- t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
- t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
- t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
- t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
- t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
- t1024qds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
-
- /* Set the two on-board RGMII PHY address */
- fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR);
- fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY1_ADDR);
-
- switch (srds_s1) {
- case 0xd5:
- case 0xd6:
- /* QSGMII in Slot2 */
- fm_info_set_phy_address(FM1_DTSEC1, 0x8);
- fm_info_set_phy_address(FM1_DTSEC2, 0x9);
- fm_info_set_phy_address(FM1_DTSEC3, 0xa);
- fm_info_set_phy_address(FM1_DTSEC4, 0xb);
- break;
- case 0x95:
- case 0x99:
- /*
- * XFI does not need a PHY to work, but to avoid U-Boot use
- * default PHY address which is zero to a MAC when it found
- * a MAC has no PHY address, we give a PHY address to XFI
- * MAC, and should not use a real XAUI PHY address, since
- * MDIO can access it successfully, and then MDIO thinks the
- * XAUI card is used for the XFI MAC, which will cause error.
- */
- fm_info_set_phy_address(FM1_10GEC1, 4);
- fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
- break;
- case 0x6f:
- /* SGMII in Slot3, Slot4, Slot5 */
- fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_AQ_PHY_ADDR_S5);
- fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_AQ_PHY_ADDR_S4);
- fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT1_PHY_ADDR);
- break;
- case 0x7f:
- fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_AQ_PHY_ADDR_S5);
- fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_AQ_PHY_ADDR_S4);
- fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_AQ_PHY_ADDR_S3);
- break;
- case 0x47:
- fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
- break;
- case 0x77:
- fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_AQ_PHY_ADDR_S3);
- break;
- case 0x5a:
- fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
- break;
- case 0x6a:
- fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT1_PHY_ADDR);
- break;
- case 0x5b:
- fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
- break;
- case 0x6b:
- fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT1_PHY_ADDR);
- break;
- default:
- break;
- }
-
- for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
- idx = i - FM1_DTSEC1;
- interface = fm_info_get_enet_if(i);
- switch (interface) {
- case PHY_INTERFACE_MODE_SGMII:
- case PHY_INTERFACE_MODE_SGMII_2500:
- case PHY_INTERFACE_MODE_QSGMII:
- if (interface == PHY_INTERFACE_MODE_SGMII) {
- lane = serdes_get_first_lane(FSL_SRDS_1,
- SGMII_FM1_DTSEC1 + idx);
- } else if (interface == PHY_INTERFACE_MODE_SGMII_2500) {
- lane = serdes_get_first_lane(FSL_SRDS_1,
- SGMII_2500_FM1_DTSEC1 + idx);
- } else {
- lane = serdes_get_first_lane(FSL_SRDS_1,
- QSGMII_FM1_A);
- }
-
- if (lane < 0)
- break;
-
- slot = lane_to_slot[lane];
- debug("FM1@DTSEC%u expects SGMII in slot %u\n",
- idx + 1, slot);
- if (QIXIS_READ(present2) & (1 << (slot - 1)))
- fm_disable_port(i);
-
- switch (slot) {
- case 2:
- mdio_mux[i] = EMI1_SLOT2;
- fm_info_set_mdio(i, mii_dev_for_muxval(
- mdio_mux[i]));
- break;
- case 3:
- mdio_mux[i] = EMI1_SLOT3;
- fm_info_set_mdio(i, mii_dev_for_muxval(
- mdio_mux[i]));
- break;
- case 4:
- mdio_mux[i] = EMI1_SLOT4;
- fm_info_set_mdio(i, mii_dev_for_muxval(
- mdio_mux[i]));
- break;
- case 5:
- mdio_mux[i] = EMI1_SLOT5;
- fm_info_set_mdio(i, mii_dev_for_muxval(
- mdio_mux[i]));
- break;
- }
- break;
- case PHY_INTERFACE_MODE_RGMII:
- if (i == FM1_DTSEC3)
- mdio_mux[i] = EMI1_RGMII2;
- else if (i == FM1_DTSEC4)
- mdio_mux[i] = EMI1_RGMII1;
- fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
- break;
- default:
- break;
- }
- }
-
- for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
- idx = i - FM1_10GEC1;
- switch (fm_info_get_enet_if(i)) {
- case PHY_INTERFACE_MODE_XGMII:
- lane = serdes_get_first_lane(FSL_SRDS_1,
- XFI_FM1_MAC1 + idx);
- if (lane < 0)
- break;
- mdio_mux[i] = EMI2;
- fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
- break;
- default:
- break;
- }
- }
-
- cpu_eth_init(bis);
-#endif /* CONFIG_FMAN_ENET */
-
- return pci_eth_init(bis);
-}
diff --git a/board/freescale/t102xqds/law.c b/board/freescale/t102xqds/law.c
deleted file mode 100644
index d3c1dba934..0000000000
--- a/board/freescale/t102xqds/law.c
+++ /dev/null
@@ -1,31 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-struct law_entry law_table[] = {
-#ifdef CONFIG_MTD_NOR_FLASH
- SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
-#endif
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
- SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
-#endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
- SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
-#endif
-#ifdef QIXIS_BASE_PHYS
- SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
-#endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
- SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
-#endif
-#ifdef CONFIG_SYS_NAND_BASE_PHYS
- SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
-#endif
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/t102xqds/pci.c b/board/freescale/t102xqds/pci.c
deleted file mode 100644
index 1b1cc0483c..0000000000
--- a/board/freescale/t102xqds/pci.c
+++ /dev/null
@@ -1,23 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <init.h>
-#include <pci.h>
-#include <asm/fsl_pci.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <asm/fsl_serdes.h>
-
-void pci_init_board(void)
-{
- fsl_pcie_init_board(0);
-}
-
-void pci_of_setup(void *blob, bd_t *bd)
-{
- FT_FSL_PCI_SETUP;
-}
diff --git a/board/freescale/t102xqds/spl.c b/board/freescale/t102xqds/spl.c
deleted file mode 100644
index 9f4a43ed56..0000000000
--- a/board/freescale/t102xqds/spl.c
+++ /dev/null
@@ -1,156 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/* Copyright 2014 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <clock_legacy.h>
-#include <console.h>
-#include <env_internal.h>
-#include <init.h>
-#include <malloc.h>
-#include <ns16550.h>
-#include <nand.h>
-#include <i2c.h>
-#include <mmc.h>
-#include <fsl_esdhc.h>
-#include <spi_flash.h>
-#include "../common/qixis.h"
-#include "t102xqds_qixis.h"
-#include "../common/spl.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-phys_size_t get_effective_memsize(void)
-{
- return CONFIG_SYS_L3_SIZE;
-}
-
-unsigned long get_board_sys_clk(void)
-{
- u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
-
- switch (sysclk_conf & 0x0F) {
- case QIXIS_SYSCLK_83:
- return 83333333;
- case QIXIS_SYSCLK_100:
- return 100000000;
- case QIXIS_SYSCLK_125:
- return 125000000;
- case QIXIS_SYSCLK_133:
- return 133333333;
- case QIXIS_SYSCLK_150:
- return 150000000;
- case QIXIS_SYSCLK_160:
- return 160000000;
- case QIXIS_SYSCLK_166:
- return 166666666;
- }
- return 66666666;
-}
-
-unsigned long get_board_ddr_clk(void)
-{
- u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
-
- switch ((ddrclk_conf & 0x30) >> 4) {
- case QIXIS_DDRCLK_100:
- return 100000000;
- case QIXIS_DDRCLK_125:
- return 125000000;
- case QIXIS_DDRCLK_133:
- return 133333333;
- }
- return 66666666;
-}
-
-void board_init_f(ulong bootflag)
-{
- u32 plat_ratio, sys_clk, ccb_clk;
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
-#if defined(CONFIG_ARCH_T1040) && defined(CONFIG_SPL_NAND_BOOT)
- /*
- * There is T1040 SoC issue where NOR, FPGA are inaccessible during
- * NAND boot because IFC signals > IFC_AD7 are not enabled.
- * This workaround changes RCW source to make all signals enabled.
- */
- u32 porsr1, pinctl;
-#define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000
-
- porsr1 = in_be32(&gur->porsr1);
- pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK)) | 0x24800000);
- out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000), pinctl);
-#endif
-
- /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
- memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
-
- /* Update GD pointer */
- gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
-
- console_init_f();
-
- /* initialize selected port with appropriate baud rate */
- sys_clk = get_board_sys_clk();
- plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
- ccb_clk = sys_clk * plat_ratio / 2;
-
- NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
- ccb_clk / 16 / CONFIG_BAUDRATE);
-
-#if defined(CONFIG_SPL_MMC_BOOT)
- puts("\nSD boot...\n");
-#elif defined(CONFIG_SPL_SPI_BOOT)
- puts("\nSPI boot...\n");
-#elif defined(CONFIG_SPL_NAND_BOOT)
- puts("\nNAND boot...\n");
-#endif
-
- relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
- bd_t *bd;
-
- bd = (bd_t *)(gd + sizeof(gd_t));
- memset(bd, 0, sizeof(bd_t));
- gd->bd = bd;
- bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
- bd->bi_memsize = CONFIG_SYS_L3_SIZE;
-
- arch_cpu_init();
- get_clocks();
- mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
- CONFIG_SPL_RELOC_MALLOC_SIZE);
- gd->flags |= GD_FLG_FULL_MALLOC_INIT;
-
-#ifdef CONFIG_SPL_NAND_BOOT
- nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
- (uchar *)SPL_ENV_ADDR);
-#endif
-#ifdef CONFIG_SPL_MMC_BOOT
- mmc_initialize(bd);
- mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
- (uchar *)SPL_ENV_ADDR);
-#endif
-#ifdef CONFIG_SPL_SPI_BOOT
- fsl_spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
- (uchar *)SPL_ENV_ADDR);
-#endif
-
- gd->env_addr = (ulong)(SPL_ENV_ADDR);
- gd->env_valid = ENV_VALID;
-
- i2c_init_all();
-
- dram_init();
-
-#ifdef CONFIG_SPL_MMC_BOOT
- mmc_boot();
-#elif defined(CONFIG_SPL_SPI_BOOT)
- fsl_spi_boot();
-#elif defined(CONFIG_SPL_NAND_BOOT)
- nand_boot();
-#endif
-}
diff --git a/board/freescale/t102xqds/t1024_nand_rcw.cfg b/board/freescale/t102xqds/t1024_nand_rcw.cfg
deleted file mode 100644
index 4b8f7194dc..0000000000
--- a/board/freescale/t102xqds/t1024_nand_rcw.cfg
+++ /dev/null
@@ -1,10 +0,0 @@
-# single-source clock:Sys_Clock = DDR_Refclock = Diff_Sysclk = 100 MHz
-# Core/DDR/Platform/FMan = 1400MHz/1600MT/s/400MHz/700MHz
-
-# PBL preamble and RCW header for T1024QDS
-aa55aa55 010e0100
-# Serdes protocol 0x6F
-0810000e 00000000 00000000 00000000
-37800001 00000012 e8104000 21000000
-00000000 00000000 00000000 00030810
-00000000 036c5a00 00000000 00000006
diff --git a/board/freescale/t102xqds/t1024_pbi.cfg b/board/freescale/t102xqds/t1024_pbi.cfg
deleted file mode 100644
index 98efca25a2..0000000000
--- a/board/freescale/t102xqds/t1024_pbi.cfg
+++ /dev/null
@@ -1,26 +0,0 @@
-#PBI commands
-#Initialize CPC1
-09010000 00200400
-09138000 00000000
-091380c0 00000100
-#Configure CPC1 as 256KB SRAM
-09010100 00000000
-09010104 fffc0007
-09010f00 081e000d
-09010000 80000000
-#Configure LAW for CPC1
-09000cd0 00000000
-09000cd4 fffc0000
-09000cd8 81000011
-#Configure alternate space
-09000010 00000000
-09000014 ff000000
-09000018 81000000
-#Configure SPI controller
-09110000 80000403
-09110020 2d170008
-09110024 00100008
-09110028 00100008
-0911002c 00100008
-#Flush PBL data
-091380c0 000FFFFF
diff --git a/board/freescale/t102xqds/t1024_sd_rcw.cfg b/board/freescale/t102xqds/t1024_sd_rcw.cfg
deleted file mode 100644
index 3eca275db3..0000000000
--- a/board/freescale/t102xqds/t1024_sd_rcw.cfg
+++ /dev/null
@@ -1,10 +0,0 @@
-# single-source clock:Sys_Clock = DDR_Refclock = Diff_Sysclk = 100 MHz
-# Core/DDR/Platform/FMan = 1400MHz/1600MT/s/400MHz/700MHz
-
-# PBL preamble and RCW header for T1024QDS
-aa55aa55 010e0100
-# Serdes protocol 0x6F
-0810000e 00000000 00000000 00000000
-37800001 00000012 68104000 21000000
-00000000 00000000 00000000 00030810
-00000000 036c5a00 00000000 00000006
diff --git a/board/freescale/t102xqds/t1024_spi_rcw.cfg b/board/freescale/t102xqds/t1024_spi_rcw.cfg
deleted file mode 100644
index 1601e35fc8..0000000000
--- a/board/freescale/t102xqds/t1024_spi_rcw.cfg
+++ /dev/null
@@ -1,10 +0,0 @@
-# single-source clock:Sys_Clock = DDR_Refclock = Diff_Sysclk = 100 MHz
-# Core/DDR/Platform/FMan = 1400MHz/1600MT/s/400MHz/700MHz
-
-# PBL preamble and RCW header for T1024QDS
-aa55aa55 010e0100
-# Serdes protocol 0x6F
-0810000e 00000000 00000000 00000000
-37800001 00000012 58104000 21000000
-00000000 00000000 00000000 00030810
-00000000 036c5a00 00000000 00000006
diff --git a/board/freescale/t102xqds/t102xqds.c b/board/freescale/t102xqds/t102xqds.c
deleted file mode 100644
index 84db2fa9bc..0000000000
--- a/board/freescale/t102xqds/t102xqds.c
+++ /dev/null
@@ -1,497 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2020 NXP
- */
-
-#include <common.h>
-#include <command.h>
-#include <env.h>
-#include <fdt_support.h>
-#include <i2c.h>
-#include <image.h>
-#include <init.h>
-#include <log.h>
-#include <netdev.h>
-#include <linux/compiler.h>
-#include <asm/mmu.h>
-#include <asm/processor.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_law.h>
-#include <asm/fsl_serdes.h>
-#include <asm/fsl_liodn.h>
-#include <fm_eth.h>
-#include <hwconfig.h>
-#include "../common/qixis.h"
-#include "t102xqds.h"
-#include "t102xqds_qixis.h"
-#include "../common/sleep.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
- char buf[64];
- struct cpu_type *cpu = gd->arch.cpu;
- static const char *const freq[] = {"100", "125", "156.25", "100.0"};
- int clock;
- u8 sw = QIXIS_READ(arch);
-
- printf("Board: %sQDS, ", cpu->name);
- printf("Sys ID: 0x%02x, Board Arch: V%d, ", QIXIS_READ(id), sw >> 4);
- printf("Board Version: %c, boot from ", (sw & 0xf) + 'A' - 1);
-
-#ifdef CONFIG_SDCARD
- puts("SD/MMC\n");
-#elif CONFIG_SPIFLASH
- puts("SPI\n");
-#else
- sw = QIXIS_READ(brdcfg[0]);
- sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
-
- if (sw < 0x8)
- printf("vBank: %d\n", sw);
- else if (sw == 0x8)
- puts("PromJet\n");
- else if (sw == 0x9)
- puts("NAND\n");
- else if (sw == 0x15)
- printf("IFC Card\n");
- else
- printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
-#endif
-
- printf("FPGA: v%d (%s), build %d",
- (int)QIXIS_READ(scver), qixis_read_tag(buf),
- (int)qixis_read_minor());
- /* the timestamp string contains "\n"@the end */
- printf(" on %s", qixis_read_time(buf));
-
- puts("SERDES Reference: ");
- sw = QIXIS_READ(brdcfg[2]);
- clock = (sw >> 6) & 3;
- printf("Clock1=%sMHz ", freq[clock]);
- clock = (sw >> 4) & 3;
- printf("Clock2=%sMHz\n", freq[clock]);
-
- return 0;
-}
-
-int select_i2c_ch_pca9547(u8 ch, int bus_num)
-{
- int ret;
-#ifdef CONFIG_DM_I2C
- struct udevice *dev;
-
- ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
- 1, &dev);
- if (ret) {
- printf("%s: Cannot find udev for a bus %d\n", __func__,
- bus_num);
- return ret;
- }
-
- ret = dm_i2c_write(dev, 0, &ch, 1);
-#else
- ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
-#endif
- if (ret) {
- puts("PCA: failed to select proper channel\n");
- return ret;
- }
-
- return 0;
-}
-
-static int board_mux_lane_to_slot(void)
-{
- ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- u32 srds_prtcl_s1;
- u8 brdcfg9;
-
- srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
- FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
- srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
-
-
- brdcfg9 = QIXIS_READ(brdcfg[9]);
- QIXIS_WRITE(brdcfg[9], brdcfg9 | BRDCFG9_XFI_TX_DISABLE);
-
- switch (srds_prtcl_s1) {
- case 0:
- /* SerDes1 is not enabled */
- break;
- case 0xd5:
- case 0x5b:
- case 0x6b:
- case 0x77:
- case 0x6f:
- case 0x7f:
- QIXIS_WRITE(brdcfg[12], 0x8c);
- break;
- case 0x40:
- QIXIS_WRITE(brdcfg[12], 0xfc);
- break;
- case 0xd6:
- case 0x5a:
- case 0x6a:
- case 0x56:
- QIXIS_WRITE(brdcfg[12], 0x88);
- break;
- case 0x47:
- QIXIS_WRITE(brdcfg[12], 0xcc);
- break;
- case 0x46:
- QIXIS_WRITE(brdcfg[12], 0xc8);
- break;
- case 0x95:
- case 0x99:
- brdcfg9 &= ~BRDCFG9_XFI_TX_DISABLE;
- QIXIS_WRITE(brdcfg[9], brdcfg9);
- QIXIS_WRITE(brdcfg[12], 0x8c);
- break;
- case 0x116:
- QIXIS_WRITE(brdcfg[12], 0x00);
- break;
- case 0x115:
- case 0x119:
- case 0x129:
- case 0x12b:
- /* Aurora, PCIe, SGMII, SATA */
- QIXIS_WRITE(brdcfg[12], 0x04);
- break;
- default:
- printf("WARNING: unsupported for SerDes Protocol %d\n",
- srds_prtcl_s1);
- return -1;
- }
-
- return 0;
-}
-
-#ifdef CONFIG_ARCH_T1024
-static void board_mux_setup(void)
-{
- u8 brdcfg15;
-
- brdcfg15 = QIXIS_READ(brdcfg[15]);
- brdcfg15 &= ~BRDCFG15_DIUSEL_MASK;
-
- if (hwconfig_arg_cmp("pin_mux", "tdm")) {
- /* Route QE_TDM multiplexed signals to TDM Riser slot */
- QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_TDM);
- QIXIS_WRITE(brdcfg[13], BRDCFG13_TDM_INTERFACE << 2);
- QIXIS_WRITE(brdcfg[5], (QIXIS_READ(brdcfg[5]) &
- ~BRDCFG5_SPIRTE_MASK) | BRDCFG5_SPIRTE_TDM);
- } else if (hwconfig_arg_cmp("pin_mux", "ucc")) {
- /* to UCC (ProfiBus) interface */
- QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_UCC);
- } else if (hwconfig_arg_cmp("pin_mux", "hdmi")) {
- /* to DVI (HDMI) encoder */
- QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_HDMI);
- } else if (hwconfig_arg_cmp("pin_mux", "lcd")) {
- /* to DFP (LCD) encoder */
- QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_LCDFM |
- BRDCFG15_LCDPD | BRDCFG15_DIUSEL_LCD);
- }
-
- if (hwconfig_arg_cmp("adaptor", "sdxc"))
- /* Route SPI_CS multiplexed signals to SD slot */
- QIXIS_WRITE(brdcfg[5], (QIXIS_READ(brdcfg[5]) &
- ~BRDCFG5_SPIRTE_MASK) | BRDCFG5_SPIRTE_SDHC);
-}
-#endif
-
-void board_retimer_ds125df111_init(void)
-{
- u8 reg;
-
-#ifdef CONFIG_DM_I2C
- struct udevice *dev;
- int ret, bus_num = 0;
-
- ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
- 1, &dev);
- if (ret)
- goto failed;
-
- /* Retimer DS125DF111 is connected to I2C1_CH7_CH5 */
- reg = I2C_MUX_CH7;
- dm_i2c_write(dev, 0, ®, 1);
-
- ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_SEC,
- 1, &dev);
- if (ret)
- goto failed;
-
- reg = I2C_MUX_CH5;
- dm_i2c_write(dev, 0, ®, 1);
-
- /* Access to Control/Shared register */
- ret = i2c_get_chip_for_busnum(bus_num, I2C_RETIMER_ADDR,
- 1, &dev);
- if (ret)
- goto failed;
- reg = 0x0;
- dm_i2c_write(dev, 0xff, ®, 1);
-
- /* Read device revision and ID */
- dm_i2c_read(dev, 1, ®, 1);
- debug("Retimer version id = 0x%x\n", reg);
-
- /* Enable Broadcast */
- reg = 0x0c;
- dm_i2c_write(dev, 0xff, ®, 1);
-
- /* Reset Channel Registers */
- dm_i2c_read(dev, 0, ®, 1);
- reg |= 0x4;
- dm_i2c_write(dev, 0, ®, 1);
-
- /* Enable override divider select and Enable Override Output Mux */
- dm_i2c_read(dev, 9, ®, 1);
- reg |= 0x24;
- dm_i2c_write(dev, 9, ®, 1);
-
- /* Select VCO Divider to full rate (000) */
- dm_i2c_read(dev, 0x18, ®, 1);
- reg &= 0x8f;
- dm_i2c_write(dev, 0x18, ®, 1);
-
- /* Select active PFD MUX input as re-timed data (001) */
- dm_i2c_read(dev, 0x1e, ®, 1);
- reg &= 0x3f;
- reg |= 0x20;
- dm_i2c_write(dev, 0x1e, ®, 1);
-
- /* Set data rate as 10.3125 Gbps */
- reg = 0x0;
- dm_i2c_write(dev, 0x60, ®, 1);
- reg = 0xb2;
- dm_i2c_write(dev, 0x61, ®, 1);
- reg = 0x90;
- dm_i2c_write(dev, 0x62, ®, 1);
- reg = 0xb3;
- dm_i2c_write(dev, 0x63, ®, 1);
- reg = 0xcd;
- dm_i2c_write(dev, 0x64, ®, 1);
- return;
-
-failed:
- printf("%s: Cannot find udev for a bus %d\n", __func__,
- bus_num);
- return;
-#else
- /* Retimer DS125DF111 is connected to I2C1_CH7_CH5 */
- reg = I2C_MUX_CH7;
- i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, ®, 1);
- reg = I2C_MUX_CH5;
- i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, ®, 1);
-
- /* Access to Control/Shared register */
- reg = 0x0;
- i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
-
- /* Read device revision and ID */
- i2c_read(I2C_RETIMER_ADDR, 1, 1, ®, 1);
- debug("Retimer version id = 0x%x\n", reg);
-
- /* Enable Broadcast */
- reg = 0x0c;
- i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
-
- /* Reset Channel Registers */
- i2c_read(I2C_RETIMER_ADDR, 0, 1, ®, 1);
- reg |= 0x4;
- i2c_write(I2C_RETIMER_ADDR, 0, 1, ®, 1);
-
- /* Enable override divider select and Enable Override Output Mux */
- i2c_read(I2C_RETIMER_ADDR, 9, 1, ®, 1);
- reg |= 0x24;
- i2c_write(I2C_RETIMER_ADDR, 9, 1, ®, 1);
-
- /* Select VCO Divider to full rate (000) */
- i2c_read(I2C_RETIMER_ADDR, 0x18, 1, ®, 1);
- reg &= 0x8f;
- i2c_write(I2C_RETIMER_ADDR, 0x18, 1, ®, 1);
-
- /* Select active PFD MUX input as re-timed data (001) */
- i2c_read(I2C_RETIMER_ADDR, 0x1e, 1, ®, 1);
- reg &= 0x3f;
- reg |= 0x20;
- i2c_write(I2C_RETIMER_ADDR, 0x1e, 1, ®, 1);
-
- /* Set data rate as 10.3125 Gbps */
- reg = 0x0;
- i2c_write(I2C_RETIMER_ADDR, 0x60, 1, ®, 1);
- reg = 0xb2;
- i2c_write(I2C_RETIMER_ADDR, 0x61, 1, ®, 1);
- reg = 0x90;
- i2c_write(I2C_RETIMER_ADDR, 0x62, 1, ®, 1);
- reg = 0xb3;
- i2c_write(I2C_RETIMER_ADDR, 0x63, 1, ®, 1);
- reg = 0xcd;
- i2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1);
-#endif
-}
-
-int board_early_init_f(void)
-{
-#if defined(CONFIG_DEEP_SLEEP)
- if (is_warm_boot())
- fsl_dp_disable_console();
-#endif
-
- return 0;
-}
-
-int board_early_init_r(void)
-{
-#ifdef CONFIG_SYS_FLASH_BASE
- const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
- int flash_esel = find_tlb_idx((void *)flashbase, 1);
-
- /*
- * Remap Boot flash + PROMJET region to caching-inhibited
- * so that flash can be erased properly.
- */
-
- /* Flush d-cache and invalidate i-cache of any FLASH data */
- flush_dcache();
- invalidate_icache();
-
- if (flash_esel == -1) {
- /* very unlikely unless something is messed up */
- puts("Error: Could not find TLB for FLASH BASE\n");
- flash_esel = 2; /* give our best effort to continue */
- } else {
- /* invalidate existing TLB entry for flash + promjet */
- disable_tlb(flash_esel);
- }
-
- set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, flash_esel, BOOKE_PAGESZ_256M, 1);
-#endif
- select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
- board_mux_lane_to_slot();
- board_retimer_ds125df111_init();
-
- /* Increase IO drive strength to address FCS error on RGMII */
- out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR, 0xbfdb7800);
-
- return 0;
-}
-
-unsigned long get_board_sys_clk(void)
-{
- u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
-
- switch (sysclk_conf & 0x0F) {
- case QIXIS_SYSCLK_64:
- return 64000000;
- case QIXIS_SYSCLK_83:
- return 83333333;
- case QIXIS_SYSCLK_100:
- return 100000000;
- case QIXIS_SYSCLK_125:
- return 125000000;
- case QIXIS_SYSCLK_133:
- return 133333333;
- case QIXIS_SYSCLK_150:
- return 150000000;
- case QIXIS_SYSCLK_160:
- return 160000000;
- case QIXIS_SYSCLK_166:
- return 166666666;
- }
- return 66666666;
-}
-
-unsigned long get_board_ddr_clk(void)
-{
- u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
-
- switch ((ddrclk_conf & 0x30) >> 4) {
- case QIXIS_DDRCLK_100:
- return 100000000;
- case QIXIS_DDRCLK_125:
- return 125000000;
- case QIXIS_DDRCLK_133:
- return 133333333;
- }
- return 66666666;
-}
-
-#define NUM_SRDS_PLL 2
-int misc_init_r(void)
-{
-#ifdef CONFIG_ARCH_T1024
- board_mux_setup();
-#endif
- return 0;
-}
-
-void fdt_fixup_spi_mux(void *blob)
-{
- int nodeoff = 0;
-
- if (hwconfig_arg_cmp("pin_mux", "tdm")) {
- while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
- "eon,en25s64")) >= 0) {
- fdt_del_node(blob, nodeoff);
- }
- } else {
- /* remove tdm node */
- while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
- "maxim,ds26522")) >= 0) {
- fdt_del_node(blob, nodeoff);
- }
- }
-}
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
- phys_addr_t base;
- phys_size_t size;
-
- ft_cpu_setup(blob, bd);
-
- base = env_get_bootm_low();
- size = env_get_bootm_size();
-
- fdt_fixup_memory(blob, (u64)base, (u64)size);
-
-#ifdef CONFIG_PCI
- pci_of_setup(blob, bd);
-#endif
-
- fdt_fixup_liodn(blob);
-
-#ifdef CONFIG_HAS_FSL_DR_USB
- fsl_fdt_fixup_dr_usb(blob, bd);
-#endif
-
-#ifdef CONFIG_SYS_DPAA_FMAN
- fdt_fixup_fman_ethernet(blob);
- fdt_fixup_board_enet(blob);
-#endif
- fdt_fixup_spi_mux(blob);
-
- return 0;
-}
-
-void qixis_dump_switch(void)
-{
- int i, nr_of_cfgsw;
-
- QIXIS_WRITE(cms[0], 0x00);
- nr_of_cfgsw = QIXIS_READ(cms[1]);
-
- puts("DIP switch settings dump:\n");
- for (i = 1; i <= nr_of_cfgsw; i++) {
- QIXIS_WRITE(cms[0], i);
- printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
- }
-}
diff --git a/board/freescale/t102xqds/t102xqds.h b/board/freescale/t102xqds/t102xqds.h
deleted file mode 100644
index d327b5edb9..0000000000
--- a/board/freescale/t102xqds/t102xqds.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2020 NXP
- */
-
-#ifndef __T102x_QDS_H__
-#define __T102x_QDS_H__
-
-void fdt_fixup_board_enet(void *blob);
-void pci_of_setup(void *blob, bd_t *bd);
-int select_i2c_ch_pca9547(u8 ch, int bus_num);
-
-#endif
diff --git a/board/freescale/t102xqds/t102xqds_qixis.h b/board/freescale/t102xqds/t102xqds_qixis.h
deleted file mode 100644
index b84a33fc48..0000000000
--- a/board/freescale/t102xqds/t102xqds_qixis.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- */
-
-#ifndef __T1024QDS_QIXIS_H__
-#define __T1024QDS_QIXIS_H__
-
-/* Definitions of QIXIS Registers for T1024/T1023 QDS */
-
-/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */
-#define BRDCFG4_EMISEL_MASK 0xE0
-#define BRDCFG4_EMISEL_SHIFT 5
-
-/* BRDCFG5[0:1] controls routing and use of I2C3 & I2C4 ports*/
-#define BRDCFG5_IMX_MASK 0xC0
-#define BRDCFG5_IMX_DIU 0x80
-
-#define BRDCFG5_SPIRTE_MASK 0x07
-#define BRDCFG5_SPIRTE_TDM 0x01
-#define BRDCFG5_SPIRTE_SDHC 0x02
-#define BRDCFG9_XFI_TX_DISABLE 0x10
-
-/* BRDCFG13[0:5] TDM configuration and setup */
-#define BRDCFG13_TDM_MASK 0xfc
-#define BRDCFG13_TDM_INTERFACE 0x37
-#define BRDCFG13_HDLC_LOOPBACK 0x29
-#define BRDCFG13_TDM_LOOPBACK 0x31
-
-/* BRDCFG15[3] controls LCD Panel Powerdown */
-#define BRDCFG15_LCDFM 0x20
-#define BRDCFG15_LCDPD 0x10
-#define BRDCFG15_LCDPD_MASK 0x10
-#define BRDCFG15_LCDPD_ENABLED 0x00
-
-/* BRDCFG15[6:7] controls DIU MUX selction*/
-#define BRDCFG15_DIUSEL_MASK 0x03
-#define BRDCFG15_DIUSEL_HDMI 0x00
-#define BRDCFG15_DIUSEL_LCD 0x01
-#define BRDCFG15_DIUSEL_UCC 0x02
-#define BRDCFG15_DIUSEL_TDM 0x03
-
-/* SYSCLK */
-#define QIXIS_SYSCLK_66 0x0
-#define QIXIS_SYSCLK_83 0x1
-#define QIXIS_SYSCLK_100 0x2
-#define QIXIS_SYSCLK_125 0x3
-#define QIXIS_SYSCLK_133 0x4
-#define QIXIS_SYSCLK_150 0x5
-#define QIXIS_SYSCLK_160 0x6
-#define QIXIS_SYSCLK_166 0x7
-#define QIXIS_SYSCLK_64 0x8
-
-/* DDRCLK */
-#define QIXIS_DDRCLK_66 0x0
-#define QIXIS_DDRCLK_100 0x1
-#define QIXIS_DDRCLK_125 0x2
-#define QIXIS_DDRCLK_133 0x3
-
-
-#define QIXIS_SRDS1CLK_122 0x5a
-#define QIXIS_SRDS1CLK_125 0x5e
-#endif
diff --git a/board/freescale/t102xqds/tlb.c b/board/freescale/t102xqds/tlb.c
deleted file mode 100644
index 3546331aab..0000000000
--- a/board/freescale/t102xqds/tlb.c
+++ /dev/null
@@ -1,116 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
- /* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
-
- /* TLB 1 */
- /* *I*** - Covers boot page */
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
- /*
- * *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the
- * SRAM is at 0xfffc0000, it covered the 0xfffff000.
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_256K, 1),
-#else
- SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_4K, 1),
-#endif
-
- /* *I*G* - CCSRBAR */
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 1, BOOKE_PAGESZ_16M, 1),
-
- /* *I*G* - Flash, localbus */
- /* This will be changed to *I*G* after relocation to RAM. */
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
- MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
- 0, 2, BOOKE_PAGESZ_256M, 1),
-
-#ifndef CONFIG_SPL_BUILD
- /* *I*G* - PCI */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 3, BOOKE_PAGESZ_1G, 1),
-
- /* *I*G* - PCI I/O */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 4, BOOKE_PAGESZ_256K, 1),
-
- /* Bman/Qman */
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
- SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 5, BOOKE_PAGESZ_16M, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
- CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 6, BOOKE_PAGESZ_16M, 1),
-#endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
- SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 7, BOOKE_PAGESZ_16M, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
- CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 8, BOOKE_PAGESZ_16M, 1),
-#endif
-#endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
- SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 9, BOOKE_PAGESZ_4M, 1),
-#endif
-#ifdef CONFIG_SYS_NAND_BASE
- SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 10, BOOKE_PAGESZ_64K, 1),
-#endif
-#ifdef QIXIS_BASE
- SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 11, BOOKE_PAGESZ_4K, 1),
-#endif
-
-#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
- SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
- 0, 12, BOOKE_PAGESZ_1G, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
- CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
- 0, 13, BOOKE_PAGESZ_1G, 1)
-#endif
- /* entry 14 and 15 has been used hard coded, they will be disabled
- * in cpu_init_f, so if needed more, will use entry 16 later.
- */
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/configs/T1024QDS_DDR4_SECURE_BOOT_defconfig b/configs/T1024QDS_DDR4_SECURE_BOOT_defconfig
deleted file mode 100644
index 2199abcb95..0000000000
--- a/configs/T1024QDS_DDR4_SECURE_BOOT_defconfig
+++ /dev/null
@@ -1,69 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T1024QDS=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_SILENT_CONSOLE=y
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_BMP=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_VIDEO=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T1024QDS_DDR4_defconfig b/configs/T1024QDS_DDR4_defconfig
deleted file mode 100644
index 0a52af48bb..0000000000
--- a/configs/T1024QDS_DDR4_defconfig
+++ /dev/null
@@ -1,64 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T1024QDS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_SILENT_CONSOLE=y
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_BMP=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_VIDEO=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T1024QDS_NAND_defconfig b/configs/T1024QDS_NAND_defconfig
deleted file mode 100644
index 9db39b1b58..0000000000
--- a/configs/T1024QDS_NAND_defconfig
+++ /dev/null
@@ -1,83 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x00201000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x140000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T1024QDS=y
-CONFIG_SYS_CUSTOM_LDSCRIPT=y
-CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL"
-CONFIG_BOOTDELAY=10
-CONFIG_SILENT_CONSOLE=y
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_NAND_BOOT=y
-CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_BMP=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_FSL_CAAM=y
-CONFIG_SYS_FSL_DDR3=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_VIDEO=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T1024QDS_SDCARD_defconfig b/configs/T1024QDS_SDCARD_defconfig
deleted file mode 100644
index 679f2ad208..0000000000
--- a/configs/T1024QDS_SDCARD_defconfig
+++ /dev/null
@@ -1,80 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x00201000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T1024QDS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD"
-CONFIG_BOOTDELAY=10
-CONFIG_SILENT_CONSOLE=y
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_MMC_BOOT=y
-CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_BMP=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_FSL_CAAM=y
-CONFIG_SYS_FSL_DDR3=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_VIDEO=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T1024QDS_SECURE_BOOT_defconfig b/configs/T1024QDS_SECURE_BOOT_defconfig
deleted file mode 100644
index cc080c7285..0000000000
--- a/configs/T1024QDS_SECURE_BOOT_defconfig
+++ /dev/null
@@ -1,70 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T1024QDS=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_SILENT_CONSOLE=y
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_BMP=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_SYS_FSL_DDR3=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_VIDEO=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T1024QDS_SPIFLASH_defconfig b/configs/T1024QDS_SPIFLASH_defconfig
deleted file mode 100644
index 01bc5111e0..0000000000
--- a/configs/T1024QDS_SPIFLASH_defconfig
+++ /dev/null
@@ -1,83 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x00201000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T1024QDS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH"
-CONFIG_BOOTDELAY=10
-CONFIG_SILENT_CONSOLE=y
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_SPI_BOOT=y
-CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_BMP=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_ADDR=0xFFFC9000
-CONFIG_FSL_CAAM=y
-CONFIG_SYS_FSL_DDR3=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_VIDEO=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T1024QDS_defconfig b/configs/T1024QDS_defconfig
deleted file mode 100644
index 6ebffb8dd1..0000000000
--- a/configs/T1024QDS_defconfig
+++ /dev/null
@@ -1,67 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T1024QDS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_SILENT_CONSOLE=y
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_BMP=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_FSL_CAAM=y
-CONFIG_SYS_FSL_DDR3=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_VIDEO=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h
deleted file mode 100644
index 53ae961837..0000000000
--- a/include/configs/T102xQDS.h
+++ /dev/null
@@ -1,756 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2020 NXP
- */
-
-/*
- * T1024/T1023 QDS board configuration file
- */
-
-#ifndef __T1024QDS_H
-#define __T1024QDS_H
-
-#include <linux/stringify.h>
-
-/* High Level Configuration Options */
-#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
-#define CONFIG_ENABLE_36BIT_PHYS
-
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_ADDR_MAP 1
-#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
-#endif
-
-#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
-#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
-
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_DEEP_SLEEP
-
-#ifdef CONFIG_RAMBOOT_PBL
-#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg
-#define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_PAD_TO 0x40000
-#define CONFIG_SPL_MAX_SIZE 0x28000
-#define RESET_VECTOR_OFFSET 0x27FFC
-#define BOOT_PAGE_OFFSET 0x27000
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SPL_SKIP_RELOCATE
-#define CONFIG_SPL_COMMON_INIT_DDR
-#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
-#endif
-
-#ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
-#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
-#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_nand_rcw.cfg
-#endif
-
-#ifdef CONFIG_SPIFLASH
-#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
-#define CONFIG_SPL_SPI_FLASH_MINIMAL
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_SYS_MPC85XX_NO_RESETVEC
-#endif
-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_spi_rcw.cfg
-#endif
-
-#ifdef CONFIG_SDCARD
-#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
-#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
-#define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
-#define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
-#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_SYS_MPC85XX_NO_RESETVEC
-#endif
-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_sd_rcw.cfg
-#endif
-
-#endif /* CONFIG_RAMBOOT_PBL */
-
-#ifndef CONFIG_RESET_VECTOR_ADDRESS
-#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
-#endif
-
-/* PCIe Boot - Master */
-#define CONFIG_SRIO_PCIE_BOOT_MASTER
-/*
- * for slave u-boot IMAGE instored in master memory space,
- * PHYS must be aligned based on the SIZE
- */
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
-#else
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
-#endif
-/*
- * for slave UCODE and ENV instored in master memory space,
- * PHYS must be aligned based on the SIZE
- */
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
-#else
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000
-#endif
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
-/* slave core release by master*/
-#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
-#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
-
-/* PCIe Boot - Slave */
-#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
-#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
-#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
- (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
-/* Set 1M boot space for PCIe boot */
-#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
-#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
- (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
-#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
-#endif
-
-#if defined(CONFIG_SPIFLASH)
-#elif defined(CONFIG_SDCARD)
-#define CONFIG_SYS_MMC_ENV_DEV 0
-#endif
-
-#ifndef __ASSEMBLY__
-unsigned long get_board_sys_clk(void);
-unsigned long get_board_ddr_clk(void);
-#endif
-
-#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
-#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
-
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_SYS_CACHE_STASHING
-#define CONFIG_BACKSIDE_L2_CACHE
-#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
-#define CONFIG_BTB /* toggle branch predition */
-#define CONFIG_DDR_ECC
-#ifdef CONFIG_DDR_ECC
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
-#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
-#endif
-
-/*
- * Config the L3 Cache as L3 SRAM
- */
-#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
-#define CONFIG_SYS_L3_SIZE (256 << 10)
-#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
-#define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
-#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
-#define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
-#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
-
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_DCSRBAR 0xf0000000
-#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
-#endif
-
-/* EEPROM */
-#define CONFIG_ID_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#define CONFIG_SYS_EEPROM_BUS_NUM 0
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
-
-/*
- * DDR Setup
- */
-#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
-#define CONFIG_DDR_SPD
-
-#define CONFIG_SYS_SPD_BUS_NUM 0
-#define SPD_EEPROM_ADDRESS 0x51
-
-#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
-
-/*
- * IFC Definitions
- */
-#define CONFIG_SYS_FLASH_BASE 0xe0000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
-#else
-#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
-#endif
-
-#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
-#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
- + 0x8000000) | \
- CSPR_PORT_SIZE_16 | \
- CSPR_MSEL_NOR | \
- CSPR_V)
-#define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
-#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
- CSPR_PORT_SIZE_16 | \
- CSPR_MSEL_NOR | \
- CSPR_V)
-#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
-/* NOR Flash Timing Params */
-#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
-#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
- FTIM0_NOR_TEADC(0x5) | \
- FTIM0_NOR_TEAHC(0x5))
-#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
- FTIM1_NOR_TRAD_NOR(0x1A) |\
- FTIM1_NOR_TSEQRAD_NOR(0x13))
-#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
- FTIM2_NOR_TCH(0x4) | \
- FTIM2_NOR_TWPH(0x0E) | \
- FTIM2_NOR_TWP(0x1c))
-#define CONFIG_SYS_NOR_FTIM3 0x0
-
-#define CONFIG_SYS_FLASH_QUIET_TEST
-#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
- + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
-#define CONFIG_FSL_QIXIS /* use common QIXIS code */
-#define QIXIS_BASE 0xffdf0000
-#ifdef CONFIG_PHYS_64BIT
-#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
-#else
-#define QIXIS_BASE_PHYS QIXIS_BASE
-#endif
-#define QIXIS_LBMAP_SWITCH 0x06
-#define QIXIS_LBMAP_MASK 0x0f
-#define QIXIS_LBMAP_SHIFT 0
-#define QIXIS_LBMAP_DFLTBANK 0x00
-#define QIXIS_LBMAP_ALTBANK 0x04
-#define QIXIS_RST_CTL_RESET 0x31
-#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
-#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
-#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
-#define QIXIS_RST_FORCE_MEM 0x01
-
-#define CONFIG_SYS_CSPR3_EXT (0xf)
-#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
- | CSPR_PORT_SIZE_8 \
- | CSPR_MSEL_GPCM \
- | CSPR_V)
-#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_CSOR3 0x0
-/* QIXIS Timing parameters for IFC CS3 */
-#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
- FTIM0_GPCM_TEADC(0x0e) | \
- FTIM0_GPCM_TEAHC(0x0e))
-#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
- FTIM1_GPCM_TRAD(0x3f))
-#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
- FTIM2_GPCM_TCH(0x8) | \
- FTIM2_GPCM_TWP(0x1f))
-#define CONFIG_SYS_CS3_FTIM3 0x0
-
-#define CONFIG_NAND_FSL_IFC
-#define CONFIG_SYS_NAND_BASE 0xff800000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
-#else
-#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
-#endif
-#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
-#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
- | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
- | CSPR_MSEL_NAND /* MSEL = NAND */ \
- | CSPR_V)
-#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
-
-#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
- | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
- | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
- | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
- | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
- | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
- | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
-
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-
-/* ONFI NAND Flash mode0 Timing Params */
-#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
- FTIM0_NAND_TWP(0x18) | \
- FTIM0_NAND_TWCHT(0x07) | \
- FTIM0_NAND_TWH(0x0a))
-#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
- FTIM1_NAND_TWBE(0x39) | \
- FTIM1_NAND_TRR(0x0e) | \
- FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
- FTIM2_NAND_TREH(0x0a) | \
- FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3 0x0
-
-#define CONFIG_SYS_NAND_DDR_LAW 11
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
-
-#if defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
-#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
-#else
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
-#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
-#endif
-
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
-#else
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#endif
-
-#if defined(CONFIG_RAMBOOT_PBL)
-#define CONFIG_SYS_RAMBOOT
-#endif
-
-#define CONFIG_HWCONFIG
-
-/* define to use L1 as initial stack */
-#define CONFIG_L1_INIT_RAM
-#define CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
-/* The assembler doesn't like typecast */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
- ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
- CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
-#else
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
-#endif
-#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
-
-/* Serial Port */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
-#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
-#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
-
-/* Video */
-#ifdef CONFIG_ARCH_T1024 /* no DIU on T1023 */
-#define CONFIG_FSL_DIU_FB
-#ifdef CONFIG_FSL_DIU_FB
-#define CONFIG_FSL_DIU_CH7301
-#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_VIDEO_BMP_LOGO
-#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
-/*
- * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
- * disable empty flash sector detection, which is I/O-intensive.
- */
-#undef CONFIG_SYS_FLASH_EMPTY_INFO
-#endif
-#endif
-
-/* I2C */
-#ifndef CONFIG_DM_I2C
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
-#else
-#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
-#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
-#endif
-
-#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
-
-#define I2C_MUX_PCA_ADDR 0x77
-#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
-#define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
-#define I2C_RETIMER_ADDR 0x18
-
-/* I2C bus multiplexer */
-#define I2C_MUX_CH_DEFAULT 0x8
-#define I2C_MUX_CH_DIU 0xC
-#define I2C_MUX_CH5 0xD
-#define I2C_MUX_CH7 0xF
-
-/* LDI/DVI Encoder for display */
-#define CONFIG_SYS_I2C_LDI_ADDR 0x38
-#define CONFIG_SYS_I2C_DVI_ADDR 0x75
-#define CONFIG_SYS_I2C_DVI_BUS_NUM 0
-
-/*
- * RTC configuration
- */
-#define RTC
-#define CONFIG_RTC_DS3231 1
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-
-/*
- * eSPI - Enhanced SPI
- */
-
-/*
- * General PCIe
- * Memory space is mapped 1-1, but I/O space must start from 0.
- */
-#define CONFIG_PCIE1 /* PCIE controller 1 */
-#define CONFIG_PCIE2 /* PCIE controller 2 */
-#define CONFIG_PCIE3 /* PCIE controller 3 */
-#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
-#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
-#define CONFIG_PCI_INDIRECT_BRIDGE
-
-#ifdef CONFIG_PCI
-/* controller 1, direct to uli, tgtid 3, Base address 20000 */
-#ifdef CONFIG_PCIE1
-#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
-#else
-#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
-#endif
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
-#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
-#else
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
-#endif
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
-#endif
-
-/* controller 2, Slot 2, tgtid 2, Base address 201000 */
-#ifdef CONFIG_PCIE2
-#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
-#else
-#define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000
-#endif
-#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
-#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
-#else
-#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
-#endif
-#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
-#endif
-
-/* controller 3, Slot 1, tgtid 1, Base address 202000 */
-#ifdef CONFIG_PCIE3
-#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
-#else
-#define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000
-#endif
-#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
-#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
-#else
-#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
-#endif
-#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
-#endif
-
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#endif /* CONFIG_PCI */
-
-/*
- *SATA
- */
-#define CONFIG_FSL_SATA_V2
-#ifdef CONFIG_FSL_SATA_V2
-#define CONFIG_SYS_SATA_MAX_DEVICE 1
-#define CONFIG_SATA1
-#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
-#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
-#define CONFIG_LBA48
-#endif
-
-/*
- * USB
- */
-#define CONFIG_HAS_FSL_DR_USB
-
-#ifdef CONFIG_HAS_FSL_DR_USB
-#define CONFIG_USB_EHCI_FSL
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#endif
-
-/*
- * SDHC
- */
-#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
-#endif
-
-/* Qman/Bman */
-#ifndef CONFIG_NOBQFMAN
-#define CONFIG_SYS_BMAN_NUM_PORTALS 10
-#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
-#else
-#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
-#endif
-#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
-#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
-#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
-#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
-#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
- CONFIG_SYS_BMAN_CENA_SIZE)
-#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
-#define CONFIG_SYS_QMAN_NUM_PORTALS 10
-#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
-#else
-#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
-#endif
-#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
-#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
-#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
-#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
-#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
- CONFIG_SYS_QMAN_CENA_SIZE)
-#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
-
-#define CONFIG_SYS_DPAA_FMAN
-
-/* Default address of microcode for the Linux FMan driver */
-#if defined(CONFIG_SPIFLASH)
-/*
- * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
- * env, so we got 0x110000.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
-#define CONFIG_SYS_QE_FW_ADDR 0x130000
-#elif defined(CONFIG_SDCARD)
-/*
- * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
- * about 1MB (2048 blocks), Env is stored after the image, and the env size is
- * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
- */
-#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
-#define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
-#elif defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
-#define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
-#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
-/*
- * Slave has no ucode locally, it can fetch this from remote. When implementing
- * in two corenet boards, slave's ucode could be stored in master's memory
- * space, the address can be mapped from slave TLB->slave LAW->
- * slave SRIO or PCIE outbound window->master inbound window->
- * master LAW->the ucode address in master's memory space.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
-#else
-#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
-#define CONFIG_SYS_QE_FW_ADDR 0xEFE00000
-#endif
-#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
-#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
-#endif /* CONFIG_NOBQFMAN */
-
-#ifdef CONFIG_SYS_DPAA_FMAN
-#define RGMII_PHY1_ADDR 0x1
-#define RGMII_PHY2_ADDR 0x2
-#define SGMII_CARD_AQ_PHY_ADDR_S3 0x3
-#define SGMII_CARD_AQ_PHY_ADDR_S4 0x4
-#define SGMII_CARD_AQ_PHY_ADDR_S5 0x5
-#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
-#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
-#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
-#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
-#endif
-
-#ifdef CONFIG_FMAN_ENET
-#define CONFIG_ETHPRIME "FM1 at DTSEC4"
-#endif
-
-/*
- * Dynamic MTD Partition support with mtdparts
- */
-
-/*
- * Environment
- */
-#define CONFIG_LOADS_ECHO /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 64 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
-#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-#define CONFIG_ROOTPATH "/opt/nfsroot"
-#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
-#define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */
-#define __USB_PHY_TYPE utmi
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "hwconfig=fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1;\0" \
- "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
- "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
- "ramdiskfile=t1024qds/ramdisk.uboot\0" \
- "fdtfile=t1024qds/t1024qds.dtb\0" \
- "netdev=eth0\0" \
- "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \
- "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
- "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
- "tftpflash=tftpboot $loadaddr $uboot && " \
- "protect off $ubootaddr +$filesize && " \
- "erase $ubootaddr +$filesize && " \
- "cp.b $loadaddr $ubootaddr $filesize && " \
- "protect on $ubootaddr +$filesize && " \
- "cmp.b $loadaddr $ubootaddr $filesize\0" \
- "consoledev=ttyS0\0" \
- "ramdiskaddr=2000000\0" \
- "fdtaddr=d00000\0" \
- "bdev=sda3\0"
-
-#define CONFIG_LINUX \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "setenv ramdiskaddr 0x02000000;" \
- "setenv fdtaddr 0x00c00000;" \
- "setenv loadaddr 0x1000000;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND CONFIG_LINUX
-
-#include <asm/fsl_secure_boot.h>
-
-#endif /* __T1024QDS_H */
--
2.25.1
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 14/24] arm: Remove configs/T1040D4RDB_NAND_defconfig board
2020-05-27 16:46 [PATCH 00/24] spi: dm-conversion (part2) Jagan Teki
` (12 preceding siblings ...)
2020-05-27 16:46 ` [PATCH 13/24] arm: Remove configs/T1024QDS_DDR4_SECURE_BOOT_defconfig board Jagan Teki
@ 2020-05-27 16:46 ` Jagan Teki
2020-05-28 7:11 ` Priyanka Jain
2020-05-27 16:46 ` [PATCH 15/24] arm: Remove configs/T1040QDS_DDR4_defconfig board Jagan Teki
` (8 subsequent siblings)
22 siblings, 1 reply; 59+ messages in thread
From: Jagan Teki @ 2020-05-27 16:46 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_SPI by the deadline.
Remove it.
Patch-cc: Priyanka Jain <priyanka.jain@nxp.com>
Patch-cc: Priyanka Jain <priyanka.jain@nxp.com>
Patch-cc: Ruchika Gupta <ruchika.gupta@nxp.com>
Patch-cc: Sumit Garg <sumit.garg@nxp.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
arch/powerpc/cpu/mpc85xx/Kconfig | 1 -
board/freescale/t104xrdb/Kconfig | 16 -
board/freescale/t104xrdb/MAINTAINERS | 38 -
board/freescale/t104xrdb/Makefile | 16 -
board/freescale/t104xrdb/README | 386 ---------
board/freescale/t104xrdb/cpld.c | 115 ---
board/freescale/t104xrdb/cpld.h | 46 -
board/freescale/t104xrdb/ddr.c | 145 ----
board/freescale/t104xrdb/ddr.h | 56 --
board/freescale/t104xrdb/diu.c | 84 --
board/freescale/t104xrdb/eth.c | 154 ----
board/freescale/t104xrdb/law.c | 31 -
board/freescale/t104xrdb/pci.c | 25 -
board/freescale/t104xrdb/spl.c | 142 ---
board/freescale/t104xrdb/t1040_nand_rcw.cfg | 7 -
board/freescale/t104xrdb/t1040_sd_rcw.cfg | 7 -
board/freescale/t104xrdb/t1040_spi_rcw.cfg | 7 -
board/freescale/t104xrdb/t1040d4_nand_rcw.cfg | 7 -
board/freescale/t104xrdb/t1040d4_sd_rcw.cfg | 7 -
board/freescale/t104xrdb/t1040d4_spi_rcw.cfg | 7 -
board/freescale/t104xrdb/t1042_nand_rcw.cfg | 7 -
.../freescale/t104xrdb/t1042_pi_nand_rcw.cfg | 7 -
board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg | 7 -
board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg | 7 -
board/freescale/t104xrdb/t1042_sd_rcw.cfg | 7 -
board/freescale/t104xrdb/t1042_spi_rcw.cfg | 7 -
board/freescale/t104xrdb/t1042d4_nand_rcw.cfg | 7 -
board/freescale/t104xrdb/t1042d4_sd_rcw.cfg | 7 -
board/freescale/t104xrdb/t1042d4_spi_rcw.cfg | 7 -
board/freescale/t104xrdb/t104x_pbi.cfg | 36 -
board/freescale/t104xrdb/t104x_pbi_sb.cfg | 38 -
board/freescale/t104xrdb/t104xrdb.c | 161 ----
board/freescale/t104xrdb/t104xrdb.h | 12 -
board/freescale/t104xrdb/tlb.c | 131 ---
configs/T1040D4RDB_NAND_defconfig | 75 --
configs/T1040D4RDB_SDCARD_defconfig | 72 --
configs/T1040D4RDB_SECURE_BOOT_defconfig | 61 --
configs/T1040D4RDB_SPIFLASH_defconfig | 75 --
configs/T1040D4RDB_defconfig | 59 --
configs/T1040RDB_NAND_defconfig | 76 --
configs/T1040RDB_SDCARD_defconfig | 73 --
configs/T1040RDB_SECURE_BOOT_defconfig | 62 --
configs/T1040RDB_SPIFLASH_defconfig | 76 --
configs/T1040RDB_defconfig | 60 --
configs/T1042D4RDB_NAND_defconfig | 86 --
configs/T1042D4RDB_SDCARD_defconfig | 83 --
configs/T1042D4RDB_SECURE_BOOT_defconfig | 64 --
configs/T1042D4RDB_SPIFLASH_defconfig | 86 --
configs/T1042D4RDB_defconfig | 71 --
.../T1042RDB_PI_NAND_SECURE_BOOT_defconfig | 85 --
configs/T1042RDB_PI_NAND_defconfig | 80 --
configs/T1042RDB_PI_SDCARD_defconfig | 77 --
configs/T1042RDB_PI_SPIFLASH_defconfig | 80 --
configs/T1042RDB_PI_defconfig | 64 --
configs/T1042RDB_SECURE_BOOT_defconfig | 61 --
configs/T1042RDB_defconfig | 59 --
include/configs/T104xRDB.h | 813 ------------------
57 files changed, 4136 deletions(-)
delete mode 100644 board/freescale/t104xrdb/Kconfig
delete mode 100644 board/freescale/t104xrdb/MAINTAINERS
delete mode 100644 board/freescale/t104xrdb/Makefile
delete mode 100644 board/freescale/t104xrdb/README
delete mode 100644 board/freescale/t104xrdb/cpld.c
delete mode 100644 board/freescale/t104xrdb/cpld.h
delete mode 100644 board/freescale/t104xrdb/ddr.c
delete mode 100644 board/freescale/t104xrdb/ddr.h
delete mode 100644 board/freescale/t104xrdb/diu.c
delete mode 100644 board/freescale/t104xrdb/eth.c
delete mode 100644 board/freescale/t104xrdb/law.c
delete mode 100644 board/freescale/t104xrdb/pci.c
delete mode 100644 board/freescale/t104xrdb/spl.c
delete mode 100644 board/freescale/t104xrdb/t1040_nand_rcw.cfg
delete mode 100644 board/freescale/t104xrdb/t1040_sd_rcw.cfg
delete mode 100644 board/freescale/t104xrdb/t1040_spi_rcw.cfg
delete mode 100644 board/freescale/t104xrdb/t1040d4_nand_rcw.cfg
delete mode 100644 board/freescale/t104xrdb/t1040d4_sd_rcw.cfg
delete mode 100644 board/freescale/t104xrdb/t1040d4_spi_rcw.cfg
delete mode 100644 board/freescale/t104xrdb/t1042_nand_rcw.cfg
delete mode 100644 board/freescale/t104xrdb/t1042_pi_nand_rcw.cfg
delete mode 100644 board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg
delete mode 100644 board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg
delete mode 100644 board/freescale/t104xrdb/t1042_sd_rcw.cfg
delete mode 100644 board/freescale/t104xrdb/t1042_spi_rcw.cfg
delete mode 100644 board/freescale/t104xrdb/t1042d4_nand_rcw.cfg
delete mode 100644 board/freescale/t104xrdb/t1042d4_sd_rcw.cfg
delete mode 100644 board/freescale/t104xrdb/t1042d4_spi_rcw.cfg
delete mode 100644 board/freescale/t104xrdb/t104x_pbi.cfg
delete mode 100644 board/freescale/t104xrdb/t104x_pbi_sb.cfg
delete mode 100644 board/freescale/t104xrdb/t104xrdb.c
delete mode 100644 board/freescale/t104xrdb/t104xrdb.h
delete mode 100644 board/freescale/t104xrdb/tlb.c
delete mode 100644 configs/T1040D4RDB_NAND_defconfig
delete mode 100644 configs/T1040D4RDB_SDCARD_defconfig
delete mode 100644 configs/T1040D4RDB_SECURE_BOOT_defconfig
delete mode 100644 configs/T1040D4RDB_SPIFLASH_defconfig
delete mode 100644 configs/T1040D4RDB_defconfig
delete mode 100644 configs/T1040RDB_NAND_defconfig
delete mode 100644 configs/T1040RDB_SDCARD_defconfig
delete mode 100644 configs/T1040RDB_SECURE_BOOT_defconfig
delete mode 100644 configs/T1040RDB_SPIFLASH_defconfig
delete mode 100644 configs/T1040RDB_defconfig
delete mode 100644 configs/T1042D4RDB_NAND_defconfig
delete mode 100644 configs/T1042D4RDB_SDCARD_defconfig
delete mode 100644 configs/T1042D4RDB_SECURE_BOOT_defconfig
delete mode 100644 configs/T1042D4RDB_SPIFLASH_defconfig
delete mode 100644 configs/T1042D4RDB_defconfig
delete mode 100644 configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig
delete mode 100644 configs/T1042RDB_PI_NAND_defconfig
delete mode 100644 configs/T1042RDB_PI_SDCARD_defconfig
delete mode 100644 configs/T1042RDB_PI_SPIFLASH_defconfig
delete mode 100644 configs/T1042RDB_PI_defconfig
delete mode 100644 configs/T1042RDB_SECURE_BOOT_defconfig
delete mode 100644 configs/T1042RDB_defconfig
delete mode 100644 include/configs/T104xRDB.h
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 96ec6360c4..657bd929b3 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -1600,7 +1600,6 @@ source "board/freescale/p1023rdb/Kconfig"
source "board/freescale/p1_twr/Kconfig"
source "board/freescale/qemu-ppce500/Kconfig"
source "board/freescale/t1040qds/Kconfig"
-source "board/freescale/t104xrdb/Kconfig"
source "board/freescale/t208xqds/Kconfig"
source "board/freescale/t208xrdb/Kconfig"
source "board/freescale/t4qds/Kconfig"
diff --git a/board/freescale/t104xrdb/Kconfig b/board/freescale/t104xrdb/Kconfig
deleted file mode 100644
index e6e46fa126..0000000000
--- a/board/freescale/t104xrdb/Kconfig
+++ /dev/null
@@ -1,16 +0,0 @@
-if TARGET_T1040RDB || TARGET_T1040D4RDB || \
- TARGET_T1042RDB || TARGET_T1042D4RDB || \
- TARGET_T1042RDB_PI
-
-config SYS_BOARD
- default "t104xrdb"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "T104xRDB"
-
-source "board/freescale/common/Kconfig"
-
-endif
diff --git a/board/freescale/t104xrdb/MAINTAINERS b/board/freescale/t104xrdb/MAINTAINERS
deleted file mode 100644
index 8e3267917f..0000000000
--- a/board/freescale/t104xrdb/MAINTAINERS
+++ /dev/null
@@ -1,38 +0,0 @@
-T104XRDB BOARD
-M: Priyanka Jain <priyanka.jain@nxp.com>
-S: Maintained
-F: board/freescale/t104xrdb/
-F: include/configs/T104xRDB.h
-F: configs/T1040RDB_defconfig
-F: configs/T1040RDB_NAND_defconfig
-F: configs/T1040RDB_SPIFLASH_defconfig
-F: configs/T1040D4RDB_defconfig
-F: configs/T1040D4RDB_NAND_defconfig
-F: configs/T1040D4RDB_SPIFLASH_defconfig
-F: configs/T1042RDB_defconfig
-F: configs/T1042D4RDB_defconfig
-F: configs/T1042D4RDB_NAND_defconfig
-F: configs/T1042D4RDB_SPIFLASH_defconfig
-F: configs/T1042RDB_PI_defconfig
-F: configs/T1042RDB_PI_NAND_defconfig
-F: configs/T1042RDB_PI_SPIFLASH_defconfig
-
-T1040RDB_SDCARD BOARD
-M: Priyanka Jain <priyanka.jain@nxp.com>
-S: Maintained
-F: configs/T1040RDB_SDCARD_defconfig
-F: configs/T1040D4RDB_SDCARD_defconfig
-F: configs/T1042D4RDB_SDCARD_defconfig
-F: configs/T1042RDB_PI_SDCARD_defconfig
-
-T1040RDB_SECURE_BOOT BOARD
-M: Ruchika Gupta <ruchika.gupta@nxp.com>
-S: Maintained
-F: configs/T1040RDB_SECURE_BOOT_defconfig
-F: configs/T1040D4RDB_SECURE_BOOT_defconfig
-F: configs/T1042RDB_SECURE_BOOT_defconfig
-F: configs/T1042D4RDB_SECURE_BOOT_defconfig
-
-M: Sumit Garg <sumit.garg@nxp.com>
-S: Maintained
-F: configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig
diff --git a/board/freescale/t104xrdb/Makefile b/board/freescale/t104xrdb/Makefile
deleted file mode 100644
index 31abbd9aca..0000000000
--- a/board/freescale/t104xrdb/Makefile
+++ /dev/null
@@ -1,16 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2013 Freescale Semiconductor, Inc.
-
-ifdef CONFIG_SPL_BUILD
-obj-y += spl.o
-else
-obj-y += t104xrdb.o
-obj-y += cpld.o
-obj-y += eth.o
-obj-$(CONFIG_PCI) += pci.o
-obj-$(CONFIG_FSL_DIU_FB)+= diu.o
-endif
-obj-y += ddr.o
-obj-y += law.o
-obj-y += tlb.o
diff --git a/board/freescale/t104xrdb/README b/board/freescale/t104xrdb/README
deleted file mode 100644
index 09cb98e33d..0000000000
--- a/board/freescale/t104xrdb/README
+++ /dev/null
@@ -1,386 +0,0 @@
-Overview
---------
-The T1040RDB is a Freescale reference board that hosts the T1040 SoC
-(and variants). Variants inclued T1042 presonality of T1040, in which
-case T1040RDB can also be called T1042RDB.
-
-The T1042RDB is a Freescale reference board that hosts the T1042 SoC
-(and variants). The board is similar to T1040RDB, T1040 is a reduced
-personality of T1040 SoC without Integrated 8-port Gigabit(L2 Switch).
-
-The T1042RDB_PI is a Freescale reference board that hosts the T1042 SoC.
-(a personality of T1040 SoC). The board is similar to T1040RDB but is
-designed specially with low power features targeted for Printing Image Market.
-
-The T1040D4RDB is a Freescale reference board that hosts the T1040 SoC.
-The board is re-designed T1040RDB board with following changes :
- - Support of DDR4 memory and some enhancements
-
-The T1042D4RDB is a Freescale reference board that hosts the T1042 SoC.
-The board is re-designed T1040RDB board with following changes :
- - Support of DDR4 memory
- - Support for 0x86 serdes protocol which can support following interfaces
- - 2 RGMII's on DTSEC4, DTSEC5
- - 3 SGMII on DTSEC1, DTSEC2 & DTSEC3
-
-Basic difference's among T1040RDB, T1042RDB_PI, T1042RDB
--------------------------------------------------------------------------
-Board Si Protocol Targeted Market
--------------------------------------------------------------------------
-T1040RDB T1040 0x66 Networking
-T1040RDB T1042 0x86 Networking
-T1042RDB_PI T1042 0x06 Printing & Imaging
-T1040D4RDB T1040 0x66 Networking
-T1042D4RDB T1042 0x86 Networking
-
-
-T1040 SoC Overview
-------------------
-The QorIQ T1040/T1042 processor support four integrated 64-bit e5500 PA
-processor cores with high-performance data path acceleration architecture
-and network peripheral interfaces required for networking & telecommunications.
-
-The T1040/T1042 SoC includes the following function and features:
-
- - Four e5500 cores, each with a private 256 KB L2 cache
- - 256 KB shared L3 CoreNet platform cache (CPC)
- - Interconnect CoreNet platform
- - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
- support
- - Data Path Acceleration Architecture (DPAA) incorporating acceleration
- for the following functions:
- - Packet parsing, classification, and distribution
- - Queue management for scheduling, packet sequencing, and congestion
- management
- - Cryptography Acceleration (SEC 5.0)
- - RegEx Pattern Matching Acceleration (PME 2.2)
- - IEEE Std 1588 support
- - Hardware buffer management for buffer allocation and deallocation
- - Ethernet interfaces
- - Integrated 8-port Gigabit Ethernet switch (T1040 only)
- - Four 1 Gbps Ethernet controllers
- - Two RGMII interfaces or one RGMII and one MII interfaces
- - High speed peripheral interfaces
- - Four PCI Express 2.0 controllers running at up to 5 GHz
- - Two SATA controllers supporting 1.5 and 3.0 Gb/s operation
- - Upto two QSGMII interface
- - Upto six SGMII interface supporting 1000 Mbps
- - One SGMII interface supporting upto 2500 Mbps
- - Additional peripheral interfaces
- - Two USB 2.0 controllers with integrated PHY
- - SD/eSDHC/eMMC
- - eSPI controller
- - Four I2C controllers
- - Four UARTs
- - Four GPIO controllers
- - Integrated flash controller (IFC)
- - LCD and HDMI interface (DIU) with 12 bit dual data rate
- - TDM interface
- - Multicore programmable interrupt controller (PIC)
- - Two 8-channel DMA engines
- - Single source clocking implementation
- - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
-
-T1040 SoC Personalities
--------------------------
-T1022 Personality:
-T1022 is a reduced personality of T1040 with less core/clusters.
-
-T1042 Personality:
-T1042 is a reduced personality of T1040 without Integrated 8-port Gigabit
-Ethernet switch. Rest of the blocks are same as T1040
-
-
-T1040RDB board Overview
--------------------------
- - SERDES Connections, 8 lanes information:
- 1: None
- 2: SGMII
- 3: QSGMII
- 4: QSGMII
- 5: PCIe1 x1 slot
- 6: mini PCIe connector
- 7: mini PCIe connector
- 8: SATA connector
- - DDR Controller
- - Supports rates of up to 1600 MHz data-rate
- - Supports one DDR3LP UDIMM/RDIMMs, of single-, dual- or quad-rank types.
- - IFC/Local Bus
- - NAND flash: 1GB 8-bit NAND flash
- - NOR: 128MB 16-bit NOR Flash
- - Ethernet
- - Two on-board RGMII 10/100/1G ethernet ports.
- - CPLD
- - Clocks
- - System and DDR clock (SYSCLK, ?DDRCLK?)
- - SERDES clocks
- - Power Supplies
- - USB
- - Supports two USB 2.0 ports with integrated PHYs
- - Two type A ports with 5V at 1.5A per port.
- - SDHC
- - SDHC/SDXC connector
- - SPI
- - On-board 64MB SPI flash
- - Other IO
- - Two Serial ports
- - Four I2C ports
-
-T1042RDB_PI board Overview
--------------------------
- - SERDES Connections, 8 lanes information:
- 1, 2, 3, 4 : PCIe x4 slot
- 5: mini PCIe connector
- 6: mini PCIe connector
- 7: NA
- 8: SATA connector
- - DDR Controller
- - Supports rates of up to 1600 MHz data-rate
- - Supports one DDR3LP UDIMM/RDIMMs, of single-, dual- or quad-rank types.
- - IFC/Local Bus
- - NAND flash: 1GB 8-bit NAND flash
- - NOR: 128MB 16-bit NOR Flash
- - Ethernet
- - Two on-board RGMII 10/100/1G ethernet ports.
- - CPLD
- - Clocks
- - System and DDR clock (SYSCLK, ?DDRCLK?)
- - SERDES clocks
- - Video
- - DIU supports video at up to 1280x1024x32bpp
- - Power Supplies
- - USB
- - Supports two USB 2.0 ports with integrated PHYs
- - Two type A ports with 5V at 1.5A per port.
- - SDHC
- - SDHC/SDXC connector
- - SPI
- - On-board 64MB SPI flash
- - Other IO
- - Two Serial ports
- - Four I2C ports
-
-Memory map
------------
-The addresses in brackets are physical addresses.
-
-Start Address End Address Description Size
-0xF_FFDF_0000 0xF_FFDF_0FFF IFC - CPLD 4KB
-0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB
-0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB
-0xF_F803_0000 0xF_F803_FFFF PCI Express 4 I/O Space 64KB
-0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB
-0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB
-0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB
-0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB
-0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB
-0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB
-0xF_0000_0000 0xF_003F_FFFF DCSR 4MB
-0xC_3000_0000 0xC_3FFF_FFFF PCI Express 4 Mem Space 256MB
-0xC_2000_0000 0xC_2FFF_FFFF PCI Express 3 Mem Space 256MB
-0xC_1000_0000 0xC_1FFF_FFFF PCI Express 2 Mem Space 256MB
-0xC_0000_0000 0xC_0FFF_FFFF PCI Express 1 Mem Space 256MB
-0x0_0000_0000 0x0_ffff_ffff DDR 2GB
-
-
-NOR Flash memory Map
----------------------
- Start End Definition Size
-0xEFF40000 0xEFFFFFFF U-Boot (current bank) 768KB
-0xEFF20000 0xEFF3FFFF U-Boot env (current bank) 128KB
-0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB
-0xED300000 0xEFEFFFFF rootfs (alt bank) 44MB
-0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB
-0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB
-0xEC000000 0xEC01FFFF RCW (alt bank) 128KB
-0xEBF40000 0xEBFFFFFF U-Boot (alt bank) 768KB
-0xEBF20000 0xEBF3FFFF U-Boot env (alt bank) 128KB
-0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB
-0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB
-0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 11MB + 512KB
-0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB
-0xE8000000 0xE801FFFF RCW (current bank) 128KB
-
-
-Various Software configurations/environment variables/commands
---------------------------------------------------------------
-The below commands apply to the board
-
-1. U-Boot environment variable hwconfig
- The default hwconfig is:
- hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;usb1:
- dr_mode=host,phy_type=utmi
- Note: For USB gadget set "dr_mode=peripheral"
-
-2. FMAN Ucode versions
- fsl_fman_ucode_t1040.bin
-
-3. Switching to alternate bank
- Commands for switching to alternate bank.
-
- 1. To change from vbank0 to vbank4
- => cpld reset altbank (it will boot using vbank4)
-
- 2.To change from vbank4 to vbank0
- => cpld reset (it will boot using vbank0)
-
-NAND boot with 2 Stage boot loader
-----------------------------------
-PBL initialise the internal SRAM and copy SPL(160KB) in SRAM.
-SPL further initialise DDR using SPD and environment variables and copy
-U-Boot(768 KB) from flash to DDR.
-Finally SPL transer control to U-Boot for futher booting.
-
-SPL has following features:
- - Executes within 256K
- - No relocation required
-
- Run time view of SPL framework during boot :-
- -----------------------------------------------
- Area | Address |
------------------------------------------------
- Secure boot | 0xFFFC0000 (32KB) |
- headers | |
- -----------------------------------------------
- GD, BD | 0xFFFC8000 (4KB) |
- -----------------------------------------------
- ENV | 0xFFFC9000 (8KB) |
- -----------------------------------------------
- HEAP | 0xFFFCB000 (30KB) |
- -----------------------------------------------
- STACK | 0xFFFD8000 (22KB) |
- -----------------------------------------------
- U-Boot SPL | 0xFFFD8000 (160KB) |
- -----------------------------------------------
-
-NAND Flash memory Map on T104xRDB
-------------------------------------------
- Start End Definition Size
-0x000000 0x0FFFFF U-Boot 1MB
-0x180000 0x19FFFF U-Boot env 128KB
-0x280000 0x29FFFF FMAN Ucode 128KB
-0x380000 0x39FFFF QE Firmware 128KB
-
-SD Card memory Map on T104xRDB
-------------------------------------------
- Block #blocks Definition Size
-0x008 2048 U-Boot 1MB
-0x800 0024 U-Boot env 8KB
-0x820 0256 FMAN Ucode 128KB
-0x920 0256 QE Firmware 128KB
-
-SPI Flash memory Map on T104xRDB
-------------------------------------------
- Start End Definition Size
-0x000000 0x0FFFFF U-Boot 1MB
-0x100000 0x101FFF U-Boot env 8KB
-0x110000 0x12FFFF FMAN Ucode 128KB
-0x130000 0x14FFFF QE Firmware 128KB
-
-Please note QE Firmware is only valid for T1040RDB
-
-
-Switch Settings for T104xRDB boards: (ON is 0, OFF is 1)
-==========================================================
-NOR boot SW setting:
-SW1: 00010011
-SW2: 10111011
-SW3: 11100001
-
-NAND boot SW setting:
-SW1: 10001000
-SW2: 00111011
-SW3: 11110001
-
-SPI boot SW setting:
-SW1: 00100010
-SW2: 10111011
-SW3: 11100001
-
-SD boot SW setting:
-SW1: 00100000
-SW2: 00111011
-SW3: 11100001
-
-Switch Settings for T104xD4RDB boards: (ON is 0, OFF is 1)
-=============================================================
-NOR boot SW setting:
-SW1: 00010011
-SW2: 10111001
-SW3: 11100001
-
-NAND boot SW setting:
-SW1: 10001000
-SW2: 00111001
-SW3: 11110001
-
-SPI boot SW setting:
-SW1: 00100010
-SW2: 10111001
-SW3: 11100001
-
-SD boot SW setting:
-SW1: 00100000
-SW2: 00111001
-SW3: 11100001
-
-PBL-based image generation
-==========================
-Changes only the required register bit in in PBI commands.
-
-Provides reference code which might needs some
-modification as per requirement.
-example:
-By default PBI_SRC=14 (which is for IFC-NAND/NOR) in rcw.cfg file
-which needs to be changed for SPI and SD.
-
-For SD-boot
-==============
-1. Set RCW[192:195], PBI_SRC bits as 6 in RCW file (t1040d4_rcw.cfg type files)
-
-example:
- RCW file: board/freescale/t104xrdb/t1040d4_rcw.cfg
-
-Change
-66000002 40000002 ec027000 01000000
-to
-66000002 40000002 6c027000 01000000
-
-2. SD does not support flush so remove flush from pbl, make changes in
- tools/pblimage.c file, Update value of pbl_end_cmd[0] = 0x09138000
- with 0x091380c0
-
-For SPI-boot
-==============
-1. Set RCW[192:195], PBI_SRC bits as 5 in RCW file (t1040d4_rcw.cfg type files)
-
-example:
- RCW file: board/freescale/t104xrdb/t1040d4_rcw.cfg
-
-Change
-66000002 40000002 ec027000 01000000
-to
-66000002 40000002 5c027000 01000000
-
-2. SPI does not support flush so remove flush from pbl, make changes in
- tools/pblimage.c file, Update value of pbl_end_cmd[0] = 0x09138000
- with 0x091380c0
-
-Device tree support and how to enable it for different configs
---------------------------------------------------------------
-Device tree support is available for t1042d4rdb for below mentioned boot,
-1. NOR Boot
-2. NAND Boot
-3. SD Boot
-4. SPIFLASH Boot
-
-To enable device tree support for other boot, below configs need to be
-enabled in relative defconfig file,
-1. CONFIG_DEFAULT_DEVICE_TREE="t1042d4rdb" (Change default device tree name if required)
-2. CONFIG_OF_CONTROL
-3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at
- CONFIG_RESET_VECTOR_ADDRESS - 0xffc
-
-If device tree support is enabled in defconfig,
-1. use 'u-boot-with-dtb.bin' for NOR boot.
-2. use 'u-boot-with-spl-pbl.bin' for other boot.
diff --git a/board/freescale/t104xrdb/cpld.c b/board/freescale/t104xrdb/cpld.c
deleted file mode 100644
index ac34095f3b..0000000000
--- a/board/freescale/t104xrdb/cpld.c
+++ /dev/null
@@ -1,115 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/**
- * Copyright 2014 Freescale Semiconductor
- *
- * This file provides support for the board-specific CPLD used on some Freescale
- * reference boards.
- *
- * The following macros need to be defined:
- *
- * CONFIG_SYS_CPLD_BASE-The virtual address of the base of the CPLD register map
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/io.h>
-
-#include "cpld.h"
-
-u8 cpld_read(unsigned int reg)
-{
- void *p = (void *)CONFIG_SYS_CPLD_BASE;
-
- return in_8(p + reg);
-}
-
-void cpld_write(unsigned int reg, u8 value)
-{
- void *p = (void *)CONFIG_SYS_CPLD_BASE;
-
- out_8(p + reg, value);
-}
-
-/**
- * Set the boot bank to the alternate bank
- */
-void cpld_set_altbank(void)
-{
- u8 reg = CPLD_READ(flash_ctl_status);
-
- reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_ALTBANK;
-
- CPLD_WRITE(flash_ctl_status, reg);
- CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET);
-}
-
-/**
- * Set the boot bank to the default bank
- */
-void cpld_set_defbank(void)
-{
- u8 reg = CPLD_READ(flash_ctl_status);
-
- reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_DFLTBANK;
-
- CPLD_WRITE(flash_ctl_status, reg);
- CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET);
-}
-
-#ifdef DEBUG
-static void cpld_dump_regs(void)
-{
- printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver));
- printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub));
- printf("hw_ver = 0x%02x\n", CPLD_READ(hw_ver));
- printf("sw_ver = 0x%02x\n", CPLD_READ(sw_ver));
- printf("reset_ctl1 = 0x%02x\n", CPLD_READ(reset_ctl1));
- printf("reset_ctl2 = 0x%02x\n", CPLD_READ(reset_ctl2));
- printf("int_status = 0x%02x\n", CPLD_READ(int_status));
- printf("flash_ctl_status = 0x%02x\n", CPLD_READ(flash_ctl_status));
- printf("fan_ctl_status = 0x%02x\n", CPLD_READ(fan_ctl_status));
-#if defined(CONFIG_TARGET_T1040D4D4RDB) || defined(CONFIG_TARGET_T1042D4RDB)
- printf("int_mask = 0x%02x\n", CPLD_READ(int_mask));
-#else
- printf("led_ctl_status = 0x%02x\n", CPLD_READ(led_ctl_status));
-#endif
- printf("sfp_ctl_status = 0x%02x\n", CPLD_READ(sfp_ctl_status));
- printf("misc_ctl_status = 0x%02x\n", CPLD_READ(misc_ctl_status));
- printf("boot_override = 0x%02x\n", CPLD_READ(boot_override));
- printf("boot_config1 = 0x%02x\n", CPLD_READ(boot_config1));
- printf("boot_config2 = 0x%02x\n", CPLD_READ(boot_config2));
- putc('\n');
-}
-#endif
-
-int do_cpld(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
-{
- int rc = 0;
-
- if (argc <= 1)
- return cmd_usage(cmdtp);
-
- if (strcmp(argv[1], "reset") == 0) {
- if (strcmp(argv[2], "altbank") == 0)
- cpld_set_altbank();
- else
- cpld_set_defbank();
-#ifdef DEBUG
- } else if (strcmp(argv[1], "dump") == 0) {
- cpld_dump_regs();
-#endif
- } else
- rc = cmd_usage(cmdtp);
-
- return rc;
-}
-
-U_BOOT_CMD(
- cpld, CONFIG_SYS_MAXARGS, 1, do_cpld,
- "Reset the board or alternate bank",
- "reset - hard reset to default bank\n"
- "cpld reset altbank - reset to alternate bank\n"
-#ifdef DEBUG
- "cpld dump - display the CPLD registers\n"
-#endif
- );
diff --git a/board/freescale/t104xrdb/cpld.h b/board/freescale/t104xrdb/cpld.h
deleted file mode 100644
index a816aef10a..0000000000
--- a/board/freescale/t104xrdb/cpld.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/**
- * Copyright 2013 Freescale Semiconductor
- *
- * This file provides support for the ngPIXIS, a board-specific FPGA used on
- * some Freescale reference boards.
- */
-
-/*
- * CPLD register set. Feel free to add board-specific #ifdefs where necessary.
- */
-struct cpld_data {
- u8 cpld_ver; /* 0x00 - CPLD Major Revision Register */
- u8 cpld_ver_sub; /* 0x01 - CPLD Minor Revision Register */
- u8 hw_ver; /* 0x02 - Hardware Revision Register */
- u8 sw_ver; /* 0x03 - Software Revision register */
- u8 res0[12]; /* 0x04 - 0x0F - not used */
- u8 reset_ctl1; /* 0x10 - Reset control Register1 */
- u8 reset_ctl2; /* 0x11 - Reset control Register2 */
- u8 int_status; /* 0x12 - Interrupt status Register */
- u8 flash_ctl_status; /* 0x13 - Flash control and status register */
- u8 fan_ctl_status; /* 0x14 - Fan control and status register */
-#if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB)
- u8 int_mask; /* 0x15 - Interrupt mask Register */
-#else
- u8 led_ctl_status; /* 0x15 - LED control and status register */
-#endif
- u8 sfp_ctl_status; /* 0x16 - SFP control and status register */
- u8 misc_ctl_status; /* 0x17 - Miscellanies ctrl & status register*/
- u8 boot_override; /* 0x18 - Boot override register */
- u8 boot_config1; /* 0x19 - Boot config override register*/
- u8 boot_config2; /* 0x1A - Boot config override register*/
-} cpld_data_t;
-
-
-/* Pointer to the CPLD register set */
-
-u8 cpld_read(unsigned int reg);
-void cpld_write(unsigned int reg, u8 value);
-
-#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg))
-#define CPLD_WRITE(reg, value)\
- cpld_write(offsetof(struct cpld_data, reg), value)
-#define MISC_CTL_SG_SEL 0x80
-#define MISC_CTL_AURORA_SEL 0x02
-#define MISC_MUX_QE_TDM 0xc0
diff --git a/board/freescale/t104xrdb/ddr.c b/board/freescale/t104xrdb/ddr.c
deleted file mode 100644
index e313bf99cf..0000000000
--- a/board/freescale/t104xrdb/ddr.c
+++ /dev/null
@@ -1,145 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <hwconfig.h>
-#include <init.h>
-#include <log.h>
-#include <asm/mmu.h>
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-#include <asm/fsl_law.h>
-#include <asm/mpc85xx_gpio.h>
-#include <linux/delay.h>
-#include "ddr.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
- ulong ddr_freq;
-
- if (ctrl_num > 1) {
- printf("Not supported controller number %d\n", ctrl_num);
- return;
- }
- if (!pdimm->n_ranks)
- return;
-
- pbsp = udimms[0];
-
- /* Get clk_adjust according to the board ddr
- * freqency and n_banks specified in board_specific_parameters table.
- */
- ddr_freq = get_ddr_freq(0) / 1000000;
- while (pbsp->datarate_mhz_high) {
- if (pbsp->n_ranks == pdimm->n_ranks &&
- (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
- if (ddr_freq <= pbsp->datarate_mhz_high) {
- popts->clk_adjust = pbsp->clk_adjust;
- popts->wrlvl_start = pbsp->wrlvl_start;
- popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
- popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
- goto found;
- }
- pbsp_highest = pbsp;
- }
- pbsp++;
- }
-
- if (pbsp_highest) {
- printf("Error: board specific timing not found\n");
- printf("for data rate %lu MT/s\n", ddr_freq);
- printf("Trying to use the highest speed (%u) parameters\n",
- pbsp_highest->datarate_mhz_high);
- popts->clk_adjust = pbsp_highest->clk_adjust;
- popts->wrlvl_start = pbsp_highest->wrlvl_start;
- popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
- popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
- } else {
- panic("DIMM is not supported by this board");
- }
-found:
- debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
- "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
- "wrlvl_ctrl_3 0x%x\n",
- pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
- pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
- pbsp->wrlvl_ctl_3);
-
- /*
- * Factors to consider for half-strength driver enable:
- * - number of DIMMs installed
- */
-#ifdef CONFIG_SYS_FSL_DDR4
- popts->half_strength_driver_enable = 1;
- /* optimize cpo for erratum A-009942 */
- popts->cpo_sample = 0x59;
-#else
- popts->half_strength_driver_enable = 0;
-#endif
- /*
- * Write leveling override
- */
- popts->wrlvl_override = 1;
- popts->wrlvl_sample = 0xf;
-
- /*
- * rtt and rtt_wr override
- */
- popts->rtt_override = 0;
-
- /* Enable ZQ calibration */
- popts->zq_en = 1;
-
- /* DHC_EN =1, ODT = 75 Ohm */
-#ifdef CONFIG_SYS_FSL_DDR4
- popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_120OHM);
- popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_120OHM) |
- DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */
-#else
- popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
- popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
-#endif
-}
-
-#if defined(CONFIG_DEEP_SLEEP)
-void board_mem_sleep_setup(void)
-{
- void __iomem *cpld_base = (void *)CONFIG_SYS_CPLD_BASE;
-
- /* does not provide HW signals for power management */
- clrbits_8(cpld_base + 0x17, 0x40);
- /* Disable MCKE isolation */
- gpio_set_value(2, 0);
- udelay(1);
-}
-#endif
-
-int dram_init(void)
-{
- phys_size_t dram_size;
-
-#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
- puts("Initializing....using SPD\n");
- dram_size = fsl_ddr_sdram();
-#else
- dram_size = fsl_ddr_sdram_size();
-#endif
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
-
-#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
- fsl_dp_resume();
-#endif
-
- gd->ram_size = dram_size;
-
- return 0;
-}
diff --git a/board/freescale/t104xrdb/ddr.h b/board/freescale/t104xrdb/ddr.h
deleted file mode 100644
index f9d667f617..0000000000
--- a/board/freescale/t104xrdb/ddr.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#ifndef __DDR_H__
-#define __DDR_H__
-struct board_specific_parameters {
- u32 n_ranks;
- u32 datarate_mhz_high;
- u32 rank_gb;
- u32 clk_adjust;
- u32 wrlvl_start;
- u32 wrlvl_ctl_2;
- u32 wrlvl_ctl_3;
-};
-
-/*
- * These tables contain all valid speeds we want to override with board
- * specific parameters. datarate_mhz_high values need to be in ascending order
- * for each n_ranks group.
- */
-
-static const struct board_specific_parameters udimm0[] = {
- /*
- * memory controller 0
- * num| hi| rank| clk| wrlvl | wrlvl
- * ranks| mhz| GB |adjst| start | ctl2
- */
-#ifdef CONFIG_SYS_FSL_DDR4
- {2, 1600, 4, 8, 6, 0x07090A0c, 0x0e0f100a},
- {1, 1600, 4, 8, 5, 0x0607080B, 0x0C0C0D09},
-#elif defined(CONFIG_SYS_FSL_DDR3)
- {2, 833, 4, 8, 6, 0x06060607, 0x08080807},
- {2, 833, 0, 8, 6, 0x06060607, 0x08080807},
- {2, 1350, 4, 8, 7, 0x0708080A, 0x0A0B0C09},
- {2, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09},
- {2, 1666, 4, 8, 7, 0x0808090B, 0x0C0D0E0A},
- {2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A},
- {1, 833, 4, 8, 6, 0x06060607, 0x08080807},
- {1, 833, 0, 8, 6, 0x06060607, 0x08080807},
- {1, 1350, 4, 8, 7, 0x0708080A, 0x0A0B0C09},
- {1, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09},
- {1, 1666, 4, 8, 7, 0x0808090B, 0x0C0D0E0A},
- {1, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A},
-#else
-#error DDR type not defined
-#endif
- {}
-};
-
-#endif
-
-static const struct board_specific_parameters *udimms[] = {
- udimm0,
-};
diff --git a/board/freescale/t104xrdb/diu.c b/board/freescale/t104xrdb/diu.c
deleted file mode 100644
index 25c8597202..0000000000
--- a/board/freescale/t104xrdb/diu.c
+++ /dev/null
@@ -1,84 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- * Author: Priyanka Jain <Priyanka.Jain@freescale.com>
- */
-
-#include <clock_legacy.h>
-#include <asm/io.h>
-#include <common.h>
-#include <command.h>
-#include <fsl_diu_fb.h>
-#include <linux/ctype.h>
-#include <video_fb.h>
-
-#include "../common/diu_ch7301.h"
-
-#include "cpld.h"
-#include "t104xrdb.h"
-
-/*
- * DIU Area Descriptor
- *
- * Note that we need to byte-swap the value before it's written to the AD
- * register. So even though the registers don't look like they're in the same
- * bit positions as they are on the MPC8610, the same value is written to the
- * AD register on the MPC8610 and on the P1022.
- */
-#define AD_BYTE_F 0x10000000
-#define AD_ALPHA_C_SHIFT 25
-#define AD_BLUE_C_SHIFT 23
-#define AD_GREEN_C_SHIFT 21
-#define AD_RED_C_SHIFT 19
-#define AD_PIXEL_S_SHIFT 16
-#define AD_COMP_3_SHIFT 12
-#define AD_COMP_2_SHIFT 8
-#define AD_COMP_1_SHIFT 4
-#define AD_COMP_0_SHIFT 0
-
-void diu_set_pixel_clock(unsigned int pixclock)
-{
- unsigned long speed_ccb, temp;
- u32 pixval;
- int ret;
-
- speed_ccb = get_bus_freq(0);
- temp = 1000000000 / pixclock;
- temp *= 1000;
- pixval = speed_ccb / temp;
-
- /* Program HDMI encoder */
- ret = diu_set_dvi_encoder(temp);
- if (ret) {
- puts("Failed to set DVI encoder\n");
- return;
- }
-
- /* Program pixel clock */
- out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR,
- ((pixval << PXCK_BITS_START) & PXCK_MASK));
-
- /* enable clock*/
- out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR, PXCKEN_MASK |
- ((pixval << PXCK_BITS_START) & PXCK_MASK));
-}
-
-int platform_diu_init(unsigned int xres, unsigned int yres, const char *port)
-{
- u32 pixel_format;
- u8 sw;
-
- /*Configure Display ouput port as HDMI*/
- sw = CPLD_READ(sfp_ctl_status);
- CPLD_WRITE(sfp_ctl_status , sw & ~(CPLD_DIU_SEL_DFP));
-
- pixel_format = cpu_to_le32(AD_BYTE_F | (3 << AD_ALPHA_C_SHIFT) |
- (0 << AD_BLUE_C_SHIFT) | (1 << AD_GREEN_C_SHIFT) |
- (2 << AD_RED_C_SHIFT) | (8 << AD_COMP_3_SHIFT) |
- (8 << AD_COMP_2_SHIFT) | (8 << AD_COMP_1_SHIFT) |
- (8 << AD_COMP_0_SHIFT) | (3 << AD_PIXEL_S_SHIFT));
-
- printf("DIU: Switching to monitor DVI @ %ux%u\n", xres, yres);
-
- return fsl_diu_init(xres, yres, pixel_format, 0);
-}
diff --git a/board/freescale/t104xrdb/eth.c b/board/freescale/t104xrdb/eth.c
deleted file mode 100644
index 9cbc8754dc..0000000000
--- a/board/freescale/t104xrdb/eth.c
+++ /dev/null
@@ -1,154 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/fsl_serdes.h>
-#include <asm/immap_85xx.h>
-#include <fm_eth.h>
-#include <fsl_mdio.h>
-#include <malloc.h>
-#include <fsl_dtsec.h>
-#include <vsc9953.h>
-
-#include "../common/fman.h"
-
-int board_eth_init(bd_t *bis)
-{
-#ifdef CONFIG_FMAN_ENET
- struct memac_mdio_info memac_mdio_info;
- unsigned int i;
- int phy_addr = 0;
-#ifdef CONFIG_VSC9953
- phy_interface_t phy_int;
- struct mii_dev *bus;
-#endif
-
- printf("Initializing Fman\n");
-
- memac_mdio_info.regs =
- (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
- memac_mdio_info.name = DEFAULT_FM_MDIO_NAME;
-
- /* Register the real 1G MDIO bus */
- fm_memac_mdio_init(bis, &memac_mdio_info);
-
- /*
- * Program on board RGMII, SGMII PHY addresses.
- */
- for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
- int idx = i - FM1_DTSEC1;
-
- switch (fm_info_get_enet_if(i)) {
-#if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB)
- case PHY_INTERFACE_MODE_SGMII:
- /* T1040RDB & T1040D4RDB only supports SGMII on
- * DTSEC3
- */
- fm_info_set_phy_address(FM1_DTSEC3,
- CONFIG_SYS_SGMII1_PHY_ADDR);
- break;
-#endif
-#ifdef CONFIG_TARGET_T1042RDB
- case PHY_INTERFACE_MODE_SGMII:
- /* T1042RDB doesn't supports SGMII on DTSEC1 & DTSEC2 */
- if ((FM1_DTSEC1 == i) || (FM1_DTSEC2 == i))
- fm_info_set_phy_address(i, 0);
- /* T1042RDB only supports SGMII on DTSEC3 */
- fm_info_set_phy_address(FM1_DTSEC3,
- CONFIG_SYS_SGMII1_PHY_ADDR);
- break;
-#endif
-#ifdef CONFIG_TARGET_T1042D4RDB
- case PHY_INTERFACE_MODE_SGMII:
- /* T1042D4RDB supports SGMII on DTSEC1, DTSEC2
- * & DTSEC3
- */
- if (FM1_DTSEC1 == i)
- phy_addr = CONFIG_SYS_SGMII1_PHY_ADDR;
- if (FM1_DTSEC2 == i)
- phy_addr = CONFIG_SYS_SGMII2_PHY_ADDR;
- if (FM1_DTSEC3 == i)
- phy_addr = CONFIG_SYS_SGMII3_PHY_ADDR;
- fm_info_set_phy_address(i, phy_addr);
- break;
-#endif
- case PHY_INTERFACE_MODE_RGMII:
- if (FM1_DTSEC4 == i)
- phy_addr = CONFIG_SYS_RGMII1_PHY_ADDR;
- if (FM1_DTSEC5 == i)
- phy_addr = CONFIG_SYS_RGMII2_PHY_ADDR;
- fm_info_set_phy_address(i, phy_addr);
- break;
- case PHY_INTERFACE_MODE_QSGMII:
- fm_info_set_phy_address(i, 0);
- break;
- case PHY_INTERFACE_MODE_NONE:
- fm_info_set_phy_address(i, 0);
- break;
- default:
- printf("Fman1: DTSEC%u set to unknown interface %i\n",
- idx + 1, fm_info_get_enet_if(i));
- fm_info_set_phy_address(i, 0);
- break;
- }
- if (fm_info_get_enet_if(i) == PHY_INTERFACE_MODE_QSGMII ||
- fm_info_get_enet_if(i) == PHY_INTERFACE_MODE_NONE)
- fm_info_set_mdio(i, NULL);
- else
- fm_info_set_mdio(i,
- miiphy_get_dev_by_name(
- DEFAULT_FM_MDIO_NAME));
- }
-
-#ifdef CONFIG_VSC9953
- /* SerDes configured for QSGMII */
- if (serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_A) >= 0) {
- for (i = 0; i < 4; i++) {
- bus = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
- phy_addr = CONFIG_SYS_FM1_QSGMII11_PHY_ADDR + i;
- phy_int = PHY_INTERFACE_MODE_QSGMII;
-
- vsc9953_port_info_set_mdio(i, bus);
- vsc9953_port_info_set_phy_address(i, phy_addr);
- vsc9953_port_info_set_phy_int(i, phy_int);
- vsc9953_port_enable(i);
- }
- }
- if (serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_B) >= 0) {
- for (i = 4; i < 8; i++) {
- bus = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
- phy_addr = CONFIG_SYS_FM1_QSGMII21_PHY_ADDR + i - 4;
- phy_int = PHY_INTERFACE_MODE_QSGMII;
-
- vsc9953_port_info_set_mdio(i, bus);
- vsc9953_port_info_set_phy_address(i, phy_addr);
- vsc9953_port_info_set_phy_int(i, phy_int);
- vsc9953_port_enable(i);
- }
- }
-
- /* Connect DTSEC1 to L2 switch if it doesn't have a PHY */
- if (serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC1) < 0)
- vsc9953_port_enable(8);
-
- /* Connect DTSEC2 to L2 switch if it doesn't have a PHY */
- if (serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC2) < 0) {
- /* Enable L2 On MAC2 using SCFG */
- struct ccsr_scfg *scfg = (struct ccsr_scfg *)
- CONFIG_SYS_MPC85xx_SCFG;
-
- out_be32(&scfg->esgmiiselcr, in_be32(&scfg->esgmiiselcr) |
- (0x80000000));
- vsc9953_port_enable(9);
- }
-#endif
-
- cpu_eth_init(bis);
-#endif
-
- return pci_eth_init(bis);
-}
diff --git a/board/freescale/t104xrdb/law.c b/board/freescale/t104xrdb/law.c
deleted file mode 100644
index 0f6b71a8c2..0000000000
--- a/board/freescale/t104xrdb/law.c
+++ /dev/null
@@ -1,31 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-struct law_entry law_table[] = {
-#ifdef CONFIG_MTD_NOR_FLASH
- SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
-#endif
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
- SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
-#endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
- SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
-#endif
-#ifdef CONFIG_SYS_CPLD_BASE_PHYS
- SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC),
-#endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
- SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
-#endif
-#ifdef CONFIG_SYS_NAND_BASE_PHYS
- SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
-#endif
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/t104xrdb/pci.c b/board/freescale/t104xrdb/pci.c
deleted file mode 100644
index ff7cf36446..0000000000
--- a/board/freescale/t104xrdb/pci.c
+++ /dev/null
@@ -1,25 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <init.h>
-#include <pci.h>
-#include <asm/fsl_pci.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <asm/fsl_serdes.h>
-
-#if !defined(CONFIG_DM_PCI)
-void pci_init_board(void)
-{
- fsl_pcie_init_board(0);
-}
-
-void pci_of_setup(void *blob, bd_t *bd)
-{
- FT_FSL_PCI_SETUP;
-}
-#endif
diff --git a/board/freescale/t104xrdb/spl.c b/board/freescale/t104xrdb/spl.c
deleted file mode 100644
index 2306d0391e..0000000000
--- a/board/freescale/t104xrdb/spl.c
+++ /dev/null
@@ -1,142 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/* Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <clock_legacy.h>
-#include <console.h>
-#include <env_internal.h>
-#include <init.h>
-#include <malloc.h>
-#include <ns16550.h>
-#include <nand.h>
-#include <i2c.h>
-#include <mmc.h>
-#include <fsl_esdhc.h>
-#include <spi_flash.h>
-#include "../common/sleep.h"
-#include "../common/spl.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-phys_size_t get_effective_memsize(void)
-{
- return CONFIG_SYS_L3_SIZE;
-}
-
-unsigned long get_board_sys_clk(void)
-{
- return CONFIG_SYS_CLK_FREQ;
-}
-
-unsigned long get_board_ddr_clk(void)
-{
- return CONFIG_DDR_CLK_FREQ;
-}
-
-#define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000
-void board_init_f(ulong bootflag)
-{
- u32 plat_ratio, sys_clk, uart_clk;
-#if defined(CONFIG_SPL_NAND_BOOT) && defined(CONFIG_A008044_WORKAROUND)
- u32 porsr1, pinctl;
- u32 svr = get_svr();
-#endif
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
-#if defined(CONFIG_SPL_NAND_BOOT) && defined(CONFIG_A008044_WORKAROUND)
- if (IS_SVR_REV(svr, 1, 0)) {
- /*
- * There is T1040 SoC issue where NOR, FPGA are inaccessible
- * during NAND boot because IFC signals > IFC_AD7 are not
- * enabled. This workaround changes RCW source to make all
- * signals enabled.
- */
- porsr1 = in_be32(&gur->porsr1);
- pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK))
- | 0x24800000);
- out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000),
- pinctl);
- }
-#endif
-
- /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
- memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
-
- /* Update GD pointer */
- gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
-
-#ifdef CONFIG_DEEP_SLEEP
- /* disable the console if boot from deep sleep */
- if (is_warm_boot())
- fsl_dp_disable_console();
-#endif
- /* compiler optimization barrier needed for GCC >= 3.4 */
- __asm__ __volatile__("" : : : "memory");
-
- console_init_f();
-
- /* initialize selected port with appropriate baud rate */
- sys_clk = get_board_sys_clk();
- plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
- uart_clk = sys_clk * plat_ratio / 2;
-
- NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
- uart_clk / 16 / CONFIG_BAUDRATE);
-
- relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
- bd_t *bd;
-
- bd = (bd_t *)(gd + sizeof(gd_t));
- memset(bd, 0, sizeof(bd_t));
- gd->bd = bd;
- bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
- bd->bi_memsize = CONFIG_SYS_L3_SIZE;
-
- arch_cpu_init();
- get_clocks();
- mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
- CONFIG_SPL_RELOC_MALLOC_SIZE);
- gd->flags |= GD_FLG_FULL_MALLOC_INIT;
-
-#ifdef CONFIG_SPL_MMC_BOOT
- mmc_initialize(bd);
-#endif
-
- /* relocate environment function pointers etc. */
-#if defined(CONFIG_ENV_IS_IN_NAND) || defined(CONFIG_ENV_IS_IN_MMC) || \
- defined(CONFIG_ENV_IS_IN_SPI_FLASH)
-#ifdef CONFIG_SPL_NAND_BOOT
- nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
- (uchar *)SPL_ENV_ADDR);
-#endif
-#ifdef CONFIG_SPL_MMC_BOOT
- mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
- (uchar *)SPL_ENV_ADDR);
-#endif
-#ifdef CONFIG_SPL_SPI_BOOT
- fsl_spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
- (uchar *)SPL_ENV_ADDR);
-#endif
- gd->env_addr = (ulong)(SPL_ENV_ADDR);
- gd->env_valid = ENV_VALID;
-#endif
-
- i2c_init_all();
-
- puts("\n\n");
-
- dram_init();
-
-#ifdef CONFIG_SPL_MMC_BOOT
- mmc_boot();
-#elif defined(CONFIG_SPL_SPI_BOOT)
- fsl_spi_boot();
-#elif defined(CONFIG_SPL_NAND_BOOT)
- nand_boot();
-#endif
-}
diff --git a/board/freescale/t104xrdb/t1040_nand_rcw.cfg b/board/freescale/t104xrdb/t1040_nand_rcw.cfg
deleted file mode 100644
index 3300c184a1..0000000000
--- a/board/freescale/t104xrdb/t1040_nand_rcw.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-#PBL preamble and RCW header
-aa55aa55 010e0100
-# serdes protocol 0x66
-0c18000e 0e000000 00000000 00000000
-66000002 80000002 e8106000 01000000
-00000000 00000000 00000000 00032810
-00000000 0342500f 00000000 00000000
diff --git a/board/freescale/t104xrdb/t1040_sd_rcw.cfg b/board/freescale/t104xrdb/t1040_sd_rcw.cfg
deleted file mode 100644
index fd3e8c5bbf..0000000000
--- a/board/freescale/t104xrdb/t1040_sd_rcw.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-#PBL preamble and RCW header
-aa55aa55 010e0100
-# serdes protocol 0x66
-0c18000e 0e000000 00000000 00000000
-66000002 80000002 68106000 01000000
-00000000 00000000 00000000 00032810
-00000000 0342500f 00000000 00000000
diff --git a/board/freescale/t104xrdb/t1040_spi_rcw.cfg b/board/freescale/t104xrdb/t1040_spi_rcw.cfg
deleted file mode 100644
index fccde5e01f..0000000000
--- a/board/freescale/t104xrdb/t1040_spi_rcw.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-#PBL preamble and RCW header
-aa55aa55 010e0100
-# serdes protocol 0x66
-0c18000e 0e000000 00000000 00000000
-66000002 80000002 58106000 01000000
-00000000 00000000 00000000 00032810
-00000000 0342500f 00000000 00000000
diff --git a/board/freescale/t104xrdb/t1040d4_nand_rcw.cfg b/board/freescale/t104xrdb/t1040d4_nand_rcw.cfg
deleted file mode 100644
index c1034b3dfa..0000000000
--- a/board/freescale/t104xrdb/t1040d4_nand_rcw.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-#PBL preamble and RCW header
-aa55aa55 010e0100
-# serdes protocol 0x66
-0c18000e 0e000000 00000000 00000000
-66000002 40000002 ec027000 01000000
-00000000 00000000 00000000 00030810
-00000000 0342580f 00000000 00000000
diff --git a/board/freescale/t104xrdb/t1040d4_sd_rcw.cfg b/board/freescale/t104xrdb/t1040d4_sd_rcw.cfg
deleted file mode 100644
index e6f7585bb0..0000000000
--- a/board/freescale/t104xrdb/t1040d4_sd_rcw.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-#PBL preamble and RCW header
-aa55aa55 010e0100
-# serdes protocol 0x66
-0c18000e 0e000000 00000000 00000000
-66000002 40000002 6c027000 01000000
-00000000 00000000 00000000 00030810
-00000000 0342580f 00000000 00000000
diff --git a/board/freescale/t104xrdb/t1040d4_spi_rcw.cfg b/board/freescale/t104xrdb/t1040d4_spi_rcw.cfg
deleted file mode 100644
index cde862dff5..0000000000
--- a/board/freescale/t104xrdb/t1040d4_spi_rcw.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-#PBL preamble and RCW header
-aa55aa55 010e0100
-# serdes protocol 0x66
-0c18000e 0e000000 00000000 00000000
-66000002 40000002 5c027000 01000000
-00000000 00000000 00000000 00030810
-00000000 0342580f 00000000 00000000
diff --git a/board/freescale/t104xrdb/t1042_nand_rcw.cfg b/board/freescale/t104xrdb/t1042_nand_rcw.cfg
deleted file mode 100644
index db4d52f397..0000000000
--- a/board/freescale/t104xrdb/t1042_nand_rcw.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-#PBL preamble and RCW header
-aa55aa55 010e0100
-# serdes protocol 0x86
-0c18000e 0e000000 00000000 00000000
-86000002 80000002 ec027000 01000000
-00000000 00000000 00000000 00032810
-00000000 0342500f 00000000 00000000
diff --git a/board/freescale/t104xrdb/t1042_pi_nand_rcw.cfg b/board/freescale/t104xrdb/t1042_pi_nand_rcw.cfg
deleted file mode 100644
index 57de89ad0e..0000000000
--- a/board/freescale/t104xrdb/t1042_pi_nand_rcw.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-#PBL preamble and RCW header
-aa55aa55 010e0100
-# serdes protocol 0x06
-0c18000e 0e000000 00000000 00000000
-06000002 00400002 e8106000 01000000
-00000000 00000000 00000000 00030810
-00000000 01fe0a06 00000000 00000000
diff --git a/board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg b/board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg
deleted file mode 100644
index bbce9a3693..0000000000
--- a/board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-#PBL preamble and RCW header
-aa55aa55 010e0100
-# serdes protocol 0x06
-0c18000e 0e000000 00000000 00000000
-06000002 00400002 68106000 01000000
-00000000 00000000 00000000 00030810
-00000000 01fe0a06 00000000 00000000
diff --git a/board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg b/board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg
deleted file mode 100644
index b1d8b4c65a..0000000000
--- a/board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-#PBL preamble and RCW header
-aa55aa55 010e0100
-# serdes protocol 0x06
-0c18000e 0e000000 00000000 00000000
-06000002 00400002 58106000 01000000
-00000000 00000000 00000000 00030810
-00000000 01fe0a06 00000000 00000000
diff --git a/board/freescale/t104xrdb/t1042_sd_rcw.cfg b/board/freescale/t104xrdb/t1042_sd_rcw.cfg
deleted file mode 100644
index d77bf189b2..0000000000
--- a/board/freescale/t104xrdb/t1042_sd_rcw.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-#PBL preamble and RCW header
-aa55aa55 010e0100
-# serdes protocol 0x86
-0c18000e 0e000000 00000000 00000000
-86000002 80000002 6c027000 01000000
-00000000 00000000 00000000 00032810
-00000000 0342500f 00000000 00000000
diff --git a/board/freescale/t104xrdb/t1042_spi_rcw.cfg b/board/freescale/t104xrdb/t1042_spi_rcw.cfg
deleted file mode 100644
index e8a3ad1280..0000000000
--- a/board/freescale/t104xrdb/t1042_spi_rcw.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-#PBL preamble and RCW header
-aa55aa55 010e0100
-# serdes protocol 0x86
-0c18000e 0e000000 00000000 00000000
-86000002 80000002 5c027000 01000000
-00000000 00000000 00000000 00032810
-00000000 0342500f 00000000 00000000
diff --git a/board/freescale/t104xrdb/t1042d4_nand_rcw.cfg b/board/freescale/t104xrdb/t1042d4_nand_rcw.cfg
deleted file mode 100644
index 9e0ee2795f..0000000000
--- a/board/freescale/t104xrdb/t1042d4_nand_rcw.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-#PBL preamble and RCW header
-aa55aa55 010e0100
-# serdes protocol 0x86
-0c18000e 0e000000 00000000 00000000
-86000002 40000002 ec027000 01000000
-00000000 00000000 00000000 00030810
-00000000 0342500f 00000000 00000000
diff --git a/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg b/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg
deleted file mode 100644
index 9d9046d654..0000000000
--- a/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-#PBL preamble and RCW header
-aa55aa55 010e0100
-# serdes protocol 0x86
-0c18000e 0e000000 00000000 00000000
-86000002 40000002 6c027000 01000000
-00000000 00000000 00000000 00030810
-00000000 0342500f 00000000 00000000
diff --git a/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg b/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg
deleted file mode 100644
index f1ec98932f..0000000000
--- a/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-#PBL preamble and RCW header
-aa55aa55 010e0100
-# serdes protocol 0x86
-0c18000e 0e000000 00000000 00000000
-86000002 40000002 5c027000 01000000
-00000000 00000000 00000000 00030810
-00000000 0342500f 00000000 00000000
diff --git a/board/freescale/t104xrdb/t104x_pbi.cfg b/board/freescale/t104xrdb/t104x_pbi.cfg
deleted file mode 100644
index 51945b4748..0000000000
--- a/board/freescale/t104xrdb/t104x_pbi.cfg
+++ /dev/null
@@ -1,36 +0,0 @@
-#PBI commands
-#Software Workaround for errata A-007662 to train PCIe2 controller in Gen2 speed
-09250100 00000400
-09250108 00002000
-#Software Workaround for errata A-008007 to reset PVR register
-09000010 0000000b
-09000014 c0000000
-09000018 81d00017
-89020400 a1000000
-091380c0 000f0000
-89020400 00000000
-#Initialize CPC1
-09010000 00200400
-09138000 00000000
-091380c0 00000100
-#Configure CPC1 as 256KB SRAM
-09010100 00000000
-09010104 fffc0007
-09010f00 081e000d
-09010000 80000000
-#Configure LAW for CPC1
-09000cd0 00000000
-09000cd4 fffc0000
-09000cd8 81000011
-#Configure alternate space
-09000010 00000000
-09000014 ff000000
-09000018 81000000
-#Configure SPI controller
-09110000 80000403
-09110020 2d170008
-09110024 00100008
-09110028 00100008
-0911002c 00100008
-#Flush PBL data
-091380c0 000FFFFF
diff --git a/board/freescale/t104xrdb/t104x_pbi_sb.cfg b/board/freescale/t104xrdb/t104x_pbi_sb.cfg
deleted file mode 100644
index 98dc8e4c24..0000000000
--- a/board/freescale/t104xrdb/t104x_pbi_sb.cfg
+++ /dev/null
@@ -1,38 +0,0 @@
-#PBI commands
-#Software Workaround for errata A-007662 to train PCIe2 controller in Gen2 speed
-09250100 00000400
-09250108 00002000
-#Software Workaround for errata A-008007 to reset PVR register
-09000010 0000000b
-09000014 c0000000
-09000018 81d00017
-89020400 a1000000
-091380c0 000f0000
-89020400 00000000
-#Initialize CPC1
-09010000 00200400
-09138000 00000000
-091380c0 00000100
-#Configure CPC1 as 256KB SRAM
-09010100 00000000
-09010104 bffc0007
-09010f00 081e000d
-09010000 80000000
-#Configure LAW for CPC1
-09000cd0 00000000
-09000cd4 bffc0000
-09000cd8 81000011
-#Configure alternate space
-09000010 00000000
-09000014 bf000000
-09000018 81000000
-#Configure SPI controller
-09110000 80000403
-09110020 2d170008
-09110024 00100008
-09110028 00100008
-0911002c 00100008
-#Flush PBL data
-091380c0 000FFFFF
-090e0200 bffd0000
-091380c0 000FFFFF
diff --git a/board/freescale/t104xrdb/t104xrdb.c b/board/freescale/t104xrdb/t104xrdb.c
deleted file mode 100644
index 6a4b351068..0000000000
--- a/board/freescale/t104xrdb/t104xrdb.c
+++ /dev/null
@@ -1,161 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <env.h>
-#include <fdt_support.h>
-#include <hwconfig.h>
-#include <image.h>
-#include <init.h>
-#include <log.h>
-#include <netdev.h>
-#include <linux/compiler.h>
-#include <asm/mmu.h>
-#include <asm/processor.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_fdt.h>
-#include <asm/fsl_law.h>
-#include <asm/fsl_serdes.h>
-#include <asm/fsl_liodn.h>
-#include <fm_eth.h>
-#include "../common/sleep.h"
-#include "t104xrdb.h"
-#include "cpld.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
- struct cpu_type *cpu = gd->arch.cpu;
- u8 sw;
-
-#if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB)
- printf("Board: %sD4RDB\n", cpu->name);
-#else
- printf("Board: %sRDB\n", cpu->name);
-#endif
- printf("Board rev: 0x%02x CPLD ver: 0x%02x, ",
- CPLD_READ(hw_ver), CPLD_READ(sw_ver));
-
- sw = CPLD_READ(flash_ctl_status);
- sw = ((sw & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
-
- printf("vBank: %d\n", sw);
-
- return 0;
-}
-
-int board_early_init_f(void)
-{
-#if defined(CONFIG_DEEP_SLEEP)
- if (is_warm_boot())
- fsl_dp_disable_console();
-#endif
-
- return 0;
-}
-
-int board_early_init_r(void)
-{
-#ifdef CONFIG_SYS_FLASH_BASE
- const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
- int flash_esel = find_tlb_idx((void *)flashbase, 1);
-
- /*
- * Remap Boot flash region to caching-inhibited
- * so that flash can be erased properly.
- */
-
- /* Flush d-cache and invalidate i-cache of any FLASH data */
- flush_dcache();
- invalidate_icache();
-
- if (flash_esel == -1) {
- /* very unlikely unless something is messed up */
- puts("Error: Could not find TLB for FLASH BASE\n");
- flash_esel = 2; /* give our best effort to continue */
- } else {
- /* invalidate existing TLB entry for flash */
- disable_tlb(flash_esel);
- }
-
- set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, flash_esel, BOOKE_PAGESZ_256M, 1);
-#endif
- return 0;
-}
-
-int misc_init_r(void)
-{
- ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- u32 srds_s1;
-
- srds_s1 = in_be32(&gur->rcwsr[4]) >> 24;
-
- printf("SERDES Reference : 0x%X\n", srds_s1);
-
- /* select SGMII*/
- if (srds_s1 == 0x86)
- CPLD_WRITE(misc_ctl_status, CPLD_READ(misc_ctl_status) |
- MISC_CTL_SG_SEL);
-
- /* select SGMII and Aurora*/
- if (srds_s1 == 0x8E)
- CPLD_WRITE(misc_ctl_status, CPLD_READ(misc_ctl_status) |
- MISC_CTL_SG_SEL | MISC_CTL_AURORA_SEL);
-
-#if defined(CONFIG_TARGET_T1040D4RDB)
- if (hwconfig("qe-tdm")) {
- CPLD_WRITE(sfp_ctl_status, CPLD_READ(sfp_ctl_status) |
- MISC_MUX_QE_TDM);
- printf("QECSR : 0x%02x, mux to qe-tdm\n",
- CPLD_READ(sfp_ctl_status));
- }
- /* Mask all CPLD interrupt sources, except QSGMII interrupts */
- if (CPLD_READ(sw_ver) < 0x03) {
- debug("CPLD SW version 0x%02x doesn't support int_mask\n",
- CPLD_READ(sw_ver));
- } else {
- CPLD_WRITE(int_mask, CPLD_INT_MASK_ALL &
- ~(CPLD_INT_MASK_QSGMII1 | CPLD_INT_MASK_QSGMII2));
- }
-#endif
-
- return 0;
-}
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
- phys_addr_t base;
- phys_size_t size;
-
- ft_cpu_setup(blob, bd);
-
- base = env_get_bootm_low();
- size = env_get_bootm_size();
-
- fdt_fixup_memory(blob, (u64)base, (u64)size);
-
-#ifdef CONFIG_PCI
- pci_of_setup(blob, bd);
-#endif
-
- fdt_fixup_liodn(blob);
-
-#ifdef CONFIG_HAS_FSL_DR_USB
- fsl_fdt_fixup_dr_usb(blob, bd);
-#endif
-
-#ifdef CONFIG_SYS_DPAA_FMAN
- fdt_fixup_fman_ethernet(blob);
-#endif
-
- if (hwconfig("qe-tdm"))
- fdt_del_diu(blob);
- return 0;
-}
diff --git a/board/freescale/t104xrdb/t104xrdb.h b/board/freescale/t104xrdb/t104xrdb.h
deleted file mode 100644
index b6459cd629..0000000000
--- a/board/freescale/t104xrdb/t104xrdb.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#ifndef __T104x_RDB_H__
-#define __T104x_RDB_H__
-
-void fdt_fixup_board_enet(void *blob);
-void pci_of_setup(void *blob, bd_t *bd);
-
-#endif
diff --git a/board/freescale/t104xrdb/tlb.c b/board/freescale/t104xrdb/tlb.c
deleted file mode 100644
index 9dcba7933f..0000000000
--- a/board/freescale/t104xrdb/tlb.c
+++ /dev/null
@@ -1,131 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
- /* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
-
- /* TLB 1 */
- /* *I*** - Covers boot page */
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) && \
- !defined(CONFIG_NXP_ESBC)
- /*
- * *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the
- * SRAM is at 0xfffc0000, it covered the 0xfffff000.
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_256K, 1),
-
-#elif defined(CONFIG_NXP_ESBC) && defined(CONFIG_SPL_BUILD)
- /*
- * *I*G - L3SRAM. When L3 is used as 256K SRAM, in case of Secure Boot
- * the physical address of the SRAM is at 0xbffc0000,
- * and virtual address is 0xfffc0000
- */
-
- SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_VADDR,
- CONFIG_SYS_INIT_L3_ADDR,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_256K, 1),
-#else
- SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_4K, 1),
-#endif
-
- /* *I*G* - CCSRBAR */
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 1, BOOKE_PAGESZ_16M, 1),
-
- /* *I*G* - Flash, localbus */
- /* This will be changed to *I*G* after relocation to RAM. */
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
- MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
- 0, 2, BOOKE_PAGESZ_256M, 1),
-
-#ifndef CONFIG_SPL_BUILD
- /* *I*G* - PCI */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 3, BOOKE_PAGESZ_1G, 1),
-
- /* *I*G* - PCI I/O */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 4, BOOKE_PAGESZ_256K, 1),
-
- /* Bman/Qman */
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
- SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 5, BOOKE_PAGESZ_16M, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
- CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 6, BOOKE_PAGESZ_16M, 1),
-#endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
- SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 7, BOOKE_PAGESZ_16M, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
- CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 8, BOOKE_PAGESZ_16M, 1),
-#endif
-#endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
- SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 9, BOOKE_PAGESZ_4M, 1),
-#endif
-#ifdef CONFIG_SYS_NAND_BASE
- /*
- * *I*G - NAND
- * entry 14 and 15 has been used hard coded, they will be disabled
- * in cpu_init_f, so we use entry 16 for nand.
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 10, BOOKE_PAGESZ_64K, 1),
-#endif
-#ifdef CONFIG_SYS_CPLD_BASE
- SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 11, BOOKE_PAGESZ_256K, 1),
-#endif
-
-#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
- SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
- 0, 12, BOOKE_PAGESZ_1G, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
- CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
- 0, 13, BOOKE_PAGESZ_1G, 1)
-#endif
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/configs/T1040D4RDB_NAND_defconfig b/configs/T1040D4RDB_NAND_defconfig
deleted file mode 100644
index 87b2a76973..0000000000
--- a/configs/T1040D4RDB_NAND_defconfig
+++ /dev/null
@@ -1,75 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x30001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x180000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T1040D4RDB=y
-CONFIG_SYS_CUSTOM_LDSCRIPT=y
-CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL"
-CONFIG_BOOTDELAY=10
-CONFIG_SILENT_CONSOLE=y
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_NAND_BOOT=y
-CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_ETHSW=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T1040D4RDB_SDCARD_defconfig b/configs/T1040D4RDB_SDCARD_defconfig
deleted file mode 100644
index 4b9e428045..0000000000
--- a/configs/T1040D4RDB_SDCARD_defconfig
+++ /dev/null
@@ -1,72 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x30001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T1040D4RDB=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD"
-CONFIG_BOOTDELAY=10
-CONFIG_SILENT_CONSOLE=y
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_MMC_BOOT=y
-CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_ETHSW=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T1040D4RDB_SECURE_BOOT_defconfig b/configs/T1040D4RDB_SECURE_BOOT_defconfig
deleted file mode 100644
index 7adffb73ea..0000000000
--- a/configs/T1040D4RDB_SECURE_BOOT_defconfig
+++ /dev/null
@@ -1,61 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T1040D4RDB=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_SILENT_CONSOLE=y
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_ETHSW=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
-CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T1040D4RDB_SPIFLASH_defconfig b/configs/T1040D4RDB_SPIFLASH_defconfig
deleted file mode 100644
index 2320b7214c..0000000000
--- a/configs/T1040D4RDB_SPIFLASH_defconfig
+++ /dev/null
@@ -1,75 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x30001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T1040D4RDB=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH"
-CONFIG_BOOTDELAY=10
-CONFIG_SILENT_CONSOLE=y
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_SPI_BOOT=y
-CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_ETHSW=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_ADDR=0xFFFC9000
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T1040D4RDB_defconfig b/configs/T1040D4RDB_defconfig
deleted file mode 100644
index eb25930ff7..0000000000
--- a/configs/T1040D4RDB_defconfig
+++ /dev/null
@@ -1,59 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T1040D4RDB=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_SILENT_CONSOLE=y
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_ETHSW=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T1040RDB_NAND_defconfig b/configs/T1040RDB_NAND_defconfig
deleted file mode 100644
index 7cf98473bd..0000000000
--- a/configs/T1040RDB_NAND_defconfig
+++ /dev/null
@@ -1,76 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x30001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x180000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T1040RDB=y
-CONFIG_SYS_CUSTOM_LDSCRIPT=y
-CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL"
-CONFIG_BOOTDELAY=10
-CONFIG_SILENT_CONSOLE=y
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_NAND_BOOT=y
-CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_ETHSW=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_FSL_CAAM=y
-CONFIG_SYS_FSL_DDR3=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T1040RDB_SDCARD_defconfig b/configs/T1040RDB_SDCARD_defconfig
deleted file mode 100644
index 321260fc8b..0000000000
--- a/configs/T1040RDB_SDCARD_defconfig
+++ /dev/null
@@ -1,73 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x30001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T1040RDB=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD"
-CONFIG_BOOTDELAY=10
-CONFIG_SILENT_CONSOLE=y
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_MMC_BOOT=y
-CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_ETHSW=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_FSL_CAAM=y
-CONFIG_SYS_FSL_DDR3=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T1040RDB_SECURE_BOOT_defconfig b/configs/T1040RDB_SECURE_BOOT_defconfig
deleted file mode 100644
index 910b984f47..0000000000
--- a/configs/T1040RDB_SECURE_BOOT_defconfig
+++ /dev/null
@@ -1,62 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T1040RDB=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_SILENT_CONSOLE=y
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_ETHSW=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
-CONFIG_DM=y
-CONFIG_SYS_FSL_DDR3=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T1040RDB_SPIFLASH_defconfig b/configs/T1040RDB_SPIFLASH_defconfig
deleted file mode 100644
index 65ab4e0c79..0000000000
--- a/configs/T1040RDB_SPIFLASH_defconfig
+++ /dev/null
@@ -1,76 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x30001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T1040RDB=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH"
-CONFIG_BOOTDELAY=10
-CONFIG_SILENT_CONSOLE=y
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_SPI_BOOT=y
-CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_ETHSW=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_ADDR=0xFFFC9000
-CONFIG_FSL_CAAM=y
-CONFIG_SYS_FSL_DDR3=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T1040RDB_defconfig b/configs/T1040RDB_defconfig
deleted file mode 100644
index e8c5393b18..0000000000
--- a/configs/T1040RDB_defconfig
+++ /dev/null
@@ -1,60 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T1040RDB=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_SILENT_CONSOLE=y
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_ETHSW=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_FSL_CAAM=y
-CONFIG_SYS_FSL_DDR3=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T1042D4RDB_NAND_defconfig b/configs/T1042D4RDB_NAND_defconfig
deleted file mode 100644
index 1602fb890e..0000000000
--- a/configs/T1042D4RDB_NAND_defconfig
+++ /dev/null
@@ -1,86 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x30001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x180000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T1042D4RDB=y
-CONFIG_SYS_CUSTOM_LDSCRIPT=y
-CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL"
-CONFIG_BOOTDELAY=10
-CONFIG_SILENT_CONSOLE=y
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_NAND_BOOT=y
-CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_BMP=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="t1042d4rdb"
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
-CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_VIDEO=y
-CONFIG_CFB_CONSOLE_ANSI=y
diff --git a/configs/T1042D4RDB_SDCARD_defconfig b/configs/T1042D4RDB_SDCARD_defconfig
deleted file mode 100644
index a4a31bfd62..0000000000
--- a/configs/T1042D4RDB_SDCARD_defconfig
+++ /dev/null
@@ -1,83 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x30001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T1042D4RDB=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD"
-CONFIG_BOOTDELAY=10
-CONFIG_SILENT_CONSOLE=y
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_MMC_BOOT=y
-CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_BMP=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="t1042d4rdb"
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
-CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_VIDEO=y
-CONFIG_CFB_CONSOLE_ANSI=y
diff --git a/configs/T1042D4RDB_SECURE_BOOT_defconfig b/configs/T1042D4RDB_SECURE_BOOT_defconfig
deleted file mode 100644
index f460b17e4d..0000000000
--- a/configs/T1042D4RDB_SECURE_BOOT_defconfig
+++ /dev/null
@@ -1,64 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T1042D4RDB=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_SILENT_CONSOLE=y
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_BMP=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
-CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_VIDEO=y
-CONFIG_CFB_CONSOLE_ANSI=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T1042D4RDB_SPIFLASH_defconfig b/configs/T1042D4RDB_SPIFLASH_defconfig
deleted file mode 100644
index 697c08dbfa..0000000000
--- a/configs/T1042D4RDB_SPIFLASH_defconfig
+++ /dev/null
@@ -1,86 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x30001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T1042D4RDB=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH"
-CONFIG_BOOTDELAY=10
-CONFIG_SILENT_CONSOLE=y
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_SPI_BOOT=y
-CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_BMP=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="t1042d4rdb"
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_ADDR=0xFFFC9000
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
-CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_VIDEO=y
-CONFIG_CFB_CONSOLE_ANSI=y
diff --git a/configs/T1042D4RDB_defconfig b/configs/T1042D4RDB_defconfig
deleted file mode 100644
index 70ddffb3a7..0000000000
--- a/configs/T1042D4RDB_defconfig
+++ /dev/null
@@ -1,71 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T1042D4RDB=y
-CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_SILENT_CONSOLE=y
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_BMP=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="t1042d4rdb"
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_VIDEO=y
-CONFIG_CFB_CONSOLE_ANSI=y
diff --git a/configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig b/configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig
deleted file mode 100644
index 167325f83c..0000000000
--- a/configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig
+++ /dev/null
@@ -1,85 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x30001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T1042RDB_PI=y
-CONFIG_SYS_CUSTOM_LDSCRIPT=y
-CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL"
-CONFIG_BOOTDELAY=0
-CONFIG_SILENT_CONSOLE=y
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_NAND_BOOT=y
-CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_CRYPTO_SUPPORT=y
-CONFIG_SPL_HASH_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_BMP=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
-CONFIG_DM=y
-CONFIG_SPL_DM=y
-CONFIG_SYS_FSL_DDR3=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_VIDEO=y
-CONFIG_CFB_CONSOLE_ANSI=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T1042RDB_PI_NAND_defconfig b/configs/T1042RDB_PI_NAND_defconfig
deleted file mode 100644
index 90bbee2508..0000000000
--- a/configs/T1042RDB_PI_NAND_defconfig
+++ /dev/null
@@ -1,80 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x30001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x180000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T1042RDB_PI=y
-CONFIG_SYS_CUSTOM_LDSCRIPT=y
-CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL"
-CONFIG_BOOTDELAY=10
-CONFIG_SILENT_CONSOLE=y
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_NAND_BOOT=y
-CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_BMP=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_FSL_CAAM=y
-CONFIG_SYS_FSL_DDR3=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_VIDEO=y
-CONFIG_CFB_CONSOLE_ANSI=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T1042RDB_PI_SDCARD_defconfig b/configs/T1042RDB_PI_SDCARD_defconfig
deleted file mode 100644
index ae664df4dd..0000000000
--- a/configs/T1042RDB_PI_SDCARD_defconfig
+++ /dev/null
@@ -1,77 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x30001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T1042RDB_PI=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD"
-CONFIG_BOOTDELAY=10
-CONFIG_SILENT_CONSOLE=y
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_MMC_BOOT=y
-CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_BMP=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_FSL_CAAM=y
-CONFIG_SYS_FSL_DDR3=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_VIDEO=y
-CONFIG_CFB_CONSOLE_ANSI=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T1042RDB_PI_SPIFLASH_defconfig b/configs/T1042RDB_PI_SPIFLASH_defconfig
deleted file mode 100644
index ef654653e5..0000000000
--- a/configs/T1042RDB_PI_SPIFLASH_defconfig
+++ /dev/null
@@ -1,80 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x30001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T1042RDB_PI=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH"
-CONFIG_BOOTDELAY=10
-CONFIG_SILENT_CONSOLE=y
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_SPI_BOOT=y
-CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_BMP=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_ADDR=0xFFFC9000
-CONFIG_FSL_CAAM=y
-CONFIG_SYS_FSL_DDR3=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_VIDEO=y
-CONFIG_CFB_CONSOLE_ANSI=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T1042RDB_PI_defconfig b/configs/T1042RDB_PI_defconfig
deleted file mode 100644
index 07ad865b6e..0000000000
--- a/configs/T1042RDB_PI_defconfig
+++ /dev/null
@@ -1,64 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T1042RDB_PI=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_SILENT_CONSOLE=y
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_BMP=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_FSL_CAAM=y
-CONFIG_SYS_FSL_DDR3=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_VIDEO=y
-CONFIG_CFB_CONSOLE_ANSI=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T1042RDB_SECURE_BOOT_defconfig b/configs/T1042RDB_SECURE_BOOT_defconfig
deleted file mode 100644
index c5f39e82f6..0000000000
--- a/configs/T1042RDB_SECURE_BOOT_defconfig
+++ /dev/null
@@ -1,61 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T1042RDB=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_SILENT_CONSOLE=y
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
-CONFIG_DM=y
-CONFIG_SYS_FSL_DDR3=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T1042RDB_defconfig b/configs/T1042RDB_defconfig
deleted file mode 100644
index c94730d79b..0000000000
--- a/configs/T1042RDB_defconfig
+++ /dev/null
@@ -1,59 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T1042RDB=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_SILENT_CONSOLE=y
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_FSL_CAAM=y
-CONFIG_SYS_FSL_DDR3=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
deleted file mode 100644
index 4237dfcd6c..0000000000
--- a/include/configs/T104xRDB.h
+++ /dev/null
@@ -1,813 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2020 NXP
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <linux/stringify.h>
-
-/*
- * T104x RDB board configuration file
- */
-#include <asm/config_mpc85xx.h>
-
-#ifdef CONFIG_RAMBOOT_PBL
-
-#ifndef CONFIG_NXP_ESBC
-#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg
-#else
-#define CONFIG_SYS_FSL_PBL_PBI \
- $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi_sb.cfg
-#endif
-
-#define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_PAD_TO 0x40000
-#define CONFIG_SPL_MAX_SIZE 0x28000
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SPL_SKIP_RELOCATE
-#define CONFIG_SPL_COMMON_INIT_DDR
-#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
-#undef CONFIG_DM_I2C
-#endif
-#define RESET_VECTOR_OFFSET 0x27FFC
-#define BOOT_PAGE_OFFSET 0x27000
-
-#ifdef CONFIG_MTD_RAW_NAND
-#ifdef CONFIG_NXP_ESBC
-#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
-/*
- * HDR would be appended@end of image and copied to DDR along
- * with U-Boot image.
- */
-#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + \
- CONFIG_U_BOOT_HDR_SIZE)
-#else
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
-#endif
-#define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
-#define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
-#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
-#ifdef CONFIG_TARGET_T1040RDB
-#define CONFIG_SYS_FSL_PBL_RCW \
-$(SRCTREE)/board/freescale/t104xrdb/t1040_nand_rcw.cfg
-#endif
-#ifdef CONFIG_TARGET_T1042RDB_PI
-#define CONFIG_SYS_FSL_PBL_RCW \
-$(SRCTREE)/board/freescale/t104xrdb/t1042_pi_nand_rcw.cfg
-#endif
-#ifdef CONFIG_TARGET_T1042RDB
-#define CONFIG_SYS_FSL_PBL_RCW \
-$(SRCTREE)/board/freescale/t104xrdb/t1042_nand_rcw.cfg
-#endif
-#ifdef CONFIG_TARGET_T1040D4RDB
-#define CONFIG_SYS_FSL_PBL_RCW \
-$(SRCTREE)/board/freescale/t104xrdb/t1040d4_nand_rcw.cfg
-#endif
-#ifdef CONFIG_TARGET_T1042D4RDB
-#define CONFIG_SYS_FSL_PBL_RCW \
-$(SRCTREE)/board/freescale/t104xrdb/t1042d4_nand_rcw.cfg
-#endif
-#endif
-
-#ifdef CONFIG_SPIFLASH
-#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
-#define CONFIG_SPL_SPI_FLASH_MINIMAL
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_SYS_MPC85XX_NO_RESETVEC
-#endif
-#ifdef CONFIG_TARGET_T1040RDB
-#define CONFIG_SYS_FSL_PBL_RCW \
-$(SRCTREE)/board/freescale/t104xrdb/t1040_spi_rcw.cfg
-#endif
-#ifdef CONFIG_TARGET_T1042RDB_PI
-#define CONFIG_SYS_FSL_PBL_RCW \
-$(SRCTREE)/board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg
-#endif
-#ifdef CONFIG_TARGET_T1042RDB
-#define CONFIG_SYS_FSL_PBL_RCW \
-$(SRCTREE)/board/freescale/t104xrdb/t1042_spi_rcw.cfg
-#endif
-#ifdef CONFIG_TARGET_T1040D4RDB
-#define CONFIG_SYS_FSL_PBL_RCW \
-$(SRCTREE)/board/freescale/t104xrdb/t1040d4_spi_rcw.cfg
-#endif
-#ifdef CONFIG_TARGET_T1042D4RDB
-#define CONFIG_SYS_FSL_PBL_RCW \
-$(SRCTREE)/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg
-#endif
-#endif
-
-#ifdef CONFIG_SDCARD
-#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
-#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
-#define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000)
-#define CONFIG_SYS_MMC_U_BOOT_START (0x30000000)
-#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_SYS_MPC85XX_NO_RESETVEC
-#endif
-#ifdef CONFIG_TARGET_T1040RDB
-#define CONFIG_SYS_FSL_PBL_RCW \
-$(SRCTREE)/board/freescale/t104xrdb/t1040_sd_rcw.cfg
-#endif
-#ifdef CONFIG_TARGET_T1042RDB_PI
-#define CONFIG_SYS_FSL_PBL_RCW \
-$(SRCTREE)/board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg
-#endif
-#ifdef CONFIG_TARGET_T1042RDB
-#define CONFIG_SYS_FSL_PBL_RCW \
-$(SRCTREE)/board/freescale/t104xrdb/t1042_sd_rcw.cfg
-#endif
-#ifdef CONFIG_TARGET_T1040D4RDB
-#define CONFIG_SYS_FSL_PBL_RCW \
-$(SRCTREE)/board/freescale/t104xrdb/t1040d4_sd_rcw.cfg
-#endif
-#ifdef CONFIG_TARGET_T1042D4RDB
-#define CONFIG_SYS_FSL_PBL_RCW \
-$(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg
-#endif
-#endif
-
-#endif
-
-/* High Level Configuration Options */
-#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
-
-/* support deep sleep */
-#define CONFIG_DEEP_SLEEP
-
-#ifndef CONFIG_RESET_VECTOR_ADDRESS
-#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
-#endif
-
-#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
-#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
-#define CONFIG_PCIE1 /* PCIE controller 1 */
-#define CONFIG_PCIE2 /* PCIE controller 2 */
-#define CONFIG_PCIE3 /* PCIE controller 3 */
-#define CONFIG_PCIE4 /* PCIE controller 4 */
-
-#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
-
-#define CONFIG_ENV_OVERWRITE
-
-#if defined(CONFIG_SPIFLASH)
-#elif defined(CONFIG_SDCARD)
-#define CONFIG_SYS_MMC_ENV_DEV 0
-#elif defined(CONFIG_MTD_RAW_NAND)
-#ifdef CONFIG_NXP_ESBC
-#define CONFIG_RAMBOOT_NAND
-#define CONFIG_BOOTSCRIPT_COPY_RAM
-#endif
-#endif
-
-#define CONFIG_SYS_CLK_FREQ 100000000
-#define CONFIG_DDR_CLK_FREQ 66666666
-
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_SYS_CACHE_STASHING
-#define CONFIG_BACKSIDE_L2_CACHE
-#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
-#define CONFIG_BTB /* toggle branch predition */
-#define CONFIG_DDR_ECC
-#ifdef CONFIG_DDR_ECC
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
-#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
-#endif
-
-#define CONFIG_ENABLE_36BIT_PHYS
-
-#define CONFIG_ADDR_MAP
-#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
-
-/*
- * Config the L3 Cache as L3 SRAM
- */
-#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
-/*
- * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence
- * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address
- * (CONFIG_SYS_INIT_L3_VADDR) will be different.
- */
-#define CONFIG_SYS_INIT_L3_VADDR 0xFFFC0000
-#define CONFIG_SYS_L3_SIZE 256 << 10
-#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_VADDR + 32 * 1024)
-#define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
-#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
-#define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
-#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
-
-#define CONFIG_SYS_DCSRBAR 0xf0000000
-#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
-
-/*
- * DDR Setup
- */
-#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
-
-#define CONFIG_DDR_SPD
-
-#define CONFIG_SYS_SPD_BUS_NUM 0
-#define SPD_EEPROM_ADDRESS 0x51
-
-#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
-
-/*
- * IFC Definitions
- */
-#define CONFIG_SYS_FLASH_BASE 0xe8000000
-#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
-
-#define CONFIG_SYS_NOR_CSPR_EXT (0xf)
-#define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
- CSPR_PORT_SIZE_16 | \
- CSPR_MSEL_NOR | \
- CSPR_V)
-#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
-
-/*
- * TDM Definition
- */
-#define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000
-
-/* NOR Flash Timing Params */
-#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
-#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
- FTIM0_NOR_TEADC(0x5) | \
- FTIM0_NOR_TEAHC(0x5))
-#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
- FTIM1_NOR_TRAD_NOR(0x1A) |\
- FTIM1_NOR_TSEQRAD_NOR(0x13))
-#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
- FTIM2_NOR_TCH(0x4) | \
- FTIM2_NOR_TWPH(0x0E) | \
- FTIM2_NOR_TWP(0x1c))
-#define CONFIG_SYS_NOR_FTIM3 0x0
-
-#define CONFIG_SYS_FLASH_QUIET_TEST
-#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
-
-/* CPLD on IFC */
-#define CPLD_LBMAP_MASK 0x3F
-#define CPLD_BANK_SEL_MASK 0x07
-#define CPLD_BANK_OVERRIDE 0x40
-#define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */
-#define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */
-#define CPLD_LBMAP_RESET 0xFF
-#define CPLD_LBMAP_SHIFT 0x03
-
-#if defined(CONFIG_TARGET_T1042RDB_PI)
-#define CPLD_DIU_SEL_DFP 0x80
-#elif defined(CONFIG_TARGET_T1042D4RDB)
-#define CPLD_DIU_SEL_DFP 0xc0
-#endif
-
-#if defined(CONFIG_TARGET_T1040D4RDB)
-#define CPLD_INT_MASK_ALL 0xFF
-#define CPLD_INT_MASK_THERM 0x80
-#define CPLD_INT_MASK_DVI_DFP 0x40
-#define CPLD_INT_MASK_QSGMII1 0x20
-#define CPLD_INT_MASK_QSGMII2 0x10
-#define CPLD_INT_MASK_SGMI1 0x08
-#define CPLD_INT_MASK_SGMI2 0x04
-#define CPLD_INT_MASK_TDMR1 0x02
-#define CPLD_INT_MASK_TDMR2 0x01
-#endif
-
-#define CONFIG_SYS_CPLD_BASE 0xffdf0000
-#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
-#define CONFIG_SYS_CSPR2_EXT (0xf)
-#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
- | CSPR_PORT_SIZE_8 \
- | CSPR_MSEL_GPCM \
- | CSPR_V)
-#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
-#define CONFIG_SYS_CSOR2 0x0
-/* CPLD Timing parameters for IFC CS2 */
-#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
- FTIM0_GPCM_TEADC(0x0e) | \
- FTIM0_GPCM_TEAHC(0x0e))
-#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
- FTIM1_GPCM_TRAD(0x1f))
-#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
- FTIM2_GPCM_TCH(0x8) | \
- FTIM2_GPCM_TWP(0x1f))
-#define CONFIG_SYS_CS2_FTIM3 0x0
-
-/* NAND Flash on IFC */
-#define CONFIG_NAND_FSL_IFC
-#define CONFIG_SYS_NAND_BASE 0xff800000
-#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
-
-#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
-#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
- | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
- | CSPR_MSEL_NAND /* MSEL = NAND */ \
- | CSPR_V)
-#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
-
-#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
- | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
- | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
- | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
- | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
- | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \
- | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
-
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-
-/* ONFI NAND Flash mode0 Timing Params */
-#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
- FTIM0_NAND_TWP(0x18) | \
- FTIM0_NAND_TWCHT(0x07) | \
- FTIM0_NAND_TWH(0x0a))
-#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
- FTIM1_NAND_TWBE(0x39) | \
- FTIM1_NAND_TRR(0x0e) | \
- FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
- FTIM2_NAND_TREH(0x0a) | \
- FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3 0x0
-
-#define CONFIG_SYS_NAND_DDR_LAW 11
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-
-#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
-
-#if defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
-#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
-#else
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
-#endif
-
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
-#else
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-#endif
-
-#if defined(CONFIG_RAMBOOT_PBL)
-#define CONFIG_SYS_RAMBOOT
-#endif
-
-#ifdef CONFIG_SYS_FSL_ERRATUM_A008044
-#if defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_A008044_WORKAROUND
-#endif
-#endif
-
-#define CONFIG_HWCONFIG
-
-/* define to use L1 as initial stack */
-#define CONFIG_L1_INIT_RAM
-#define CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
-/* The assembler doesn't like typecast */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
- ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
- CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
-#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
-
-/* Serial Port - controlled on board with jumper J8
- * open - index 2
- * shorted - index 1
- */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
-#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
-#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
-
-#if defined(CONFIG_TARGET_T1042RDB_PI) || defined(CONFIG_TARGET_T1042D4RDB)
-/* Video */
-#define CONFIG_FSL_DIU_FB
-
-#ifdef CONFIG_FSL_DIU_FB
-#define CONFIG_FSL_DIU_CH7301
-#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_VIDEO_BMP_LOGO
-#endif
-#endif
-
-/* I2C */
-#ifndef CONFIG_DM_I2C
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */
-#define CONFIG_SYS_FSL_I2C2_SPEED 400000
-#define CONFIG_SYS_FSL_I2C3_SPEED 400000
-#define CONFIG_SYS_FSL_I2C4_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
-#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
-#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
-#else
-#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
-#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
-#endif
-
-#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
-/* I2C bus multiplexer */
-#define I2C_MUX_PCA_ADDR 0x70
-#define I2C_MUX_CH_DEFAULT 0x8
-
-#if defined(CONFIG_TARGET_T1042RDB_PI) || \
- defined(CONFIG_TARGET_T1040D4RDB) || \
- defined(CONFIG_TARGET_T1042D4RDB)
-/* LDI/DVI Encoder for display */
-#define CONFIG_SYS_I2C_LDI_ADDR 0x38
-#define CONFIG_SYS_I2C_DVI_ADDR 0x75
-#define CONFIG_SYS_I2C_DVI_BUS_NUM 0
-
-/*
- * RTC configuration
- */
-#define RTC
-#define CONFIG_RTC_DS1337 1
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-
-/*DVI encoder*/
-#define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75
-#endif
-
-/*
- * eSPI - Enhanced SPI
- */
-
-/*
- * General PCI
- * Memory space is mapped 1-1, but I/O space must start from 0.
- */
-
-#ifdef CONFIG_PCI
-/* controller 1, direct to uli, tgtid 3, Base address 20000 */
-#ifdef CONFIG_PCIE1
-#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
-#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
-#endif
-
-/* controller 2, Slot 2, tgtid 2, Base address 201000 */
-#ifdef CONFIG_PCIE2
-#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
-#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
-#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
-#endif
-
-/* controller 3, Slot 1, tgtid 1, Base address 202000 */
-#ifdef CONFIG_PCIE3
-#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
-#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
-#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
-#endif
-
-/* controller 4, Base address 203000 */
-#ifdef CONFIG_PCIE4
-#define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
-#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
-#define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
-#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
-#endif
-
-#if !defined(CONFIG_DM_PCI)
-#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
-#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
-#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#endif
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#endif /* CONFIG_PCI */
-
-/* SATA */
-#define CONFIG_FSL_SATA_V2
-#ifdef CONFIG_FSL_SATA_V2
-#define CONFIG_SYS_SATA_MAX_DEVICE 1
-#define CONFIG_SATA1
-#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
-#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
-
-#define CONFIG_LBA48
-#endif
-
-/*
-* USB
-*/
-#define CONFIG_HAS_FSL_DR_USB
-
-#ifdef CONFIG_HAS_FSL_DR_USB
-#ifdef CONFIG_USB_EHCI_HCD
-#define CONFIG_USB_EHCI_FSL
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#endif
-#endif
-
-#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
-#endif
-
-/* Qman/Bman */
-#ifndef CONFIG_NOBQFMAN
-#define CONFIG_SYS_BMAN_NUM_PORTALS 10
-#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
-#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
-#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
-#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
-#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
-#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
-#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
- CONFIG_SYS_BMAN_CENA_SIZE)
-#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
-#define CONFIG_SYS_QMAN_NUM_PORTALS 10
-#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
-#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
-#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
-#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
-#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
-#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
-#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
- CONFIG_SYS_QMAN_CENA_SIZE)
-#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
-
-#define CONFIG_SYS_DPAA_FMAN
-#define CONFIG_SYS_DPAA_PME
-
-#define CONFIG_U_QE
-
-/* Default address of microcode for the Linux Fman driver */
-#if defined(CONFIG_SPIFLASH)
-/*
- * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
- * env, so we got 0x110000.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
-#elif defined(CONFIG_SDCARD)
-/*
- * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
- * about 1MB (2048 blocks), Env is stored after the image, and the env size is
- * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
-#elif defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
-#else
-#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
-#endif
-
-#if defined(CONFIG_SPIFLASH)
-#define CONFIG_SYS_QE_FW_ADDR 0x130000
-#elif defined(CONFIG_SDCARD)
-#define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
-#elif defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_QE_FW_ADDR (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
-#else
-#define CONFIG_SYS_QE_FW_ADDR 0xEFF10000
-#endif
-
-#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
-#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
-#endif /* CONFIG_NOBQFMAN */
-
-#ifdef CONFIG_FMAN_ENET
-#if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1042RDB)
-#define CONFIG_SYS_SGMII1_PHY_ADDR 0x03
-#elif defined(CONFIG_TARGET_T1040D4RDB)
-#define CONFIG_SYS_SGMII1_PHY_ADDR 0x01
-#elif defined(CONFIG_TARGET_T1042D4RDB)
-#define CONFIG_SYS_SGMII1_PHY_ADDR 0x02
-#define CONFIG_SYS_SGMII2_PHY_ADDR 0x03
-#define CONFIG_SYS_SGMII3_PHY_ADDR 0x01
-#endif
-
-#if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB)
-#define CONFIG_SYS_RGMII1_PHY_ADDR 0x04
-#define CONFIG_SYS_RGMII2_PHY_ADDR 0x05
-#else
-#define CONFIG_SYS_RGMII1_PHY_ADDR 0x01
-#define CONFIG_SYS_RGMII2_PHY_ADDR 0x02
-#endif
-
-/* Enable VSC9953 L2 Switch driver on T1040 SoC */
-#if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB)
-#define CONFIG_VSC9953
-#ifdef CONFIG_TARGET_T1040RDB
-#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04
-#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08
-#else
-#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x08
-#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c
-#endif
-#endif
-
-#define CONFIG_ETHPRIME "FM1 at DTSEC4"
-#endif
-
-/*
- * Environment
- */
-#define CONFIG_LOADS_ECHO /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 64 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
-#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
-/*
- * Dynamic MTD Partition support with mtdparts
- */
-
-/*
- * Environment Configuration
- */
-#define CONFIG_ROOTPATH "/opt/nfsroot"
-#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
-
-/* default location for tftp and bootm */
-#define CONFIG_LOADADDR 1000000
-
-#define __USB_PHY_TYPE utmi
-#define RAMDISKFILE "t104xrdb/ramdisk.uboot"
-
-#ifdef CONFIG_TARGET_T1040RDB
-#define FDTFILE "t1040rdb/t1040rdb.dtb"
-#elif defined(CONFIG_TARGET_T1042RDB_PI)
-#define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb"
-#elif defined(CONFIG_TARGET_T1042RDB)
-#define FDTFILE "t1042rdb/t1042rdb.dtb"
-#elif defined(CONFIG_TARGET_T1040D4RDB)
-#define FDTFILE "t1042rdb/t1040d4rdb.dtb"
-#elif defined(CONFIG_TARGET_T1042D4RDB)
-#define FDTFILE "t1042rdb/t1042d4rdb.dtb"
-#endif
-
-#ifdef CONFIG_FSL_DIU_FB
-#define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi"
-#else
-#define DIU_ENVIRONMENT
-#endif
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \
- "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
- "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
- "netdev=eth0\0" \
- "video-mode=" __stringify(DIU_ENVIRONMENT) "\0" \
- "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
- "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
- "tftpflash=tftpboot $loadaddr $uboot && " \
- "protect off $ubootaddr +$filesize && " \
- "erase $ubootaddr +$filesize && " \
- "cp.b $loadaddr $ubootaddr $filesize && " \
- "protect on $ubootaddr +$filesize && " \
- "cmp.b $loadaddr $ubootaddr $filesize\0" \
- "consoledev=ttyS0\0" \
- "ramdiskaddr=2000000\0" \
- "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \
- "fdtaddr=1e00000\0" \
- "fdtfile=" __stringify(FDTFILE) "\0" \
- "bdev=sda3\0"
-
-#define CONFIG_LINUX \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "setenv ramdiskaddr 0x02000000;" \
- "setenv fdtaddr 0x00c00000;" \
- "setenv loadaddr 0x1000000;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_HDBOOT \
- "setenv bootargs root=/dev/$bdev rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND CONFIG_LINUX
-
-#include <asm/fsl_secure_boot.h>
-
-#endif /* __CONFIG_H */
--
2.25.1
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 15/24] arm: Remove configs/T1040QDS_DDR4_defconfig board
2020-05-27 16:46 [PATCH 00/24] spi: dm-conversion (part2) Jagan Teki
` (13 preceding siblings ...)
2020-05-27 16:46 ` [PATCH 14/24] arm: Remove configs/T1040D4RDB_NAND_defconfig board Jagan Teki
@ 2020-05-27 16:46 ` Jagan Teki
2020-05-28 7:01 ` Priyanka Jain
2020-05-27 16:46 ` [PATCH 16/24] arm: Remove configs/T2080QDS_NAND_defconfig board Jagan Teki
` (7 subsequent siblings)
22 siblings, 1 reply; 59+ messages in thread
From: Jagan Teki @ 2020-05-27 16:46 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_SPI by the deadline.
Remove it.
Patch-cc: Poonam Aggrwal <poonam.aggrwal@nxp.com>
Patch-cc: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
arch/powerpc/cpu/mpc85xx/Kconfig | 1 -
board/freescale/t1040qds/Kconfig | 14 -
board/freescale/t1040qds/MAINTAINERS | 12 -
board/freescale/t1040qds/Makefile | 11 -
board/freescale/t1040qds/README | 169 ------
board/freescale/t1040qds/ddr.c | 142 -----
board/freescale/t1040qds/ddr.h | 52 --
board/freescale/t1040qds/diu.c | 98 ----
board/freescale/t1040qds/eth.c | 592 -------------------
board/freescale/t1040qds/law.c | 31 -
board/freescale/t1040qds/pci.c | 23 -
board/freescale/t1040qds/t1040_pbi.cfg | 27 -
board/freescale/t1040qds/t1040_rcw.cfg | 7 -
board/freescale/t1040qds/t1040qds.c | 305 ----------
board/freescale/t1040qds/t1040qds.h | 14 -
board/freescale/t1040qds/t1040qds_qixis.h | 51 --
board/freescale/t1040qds/tlb.c | 107 ----
configs/T1040QDS_DDR4_defconfig | 67 ---
configs/T1040QDS_SECURE_BOOT_defconfig | 70 ---
configs/T1040QDS_defconfig | 68 ---
include/configs/T1040QDS.h | 667 ----------------------
21 files changed, 2528 deletions(-)
delete mode 100644 board/freescale/t1040qds/Kconfig
delete mode 100644 board/freescale/t1040qds/MAINTAINERS
delete mode 100644 board/freescale/t1040qds/Makefile
delete mode 100644 board/freescale/t1040qds/README
delete mode 100644 board/freescale/t1040qds/ddr.c
delete mode 100644 board/freescale/t1040qds/ddr.h
delete mode 100644 board/freescale/t1040qds/diu.c
delete mode 100644 board/freescale/t1040qds/eth.c
delete mode 100644 board/freescale/t1040qds/law.c
delete mode 100644 board/freescale/t1040qds/pci.c
delete mode 100644 board/freescale/t1040qds/t1040_pbi.cfg
delete mode 100644 board/freescale/t1040qds/t1040_rcw.cfg
delete mode 100644 board/freescale/t1040qds/t1040qds.c
delete mode 100644 board/freescale/t1040qds/t1040qds.h
delete mode 100644 board/freescale/t1040qds/t1040qds_qixis.h
delete mode 100644 board/freescale/t1040qds/tlb.c
delete mode 100644 configs/T1040QDS_DDR4_defconfig
delete mode 100644 configs/T1040QDS_SECURE_BOOT_defconfig
delete mode 100644 configs/T1040QDS_defconfig
delete mode 100644 include/configs/T1040QDS.h
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 657bd929b3..35a1b29ef8 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -1599,7 +1599,6 @@ source "board/freescale/mpc8572ds/Kconfig"
source "board/freescale/p1023rdb/Kconfig"
source "board/freescale/p1_twr/Kconfig"
source "board/freescale/qemu-ppce500/Kconfig"
-source "board/freescale/t1040qds/Kconfig"
source "board/freescale/t208xqds/Kconfig"
source "board/freescale/t208xrdb/Kconfig"
source "board/freescale/t4qds/Kconfig"
diff --git a/board/freescale/t1040qds/Kconfig b/board/freescale/t1040qds/Kconfig
deleted file mode 100644
index ec3ff0c1ec..0000000000
--- a/board/freescale/t1040qds/Kconfig
+++ /dev/null
@@ -1,14 +0,0 @@
-if TARGET_T1040QDS
-
-config SYS_BOARD
- default "t1040qds"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "T1040QDS"
-
-source "board/freescale/common/Kconfig"
-
-endif
diff --git a/board/freescale/t1040qds/MAINTAINERS b/board/freescale/t1040qds/MAINTAINERS
deleted file mode 100644
index 1e276e3db9..0000000000
--- a/board/freescale/t1040qds/MAINTAINERS
+++ /dev/null
@@ -1,12 +0,0 @@
-T1040QDS BOARD
-M: Poonam Aggrwal <poonam.aggrwal@nxp.com>
-S: Maintained
-F: board/freescale/t1040qds/
-F: include/configs/T1040QDS.h
-F: configs/T1040QDS_defconfig
-F: configs/T1040QDS_DDR4_defconfig
-
-T1040QDS_SECURE_BOOT BOARD
-M: Ruchika Gupta <ruchika.gupta@nxp.com>
-S: Maintained
-F: configs/T1040QDS_SECURE_BOOT_defconfig
diff --git a/board/freescale/t1040qds/Makefile b/board/freescale/t1040qds/Makefile
deleted file mode 100644
index e10a54af88..0000000000
--- a/board/freescale/t1040qds/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2013 Freescale Semiconductor, Inc.
-
-obj-y += t1040qds.o
-obj-y += ddr.o
-obj-$(CONFIG_PCI) += pci.o
-obj-y += law.o
-obj-y += tlb.o
-obj-y += eth.o
-obj-y += diu.o
diff --git a/board/freescale/t1040qds/README b/board/freescale/t1040qds/README
deleted file mode 100644
index 6c5ffc07f8..0000000000
--- a/board/freescale/t1040qds/README
+++ /dev/null
@@ -1,169 +0,0 @@
-Overview
---------
-The T1040QDS is a Freescale reference board that hosts the T1040 SoC
-(and variants).
-
-T1040 SoC Overview
-------------------
-The QorIQ T1040/T1042 processor support four integrated 64-bit e5500 PA
-processor cores with high-performance data path acceleration architecture
-and network peripheral interfaces required for networking & telecommunications.
-
-The T1040/T1042 SoC includes the following function and features:
-
- - Four e5500 cores, each with a private 256 KB L2 cache
- - 256 KB shared L3 CoreNet platform cache (CPC)
- - Interconnect CoreNet platform
- - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
- support
- - Data Path Acceleration Architecture (DPAA) incorporating acceleration
- for the following functions:
- - Packet parsing, classification, and distribution
- - Queue management for scheduling, packet sequencing, and congestion
- management
- - Cryptography Acceleration (SEC 5.0)
- - RegEx Pattern Matching Acceleration (PME 2.2)
- - IEEE Std 1588 support
- - Hardware buffer management for buffer allocation and deallocation
- - Ethernet interfaces
- - Integrated 8-port Gigabit Ethernet switch (T1040 only)
- - Four 1 Gbps Ethernet controllers
- - Two RGMII interfaces or one RGMII and one MII interfaces
- - High speed peripheral interfaces
- - Four PCI Express 2.0 controllers running at up to 5 GHz
- - Two SATA controllers supporting 1.5 and 3.0 Gb/s operation
- - Upto two QSGMII interface
- - Upto six SGMII interface supporting 1000 Mbps
- - One SGMII interface supporting upto 2500 Mbps
- - Additional peripheral interfaces
- - Two USB 2.0 controllers with integrated PHY
- - SD/eSDHC/eMMC
- - eSPI controller
- - Four I2C controllers
- - Four UARTs
- - Four GPIO controllers
- - Integrated flash controller (IFC)
- - LCD and HDMI interface (DIU) with 12 bit dual data rate
- - TDM interface
- - Multicore programmable interrupt controller (PIC)
- - Two 8-channel DMA engines
- - Single source clocking implementation
- - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
-
- T1040QDS board Overview
- -----------------------
- - SERDES Connections, 8 lanes supporting:
- ? PCI Express: supporting Gen 1 and Gen 2;
- ? SGMII
- ? QSGMII
- ? SATA 2.0
- ? Aurora debug with dedicated connectors (T1040 only)
- - DDR Controller
- - Supports rates of up to 1600 MHz data-rate
- - Supports one DDR3LP UDIMM/RDIMMs, of single-, dual- or quad-rank types.
- -IFC/Local Bus
- - NAND flash: 8-bit, async, up to 2GB.
- - NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB
- - GASIC: Simple (minimal) target within Qixis FPGA
- - PromJET rapid memory download support
- - Ethernet
- - Two on-board RGMII 10/100/1G ethernet ports.
- - PHY #0 remains powered up during deep-sleep (T1040 only)
- - QIXIS System Logic FPGA
- - Clocks
- - System and DDR clock (SYSCLK, ?DDRCLK?)
- - SERDES clocks
- - Power Supplies
- - Video
- - DIU supports video at up to 1280x1024x32bpp
- - USB
- - Supports two USB 2.0 ports with integrated PHYs
- ? Two type A ports with 5V at 1.5A per port.
- ? Second port can be converted to OTG mini-AB
- - SDHC
- - SDHC port connects directly to an adapter card slot, featuring:
- - Supporting SD slots for: SD, SDHC (1x, 4x, 8x) and/or MMC
- ? Supporting eMMC memory devices
- - SPI
- - On-board support of 3 different devices and sizes
- - Other IO
- - Two Serial ports
- - ProfiBus port
- - Four I2C ports
-
-Memory map on T1040QDS
-----------------------
-The addresses in brackets are physical addresses.
-
-Start Address End Address Description Size
-0xF_FFDF_0000 0xF_FFDF_0FFF IFC - FPGA 4KB
-0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB
-0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB
-0xF_F803_0000 0xF_F803_FFFF PCI Express 4 I/O Space 64KB
-0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB
-0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB
-0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB
-0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB
-0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB
-0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB
-0xF_E000_0000 0xF_E7FF_FFFF Promjet 128MB
-0xF_0000_0000 0xF_003F_FFFF DCSR 4MB
-0xC_3000_0000 0xC_3FFF_FFFF PCI Express 4 Mem Space 256MB
-0xC_2000_0000 0xC_2FFF_FFFF PCI Express 3 Mem Space 256MB
-0xC_1000_0000 0xC_1FFF_FFFF PCI Express 2 Mem Space 256MB
-0xC_0000_0000 0xC_0FFF_FFFF PCI Express 1 Mem Space 256MB
-0x0_0000_0000 0x0_ffff_ffff DDR 2GB
-
-
-NOR Flash memory Map on T1040QDS
---------------------------------
- Start End Definition Size
-0xEFF40000 0xEFFFFFFF U-Boot (current bank) 768KB
-0xEFF20000 0xEFF3FFFF U-Boot env (current bank) 128KB
-0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB
-0xED300000 0xEFEFFFFF rootfs (alt bank) 44MB
-0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB
-0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB
-0xEC000000 0xEC01FFFF RCW (alt bank) 128KB
-0xEBF40000 0xEBFFFFFF U-Boot (alt bank) 768KB
-0xEBF20000 0xEBF3FFFF U-Boot env (alt bank) 128KB
-0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB
-0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB
-0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 11MB + 512KB
-0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB
-0xE8000000 0xE801FFFF RCW (current bank) 128KB
-
-
-Various Software configurations/environment variables/commands
---------------------------------------------------------------
-The below commands apply to T1040QDS
-
-1. U-Boot environment variable hwconfig
- The default hwconfig is:
- hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;usb1:
- dr_mode=host,phy_type=utmi
- Note: For USB gadget set "dr_mode=peripheral"
-
-2. FMAN Ucode versions
- fsl_fman_ucode_t1040.bin
-
-3. Switching to alternate bank
- Commands for switching to alternate bank.
-
- 1. To change from vbank0 to vbank4
- => qixis_reset altbank (it will boot using vbank4)
-
- 2.To change from vbank4 to vbank0
- => qixis reset (it will boot using vbank0)
-
-T1040 Personality
---------------------
-
-T1022 Personality
---------------------
-T1022 is a reduced personality of T1040 with less core/clusters.
-
-T1042 Personality
---------------------
-T1042 is a reduced personality of T1040 without Integrated 8-port Gigabit
-Ethernet switch. Rest of the blocks are same as T1040
diff --git a/board/freescale/t1040qds/ddr.c b/board/freescale/t1040qds/ddr.c
deleted file mode 100644
index 0a817d0ee8..0000000000
--- a/board/freescale/t1040qds/ddr.c
+++ /dev/null
@@ -1,142 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013-2014 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <hwconfig.h>
-#include <init.h>
-#include <log.h>
-#include <asm/mmu.h>
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-#include <asm/fsl_law.h>
-#include <asm/mpc85xx_gpio.h>
-#include <linux/delay.h>
-#include "ddr.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
- ulong ddr_freq;
-
- if (ctrl_num > 2) {
- printf("Not supported controller number %d\n", ctrl_num);
- return;
- }
- if (!pdimm->n_ranks)
- return;
-
- pbsp = udimms[0];
-
- /* Get clk_adjust, cpo, write_data_delay,2t, according to the board ddr
- * freqency and n_banks specified in board_specific_parameters table.
- */
- ddr_freq = get_ddr_freq(0) / 1000000;
- while (pbsp->datarate_mhz_high) {
- if (pbsp->n_ranks == pdimm->n_ranks &&
- (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
- if (ddr_freq <= pbsp->datarate_mhz_high) {
- popts->clk_adjust = pbsp->clk_adjust;
- popts->wrlvl_start = pbsp->wrlvl_start;
- popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
- popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
- goto found;
- }
- pbsp_highest = pbsp;
- }
- pbsp++;
- }
-
- if (pbsp_highest) {
- printf("Error: board specific timing not found\n");
- printf("for data rate %lu MT/s\n", ddr_freq);
- printf("Trying to use the highest speed (%u) parameters\n",
- pbsp_highest->datarate_mhz_high);
- popts->clk_adjust = pbsp_highest->clk_adjust;
- popts->wrlvl_start = pbsp_highest->wrlvl_start;
- popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
- popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
- } else {
- panic("DIMM is not supported by this board");
- }
-found:
- debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
- "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
- "wrlvl_ctrl_3 0x%x\n",
- pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
- pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
- pbsp->wrlvl_ctl_3);
-
- /*
- * Factors to consider for half-strength driver enable:
- * - number of DIMMs installed
- */
- popts->half_strength_driver_enable = 1;
- /*
- * Write leveling override
- */
- popts->wrlvl_override = 1;
- popts->wrlvl_sample = 0xf;
-
- /*
- * rtt and rtt_wr override
- */
- popts->rtt_override = 0;
-
- /* Enable ZQ calibration */
- popts->zq_en = 1;
-
- /* DHC_EN =1, ODT = 75 Ohm */
-#ifdef CONFIG_SYS_FSL_DDR4
- popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
- popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
- DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */
-
- /* optimize cpo for erratum A-009942 */
- popts->cpo_sample = 0x69;
-#else
- popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
- popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
-#endif
-}
-
-#if defined(CONFIG_DEEP_SLEEP)
-void board_mem_sleep_setup(void)
-{
- void __iomem *qixis_base = (void *)QIXIS_BASE;
-
- /* does not provide HW signals for power management */
- clrbits_8(qixis_base + 0x21, 0x2);
- /* Disable MCKE isolation */
- gpio_set_value(2, 0);
- udelay(1);
-}
-#endif
-
-int dram_init(void)
-{
- phys_size_t dram_size;
-
- puts("Initializing....using SPD\n");
-
- dram_size = fsl_ddr_sdram();
-
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
-
- puts(" DDR: ");
-
-#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
- fsl_dp_resume();
-#endif
-
- gd->ram_size = dram_size;
-
- return 0;
-}
diff --git a/board/freescale/t1040qds/ddr.h b/board/freescale/t1040qds/ddr.h
deleted file mode 100644
index 0f88698ab5..0000000000
--- a/board/freescale/t1040qds/ddr.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2013-2014 Freescale Semiconductor, Inc.
- */
-
-#ifndef __DDR_H__
-#define __DDR_H__
-struct board_specific_parameters {
- u32 n_ranks;
- u32 datarate_mhz_high;
- u32 rank_gb;
- u32 clk_adjust;
- u32 wrlvl_start;
- u32 wrlvl_ctl_2;
- u32 wrlvl_ctl_3;
-};
-
-/*
- * These tables contain all valid speeds we want to override with board
- * specific parameters. datarate_mhz_high values need to be in ascending order
- * for each n_ranks group.
- */
-
-static const struct board_specific_parameters udimm0[] = {
- /*
- * memory controller 0
- * num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
- * ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
- */
-#ifdef CONFIG_SYS_FSL_DDR4
- {2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,},
- {2, 1900, 0, 8, 6, 0x08080A0C, 0x0D0E0F0A,},
- {1, 1666, 0, 8, 6, 0x0708090B, 0x0C0D0E09,},
- {1, 1900, 0, 8, 6, 0x08080A0C, 0x0D0E0F0A,},
- {1, 2200, 0, 8, 7, 0x08090A0D, 0x0F0F100C,},
-#elif defined(CONFIG_SYS_FSL_DDR3)
- {2, 833, 0, 8, 6, 0x06060607, 0x08080807,},
- {2, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09,},
- {2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,},
- {1, 833, 0, 8, 6, 0x06060607, 0x08080807,},
- {1, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09,},
- {1, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,},
-#else
-#error DDR type not defined
-#endif
- {}
-};
-
-static const struct board_specific_parameters *udimms[] = {
- udimm0,
-};
-#endif
diff --git a/board/freescale/t1040qds/diu.c b/board/freescale/t1040qds/diu.c
deleted file mode 100644
index 0b1aeed69e..0000000000
--- a/board/freescale/t1040qds/diu.c
+++ /dev/null
@@ -1,98 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2020 NXP
- * Author: Priyanka Jain <Priyanka.Jain@freescale.com>
- */
-
-#include <common.h>
-#include <clock_legacy.h>
-#include <command.h>
-#include <linux/ctype.h>
-#include <asm/io.h>
-#include <stdio_dev.h>
-#include <video_fb.h>
-#include <fsl_diu_fb.h>
-#include "../common/qixis.h"
-#include "../common/diu_ch7301.h"
-#include "t1040qds.h"
-#include "t1040qds_qixis.h"
-
-/*
- * DIU Area Descriptor
- *
- * Note that we need to byte-swap the value before it's written to the AD
- * register. So even though the registers don't look like they're in the same
- * bit positions as they are on the MPC8610, the same value is written to the
- * AD register on the MPC8610 and on the P1022.
- */
-#define AD_BYTE_F 0x10000000
-#define AD_ALPHA_C_SHIFT 25
-#define AD_BLUE_C_SHIFT 23
-#define AD_GREEN_C_SHIFT 21
-#define AD_RED_C_SHIFT 19
-#define AD_PIXEL_S_SHIFT 16
-#define AD_COMP_3_SHIFT 12
-#define AD_COMP_2_SHIFT 8
-#define AD_COMP_1_SHIFT 4
-#define AD_COMP_0_SHIFT 0
-
-void diu_set_pixel_clock(unsigned int pixclock)
-{
- unsigned long speed_ccb, temp;
- u32 pixval;
- int ret = 0;
- speed_ccb = get_bus_freq(0);
- temp = 1000000000 / pixclock;
- temp *= 1000;
- pixval = speed_ccb / temp;
-
- /* Program HDMI encoder */
- /* Switch channel to DIU */
- select_i2c_ch_pca9547(I2C_MUX_CH_DIU, 0);
-
- /* Set dispaly encoder */
- ret = diu_set_dvi_encoder(temp);
- if (ret) {
- puts("Failed to set DVI encoder\n");
- return;
- }
-
- /* Switch channel to default */
- select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
-
- /* Program pixel clock */
- out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR,
- ((pixval << PXCK_BITS_START) & PXCK_MASK));
- /* enable clock*/
- out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR, PXCKEN_MASK |
- ((pixval << PXCK_BITS_START) & PXCK_MASK));
-}
-
-int platform_diu_init(unsigned int xres, unsigned int yres, const char *port)
-{
- u32 pixel_format;
- u8 sw;
-
- /*Route I2C4 to DIU system as HSYNC/VSYNC*/
- sw = QIXIS_READ(brdcfg[5]);
- QIXIS_WRITE(brdcfg[5],
- ((sw & ~(BRDCFG5_IMX_MASK)) | (BRDCFG5_IMX_DIU)));
-
- /*Configure Display ouput port as HDMI*/
- sw = QIXIS_READ(brdcfg[15]);
- QIXIS_WRITE(brdcfg[15],
- ((sw & ~(BRDCFG15_LCDPD_MASK | BRDCFG15_DIUSEL_MASK))
- | (BRDCFG15_LCDPD_ENABLED | BRDCFG15_DIUSEL_HDMI)));
-
- pixel_format = cpu_to_le32(AD_BYTE_F | (3 << AD_ALPHA_C_SHIFT) |
- (0 << AD_BLUE_C_SHIFT) | (1 << AD_GREEN_C_SHIFT) |
- (2 << AD_RED_C_SHIFT) | (8 << AD_COMP_3_SHIFT) |
- (8 << AD_COMP_2_SHIFT) | (8 << AD_COMP_1_SHIFT) |
- (8 << AD_COMP_0_SHIFT) | (3 << AD_PIXEL_S_SHIFT));
-
- printf("DIU: Switching to monitor @ %ux%u\n", xres, yres);
-
-
- return fsl_diu_init(xres, yres, pixel_format, 0);
-}
diff --git a/board/freescale/t1040qds/eth.c b/board/freescale/t1040qds/eth.c
deleted file mode 100644
index b349b77951..0000000000
--- a/board/freescale/t1040qds/eth.c
+++ /dev/null
@@ -1,592 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-/*
- * The RGMII PHYs are provided by the two on-board PHY connected to
- * dTSEC instances 4 and 5. The SGMII PHYs are provided by one on-board
- * PHY or by the standard four-port SGMII riser card (VSC).
- */
-
-#include <common.h>
-#include <fdt_support.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/fsl_serdes.h>
-#include <asm/immap_85xx.h>
-#include <fm_eth.h>
-#include <fsl_mdio.h>
-#include <malloc.h>
-#include <fsl_dtsec.h>
-#include <vsc9953.h>
-
-#include "../common/fman.h"
-#include "../common/qixis.h"
-
-#include "t1040qds_qixis.h"
-
-#ifdef CONFIG_FMAN_ENET
- /* - In T1040 there are only 8 SERDES lanes, spread across 2 SERDES banks.
- * Bank 1 -> Lanes A, B, C, D
- * Bank 2 -> Lanes E, F, G, H
- */
-
- /* Mapping of 8 SERDES lanes to T1040 QDS board slots. A value of '0' here
- * means that the mapping must be determined dynamically, or that the lane
- * maps to something other than a board slot.
- */
-static u8 lane_to_slot[] = {
- 0, 0, 0, 0, 0, 0, 0, 0
-};
-
-/* On the Vitesse VSC8234XHG SGMII riser card there are 4 SGMII PHYs
- * housed.
- */
-static int riser_phy_addr[] = {
- CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR,
- CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR,
- CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR,
- CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR,
-};
-
-/* Slot2 does not have EMI connections */
-#define EMI_NONE 0xFFFFFFFF
-#define EMI1_RGMII0 0
-#define EMI1_RGMII1 1
-#define EMI1_SLOT1 2
-#define EMI1_SLOT3 3
-#define EMI1_SLOT4 4
-#define EMI1_SLOT5 5
-#define EMI1_SLOT6 6
-#define EMI1_SLOT7 7
-#define EMI2 8
-
-static int mdio_mux[NUM_FM_PORTS];
-
-static const char * const mdio_names[] = {
- "T1040_QDS_MDIO0",
- "T1040_QDS_MDIO1",
- "T1040_QDS_MDIO2",
- "T1040_QDS_MDIO3",
- "T1040_QDS_MDIO4",
- "T1040_QDS_MDIO5",
- "T1040_QDS_MDIO6",
- "T1040_QDS_MDIO7",
-};
-
-struct t1040_qds_mdio {
- u8 muxval;
- struct mii_dev *realbus;
-};
-
-static const char *t1040_qds_mdio_name_for_muxval(u8 muxval)
-{
- return mdio_names[muxval];
-}
-
-struct mii_dev *mii_dev_for_muxval(u8 muxval)
-{
- struct mii_dev *bus;
- const char *name = t1040_qds_mdio_name_for_muxval(muxval);
-
- if (!name) {
- printf("No bus for muxval %x\n", muxval);
- return NULL;
- }
-
- bus = miiphy_get_dev_by_name(name);
-
- if (!bus) {
- printf("No bus by name %s\n", name);
- return NULL;
- }
-
- return bus;
-}
-
-static void t1040_qds_mux_mdio(u8 muxval)
-{
- u8 brdcfg4;
- if (muxval <= 7) {
- brdcfg4 = QIXIS_READ(brdcfg[4]);
- brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
- brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
- QIXIS_WRITE(brdcfg[4], brdcfg4);
- }
-}
-
-static int t1040_qds_mdio_read(struct mii_dev *bus, int addr, int devad,
- int regnum)
-{
- struct t1040_qds_mdio *priv = bus->priv;
-
- t1040_qds_mux_mdio(priv->muxval);
-
- return priv->realbus->read(priv->realbus, addr, devad, regnum);
-}
-
-static int t1040_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
- int regnum, u16 value)
-{
- struct t1040_qds_mdio *priv = bus->priv;
-
- t1040_qds_mux_mdio(priv->muxval);
-
- return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
-}
-
-static int t1040_qds_mdio_reset(struct mii_dev *bus)
-{
- struct t1040_qds_mdio *priv = bus->priv;
-
- return priv->realbus->reset(priv->realbus);
-}
-
-static int t1040_qds_mdio_init(char *realbusname, u8 muxval)
-{
- struct t1040_qds_mdio *pmdio;
- struct mii_dev *bus = mdio_alloc();
-
- if (!bus) {
- printf("Failed to allocate t1040_qds MDIO bus\n");
- return -1;
- }
-
- pmdio = malloc(sizeof(*pmdio));
- if (!pmdio) {
- printf("Failed to allocate t1040_qds private data\n");
- free(bus);
- return -1;
- }
-
- bus->read = t1040_qds_mdio_read;
- bus->write = t1040_qds_mdio_write;
- bus->reset = t1040_qds_mdio_reset;
- strcpy(bus->name, t1040_qds_mdio_name_for_muxval(muxval));
-
- pmdio->realbus = miiphy_get_dev_by_name(realbusname);
-
- if (!pmdio->realbus) {
- printf("No bus with name %s\n", realbusname);
- free(bus);
- free(pmdio);
- return -1;
- }
-
- pmdio->muxval = muxval;
- bus->priv = pmdio;
-
- return mdio_register(bus);
-}
-
-/*
- * Initialize the lane_to_slot[] array.
- *
- * On the T1040QDS board the mapping is controlled by ?? register.
- */
-static void initialize_lane_to_slot(void)
-{
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
- int serdes1_prtcl = (in_be32(&gur->rcwsr[4]) &
- FSL_CORENET2_RCWSR4_SRDS1_PRTCL)
- >> FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
-
- QIXIS_WRITE(cms[0], 0x07);
-
- switch (serdes1_prtcl) {
- case 0x60:
- case 0x66:
- case 0x67:
- case 0x69:
- lane_to_slot[1] = 7;
- lane_to_slot[2] = 6;
- lane_to_slot[3] = 5;
- break;
- case 0x86:
- lane_to_slot[1] = 7;
- lane_to_slot[2] = 7;
- lane_to_slot[3] = 7;
- break;
- case 0x87:
- lane_to_slot[1] = 7;
- lane_to_slot[2] = 7;
- lane_to_slot[3] = 7;
- lane_to_slot[7] = 7;
- break;
- case 0x89:
- lane_to_slot[1] = 7;
- lane_to_slot[2] = 7;
- lane_to_slot[3] = 7;
- lane_to_slot[6] = 7;
- lane_to_slot[7] = 7;
- break;
- case 0x8d:
- lane_to_slot[1] = 7;
- lane_to_slot[2] = 7;
- lane_to_slot[3] = 7;
- lane_to_slot[5] = 3;
- lane_to_slot[6] = 3;
- lane_to_slot[7] = 3;
- break;
- case 0x8F:
- case 0x85:
- lane_to_slot[1] = 7;
- lane_to_slot[2] = 6;
- lane_to_slot[3] = 5;
- lane_to_slot[6] = 3;
- lane_to_slot[7] = 3;
- break;
- case 0xA5:
- lane_to_slot[1] = 7;
- lane_to_slot[6] = 3;
- lane_to_slot[7] = 3;
- break;
- case 0xA7:
- lane_to_slot[1] = 7;
- lane_to_slot[2] = 6;
- lane_to_slot[3] = 5;
- lane_to_slot[7] = 7;
- break;
- case 0xAA:
- lane_to_slot[1] = 7;
- lane_to_slot[6] = 7;
- lane_to_slot[7] = 7;
- break;
- case 0x40:
- lane_to_slot[2] = 7;
- lane_to_slot[3] = 7;
- break;
- default:
- printf("qds: Fman: Unsupported SerDes Protocol 0x%02x\n",
- serdes1_prtcl);
- break;
- }
-}
-
-/*
- * Given the following ...
- *
- * 1) A pointer to an Fman Ethernet node (as identified by the 'compat'
- * compatible string and 'addr' physical address)
- *
- * 2) An Fman port
- *
- * ... update the phy-handle property of the Ethernet node to point to the
- * right PHY. This assumes that we already know the PHY for each port.
- *
- * The offset of the Fman Ethernet node is also passed in for convenience, but
- * it is not used, and we recalculate the offset anyway.
- *
- * Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC.
- * Inside the Fman, "ports" are things that connect to MACs. We only call them
- * ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs
- * and ports are the same thing.
- *
- */
-void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
- enum fm_port port, int offset)
-{
- phy_interface_t intf = fm_info_get_enet_if(port);
- char phy[16];
-
- /* The RGMII PHY is identified by the MAC connected to it */
- if (intf == PHY_INTERFACE_MODE_RGMII) {
- sprintf(phy, "rgmii_phy%u", port == FM1_DTSEC4 ? 1 : 2);
- fdt_set_phy_handle(fdt, compat, addr, phy);
- }
-
- /* The SGMII PHY is identified by the MAC connected to it */
- if (intf == PHY_INTERFACE_MODE_SGMII) {
- int lane = serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC1
- + port);
- u8 slot;
- if (lane < 0)
- return;
- slot = lane_to_slot[lane];
- if (slot) {
- /* Slot housing a SGMII riser card */
- sprintf(phy, "phy_s%x_%02x", slot,
- (fm_info_get_phy_address(port - FM1_DTSEC1)-
- CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR + 1));
- fdt_set_phy_handle(fdt, compat, addr, phy);
- }
- }
-}
-
-void fdt_fixup_board_enet(void *fdt)
-{
- int i, lane, idx;
-
- for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
- idx = i - FM1_DTSEC1;
- switch (fm_info_get_enet_if(i)) {
- case PHY_INTERFACE_MODE_SGMII:
- lane = serdes_get_first_lane(FSL_SRDS_1,
- SGMII_FM1_DTSEC1 + idx);
- if (lane < 0)
- break;
-
- switch (mdio_mux[i]) {
- case EMI1_SLOT3:
- fdt_status_okay_by_alias(fdt, "emi1_slot3");
- break;
- case EMI1_SLOT5:
- fdt_status_okay_by_alias(fdt, "emi1_slot5");
- break;
- case EMI1_SLOT6:
- fdt_status_okay_by_alias(fdt, "emi1_slot6");
- break;
- case EMI1_SLOT7:
- fdt_status_okay_by_alias(fdt, "emi1_slot7");
- break;
- }
- break;
- case PHY_INTERFACE_MODE_RGMII:
- if (i == FM1_DTSEC4)
- fdt_status_okay_by_alias(fdt, "emi1_rgmii0");
-
- if (i == FM1_DTSEC5)
- fdt_status_okay_by_alias(fdt, "emi1_rgmii1");
- break;
- default:
- break;
- }
- }
-}
-#endif /* #ifdef CONFIG_FMAN_ENET */
-
-static void set_brdcfg9_for_gtx_clk(void)
-{
- u8 brdcfg9;
- brdcfg9 = QIXIS_READ(brdcfg[9]);
-/* Initializing EPHY2 clock to RGMII mode */
- brdcfg9 &= ~(BRDCFG9_EPHY2_MASK);
- brdcfg9 |= (BRDCFG9_EPHY2_VAL);
- QIXIS_WRITE(brdcfg[9], brdcfg9);
-}
-
-void t1040_handle_phy_interface_sgmii(int i)
-{
- int lane, idx, slot;
- idx = i - FM1_DTSEC1;
- lane = serdes_get_first_lane(FSL_SRDS_1,
- SGMII_FM1_DTSEC1 + idx);
-
- if (lane < 0)
- return;
- slot = lane_to_slot[lane];
-
- switch (slot) {
- case 1:
- mdio_mux[i] = EMI1_SLOT1;
- fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
- break;
- case 3:
- if (FM1_DTSEC4 == i)
- fm_info_set_phy_address(i, riser_phy_addr[0]);
- if (FM1_DTSEC5 == i)
- fm_info_set_phy_address(i, riser_phy_addr[1]);
-
- mdio_mux[i] = EMI1_SLOT3;
-
- fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
- break;
- case 4:
- mdio_mux[i] = EMI1_SLOT4;
- fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
- break;
- case 5:
- /* Slot housing a SGMII riser card? */
- fm_info_set_phy_address(i, riser_phy_addr[0]);
- mdio_mux[i] = EMI1_SLOT5;
- fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
- break;
- case 6:
- /* Slot housing a SGMII riser card? */
- fm_info_set_phy_address(i, riser_phy_addr[0]);
- mdio_mux[i] = EMI1_SLOT6;
- fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
- break;
- case 7:
- if (FM1_DTSEC1 == i)
- fm_info_set_phy_address(i, riser_phy_addr[0]);
- if (FM1_DTSEC2 == i)
- fm_info_set_phy_address(i, riser_phy_addr[1]);
- if (FM1_DTSEC3 == i)
- fm_info_set_phy_address(i, riser_phy_addr[2]);
- if (FM1_DTSEC5 == i)
- fm_info_set_phy_address(i, riser_phy_addr[3]);
-
- mdio_mux[i] = EMI1_SLOT7;
- fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
- break;
- default:
- break;
- }
- fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
-}
-void t1040_handle_phy_interface_rgmii(int i)
-{
- fm_info_set_phy_address(i, i == FM1_DTSEC5 ?
- CONFIG_SYS_FM1_DTSEC5_PHY_ADDR :
- CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
- mdio_mux[i] = (i == FM1_DTSEC5) ? EMI1_RGMII1 :
- EMI1_RGMII0;
- fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
-}
-
-int board_eth_init(bd_t *bis)
-{
-#ifdef CONFIG_FMAN_ENET
- struct memac_mdio_info memac_mdio_info;
- unsigned int i;
-#ifdef CONFIG_VSC9953
- int lane;
- int phy_addr;
- phy_interface_t phy_int;
- struct mii_dev *bus;
-#endif
-
- printf("Initializing Fman\n");
- set_brdcfg9_for_gtx_clk();
-
- initialize_lane_to_slot();
-
- /* Initialize the mdio_mux array so we can recognize empty elements */
- for (i = 0; i < NUM_FM_PORTS; i++)
- mdio_mux[i] = EMI_NONE;
-
- memac_mdio_info.regs =
- (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
- memac_mdio_info.name = DEFAULT_FM_MDIO_NAME;
-
- /* Register the real 1G MDIO bus */
- fm_memac_mdio_init(bis, &memac_mdio_info);
-
- /* Register the muxing front-ends to the MDIO buses */
- t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII0);
- t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
- t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
- t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
- t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
- t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
- t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT6);
- t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7);
-
- /*
- * Program on board RGMII PHY addresses. If the SGMII Riser
- * card used, we'll override the PHY address later. For any DTSEC that
- * is RGMII, we'll also override its PHY address later. We assume that
- * DTSEC4 and DTSEC5 are used for RGMII.
- */
- fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_DTSEC5_PHY_ADDR);
-
- for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
- switch (fm_info_get_enet_if(i)) {
- case PHY_INTERFACE_MODE_QSGMII:
- fm_info_set_mdio(i, NULL);
- break;
- case PHY_INTERFACE_MODE_SGMII:
- t1040_handle_phy_interface_sgmii(i);
- break;
-
- case PHY_INTERFACE_MODE_RGMII:
- /* Only DTSEC4 and DTSEC5 can be routed to RGMII */
- t1040_handle_phy_interface_rgmii(i);
- break;
- default:
- break;
- }
- }
-
-#ifdef CONFIG_VSC9953
- for (i = 0; i < VSC9953_MAX_PORTS; i++) {
- lane = -1;
- phy_addr = 0;
- phy_int = PHY_INTERFACE_MODE_NONE;
- switch (i) {
- case 0:
- case 1:
- case 2:
- case 3:
- lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_A);
- /* PHYs connected over QSGMII */
- if (lane >= 0) {
- phy_addr = CONFIG_SYS_FM1_QSGMII21_PHY_ADDR +
- i;
- phy_int = PHY_INTERFACE_MODE_QSGMII;
- break;
- }
- lane = serdes_get_first_lane(FSL_SRDS_1,
- SGMII_SW1_MAC1 + i);
-
- if (lane < 0)
- break;
-
- /* PHYs connected over QSGMII */
- if (i != 3 || lane_to_slot[lane] == 7)
- phy_addr = CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR
- + i;
- else
- phy_addr = CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR;
- phy_int = PHY_INTERFACE_MODE_SGMII;
- break;
- case 4:
- case 5:
- case 6:
- case 7:
- lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_B);
- /* PHYs connected over QSGMII */
- if (lane >= 0) {
- phy_addr = CONFIG_SYS_FM1_QSGMII11_PHY_ADDR +
- i - 4;
- phy_int = PHY_INTERFACE_MODE_QSGMII;
- break;
- }
- lane = serdes_get_first_lane(FSL_SRDS_1,
- SGMII_SW1_MAC1 + i);
- /* PHYs connected over SGMII */
- if (lane >= 0) {
- phy_addr = CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR
- + i - 3;
- phy_int = PHY_INTERFACE_MODE_SGMII;
- }
- break;
- case 8:
- if (serdes_get_first_lane(FSL_SRDS_1,
- SGMII_FM1_DTSEC1) < 0)
- /* FM1 at DTSEC1 is connected to SW1@PORT8 */
- vsc9953_port_enable(i);
- break;
- case 9:
- if (serdes_get_first_lane(FSL_SRDS_1,
- SGMII_FM1_DTSEC2) < 0) {
- /* Enable L2 On MAC2 using SCFG */
- struct ccsr_scfg *scfg = (struct ccsr_scfg *)
- CONFIG_SYS_MPC85xx_SCFG;
-
- out_be32(&scfg->esgmiiselcr,
- in_be32(&scfg->esgmiiselcr) |
- (0x80000000));
- vsc9953_port_enable(i);
- }
- break;
- }
-
- if (lane >= 0) {
- bus = mii_dev_for_muxval(lane_to_slot[lane]);
- vsc9953_port_info_set_mdio(i, bus);
- vsc9953_port_enable(i);
- }
- vsc9953_port_info_set_phy_address(i, phy_addr);
- vsc9953_port_info_set_phy_int(i, phy_int);
- }
-
-#endif
- cpu_eth_init(bis);
-#endif
-
- return pci_eth_init(bis);
-}
diff --git a/board/freescale/t1040qds/law.c b/board/freescale/t1040qds/law.c
deleted file mode 100644
index cf27655c14..0000000000
--- a/board/freescale/t1040qds/law.c
+++ /dev/null
@@ -1,31 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-struct law_entry law_table[] = {
-#ifdef CONFIG_MTD_NOR_FLASH
- SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
-#endif
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
- SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
-#endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
- SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
-#endif
-#ifdef QIXIS_BASE_PHYS
- SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
-#endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
- SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
-#endif
-#ifdef CONFIG_SYS_NAND_BASE_PHYS
- SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
-#endif
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/t1040qds/pci.c b/board/freescale/t1040qds/pci.c
deleted file mode 100644
index 5152cdf18a..0000000000
--- a/board/freescale/t1040qds/pci.c
+++ /dev/null
@@ -1,23 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <init.h>
-#include <pci.h>
-#include <asm/fsl_pci.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <asm/fsl_serdes.h>
-
-void pci_init_board(void)
-{
- fsl_pcie_init_board(0);
-}
-
-void pci_of_setup(void *blob, bd_t *bd)
-{
- FT_FSL_PCI_SETUP;
-}
diff --git a/board/freescale/t1040qds/t1040_pbi.cfg b/board/freescale/t1040qds/t1040_pbi.cfg
deleted file mode 100644
index 121b005baf..0000000000
--- a/board/freescale/t1040qds/t1040_pbi.cfg
+++ /dev/null
@@ -1,27 +0,0 @@
-#PBI commands
-#Initialize CPC1
-09010000 00200400
-09138000 00000000
-091380c0 00000100
-#Configure CPC1 as 256KB SRAM
-09010100 00000000
-09010104 fffc0007
-09010f00 081e000d
-09010000 80000000
-#Configure LAW for CPC1
-09000cf0 00000000
-09000cf4 fffc0000
-09000cf8 81000011
-#Configure alternate space
-09000010 00000000
-09000014 ff000000
-09000018 81000000
-#Configure SPI controller
-09110000 80000403
-09110020 2d170008
-09110024 00100008
-09110028 00100008
-0911002c 00100008
-#Flush PBL data
-09138000 00000000
-091380c0 00000000
diff --git a/board/freescale/t1040qds/t1040_rcw.cfg b/board/freescale/t1040qds/t1040_rcw.cfg
deleted file mode 100644
index 0d0dfa5a46..0000000000
--- a/board/freescale/t1040qds/t1040_rcw.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-#PBL preamble and RCW header
-aa55aa55 010e0100
-# serdes protocol 0x66
-0a10000c 0c000000 00000000 00000000
-66000002 00000000 fc027000 01000000
-00000000 00000000 00000000 00030810
-00000000 03fc500f 00000000 00000000
diff --git a/board/freescale/t1040qds/t1040qds.c b/board/freescale/t1040qds/t1040qds.c
deleted file mode 100644
index c166403ba4..0000000000
--- a/board/freescale/t1040qds/t1040qds.c
+++ /dev/null
@@ -1,305 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- * Copyright 2020 NXP
- */
-
-#include <common.h>
-#include <command.h>
-#include <env.h>
-#include <fdt_support.h>
-#include <i2c.h>
-#include <image.h>
-#include <init.h>
-#include <netdev.h>
-#include <linux/compiler.h>
-#include <asm/mmu.h>
-#include <asm/processor.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_law.h>
-#include <asm/fsl_serdes.h>
-#include <asm/fsl_liodn.h>
-#include <fm_eth.h>
-#include <hwconfig.h>
-
-#include "../common/sleep.h"
-#include "../common/qixis.h"
-#include "t1040qds.h"
-#include "t1040qds_qixis.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
- char buf[64];
- u8 sw;
- struct cpu_type *cpu = gd->arch.cpu;
- static const char *const freq[] = {"100", "125", "156.25", "161.13",
- "122.88", "122.88", "122.88"};
- int clock;
-
- printf("Board: %sQDS, ", cpu->name);
- printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ",
- QIXIS_READ(id), QIXIS_READ(arch));
-
- sw = QIXIS_READ(brdcfg[0]);
- sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
-
- if (sw < 0x8)
- printf("vBank: %d\n", sw);
- else if (sw == 0x8)
- puts("PromJet\n");
- else if (sw == 0x9)
- puts("NAND\n");
- else if (sw == 0x15)
- printf("IFCCard\n");
- else
- printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
-
- printf("FPGA: v%d (%s), build %d",
- (int)QIXIS_READ(scver), qixis_read_tag(buf),
- (int)qixis_read_minor());
- /* the timestamp string contains "\n"@the end */
- printf(" on %s", qixis_read_time(buf));
-
- /*
- * Display the actual SERDES reference clocks as configured by the
- * dip switches on the board. Note that the SWx registers could
- * technically be set to force the reference clocks to match the
- * values that the SERDES expects (or vice versa). For now, however,
- * we just display both values and hope the user notices when they
- * don't match.
- */
- puts("SERDES Reference: ");
- sw = QIXIS_READ(brdcfg[2]);
- clock = (sw >> 6) & 3;
- printf("Clock1=%sMHz ", freq[clock]);
- clock = (sw >> 4) & 3;
- printf("Clock2=%sMHz\n", freq[clock]);
-
- return 0;
-}
-
-int select_i2c_ch_pca9547(u8 ch, int bus_num)
-{
- int ret;
-
-#ifdef CONFIG_DM_I2C
- struct udevice *dev;
-
- ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
- if (ret) {
- printf("%s: Cannot find udev for a bus %d\n", __func__,
- bus_num);
- return ret;
- }
-
- ret = dm_i2c_write(dev, 0, &ch, 1);
-#else
- ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
-#endif
- if (ret) {
- puts("PCA: failed to select proper channel\n");
- return ret;
- }
-
- return 0;
-}
-
-static void qe_board_setup(void)
-{
- u8 brdcfg15, brdcfg9;
-
- if (hwconfig("qe") && hwconfig("tdm")) {
- brdcfg15 = QIXIS_READ(brdcfg[15]);
- /*
- * TDMRiser uses QE-TDM
- * Route QE_TDM signals to TDM Riser slot
- */
- QIXIS_WRITE(brdcfg[15], brdcfg15 | 7);
- } else if (hwconfig("qe") && hwconfig("uart")) {
- brdcfg15 = QIXIS_READ(brdcfg[15]);
- brdcfg9 = QIXIS_READ(brdcfg[9]);
- /*
- * Route QE_TDM signals to UCC
- * ProfiBus controlled by UCC3
- */
- brdcfg15 &= 0xfc;
- QIXIS_WRITE(brdcfg[15], brdcfg15 | 2);
- QIXIS_WRITE(brdcfg[9], brdcfg9 | 4);
- }
-}
-
-int board_early_init_f(void)
-{
-#if defined(CONFIG_DEEP_SLEEP)
- if (is_warm_boot())
- fsl_dp_disable_console();
-#endif
-
- return 0;
-}
-
-int board_early_init_r(void)
-{
-#ifdef CONFIG_SYS_FLASH_BASE
- const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
- int flash_esel = find_tlb_idx((void *)flashbase, 1);
-
- /*
- * Remap Boot flash + PROMJET region to caching-inhibited
- * so that flash can be erased properly.
- */
-
- /* Flush d-cache and invalidate i-cache of any FLASH data */
- flush_dcache();
- invalidate_icache();
-
- if (flash_esel == -1) {
- /* very unlikely unless something is messed up */
- puts("Error: Could not find TLB for FLASH BASE\n");
- flash_esel = 2; /* give our best effort to continue */
- } else {
- /* invalidate existing TLB entry for flash + promjet */
- disable_tlb(flash_esel);
- }
-
- set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, flash_esel, BOOKE_PAGESZ_256M, 1);
-#endif
- select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
-
- return 0;
-}
-
-unsigned long get_board_sys_clk(void)
-{
- u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
-
- switch (sysclk_conf & 0x0F) {
- case QIXIS_SYSCLK_64:
- return 64000000;
- case QIXIS_SYSCLK_83:
- return 83333333;
- case QIXIS_SYSCLK_100:
- return 100000000;
- case QIXIS_SYSCLK_125:
- return 125000000;
- case QIXIS_SYSCLK_133:
- return 133333333;
- case QIXIS_SYSCLK_150:
- return 150000000;
- case QIXIS_SYSCLK_160:
- return 160000000;
- case QIXIS_SYSCLK_166:
- return 166666666;
- }
- return 66666666;
-}
-
-unsigned long get_board_ddr_clk(void)
-{
- u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
-
- switch ((ddrclk_conf & 0x30) >> 4) {
- case QIXIS_DDRCLK_100:
- return 100000000;
- case QIXIS_DDRCLK_125:
- return 125000000;
- case QIXIS_DDRCLK_133:
- return 133333333;
- }
- return 66666666;
-}
-
-#define NUM_SRDS_BANKS 2
-int misc_init_r(void)
-{
- u8 sw;
- serdes_corenet_t *srds_regs =
- (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
- u32 actual[NUM_SRDS_BANKS] = { 0 };
- int i;
-
- sw = QIXIS_READ(brdcfg[2]);
- for (i = 0; i < NUM_SRDS_BANKS; i++) {
- unsigned int clock = (sw >> (6 - 2 * i)) & 3;
- switch (clock) {
- case 0:
- actual[i] = SRDS_PLLCR0_RFCK_SEL_100;
- break;
- case 1:
- actual[i] = SRDS_PLLCR0_RFCK_SEL_125;
- break;
- case 2:
- actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25;
- break;
- }
- }
-
- puts("SerDes1");
- for (i = 0; i < NUM_SRDS_BANKS; i++) {
- u32 pllcr0 = srds_regs->bank[i].pllcr0;
- u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
- if (expected != actual[i]) {
- printf("expects ref clk%d %sMHz, but actual is %sMHz\n",
- i + 1, serdes_clock_to_string(expected),
- serdes_clock_to_string(actual[i]));
- }
- }
-
- qe_board_setup();
-
- return 0;
-}
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
- phys_addr_t base;
- phys_size_t size;
-
- ft_cpu_setup(blob, bd);
-
- base = env_get_bootm_low();
- size = env_get_bootm_size();
-
- fdt_fixup_memory(blob, (u64)base, (u64)size);
-
-#ifdef CONFIG_PCI
- pci_of_setup(blob, bd);
-#endif
-
- fdt_fixup_liodn(blob);
-
-#ifdef CONFIG_HAS_FSL_DR_USB
- fsl_fdt_fixup_dr_usb(blob, bd);
-#endif
-
-#ifdef CONFIG_SYS_DPAA_FMAN
- fdt_fixup_fman_ethernet(blob);
- fdt_fixup_board_enet(blob);
-#endif
-
- return 0;
-}
-
-void qixis_dump_switch(void)
-{
- int i, nr_of_cfgsw;
-
- QIXIS_WRITE(cms[0], 0x00);
- nr_of_cfgsw = QIXIS_READ(cms[1]);
-
- puts("DIP switch settings dump:\n");
- for (i = 1; i <= nr_of_cfgsw; i++) {
- QIXIS_WRITE(cms[0], i);
- printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
- }
-}
-
-int board_need_mem_reset(void)
-{
- return 1;
-}
diff --git a/board/freescale/t1040qds/t1040qds.h b/board/freescale/t1040qds/t1040qds.h
deleted file mode 100644
index 781bcdefc9..0000000000
--- a/board/freescale/t1040qds/t1040qds.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- * Copyright 2020 NXP
- */
-
-#ifndef __T1040_QDS_H__
-#define __T1040_QDS_H__
-
-void fdt_fixup_board_enet(void *blob);
-void pci_of_setup(void *blob, bd_t *bd);
-int select_i2c_ch_pca9547(u8 ch, int bus_bum);
-
-#endif
diff --git a/board/freescale/t1040qds/t1040qds_qixis.h b/board/freescale/t1040qds/t1040qds_qixis.h
deleted file mode 100644
index 213d7011db..0000000000
--- a/board/freescale/t1040qds/t1040qds_qixis.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#ifndef __T1040QDS_QIXIS_H__
-#define __T1040QDS_QIXIS_H__
-
-/* Definitions of QIXIS Registers for T1040QDS */
-
-/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */
-#define BRDCFG4_EMISEL_MASK 0xE0
-#define BRDCFG4_EMISEL_SHIFT 5
-
-/* BRDCFG5[0:1] controls routing and use of I2C3 & I2C4 ports*/
-#define BRDCFG5_IMX_MASK 0xC0
-#define BRDCFG5_IMX_DIU 0x80
-
-/* BRDCFG9[2] controls EPHY2 Clock */
-#define BRDCFG9_EPHY2_MASK 0x20
-#define BRDCFG9_EPHY2_VAL 0x00
-
-/* BRDCFG15[3] controls LCD Panel Powerdown*/
-#define BRDCFG15_LCDPD_MASK 0x10
-#define BRDCFG15_LCDPD_ENABLED 0x00
-
-/* BRDCFG15[6:7] controls DIU MUX selction*/
-#define BRDCFG15_DIUSEL_MASK 0x03
-#define BRDCFG15_DIUSEL_HDMI 0x00
-
-/* SYSCLK */
-#define QIXIS_SYSCLK_66 0x0
-#define QIXIS_SYSCLK_83 0x1
-#define QIXIS_SYSCLK_100 0x2
-#define QIXIS_SYSCLK_125 0x3
-#define QIXIS_SYSCLK_133 0x4
-#define QIXIS_SYSCLK_150 0x5
-#define QIXIS_SYSCLK_160 0x6
-#define QIXIS_SYSCLK_166 0x7
-#define QIXIS_SYSCLK_64 0x8
-
-/* DDRCLK */
-#define QIXIS_DDRCLK_66 0x0
-#define QIXIS_DDRCLK_100 0x1
-#define QIXIS_DDRCLK_125 0x2
-#define QIXIS_DDRCLK_133 0x3
-
-
-#define QIXIS_SRDS1CLK_122 0x5a
-#define QIXIS_SRDS1CLK_125 0x5e
-#endif
diff --git a/board/freescale/t1040qds/tlb.c b/board/freescale/t1040qds/tlb.c
deleted file mode 100644
index 216b119135..0000000000
--- a/board/freescale/t1040qds/tlb.c
+++ /dev/null
@@ -1,107 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
- /* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
-
- /* TLB 1 */
- /* *I*** - Covers boot page */
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
- /*
- * *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the
- * SRAM is at 0xfffc0000, it covered the 0xfffff000.
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_256K, 1),
-#else
- SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_4K, 1),
-#endif
-
- /* *I*G* - CCSRBAR */
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 1, BOOKE_PAGESZ_16M, 1),
-
- /* *I*G* - Flash, localbus */
- /* This will be changed to *I*G* after relocation to RAM. */
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
- MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
- 0, 2, BOOKE_PAGESZ_256M, 1),
-
- /* *I*G* - PCI */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 3, BOOKE_PAGESZ_1G, 1),
-
- /* *I*G* - PCI I/O */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 4, BOOKE_PAGESZ_256K, 1),
-
- /* Bman/Qman */
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
- SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 5, BOOKE_PAGESZ_16M, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
- CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 6, BOOKE_PAGESZ_16M, 1),
-#endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
- SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 7, BOOKE_PAGESZ_16M, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
- CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 8, BOOKE_PAGESZ_16M, 1),
-#endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
- SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 9, BOOKE_PAGESZ_4M, 1),
-#endif
-#ifdef CONFIG_SYS_NAND_BASE
- /*
- * *I*G - NAND
- * entry 14 and 15 has been used hard coded, they will be disabled
- * in cpu_init_f, so we use entry 16 for nand.
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 10, BOOKE_PAGESZ_64K, 1),
-#endif
-#ifdef QIXIS_BASE
- SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 11, BOOKE_PAGESZ_4K, 1),
-#endif
-
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/configs/T1040QDS_DDR4_defconfig b/configs/T1040QDS_DDR4_defconfig
deleted file mode 100644
index a575b6fbc6..0000000000
--- a/configs/T1040QDS_DDR4_defconfig
+++ /dev/null
@@ -1,67 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T1040QDS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_SILENT_CONSOLE=y
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_ETHSW=y
-CONFIG_CMD_BMP=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_VIDEO=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T1040QDS_SECURE_BOOT_defconfig b/configs/T1040QDS_SECURE_BOOT_defconfig
deleted file mode 100644
index e616f0d232..0000000000
--- a/configs/T1040QDS_SECURE_BOOT_defconfig
+++ /dev/null
@@ -1,70 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T1040QDS=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_SILENT_CONSOLE=y
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_ETHSW=y
-CONFIG_CMD_BMP=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
-CONFIG_DM=y
-CONFIG_SYS_FSL_DDR3=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_VIDEO=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T1040QDS_defconfig b/configs/T1040QDS_defconfig
deleted file mode 100644
index 0b1c7cd12d..0000000000
--- a/configs/T1040QDS_defconfig
+++ /dev/null
@@ -1,68 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T1040QDS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_SILENT_CONSOLE=y
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_ETHSW=y
-CONFIG_CMD_BMP=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_FSL_CAAM=y
-CONFIG_SYS_FSL_DDR3=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_VIDEO=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h
deleted file mode 100644
index 7ad018b6d7..0000000000
--- a/include/configs/T1040QDS.h
+++ /dev/null
@@ -1,667 +0,0 @@
-/*
- * Copyright 2013-2014 Freescale Semiconductor, Inc.
- * Copyright 2020 NXP
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <linux/stringify.h>
-
-/*
- * T1040 QDS board configuration file
- */
-
-#ifdef CONFIG_RAMBOOT_PBL
-#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
-#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t1040qds/t1040_pbi.cfg
-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t1040qds/t1040_rcw.cfg
-#endif
-
-/* High Level Configuration Options */
-#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
-
-/* support deep sleep */
-#define CONFIG_DEEP_SLEEP
-
-#ifndef CONFIG_RESET_VECTOR_ADDRESS
-#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
-#endif
-
-#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
-#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_PCIE1 /* PCIE controller 1 */
-#define CONFIG_PCIE2 /* PCIE controller 2 */
-#define CONFIG_PCIE3 /* PCIE controller 3 */
-#define CONFIG_PCIE4 /* PCIE controller 4 */
-
-#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
-#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
-
-#define CONFIG_ENV_OVERWRITE
-
-#ifdef CONFIG_MTD_NOR_FLASH
-#if defined(CONFIG_SPIFLASH)
-#elif defined(CONFIG_SDCARD)
-#define CONFIG_SYS_MMC_ENV_DEV 0
-#endif
-#endif
-
-#ifndef __ASSEMBLY__
-unsigned long get_board_sys_clk(void);
-unsigned long get_board_ddr_clk(void);
-#endif
-
-#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
-#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
-
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_SYS_CACHE_STASHING
-#define CONFIG_BACKSIDE_L2_CACHE
-#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
-#define CONFIG_BTB /* toggle branch predition */
-#define CONFIG_DDR_ECC
-#ifdef CONFIG_DDR_ECC
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
-#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
-#endif
-
-#define CONFIG_ENABLE_36BIT_PHYS
-
-#define CONFIG_ADDR_MAP
-#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
-
-/*
- * Config the L3 Cache as L3 SRAM
- */
-#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
-
-#define CONFIG_SYS_DCSRBAR 0xf0000000
-#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
-
-/* EEPROM */
-#define CONFIG_ID_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#define CONFIG_SYS_EEPROM_BUS_NUM 0
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
-
-/*
- * DDR Setup
- */
-#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
-
-#define CONFIG_DDR_SPD
-
-#define CONFIG_SYS_SPD_BUS_NUM 0
-#define SPD_EEPROM_ADDRESS 0x51
-
-#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
-
-/*
- * IFC Definitions
- */
-#define CONFIG_SYS_FLASH_BASE 0xe0000000
-#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
-
-#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
-#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
- + 0x8000000) | \
- CSPR_PORT_SIZE_16 | \
- CSPR_MSEL_NOR | \
- CSPR_V)
-#define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
-#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
- CSPR_PORT_SIZE_16 | \
- CSPR_MSEL_NOR | \
- CSPR_V)
-#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
-
-/*
- * TDM Definition
- */
-#define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000
-
-/* NOR Flash Timing Params */
-#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
-#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
- FTIM0_NOR_TEADC(0x5) | \
- FTIM0_NOR_TEAHC(0x5))
-#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
- FTIM1_NOR_TRAD_NOR(0x1A) |\
- FTIM1_NOR_TSEQRAD_NOR(0x13))
-#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
- FTIM2_NOR_TCH(0x4) | \
- FTIM2_NOR_TWPH(0x0E) | \
- FTIM2_NOR_TWP(0x1c))
-#define CONFIG_SYS_NOR_FTIM3 0x0
-
-#define CONFIG_SYS_FLASH_QUIET_TEST
-#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
- + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
-#define CONFIG_FSL_QIXIS /* use common QIXIS code */
-#define QIXIS_BASE 0xffdf0000
-#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
-#define QIXIS_LBMAP_SWITCH 0x06
-#define QIXIS_LBMAP_MASK 0x0f
-#define QIXIS_LBMAP_SHIFT 0
-#define QIXIS_LBMAP_DFLTBANK 0x00
-#define QIXIS_LBMAP_ALTBANK 0x04
-#define QIXIS_RST_CTL_RESET 0x31
-#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
-#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
-#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
-#define QIXIS_RST_FORCE_MEM 0x01
-
-#define CONFIG_SYS_CSPR3_EXT (0xf)
-#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
- | CSPR_PORT_SIZE_8 \
- | CSPR_MSEL_GPCM \
- | CSPR_V)
-#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_CSOR3 0x0
-/* QIXIS Timing parameters for IFC CS3 */
-#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
- FTIM0_GPCM_TEADC(0x0e) | \
- FTIM0_GPCM_TEAHC(0x0e))
-#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
- FTIM1_GPCM_TRAD(0x3f))
-#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
- FTIM2_GPCM_TCH(0x8) | \
- FTIM2_GPCM_TWP(0x1f))
-#define CONFIG_SYS_CS3_FTIM3 0x0
-
-#define CONFIG_NAND_FSL_IFC
-#define CONFIG_SYS_NAND_BASE 0xff800000
-#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
-
-#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
-#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
- | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
- | CSPR_MSEL_NAND /* MSEL = NAND */ \
- | CSPR_V)
-#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
-
-#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
- | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
- | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
- | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
- | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
- | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
- | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
-
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-
-/* ONFI NAND Flash mode0 Timing Params */
-#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
- FTIM0_NAND_TWP(0x18) | \
- FTIM0_NAND_TWCHT(0x07) | \
- FTIM0_NAND_TWH(0x0a))
-#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
- FTIM1_NAND_TWBE(0x39) | \
- FTIM1_NAND_TRR(0x0e) | \
- FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
- FTIM2_NAND_TREH(0x0a) | \
- FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3 0x0
-
-#define CONFIG_SYS_NAND_DDR_LAW 11
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
-
-#if defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
-#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
-#else
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
-#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
-#endif
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-
-#if defined(CONFIG_RAMBOOT_PBL)
-#define CONFIG_SYS_RAMBOOT
-#endif
-
-#define CONFIG_HWCONFIG
-
-/* define to use L1 as initial stack */
-#define CONFIG_L1_INIT_RAM
-#define CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
-/* The assembler doesn't like typecast */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
- ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
- CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
-#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
-
-/* Serial Port - controlled on board with jumper J8
- * open - index 2
- * shorted - index 1
- */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
-#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
-#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
-
-/* Video */
-#define CONFIG_FSL_DIU_FB
-#ifdef CONFIG_FSL_DIU_FB
-#define CONFIG_FSL_DIU_CH7301
-#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_VIDEO_BMP_LOGO
-#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
-/*
- * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
- * disable empty flash sector detection, which is I/O-intensive.
- */
-#undef CONFIG_SYS_FLASH_EMPTY_INFO
-#endif
-
-/* I2C */
-
-#ifndef CONFIG_DM_I2C
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
-#define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */
-#define CONFIG_SYS_FSL_I2C2_SPEED 50000
-#define CONFIG_SYS_FSL_I2C3_SPEED 50000
-#define CONFIG_SYS_FSL_I2C4_SPEED 50000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
-#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
-#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
-#endif
-
-#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
-
-#define I2C_MUX_PCA_ADDR 0x77
-#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
-
-/* I2C bus multiplexer */
-#define I2C_MUX_CH_DEFAULT 0x8
-#define I2C_MUX_CH_DIU 0xC
-
-/* LDI/DVI Encoder for display */
-#define CONFIG_SYS_I2C_LDI_ADDR 0x38
-#define CONFIG_SYS_I2C_DVI_ADDR 0x75
-#define CONFIG_SYS_I2C_DVI_BUS_NUM 0
-
-/*
- * RTC configuration
- */
-#define RTC
-#define CONFIG_RTC_DS3231 1
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-
-/*
- * eSPI - Enhanced SPI
- */
-
-/*
- * General PCI
- * Memory space is mapped 1-1, but I/O space must start from 0.
- */
-
-#ifdef CONFIG_PCI
-/* controller 1, direct to uli, tgtid 3, Base address 20000 */
-#ifdef CONFIG_PCIE1
-#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
-#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
-#endif
-
-/* controller 2, Slot 2, tgtid 2, Base address 201000 */
-#ifdef CONFIG_PCIE2
-#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
-#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
-#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
-#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
-#endif
-
-/* controller 3, Slot 1, tgtid 1, Base address 202000 */
-#ifdef CONFIG_PCIE3
-#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
-#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
-#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
-#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
-#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
-#endif
-
-/* controller 4, Base address 203000 */
-#ifdef CONFIG_PCIE4
-#define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
-#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
-#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
-#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
-#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
-#endif
-
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#endif /* CONFIG_PCI */
-
-/* SATA */
-#define CONFIG_FSL_SATA_V2
-#ifdef CONFIG_FSL_SATA_V2
-#define CONFIG_SYS_SATA_MAX_DEVICE 2
-#define CONFIG_SATA1
-#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
-#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
-#define CONFIG_SATA2
-#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
-#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
-
-#define CONFIG_LBA48
-#endif
-
-/*
-* USB
-*/
-#define CONFIG_HAS_FSL_DR_USB
-
-#ifdef CONFIG_HAS_FSL_DR_USB
-#ifdef CONFIG_USB_EHCI_HCD
-#define CONFIG_USB_EHCI_FSL
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#endif
-#endif
-
-#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
-#define CONFIG_FSL_ESDHC_ADAPTER_IDENT
-#endif
-
-/* Qman/Bman */
-#ifndef CONFIG_NOBQFMAN
-#define CONFIG_SYS_BMAN_NUM_PORTALS 10
-#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
-#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
-#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
-#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
-#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
-#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
-#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
- CONFIG_SYS_BMAN_CENA_SIZE)
-#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
-#define CONFIG_SYS_QMAN_NUM_PORTALS 10
-#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
-#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
-#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
-#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
-#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
-#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
-#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
- CONFIG_SYS_QMAN_CENA_SIZE)
-#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
-
-#define CONFIG_SYS_DPAA_FMAN
-#define CONFIG_SYS_DPAA_PME
-
-/* Default address of microcode for the Linux Fman driver */
-#if defined(CONFIG_SPIFLASH)
-/*
- * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
- * env, so we got 0x110000.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
-#elif defined(CONFIG_SDCARD)
-/*
- * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
- * about 825KB (1650 blocks), Env is stored after the image, and the env size is
- * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
-#elif defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
-#else
-#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
-#define CONFIG_SYS_QE_FW_ADDR 0xEFF10000
-#endif
-#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
-#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
-#endif /* CONFIG_NOBQFMAN */
-
-#ifdef CONFIG_SYS_DPAA_FMAN
-#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
-#define SGMII_CARD_PORT2_PHY_ADDR 0x10
-#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
-#define SGMII_CARD_PORT4_PHY_ADDR 0x11
-#endif
-
-#ifdef CONFIG_FMAN_ENET
-#define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x01
-#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x02
-
-#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
-#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
-#define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
-#define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
-
-#define CONFIG_ETHPRIME "FM1 at DTSEC1"
-#endif
-
-/* Enable VSC9953 L2 Switch driver */
-#define CONFIG_VSC9953
-#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x14
-#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x18
-
-/*
- * Dynamic MTD Partition support with mtdparts
- */
-
-/*
- * Environment
- */
-#define CONFIG_LOADS_ECHO /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 64 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
-#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-#define CONFIG_ROOTPATH "/opt/nfsroot"
-#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
-
-/* default location for tftp and bootm */
-#define CONFIG_LOADADDR 1000000
-
-#define __USB_PHY_TYPE utmi
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "hwconfig=fsl_ddr:bank_intlv=auto;" \
- "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
- "netdev=eth0\0" \
- "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \
- "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
- "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
- "tftpflash=tftpboot $loadaddr $uboot && " \
- "protect off $ubootaddr +$filesize && " \
- "erase $ubootaddr +$filesize && " \
- "cp.b $loadaddr $ubootaddr $filesize && " \
- "protect on $ubootaddr +$filesize && " \
- "cmp.b $loadaddr $ubootaddr $filesize\0" \
- "consoledev=ttyS0\0" \
- "ramdiskaddr=2000000\0" \
- "ramdiskfile=t1040qds/ramdisk.uboot\0" \
- "fdtaddr=1e00000\0" \
- "fdtfile=t1040qds/t1040qds.dtb\0" \
- "bdev=sda3\0"
-
-#define CONFIG_LINUX \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "setenv ramdiskaddr 0x02000000;" \
- "setenv fdtaddr 0x00c00000;" \
- "setenv loadaddr 0x1000000;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_HDBOOT \
- "setenv bootargs root=/dev/$bdev rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND CONFIG_LINUX
-
-#include <asm/fsl_secure_boot.h>
-
-#endif /* __CONFIG_H */
--
2.25.1
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 16/24] arm: Remove configs/T2080QDS_NAND_defconfig board
2020-05-27 16:46 [PATCH 00/24] spi: dm-conversion (part2) Jagan Teki
` (14 preceding siblings ...)
2020-05-27 16:46 ` [PATCH 15/24] arm: Remove configs/T1040QDS_DDR4_defconfig board Jagan Teki
@ 2020-05-27 16:46 ` Jagan Teki
2020-05-28 7:14 ` Priyanka Jain
2020-05-27 16:46 ` [PATCH 17/24] arm: Remove configs/T2080RDB_NAND_defconfig board Jagan Teki
` (6 subsequent siblings)
22 siblings, 1 reply; 59+ messages in thread
From: Jagan Teki @ 2020-05-27 16:46 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_SPI by the deadline.
Remove it.
Patch-cc: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Patch-cc: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
arch/powerpc/cpu/mpc85xx/Kconfig | 1 -
board/freescale/t208xqds/Kconfig | 14 -
board/freescale/t208xqds/MAINTAINERS | 20 -
board/freescale/t208xqds/Makefile | 17 -
board/freescale/t208xqds/README | 293 -------
board/freescale/t208xqds/ddr.c | 125 ---
board/freescale/t208xqds/ddr.h | 70 --
board/freescale/t208xqds/eth_t208xqds.c | 826 --------------------
board/freescale/t208xqds/law.c | 33 -
board/freescale/t208xqds/pci.c | 25 -
board/freescale/t208xqds/spl.c | 142 ----
board/freescale/t208xqds/t2080_nand_rcw.cfg | 16 -
board/freescale/t208xqds/t2080_sd_rcw.cfg | 16 -
board/freescale/t208xqds/t2080_spi_rcw.cfg | 16 -
board/freescale/t208xqds/t2081_nand_rcw.cfg | 8 -
board/freescale/t208xqds/t2081_sd_rcw.cfg | 8 -
board/freescale/t208xqds/t2081_spi_rcw.cfg | 8 -
board/freescale/t208xqds/t208x_pbi.cfg | 40 -
board/freescale/t208xqds/t208xqds.c | 489 ------------
board/freescale/t208xqds/t208xqds.h | 12 -
board/freescale/t208xqds/t208xqds_qixis.h | 48 --
board/freescale/t208xqds/tlb.c | 152 ----
configs/T2080QDS_NAND_defconfig | 83 --
configs/T2080QDS_SDCARD_defconfig | 80 --
configs/T2080QDS_SECURE_BOOT_defconfig | 70 --
configs/T2080QDS_SPIFLASH_defconfig | 83 --
configs/T2080QDS_SRIO_PCIE_BOOT_defconfig | 60 --
configs/T2080QDS_defconfig | 68 --
configs/T2081QDS_NAND_defconfig | 75 --
configs/T2081QDS_SDCARD_defconfig | 72 --
configs/T2081QDS_SPIFLASH_defconfig | 75 --
configs/T2081QDS_SRIO_PCIE_BOOT_defconfig | 51 --
configs/T2081QDS_defconfig | 59 --
include/configs/T208xQDS.h | 771 ------------------
34 files changed, 3926 deletions(-)
delete mode 100644 board/freescale/t208xqds/Kconfig
delete mode 100644 board/freescale/t208xqds/MAINTAINERS
delete mode 100644 board/freescale/t208xqds/Makefile
delete mode 100755 board/freescale/t208xqds/README
delete mode 100644 board/freescale/t208xqds/ddr.c
delete mode 100644 board/freescale/t208xqds/ddr.h
delete mode 100644 board/freescale/t208xqds/eth_t208xqds.c
delete mode 100644 board/freescale/t208xqds/law.c
delete mode 100644 board/freescale/t208xqds/pci.c
delete mode 100644 board/freescale/t208xqds/spl.c
delete mode 100644 board/freescale/t208xqds/t2080_nand_rcw.cfg
delete mode 100644 board/freescale/t208xqds/t2080_sd_rcw.cfg
delete mode 100644 board/freescale/t208xqds/t2080_spi_rcw.cfg
delete mode 100644 board/freescale/t208xqds/t2081_nand_rcw.cfg
delete mode 100644 board/freescale/t208xqds/t2081_sd_rcw.cfg
delete mode 100644 board/freescale/t208xqds/t2081_spi_rcw.cfg
delete mode 100644 board/freescale/t208xqds/t208x_pbi.cfg
delete mode 100644 board/freescale/t208xqds/t208xqds.c
delete mode 100644 board/freescale/t208xqds/t208xqds.h
delete mode 100644 board/freescale/t208xqds/t208xqds_qixis.h
delete mode 100644 board/freescale/t208xqds/tlb.c
delete mode 100644 configs/T2080QDS_NAND_defconfig
delete mode 100644 configs/T2080QDS_SDCARD_defconfig
delete mode 100644 configs/T2080QDS_SECURE_BOOT_defconfig
delete mode 100644 configs/T2080QDS_SPIFLASH_defconfig
delete mode 100644 configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
delete mode 100644 configs/T2080QDS_defconfig
delete mode 100644 configs/T2081QDS_NAND_defconfig
delete mode 100644 configs/T2081QDS_SDCARD_defconfig
delete mode 100644 configs/T2081QDS_SPIFLASH_defconfig
delete mode 100644 configs/T2081QDS_SRIO_PCIE_BOOT_defconfig
delete mode 100644 configs/T2081QDS_defconfig
delete mode 100644 include/configs/T208xQDS.h
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 35a1b29ef8..edccf3698c 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -1599,7 +1599,6 @@ source "board/freescale/mpc8572ds/Kconfig"
source "board/freescale/p1023rdb/Kconfig"
source "board/freescale/p1_twr/Kconfig"
source "board/freescale/qemu-ppce500/Kconfig"
-source "board/freescale/t208xqds/Kconfig"
source "board/freescale/t208xrdb/Kconfig"
source "board/freescale/t4qds/Kconfig"
source "board/freescale/t4rdb/Kconfig"
diff --git a/board/freescale/t208xqds/Kconfig b/board/freescale/t208xqds/Kconfig
deleted file mode 100644
index 5a435c2695..0000000000
--- a/board/freescale/t208xqds/Kconfig
+++ /dev/null
@@ -1,14 +0,0 @@
-if TARGET_T2080QDS || TARGET_T2081QDS
-
-config SYS_BOARD
- default "t208xqds"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "T208xQDS"
-
-source "board/freescale/common/Kconfig"
-
-endif
diff --git a/board/freescale/t208xqds/MAINTAINERS b/board/freescale/t208xqds/MAINTAINERS
deleted file mode 100644
index 790b009c51..0000000000
--- a/board/freescale/t208xqds/MAINTAINERS
+++ /dev/null
@@ -1,20 +0,0 @@
-T208XQDS BOARD
-M: Shengzhou Liu <Shengzhou.Liu@nxp.com>
-S: Maintained
-F: board/freescale/t208xqds/
-F: include/configs/T208xQDS.h
-F: configs/T2080QDS_defconfig
-F: configs/T2080QDS_NAND_defconfig
-F: configs/T2080QDS_SDCARD_defconfig
-F: configs/T2080QDS_SPIFLASH_defconfig
-F: configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
-F: configs/T2081QDS_defconfig
-F: configs/T2081QDS_NAND_defconfig
-F: configs/T2081QDS_SDCARD_defconfig
-F: configs/T2081QDS_SPIFLASH_defconfig
-F: configs/T2081QDS_SRIO_PCIE_BOOT_defconfig
-
-T2080QDS_SECURE_BOOT BOARD
-M: Ruchika Gupta <ruchika.gupta@nxp.com>
-S: Maintained
-F: configs/T2080QDS_SECURE_BOOT_defconfig
diff --git a/board/freescale/t208xqds/Makefile b/board/freescale/t208xqds/Makefile
deleted file mode 100644
index 587903a623..0000000000
--- a/board/freescale/t208xqds/Makefile
+++ /dev/null
@@ -1,17 +0,0 @@
-#
-# Copyright 2013 Freescale Semiconductor, Inc.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-ifdef CONFIG_SPL_BUILD
-obj-y += spl.o
-else
-obj-$(CONFIG_TARGET_T2080QDS) += t208xqds.o eth_t208xqds.o
-obj-$(CONFIG_TARGET_T2081QDS) += t208xqds.o eth_t208xqds.o
-obj-$(CONFIG_PCI) += pci.o
-endif
-
-obj-y += ddr.o
-obj-y += law.o
-obj-y += tlb.o
diff --git a/board/freescale/t208xqds/README b/board/freescale/t208xqds/README
deleted file mode 100755
index d690857f2e..0000000000
--- a/board/freescale/t208xqds/README
+++ /dev/null
@@ -1,293 +0,0 @@
-The T2080QDS is a high-performance computing evaluation, development and
-test platform supporting the T2080 QorIQ Power Architecture processor.
-
-T2080 SoC Overview
-------------------
-The T2080 QorIQ multicore processor combines four dual-threaded e6500 Power
-Architecture processor cores with high-performance datapath acceleration
-logic and network and peripheral bus interfaces required for networking,
-telecom/datacom, wireless infrastructure, and mil/aerospace applications.
-
-T2080 includes the following functions and features:
- - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz
- - 2MB L2 cache and 512KB CoreNet platform cache (CPC)
- - Hierarchical interconnect fabric
- - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
- - Data Path Acceleration Architecture (DPAA) incorporating acceleration
- - 16 SerDes lanes up to 10.3125 GHz
- - 8 Ethernet interfaces, supporting combinations of the following:
- - Up to four 10 Gbps Ethernet MACs
- - Up to eight 1 Gbps Ethernet MACs
- - Up to four 2.5 Gbps Ethernet MACs
- - High-speed peripheral interfaces
- - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
- - Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz
- - Additional peripheral interfaces
- - Two serial ATA (SATA 2.0) controllers
- - Two high-speed USB 2.0 controllers with integrated PHY
- - Enhanced secure digital host controller (SD/SDHC/SDXC/eMMC)
- - Enhanced serial peripheral interface (eSPI)
- - Four I2C controllers
- - Four 2-pin UARTs or two 4-pin UARTs
- - Integrated Flash Controller supporting NAND and NOR flash
- - Three eight-channel DMA engines
- - Support for hardware virtualization and partitioning enforcement
- - QorIQ Platform's Trust Architecture 2.0
-
-Differences between T2080 and T2081
------------------------------------
- Feature T2080 T2081
- 1G Ethernet numbers: 8 6
- 10G Ethernet numbers: 4 2
- SerDes lanes: 16 8
- Serial RapidIO,RMan: 2 no
- SATA Controller: 2 no
- Aurora: yes no
- SoC Package: 896-pins 780-pins
-
-
-T2080QDS feature overview
--------------------------
-Processor:
- - T2080 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz
-Memory:
- - Single memory controller capable of supporting DDR3 and DDR3-LV devices
- - Two DDR3 DIMMs up to 4GB, Dual rank @ 2133MT/s and ECC support
-Ethernet interfaces:
- - Two 1Gbps RGMII on-board ports
- - Four 10Gbps XFI on-board cages
- - 1Gbps/2.5Gbps SGMII Riser card
- - 10Gbps XAUI Riser card
-Accelerator:
- - DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC
-SerDes:
- - 16 lanes up to 10.3125GHz
- - Supports Aurora debug, PEX, SATA, SGMII, sRIO, HiGig, XFI and XAUI
-IFC:
- - 128MB NOR Flash, 512MB NAND Flash, PromJet debug port and FPGA
-eSPI:
- - Three SPI flash (16MB N25Q128A + 16MB EN25S64 + 512KB SST25WF040)
-USB:
- - Two USB2.0 ports with internal PHY (one Type-A + one micro Type-AB)
-PCIE:
- - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
-SATA:
- - Two SATA 2.0 ports on-board
-SRIO:
- - Two Serial RapidIO 2.0 ports up to 5 GHz
-eSDHC:
- - Supports SD/SDHC/SDXC/eMMC Card
-I2C:
- - Four I2C controllers.
-UART:
- - Dual 4-pins UART serial ports
-System Logic:
- - QIXIS-II FPGA system controll
-Debug Features:
- - Support Legacy, COP/JTAG, Aurora, Event and EVT
-XFI:
- - XFI is supported on T2080QDS through Lane A/B/C/D on Serdes 1 routed to
- a on-board SFP+ cages, which to house optical module (fiber cable) or
- direct attach cable(copper), the copper cable is used to emulate
- 10GBASE-KR scenario.
- So, for XFI usage, there are two scenarios, one will use fiber cable,
- another will use copper cable. An hwconfig env "fsl_10gkr_copper" is
- introduced to indicate a XFI port will use copper cable, and U-Boot
- will fixup the dtb accordingly.
- It's used as: fsl_10gkr_copper:<10g_mac_name>
- The <10g_mac_name> can be fm1_10g1, fm1_10g2, fm1_10g3, fm1_10g4, they
- do not have to be coexist in hwconfig. If a MAC is listed in the env
- "fsl_10gkr_copper", it will use copper cable, otherwise, fiber cable
- will be used by default.
- for ex. set "fsl_10gkr_copper:fm1_10g1,fm1_10g2,fm1_10g3,fm1_10g4" in
- hwconfig, then both four XFI ports will use copper cable.
- set "fsl_10gkr_copper:fm1_10g1,fm1_10g2" in hwconfig, then first two
- XFI ports will use copper cable, the other two XFI ports will use fiber
- cable.
-1000BASE-KX(1G-KX):
- - T2080QDS can support 1G-KX by using SGMII protocol, but serdes lane
- runs in 1G-KX mode. By default, the lane runs in SGMII mode, to set a lane
- in 1G-KX mode, need to set corresponding bit in SerDes Protocol Configuration
- Register 1 (PCCR1), and U-Boot fixup the dtb for kernel to do proper
- initialization.
- Hwconfig "fsl_1gkx" is used to indicate a lane runs in 1G-KX mode, MAC
- 1/2/5/6/9/10 are available for 1G-KX, MAC 3/4 run in RGMII mode. To set a
- MAC to use 1G-KX mode, set its' corresponding env in "fsl_1gkx", 'fm1_1g1'
- stands for MAC 1, 'fm1_1g2' stands for MAC 2, etc.
- For ex. set "fsl_1gkx:fm1_1g1,fm1_1g2,fm1_1g5,fm1_1g6,fm1_1g9,fm1_1g10" in
- hwconfig, MAC 1/2/5/6/9/10 will use 1G-KX mode.
-
-System Memory map
-----------------
-
-Start Address End Address Description Size
-0xF_FFDF_0000 0xF_FFDF_0FFF IFC - CPLD 4KB
-0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB
-0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB
-0xF_F803_0000 0xF_F803_FFFF PCI Express 4 I/O Space 64KB
-0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB
-0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB
-0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB
-0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB
-0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB
-0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB
-0xF_0000_0000 0xF_003F_FFFF DCSR 4MB
-0xC_4000_0000 0xC_4FFF_FFFF PCI Express 4 Mem Space 256MB
-0xC_3000_0000 0xC_3FFF_FFFF PCI Express 3 Mem Space 256MB
-0xC_2000_0000 0xC_2FFF_FFFF PCI Express 2 Mem Space 256MB
-0xC_0000_0000 0xC_1FFF_FFFF PCI Express 1 Mem Space 512MB
-0x0_0000_0000 0x0_ffff_ffff DDR 4GB
-
-
-128M NOR Flash memory Map
--------------------------
-Start Address End Address Definition Max size
-0xEFF40000 0xEFFFFFFF U-Boot (current bank) 768KB
-0xEFF20000 0xEFF3FFFF U-Boot env (current bank) 128KB
-0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB
-0xED300000 0xEFEFFFFF rootfs (alt bank) 44MB
-0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB
-0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB
-0xEC000000 0xEC01FFFF RCW (alt bank) 128KB
-0xEBF40000 0xEBFFFFFF U-Boot (alt bank) 768KB
-0xEBF20000 0xEBF3FFFF U-Boot env (alt bank) 128KB
-0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB
-0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB
-0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 1MB
-0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB
-0xE8000000 0xE801FFFF RCW (current bank) 128KB
-
-
-
-Software configurations and board settings
-------------------------------------------
-1. NOR boot:
- a. build NOR boot image
- $ make T2080QDS_config
- $ make
- b. program u-boot.bin image to NOR flash
- => tftp 1000000 u-boot.bin
- => pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize
- set SW1[1:8] = '00010011', SW2[1] = '1', SW6[1:4] = '0000' for NOR boot
-
- Switching between default bank0 and alternate bank4 on NOR flash
- To change boot source to vbank4:
- by software: run command 'qixis_reset altbank' in U-Boot.
- by DIP-switch: set SW6[1:4] = '0100'
-
- To change boot source to vbank0:
- by software: run command 'qixis_reset' in U-Boot.
- by DIP-Switch: set SW6[1:4] = '0000'
-
-2. NAND Boot:
- a. build PBL image for NAND boot
- $ make T2080QDS_NAND_config
- $ make
- b. program u-boot-with-spl-pbl.bin to NAND flash
- => tftp 1000000 u-boot-with-spl-pbl.bin
- => nand erase 0 $filesize
- => nand write 1000000 0 $filesize
- set SW1[1:8] = '10000010', SW2[1] = '0' and SW6[1:4] = '1001' for NAND boot
-
-3. SPI Boot:
- a. build PBL image for SPI boot
- $ make T2080QDS_SPIFLASH_config
- $ make
- b. program u-boot-with-spl-pbl.bin to SPI flash
- => tftp 1000000 u-boot-with-spl-pbl.bin
- => sf probe 0
- => sf erase 0 f0000
- => sf write 1000000 0 $filesize
- set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot
-
-4. SD Boot:
- a. build PBL image for SD boot
- $ make T2080QDS_SDCARD_config
- $ make
- b. program u-boot-with-spl-pbl.bin to SD/MMC card
- => tftp 1000000 u-boot-with-spl-pbl.bin
- => mmc write 1000000 8 0x800
- => tftp 1000000 fsl_fman_ucode_T2080_xx.bin
- => mmc write 1000000 0x820 80
- set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot
-
-
-2-stage NAND/SPI/SD boot loader
--------------------------------
-PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM.
-SPL further initializes DDR using SPD and environment variables
-and copy U-Boot(768 KB) from NAND/SPI/SD device to DDR.
-Finally SPL transers control to U-Boot for futher booting.
-
-SPL has following features:
- - Executes within 256K
- - No relocation required
-
-Run time view of SPL framework
--------------------------------------------------
-|Area | Address |
--------------------------------------------------
-|SecureBoot header | 0xFFFC0000 (32KB) |
--------------------------------------------------
-|GD, BD | 0xFFFC8000 (4KB) |
--------------------------------------------------
-|ENV | 0xFFFC9000 (8KB) |
--------------------------------------------------
-|HEAP | 0xFFFCB000 (50KB) |
--------------------------------------------------
-|STACK | 0xFFFD8000 (22KB) |
--------------------------------------------------
-|U-Boot SPL | 0xFFFD8000 (160KB) |
--------------------------------------------------
-
-NAND Flash memory Map on T2080QDS
---------------------------------------------------------------
-Start End Definition Size
-0x000000 0x0FFFFF U-Boot img 1MB (2 blocks)
-0x100000 0x17FFFF U-Boot env 512KB (1 block)
-0x180000 0x1FFFFF FMAN ucode 512KB (1 block)
-
-
-Micro SD Card memory Map on T2080QDS
-----------------------------------------------------
-Block #blocks Definition Size
-0x008 2048 U-Boot img 1MB
-0x800 0016 U-Boot env 8KB
-0x820 0128 FMAN ucode 64KB
-
-
-SPI Flash memory Map on T2080QDS
-----------------------------------------------------
-Start End Definition Size
-0x000000 0x0FFFFF U-Boot img 1MB
-0x100000 0x101FFF U-Boot env 8KB
-0x110000 0x11FFFF FMAN ucode 64KB
-
-
-How to update the ucode of Freescale FMAN
------------------------------------------
-=> tftp 1000000 fsl_fman_ucode_t2080_xx.bin
-=> pro off all;erase 0xeff00000 0xeff1ffff;cp 1000000 0xeff00000 $filesize
-
-
-For more details, please refer to T2080QDS User Guide and access
-website www.freescale.com and Freescale QorIQ SDK Infocenter document.
-
-Device tree support and how to enable it for different configs
---------------------------------------------------------------
-Device tree support is available for t2080qds for below mentioned boot,
-1. NOR Boot
-2. NAND Boot
-3. SD Boot
-4. SPIFLASH Boot
-
-To enable device tree support for other boot, below configs need to be
-enabled in relative defconfig file,
-1. CONFIG_DEFAULT_DEVICE_TREE="t2080qds" (Change default device tree name if required)
-2. CONFIG_OF_CONTROL
-3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at
- CONFIG_RESET_VECTOR_ADDRESS - 0xffc
-
-If device tree support is enabled in defconfig,
-1. use 'u-boot-with-dtb.bin' for NOR boot.
-2. use 'u-boot-with-spl-pbl.bin' for other boot.
diff --git a/board/freescale/t208xqds/ddr.c b/board/freescale/t208xqds/ddr.c
deleted file mode 100644
index 3317f99c81..0000000000
--- a/board/freescale/t208xqds/ddr.c
+++ /dev/null
@@ -1,125 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <hwconfig.h>
-#include <init.h>
-#include <log.h>
-#include <asm/mmu.h>
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-#include <asm/fsl_law.h>
-#include "ddr.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
- ulong ddr_freq;
-
- if (ctrl_num > 1) {
- printf("Not supported controller number %d\n", ctrl_num);
- return;
- }
- if (!pdimm->n_ranks)
- return;
-
- /*
- * we use identical timing for all slots. If needed, change the code
- * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
- */
- if (popts->registered_dimm_en)
- pbsp = rdimms[0];
- else
- pbsp = udimms[0];
-
- /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
- * freqency and n_banks specified in board_specific_parameters table.
- */
- ddr_freq = get_ddr_freq(0) / 1000000;
- while (pbsp->datarate_mhz_high) {
- if (pbsp->n_ranks == pdimm->n_ranks &&
- (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
- if (ddr_freq <= pbsp->datarate_mhz_high) {
- popts->clk_adjust = pbsp->clk_adjust;
- popts->wrlvl_start = pbsp->wrlvl_start;
- popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
- popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
- goto found;
- }
- pbsp_highest = pbsp;
- }
- pbsp++;
- }
-
- if (pbsp_highest) {
- printf("Error: board specific timing not found");
- printf("for data rate %lu MT/s\n", ddr_freq);
- printf("Trying to use the highest speed (%u) parameters\n",
- pbsp_highest->datarate_mhz_high);
- popts->clk_adjust = pbsp_highest->clk_adjust;
- popts->wrlvl_start = pbsp_highest->wrlvl_start;
- popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
- popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
- } else {
- panic("DIMM is not supported by this board");
- }
-found:
- debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
- "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
- "wrlvl_ctrl_3 0x%x\n",
- pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
- pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
- pbsp->wrlvl_ctl_3);
-
- /*
- * Factors to consider for half-strength driver enable:
- * - number of DIMMs installed
- */
- popts->half_strength_driver_enable = 0;
- /*
- * Write leveling override
- */
- popts->wrlvl_override = 1;
- popts->wrlvl_sample = 0xf;
-
- /*
- * Rtt and Rtt_WR override
- */
- popts->rtt_override = 0;
-
- /* Enable ZQ calibration */
- popts->zq_en = 1;
-
- /* DHC_EN =1, ODT = 75 Ohm */
- popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
- popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
-
- /* optimize cpo for erratum A-009942 */
- popts->cpo_sample = 0x64;
-}
-
-int dram_init(void)
-{
- phys_size_t dram_size;
-
-#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
- puts("Initializing....using SPD\n");
- dram_size = fsl_ddr_sdram();
-#else
- /* DDR has been initialised by first stage boot loader */
- dram_size = fsl_ddr_sdram_size();
-#endif
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
-
- gd->ram_size = dram_size;
-
- return 0;
-}
diff --git a/board/freescale/t208xqds/ddr.h b/board/freescale/t208xqds/ddr.h
deleted file mode 100644
index 9dd39813bf..0000000000
--- a/board/freescale/t208xqds/ddr.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#ifndef __DDR_H__
-#define __DDR_H__
-struct board_specific_parameters {
- u32 n_ranks;
- u32 datarate_mhz_high;
- u32 rank_gb;
- u32 clk_adjust;
- u32 wrlvl_start;
- u32 wrlvl_ctl_2;
- u32 wrlvl_ctl_3;
-};
-
-/*
- * These tables contain all valid speeds we want to override with board
- * specific parameters. datarate_mhz_high values need to be in ascending order
- * for each n_ranks group.
- */
-
-static const struct board_specific_parameters udimm0[] = {
- /*
- * memory controller 0
- * num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
- * ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
- */
- {2, 1200, 0, 10, 7, 0x0708090a, 0x0b0c0d09},
- {2, 1400, 0, 10, 7, 0x08090a0c, 0x0d0e0f0a},
- {2, 1700, 0, 10, 8, 0x090a0b0c, 0x0e10110c},
- {2, 1900, 0, 10, 8, 0x090b0c0f, 0x1012130d},
- {2, 2140, 0, 10, 8, 0x090b0c0f, 0x1012130d},
- {1, 1200, 0, 10, 7, 0x0808090a, 0x0b0c0c0a},
- {1, 1500, 0, 10, 6, 0x07070809, 0x0a0b0b09},
- {1, 1600, 0, 10, 8, 0x090b0b0d, 0x0d0e0f0b},
- {1, 1700, 0, 8, 8, 0x080a0a0c, 0x0c0d0e0a},
- {1, 1900, 0, 10, 8, 0x090a0c0d, 0x0e0f110c},
- {1, 2140, 0, 8, 8, 0x090a0b0d, 0x0e0f110b},
- {}
-};
-
-static const struct board_specific_parameters rdimm0[] = {
- /*
- * memory controller 0
- * num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
- * ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
- */
- /* TODO: need tuning these parameters if RDIMM is used */
- {4, 1350, 0, 10, 9, 0x08070605, 0x06070806},
- {4, 1666, 0, 10, 11, 0x0a080706, 0x07090906},
- {4, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07},
- {2, 1350, 0, 10, 9, 0x08070605, 0x06070806},
- {2, 1666, 0, 10, 11, 0x0a090806, 0x08090a06},
- {2, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07},
- {1, 1350, 0, 10, 9, 0x08070605, 0x06070806},
- {1, 1666, 0, 10, 11, 0x0a090806, 0x08090a06},
- {1, 2140, 0, 8, 12, 0x0b090807, 0x080a0b07},
- {}
-};
-
-static const struct board_specific_parameters *udimms[] = {
- udimm0,
-};
-
-static const struct board_specific_parameters *rdimms[] = {
- rdimm0,
-};
-#endif
diff --git a/board/freescale/t208xqds/eth_t208xqds.c b/board/freescale/t208xqds/eth_t208xqds.c
deleted file mode 100644
index 938e606641..0000000000
--- a/board/freescale/t208xqds/eth_t208xqds.c
+++ /dev/null
@@ -1,826 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- * Copyright 2020 NXP
- *
- * Shengzhou Liu <Shengzhou.Liu@freescale.com>
- */
-
-#include <common.h>
-#include <command.h>
-#include <fdt_support.h>
-#include <log.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/mmu.h>
-#include <asm/processor.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_law.h>
-#include <asm/fsl_serdes.h>
-#include <asm/fsl_portals.h>
-#include <asm/fsl_liodn.h>
-#include <malloc.h>
-#include <fm_eth.h>
-#include <fsl_mdio.h>
-#include <miiphy.h>
-#include <phy.h>
-#include <fsl_dtsec.h>
-#include <asm/fsl_serdes.h>
-#include <hwconfig.h>
-#include "../common/qixis.h"
-#include "../common/fman.h"
-#include "t208xqds_qixis.h"
-#include <linux/libfdt.h>
-
-#define EMI_NONE 0xFFFFFFFF
-#define EMI1_RGMII1 0
-#define EMI1_RGMII2 1
-#define EMI1_SLOT1 2
-#if defined(CONFIG_TARGET_T2080QDS)
-#define EMI1_SLOT2 6
-#define EMI1_SLOT3 3
-#define EMI1_SLOT4 4
-#define EMI1_SLOT5 5
-#define EMI2 7
-#elif defined(CONFIG_TARGET_T2081QDS)
-#define EMI1_SLOT2 3
-#define EMI1_SLOT3 4
-#define EMI1_SLOT5 5
-#define EMI1_SLOT6 6
-#define EMI1_SLOT7 7
-#define EMI2 8
-#endif
-
-#define PCCR1_SGMIIA_KX_MASK 0x00008000
-#define PCCR1_SGMIIB_KX_MASK 0x00004000
-#define PCCR1_SGMIIC_KX_MASK 0x00002000
-#define PCCR1_SGMIID_KX_MASK 0x00001000
-#define PCCR1_SGMIIE_KX_MASK 0x00000800
-#define PCCR1_SGMIIF_KX_MASK 0x00000400
-#define PCCR1_SGMIIG_KX_MASK 0x00000200
-#define PCCR1_SGMIIH_KX_MASK 0x00000100
-
-static int mdio_mux[NUM_FM_PORTS];
-
-static const char * const mdio_names[] = {
-#if defined(CONFIG_TARGET_T2080QDS)
- "T2080QDS_MDIO_RGMII1",
- "T2080QDS_MDIO_RGMII2",
- "T2080QDS_MDIO_SLOT1",
- "T2080QDS_MDIO_SLOT3",
- "T2080QDS_MDIO_SLOT4",
- "T2080QDS_MDIO_SLOT5",
- "T2080QDS_MDIO_SLOT2",
- "T2080QDS_MDIO_10GC",
-#elif defined(CONFIG_TARGET_T2081QDS)
- "T2081QDS_MDIO_RGMII1",
- "T2081QDS_MDIO_RGMII2",
- "T2081QDS_MDIO_SLOT1",
- "T2081QDS_MDIO_SLOT2",
- "T2081QDS_MDIO_SLOT3",
- "T2081QDS_MDIO_SLOT5",
- "T2081QDS_MDIO_SLOT6",
- "T2081QDS_MDIO_SLOT7",
- "T2081QDS_MDIO_10GC",
-#endif
-};
-
-/* Map SerDes1 8 lanes to default slot, will be initialized dynamically */
-#if defined(CONFIG_TARGET_T2080QDS)
-static u8 lane_to_slot[] = {3, 3, 3, 3, 1, 1, 1, 1};
-#elif defined(CONFIG_TARGET_T2081QDS)
-static u8 lane_to_slot[] = {2, 2, 2, 2, 1, 1, 1, 1};
-#endif
-
-static const char *t208xqds_mdio_name_for_muxval(u8 muxval)
-{
- return mdio_names[muxval];
-}
-
-struct mii_dev *mii_dev_for_muxval(u8 muxval)
-{
- struct mii_dev *bus;
- const char *name = t208xqds_mdio_name_for_muxval(muxval);
-
- if (!name) {
- printf("No bus for muxval %x\n", muxval);
- return NULL;
- }
-
- bus = miiphy_get_dev_by_name(name);
-
- if (!bus) {
- printf("No bus by name %s\n", name);
- return NULL;
- }
-
- return bus;
-}
-
-struct t208xqds_mdio {
- u8 muxval;
- struct mii_dev *realbus;
-};
-
-static void t208xqds_mux_mdio(u8 muxval)
-{
- u8 brdcfg4;
- if (muxval < 8) {
- brdcfg4 = QIXIS_READ(brdcfg[4]);
- brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
- brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
- QIXIS_WRITE(brdcfg[4], brdcfg4);
- }
-}
-
-static int t208xqds_mdio_read(struct mii_dev *bus, int addr, int devad,
- int regnum)
-{
- struct t208xqds_mdio *priv = bus->priv;
-
- t208xqds_mux_mdio(priv->muxval);
-
- return priv->realbus->read(priv->realbus, addr, devad, regnum);
-}
-
-static int t208xqds_mdio_write(struct mii_dev *bus, int addr, int devad,
- int regnum, u16 value)
-{
- struct t208xqds_mdio *priv = bus->priv;
-
- t208xqds_mux_mdio(priv->muxval);
-
- return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
-}
-
-static int t208xqds_mdio_reset(struct mii_dev *bus)
-{
- struct t208xqds_mdio *priv = bus->priv;
-
- return priv->realbus->reset(priv->realbus);
-}
-
-static int t208xqds_mdio_init(char *realbusname, u8 muxval)
-{
- struct t208xqds_mdio *pmdio;
- struct mii_dev *bus = mdio_alloc();
-
- if (!bus) {
- printf("Failed to allocate t208xqds MDIO bus\n");
- return -1;
- }
-
- pmdio = malloc(sizeof(*pmdio));
- if (!pmdio) {
- printf("Failed to allocate t208xqds private data\n");
- free(bus);
- return -1;
- }
-
- bus->read = t208xqds_mdio_read;
- bus->write = t208xqds_mdio_write;
- bus->reset = t208xqds_mdio_reset;
- strcpy(bus->name, t208xqds_mdio_name_for_muxval(muxval));
-
- pmdio->realbus = miiphy_get_dev_by_name(realbusname);
-
- if (!pmdio->realbus) {
- printf("No bus with name %s\n", realbusname);
- free(bus);
- free(pmdio);
- return -1;
- }
-
- pmdio->muxval = muxval;
- bus->priv = pmdio;
- return mdio_register(bus);
-}
-
-void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
- enum fm_port port, int offset)
-{
- int phy;
- char alias[20];
- char lane_mode[2][20] = {"1000BASE-KX", "10GBASE-KR"};
- char buf[32] = "serdes-1,";
- struct fixed_link f_link;
- int media_type = 0;
- const char *phyconn;
- int off;
-
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-#ifdef CONFIG_TARGET_T2080QDS
- serdes_corenet_t *srds_regs =
- (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
- u32 srds1_pccr1 = in_be32(&srds_regs->srdspccr1);
-#endif
- u32 srds_s1 = in_be32(&gur->rcwsr[4]) &
- FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
-
- srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
-
- if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
- phy = fm_info_get_phy_address(port);
- switch (port) {
-#if defined(CONFIG_TARGET_T2080QDS)
- case FM1_DTSEC1:
- if (hwconfig_sub("fsl_1gkx", "fm1_1g1")) {
- media_type = 1;
- fdt_set_phy_handle(fdt, compat, addr,
- "phy_1gkx1");
- fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio1");
- sprintf(buf, "%s%s%s", buf, "lane-c,",
- (char *)lane_mode[0]);
- out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
- PCCR1_SGMIIH_KX_MASK);
- break;
- }
- case FM1_DTSEC2:
- if (hwconfig_sub("fsl_1gkx", "fm1_1g2")) {
- media_type = 1;
- fdt_set_phy_handle(fdt, compat, addr,
- "phy_1gkx2");
- fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio2");
- sprintf(buf, "%s%s%s", buf, "lane-d,",
- (char *)lane_mode[0]);
- out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
- PCCR1_SGMIIG_KX_MASK);
- break;
- }
- case FM1_DTSEC9:
- if (hwconfig_sub("fsl_1gkx", "fm1_1g9")) {
- media_type = 1;
- fdt_set_phy_handle(fdt, compat, addr,
- "phy_1gkx9");
- fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio9");
- sprintf(buf, "%s%s%s", buf, "lane-a,",
- (char *)lane_mode[0]);
- out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
- PCCR1_SGMIIE_KX_MASK);
- break;
- }
- case FM1_DTSEC10:
- if (hwconfig_sub("fsl_1gkx", "fm1_1g10")) {
- media_type = 1;
- fdt_set_phy_handle(fdt, compat, addr,
- "phy_1gkx10");
- fdt_status_okay_by_alias(fdt,
- "1gkx_pcs_mdio10");
- sprintf(buf, "%s%s%s", buf, "lane-b,",
- (char *)lane_mode[0]);
- out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
- PCCR1_SGMIIF_KX_MASK);
- break;
- }
- if (mdio_mux[port] == EMI1_SLOT2) {
- sprintf(alias, "phy_sgmii_s2_%x", phy);
- fdt_set_phy_handle(fdt, compat, addr, alias);
- fdt_status_okay_by_alias(fdt, "emi1_slot2");
- } else if (mdio_mux[port] == EMI1_SLOT3) {
- sprintf(alias, "phy_sgmii_s3_%x", phy);
- fdt_set_phy_handle(fdt, compat, addr, alias);
- fdt_status_okay_by_alias(fdt, "emi1_slot3");
- }
- break;
- case FM1_DTSEC5:
- if (hwconfig_sub("fsl_1gkx", "fm1_1g5")) {
- media_type = 1;
- fdt_set_phy_handle(fdt, compat, addr,
- "phy_1gkx5");
- fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio5");
- sprintf(buf, "%s%s%s", buf, "lane-g,",
- (char *)lane_mode[0]);
- out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
- PCCR1_SGMIIC_KX_MASK);
- break;
- }
- case FM1_DTSEC6:
- if (hwconfig_sub("fsl_1gkx", "fm1_1g6")) {
- media_type = 1;
- fdt_set_phy_handle(fdt, compat, addr,
- "phy_1gkx6");
- fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio6");
- sprintf(buf, "%s%s%s", buf, "lane-h,",
- (char *)lane_mode[0]);
- out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
- PCCR1_SGMIID_KX_MASK);
- break;
- }
- if (mdio_mux[port] == EMI1_SLOT1) {
- sprintf(alias, "phy_sgmii_s1_%x", phy);
- fdt_set_phy_handle(fdt, compat, addr, alias);
- fdt_status_okay_by_alias(fdt, "emi1_slot1");
- } else if (mdio_mux[port] == EMI1_SLOT2) {
- sprintf(alias, "phy_sgmii_s2_%x", phy);
- fdt_set_phy_handle(fdt, compat, addr, alias);
- fdt_status_okay_by_alias(fdt, "emi1_slot2");
- }
- break;
-#elif defined(CONFIG_TARGET_T2081QDS)
- case FM1_DTSEC1:
- case FM1_DTSEC2:
- case FM1_DTSEC5:
- case FM1_DTSEC6:
- case FM1_DTSEC9:
- case FM1_DTSEC10:
- if (mdio_mux[port] == EMI1_SLOT2) {
- sprintf(alias, "phy_sgmii_s2_%x", phy);
- fdt_set_phy_handle(fdt, compat, addr, alias);
- fdt_status_okay_by_alias(fdt, "emi1_slot2");
- } else if (mdio_mux[port] == EMI1_SLOT3) {
- sprintf(alias, "phy_sgmii_s3_%x", phy);
- fdt_set_phy_handle(fdt, compat, addr, alias);
- fdt_status_okay_by_alias(fdt, "emi1_slot3");
- } else if (mdio_mux[port] == EMI1_SLOT5) {
- sprintf(alias, "phy_sgmii_s5_%x", phy);
- fdt_set_phy_handle(fdt, compat, addr, alias);
- fdt_status_okay_by_alias(fdt, "emi1_slot5");
- } else if (mdio_mux[port] == EMI1_SLOT6) {
- sprintf(alias, "phy_sgmii_s6_%x", phy);
- fdt_set_phy_handle(fdt, compat, addr, alias);
- fdt_status_okay_by_alias(fdt, "emi1_slot6");
- } else if (mdio_mux[port] == EMI1_SLOT7) {
- sprintf(alias, "phy_sgmii_s7_%x", phy);
- fdt_set_phy_handle(fdt, compat, addr, alias);
- fdt_status_okay_by_alias(fdt, "emi1_slot7");
- }
- break;
-#endif
- default:
- break;
- }
- if (media_type) {
- /* set property for 1000BASE-KX in dtb */
- off = fdt_node_offset_by_compat_reg(fdt,
- "fsl,fman-memac-mdio", addr + 0x1000);
- fdt_setprop_string(fdt, off, "lane-instance", buf);
- }
-
- } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) {
- switch (srds_s1) {
- case 0x66: /* XFI interface */
- case 0x6b:
- case 0x6c:
- case 0x6d:
- case 0x71:
- /*
- * if the 10G is XFI, check hwconfig to see what is the
- * media type, there are two types, fiber or copper,
- * fix the dtb accordingly.
- */
- switch (port) {
- case FM1_10GEC1:
- if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g1")) {
- /* it's MAC9 */
- media_type = 1;
- fdt_set_phy_handle(fdt, compat, addr,
- "phy_xfi9");
- fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio9");
- sprintf(buf, "%s%s%s", buf, "lane-a,",
- (char *)lane_mode[1]);
- }
- break;
- case FM1_10GEC2:
- if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g2")) {
- /* it's MAC10 */
- media_type = 1;
- fdt_set_phy_handle(fdt, compat, addr,
- "phy_xfi10");
- fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio10");
- sprintf(buf, "%s%s%s", buf, "lane-b,",
- (char *)lane_mode[1]);
- }
- break;
- case FM1_10GEC3:
- if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g3")) {
- /* it's MAC1 */
- media_type = 1;
- fdt_set_phy_handle(fdt, compat, addr,
- "phy_xfi1");
- fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio1");
- sprintf(buf, "%s%s%s", buf, "lane-c,",
- (char *)lane_mode[1]);
- }
- break;
- case FM1_10GEC4:
- if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g4")) {
- /* it's MAC2 */
- media_type = 1;
- fdt_set_phy_handle(fdt, compat, addr,
- "phy_xfi2");
- fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio2");
- sprintf(buf, "%s%s%s", buf, "lane-d,",
- (char *)lane_mode[1]);
- }
- break;
- default:
- return;
- }
-
- if (!media_type) {
- phyconn = fdt_getprop(fdt, offset,
- "phy-connection-type",
- NULL);
- if (is_backplane_mode(phyconn)) {
- /* Backplane KR mode: skip fixups */
- printf("Interface %d in backplane KR mode\n",
- port);
- } else {
- /* fixed-link for XFI fiber cable */
- f_link.phy_id = port;
- f_link.duplex = 1;
- f_link.link_speed = 10000;
- f_link.pause = 0;
- f_link.asym_pause = 0;
- fdt_delprop(fdt, offset, "phy-handle");
- fdt_setprop(fdt, offset, "fixed-link",
- &f_link, sizeof(f_link));
- }
- } else {
- /* set property for copper cable */
- off = fdt_node_offset_by_compat_reg(fdt,
- "fsl,fman-memac-mdio", addr + 0x1000);
- fdt_setprop_string(fdt, off,
- "lane-instance", buf);
- }
- break;
- default:
- break;
- }
- }
-}
-
-void fdt_fixup_board_enet(void *fdt)
-{
- return;
-}
-
-/*
- * This function reads RCW to check if Serdes1{A:H} is configured
- * to slot 1/2/3/4/5/6/7 and update the lane_to_slot[] array accordingly
- */
-static void initialize_lane_to_slot(void)
-{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- u32 srds_s1 = in_be32(&gur->rcwsr[4]) &
- FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
-
- srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
-
- switch (srds_s1) {
-#if defined(CONFIG_TARGET_T2080QDS)
- case 0x51:
- case 0x5f:
- case 0x65:
- case 0x6b:
- case 0x71:
- lane_to_slot[5] = 2;
- lane_to_slot[6] = 2;
- lane_to_slot[7] = 2;
- break;
- case 0xa6:
- case 0x8e:
- case 0x8f:
- case 0x82:
- case 0x83:
- case 0xd3:
- case 0xd9:
- case 0xcb:
- lane_to_slot[6] = 2;
- lane_to_slot[7] = 2;
- break;
- case 0xda:
- lane_to_slot[4] = 3;
- lane_to_slot[5] = 3;
- lane_to_slot[6] = 3;
- lane_to_slot[7] = 3;
- break;
-#elif defined(CONFIG_TARGET_T2081QDS)
- case 0x6b:
- lane_to_slot[4] = 1;
- lane_to_slot[5] = 3;
- lane_to_slot[6] = 3;
- lane_to_slot[7] = 3;
- break;
- case 0xca:
- case 0xcb:
- lane_to_slot[1] = 7;
- lane_to_slot[2] = 6;
- lane_to_slot[3] = 5;
- lane_to_slot[5] = 3;
- lane_to_slot[6] = 3;
- lane_to_slot[7] = 3;
- break;
- case 0xf2:
- lane_to_slot[1] = 7;
- lane_to_slot[2] = 7;
- lane_to_slot[3] = 7;
- lane_to_slot[5] = 4;
- lane_to_slot[6] = 3;
- lane_to_slot[7] = 7;
- break;
-#endif
- default:
- break;
- }
-}
-
-int board_eth_init(bd_t *bis)
-{
-#if defined(CONFIG_FMAN_ENET)
- int i, idx, lane, slot, interface;
- struct memac_mdio_info dtsec_mdio_info;
- struct memac_mdio_info tgec_mdio_info;
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
- u32 srds_s1;
-
- srds_s1 = in_be32(&gur->rcwsr[4]) &
- FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
- srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
-
- initialize_lane_to_slot();
-
- /* Initialize the mdio_mux array so we can recognize empty elements */
- for (i = 0; i < NUM_FM_PORTS; i++)
- mdio_mux[i] = EMI_NONE;
-
- dtsec_mdio_info.regs =
- (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
-
- dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
-
- /* Register the 1G MDIO bus */
- fm_memac_mdio_init(bis, &dtsec_mdio_info);
-
- tgec_mdio_info.regs =
- (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
- tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
-
- /* Register the 10G MDIO bus */
- fm_memac_mdio_init(bis, &tgec_mdio_info);
-
- /* Register the muxing front-ends to the MDIO buses */
- t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
- t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);
- t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
- t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
- t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
-#if defined(CONFIG_TARGET_T2080QDS)
- t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
-#endif
- t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
-#if defined(CONFIG_TARGET_T2081QDS)
- t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT6);
- t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7);
-#endif
- t208xqds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
-
- /* Set the two on-board RGMII PHY address */
- fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
- if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
- FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII)
- fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
- else
- fm_info_set_phy_address(FM1_DTSEC10, RGMII_PHY2_ADDR);
-
- switch (srds_s1) {
- case 0x1b:
- case 0x1c:
- case 0x95:
- case 0xa2:
- case 0x94:
- /* T2080QDS: SGMII in Slot3; T2081QDS: SGMII in Slot2 */
- fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
- /* T2080QDS: SGMII in Slot2; T2081QDS: SGMII in Slot1 */
- fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
- break;
- case 0x50:
- case 0x51:
- case 0x5e:
- case 0x5f:
- case 0x64:
- case 0x65:
- /* T2080QDS: XAUI/HiGig in Slot3; T2081QDS: in Slot2 */
- fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
- /* T2080QDS: SGMII in Slot2; T2081QDS: in Slot3 */
- fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
- break;
- case 0x66:
- case 0x67:
- /*
- * XFI does not need a PHY to work, but to avoid U-Boot use
- * default PHY address which is zero to a MAC when it found
- * a MAC has no PHY address, we give a PHY address to XFI
- * MAC, and should not use a real XAUI PHY address, since
- * MDIO can access it successfully, and then MDIO thinks
- * the XAUI card is used for the XFI MAC, which will cause
- * error.
- */
- fm_info_set_phy_address(FM1_10GEC1, 4);
- fm_info_set_phy_address(FM1_10GEC2, 5);
- fm_info_set_phy_address(FM1_10GEC3, 6);
- fm_info_set_phy_address(FM1_10GEC4, 7);
- break;
- case 0x6a:
- case 0x6b:
- fm_info_set_phy_address(FM1_10GEC1, 4);
- fm_info_set_phy_address(FM1_10GEC2, 5);
- fm_info_set_phy_address(FM1_10GEC3, 6);
- fm_info_set_phy_address(FM1_10GEC4, 7);
- /* T2080QDS: SGMII in Slot2; T2081QDS: in Slot3 */
- fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
- break;
- case 0x6c:
- case 0x6d:
- fm_info_set_phy_address(FM1_10GEC1, 4);
- fm_info_set_phy_address(FM1_10GEC2, 5);
- /* T2080QDS: SGMII in Slot3; T2081QDS: in Slot2 */
- fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
- break;
- case 0x70:
- case 0x71:
- /* SGMII in Slot3 */
- fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
- /* SGMII in Slot2 */
- fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
- break;
- case 0xa6:
- case 0x8e:
- case 0x8f:
- case 0x82:
- case 0x83:
- /* SGMII in Slot3 */
- fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
- /* SGMII in Slot2 */
- fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
- break;
- case 0xa4:
- case 0x96:
- case 0x8a:
- /* SGMII in Slot3 */
- fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
- break;
-#if defined(CONFIG_TARGET_T2080QDS)
- case 0xd9:
- case 0xd3:
- case 0xcb:
- /* SGMII in Slot3 */
- fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
- /* SGMII in Slot2 */
- fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
- break;
-#elif defined(CONFIG_TARGET_T2081QDS)
- case 0xca:
- case 0xcb:
- /* SGMII in Slot3 */
- fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
- /* SGMII in Slot5 */
- fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
- /* SGMII in Slot6 */
- fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
- /* SGMII in Slot7 */
- fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR);
- break;
-#endif
- case 0xf2:
- /* T2080QDS: SGMII in Slot3; T2081QDS: SGMII in Slot7 */
- fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
- break;
- default:
- break;
- }
-
- for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
- idx = i - FM1_DTSEC1;
- interface = fm_info_get_enet_if(i);
- switch (interface) {
- case PHY_INTERFACE_MODE_SGMII:
- lane = serdes_get_first_lane(FSL_SRDS_1,
- SGMII_FM1_DTSEC1 + idx);
- if (lane < 0)
- break;
- slot = lane_to_slot[lane];
- debug("FM1 at DTSEC%u expects SGMII in slot %u\n",
- idx + 1, slot);
- if (QIXIS_READ(present2) & (1 << (slot - 1)))
- fm_disable_port(i);
-
- switch (slot) {
- case 1:
- mdio_mux[i] = EMI1_SLOT1;
- fm_info_set_mdio(i, mii_dev_for_muxval(
- mdio_mux[i]));
- break;
- case 2:
- mdio_mux[i] = EMI1_SLOT2;
- fm_info_set_mdio(i, mii_dev_for_muxval(
- mdio_mux[i]));
- break;
- case 3:
- mdio_mux[i] = EMI1_SLOT3;
- fm_info_set_mdio(i, mii_dev_for_muxval(
- mdio_mux[i]));
- break;
-#if defined(CONFIG_TARGET_T2081QDS)
- case 5:
- mdio_mux[i] = EMI1_SLOT5;
- fm_info_set_mdio(i, mii_dev_for_muxval(
- mdio_mux[i]));
- break;
- case 6:
- mdio_mux[i] = EMI1_SLOT6;
- fm_info_set_mdio(i, mii_dev_for_muxval(
- mdio_mux[i]));
- break;
- case 7:
- mdio_mux[i] = EMI1_SLOT7;
- fm_info_set_mdio(i, mii_dev_for_muxval(
- mdio_mux[i]));
- break;
-#endif
- }
- break;
- case PHY_INTERFACE_MODE_RGMII:
- if (i == FM1_DTSEC3)
- mdio_mux[i] = EMI1_RGMII1;
- else if (i == FM1_DTSEC4 || FM1_DTSEC10)
- mdio_mux[i] = EMI1_RGMII2;
- fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
- break;
- default:
- break;
- }
- }
-
- for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
- idx = i - FM1_10GEC1;
- switch (fm_info_get_enet_if(i)) {
- case PHY_INTERFACE_MODE_XGMII:
- if (srds_s1 == 0x51) {
- lane = serdes_get_first_lane(FSL_SRDS_1,
- XAUI_FM1_MAC9 + idx);
- } else if ((srds_s1 == 0x5f) || (srds_s1 == 0x65)) {
- lane = serdes_get_first_lane(FSL_SRDS_1,
- HIGIG_FM1_MAC9 + idx);
- } else {
- if (i == FM1_10GEC1 || i == FM1_10GEC2)
- lane = serdes_get_first_lane(FSL_SRDS_1,
- XFI_FM1_MAC9 + idx);
- else
- lane = serdes_get_first_lane(FSL_SRDS_1,
- XFI_FM1_MAC1 + idx);
- }
-
- if (lane < 0)
- break;
- mdio_mux[i] = EMI2;
- fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
-
- if ((srds_s1 == 0x66) || (srds_s1 == 0x6b) ||
- (srds_s1 == 0x6a) || (srds_s1 == 0x70) ||
- (srds_s1 == 0x6c) || (srds_s1 == 0x6d) ||
- (srds_s1 == 0x71)) {
- /* As XFI is in cage intead of a slot, so
- * ensure doesn't disable the corresponding port
- */
- break;
- }
-
- slot = lane_to_slot[lane];
- if (QIXIS_READ(present2) & (1 << (slot - 1)))
- fm_disable_port(i);
- break;
- default:
- break;
- }
- }
-
- cpu_eth_init(bis);
-#endif /* CONFIG_FMAN_ENET */
-
- return pci_eth_init(bis);
-}
diff --git a/board/freescale/t208xqds/law.c b/board/freescale/t208xqds/law.c
deleted file mode 100644
index 40fdcf61c0..0000000000
--- a/board/freescale/t208xqds/law.c
+++ /dev/null
@@ -1,33 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008-2012 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-struct law_entry law_table[] = {
- SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
- SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
-#endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
- SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
-#endif
-#ifdef QIXIS_BASE_PHYS
- SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
-#endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
- /* Limit DCSR to 32M to access NPC Trace Buffer */
- SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
-#endif
-#ifdef CONFIG_SYS_NAND_BASE_PHYS
- SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
-#endif
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/t208xqds/pci.c b/board/freescale/t208xqds/pci.c
deleted file mode 100644
index e335592776..0000000000
--- a/board/freescale/t208xqds/pci.c
+++ /dev/null
@@ -1,25 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2007-2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <init.h>
-#include <pci.h>
-#include <asm/fsl_pci.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <asm/fsl_serdes.h>
-
-#if !defined(CONFIG_DM_PCI)
-void pci_init_board(void)
-{
- fsl_pcie_init_board(0);
-}
-
-void pci_of_setup(void *blob, bd_t *bd)
-{
- FT_FSL_PCI_SETUP;
-}
-#endif
diff --git a/board/freescale/t208xqds/spl.c b/board/freescale/t208xqds/spl.c
deleted file mode 100644
index 40eb5d30a6..0000000000
--- a/board/freescale/t208xqds/spl.c
+++ /dev/null
@@ -1,142 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/* Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <clock_legacy.h>
-#include <console.h>
-#include <env_internal.h>
-#include <init.h>
-#include <malloc.h>
-#include <ns16550.h>
-#include <nand.h>
-#include <i2c.h>
-#include <mmc.h>
-#include <fsl_esdhc.h>
-#include <spi_flash.h>
-#include "../common/qixis.h"
-#include "t208xqds_qixis.h"
-#include "../common/spl.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-phys_size_t get_effective_memsize(void)
-{
- return CONFIG_SYS_L3_SIZE;
-}
-
-unsigned long get_board_sys_clk(void)
-{
- u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
-
- switch (sysclk_conf & 0x0F) {
- case QIXIS_SYSCLK_83:
- return 83333333;
- case QIXIS_SYSCLK_100:
- return 100000000;
- case QIXIS_SYSCLK_125:
- return 125000000;
- case QIXIS_SYSCLK_133:
- return 133333333;
- case QIXIS_SYSCLK_150:
- return 150000000;
- case QIXIS_SYSCLK_160:
- return 160000000;
- case QIXIS_SYSCLK_166:
- return 166666666;
- }
- return 66666666;
-}
-
-unsigned long get_board_ddr_clk(void)
-{
- u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
-
- switch ((ddrclk_conf & 0x30) >> 4) {
- case QIXIS_DDRCLK_100:
- return 100000000;
- case QIXIS_DDRCLK_125:
- return 125000000;
- case QIXIS_DDRCLK_133:
- return 133333333;
- }
- return 66666666;
-}
-
-void board_init_f(ulong bootflag)
-{
- u32 plat_ratio, sys_clk, ccb_clk;
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
- /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
- memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
-
- /* Update GD pointer */
- gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
-
- console_init_f();
-
- /* initialize selected port with appropriate baud rate */
- sys_clk = get_board_sys_clk();
- plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
- ccb_clk = sys_clk * plat_ratio / 2;
-
- NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
- ccb_clk / 16 / CONFIG_BAUDRATE);
-
-#if defined(CONFIG_SPL_MMC_BOOT)
- puts("\nSD boot...\n");
-#elif defined(CONFIG_SPL_SPI_BOOT)
- puts("\nSPI boot...\n");
-#elif defined(CONFIG_SPL_NAND_BOOT)
- puts("\nNAND boot...\n");
-#endif
-
- relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
- bd_t *bd;
-
- bd = (bd_t *)(gd + sizeof(gd_t));
- memset(bd, 0, sizeof(bd_t));
- gd->bd = bd;
- bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
- bd->bi_memsize = CONFIG_SYS_L3_SIZE;
-
- arch_cpu_init();
- get_clocks();
- mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
- CONFIG_SPL_RELOC_MALLOC_SIZE);
- gd->flags |= GD_FLG_FULL_MALLOC_INIT;
-
-#ifdef CONFIG_SPL_NAND_BOOT
- nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
- (uchar *)SPL_ENV_ADDR);
-#endif
-#ifdef CONFIG_SPL_MMC_BOOT
- mmc_initialize(bd);
- mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
- (uchar *)SPL_ENV_ADDR);
-#endif
-#ifdef CONFIG_SPL_SPI_BOOT
- fsl_spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
- (uchar *)SPL_ENV_ADDR);
-#endif
-
- gd->env_addr = (ulong)(SPL_ENV_ADDR);
- gd->env_valid = ENV_VALID;
-
- i2c_init_all();
-
- dram_init();
-
-#ifdef CONFIG_SPL_MMC_BOOT
- mmc_boot();
-#elif defined(CONFIG_SPL_SPI_BOOT)
- fsl_spi_boot();
-#elif defined(CONFIG_SPL_NAND_BOOT)
- nand_boot();
-#endif
-}
diff --git a/board/freescale/t208xqds/t2080_nand_rcw.cfg b/board/freescale/t208xqds/t2080_nand_rcw.cfg
deleted file mode 100644
index 52a1652a22..0000000000
--- a/board/freescale/t208xqds/t2080_nand_rcw.cfg
+++ /dev/null
@@ -1,16 +0,0 @@
-#PBL preamble and RCW header
-aa55aa55 010e0100
-
-#For T2080 v1.0
-#SerDes=0x66_0x16, Core=1533MHz, DDR=2133MT/s
-#12100017 15000000 00000000 00000000
-#66150002 00008400 e8104000 c1000000
-#00000000 00000000 00000000 000307fc
-#00000000 00000000 00000000 00000004
-
-#For T2080 v1.1
-#SerDes=0x66_0x15, Core=1800MHz, DDR=1867MT/s
-0c070012 0e000000 00000000 00000000
-66150002 00000000 e8104000 c1000000
-00000000 00000000 00000000 000307fc
-00000000 00000000 00000000 00000004
diff --git a/board/freescale/t208xqds/t2080_sd_rcw.cfg b/board/freescale/t208xqds/t2080_sd_rcw.cfg
deleted file mode 100644
index 73f53faa25..0000000000
--- a/board/freescale/t208xqds/t2080_sd_rcw.cfg
+++ /dev/null
@@ -1,16 +0,0 @@
-#PBL preamble and RCW header
-aa55aa55 010e0100
-
-#For T2080 v1.0
-#SerDes=0x66_0x16, Core=1533MHz, DDR=2133MT/s
-#12100017 15000000 00000000 00000000
-#66150002 00008400 e8104000 c1000000
-#00000000 00000000 00000000 000307fc
-#00000000 00000000 00000000 00000004
-
-#For T2080 v1.1
-#SerDes=0x66_0x15, Core=1800MHz, DDR=1867MT/s
-0c070012 0e000000 00000000 00000000
-66150002 00000000 68104000 c1000000
-00000000 00000000 00000000 000307fc
-00000000 00000000 00000000 00000004
diff --git a/board/freescale/t208xqds/t2080_spi_rcw.cfg b/board/freescale/t208xqds/t2080_spi_rcw.cfg
deleted file mode 100644
index 8474c8ef7c..0000000000
--- a/board/freescale/t208xqds/t2080_spi_rcw.cfg
+++ /dev/null
@@ -1,16 +0,0 @@
-#PBL preamble and RCW header
-aa55aa55 010e0100
-
-#For T2080 v1.0
-#SerDes=0x66_0x16, Core=1533MHz, DDR=2133MT/s
-#12100017 15000000 00000000 00000000
-#66150002 00008400 e8104000 c1000000
-#00000000 00000000 00000000 000307fc
-#00000000 00000000 00000000 00000004
-
-#For T2080 v1.1
-#SerDes=0x66_0x15, Core=1800MHz, DDR=1867MT/s
-0c070012 0e000000 00000000 00000000
-66150002 00000000 58104000 c1000000
-00000000 00000000 00000000 000307fc
-00000000 00000000 00000000 00000004
diff --git a/board/freescale/t208xqds/t2081_nand_rcw.cfg b/board/freescale/t208xqds/t2081_nand_rcw.cfg
deleted file mode 100644
index a2d5ecf4ad..0000000000
--- a/board/freescale/t208xqds/t2081_nand_rcw.cfg
+++ /dev/null
@@ -1,8 +0,0 @@
-#PBL preamble and RCW header
-aa55aa55 010e0100
-#Default SerDes Protocol: 0x6C
-#Core/DDR: 1533Mhz/2133MT/s
-12100017 15000000 00000000 00000000
-6c000002 00008000 e8104000 c1000000
-00000000 00000000 00000000 000307fc
-00000000 00000000 00000000 00000004
diff --git a/board/freescale/t208xqds/t2081_sd_rcw.cfg b/board/freescale/t208xqds/t2081_sd_rcw.cfg
deleted file mode 100644
index daced6796b..0000000000
--- a/board/freescale/t208xqds/t2081_sd_rcw.cfg
+++ /dev/null
@@ -1,8 +0,0 @@
-#PBL preamble and RCW header
-aa55aa55 010e0100
-#Default SerDes Protocol: 0x6C
-#Core/DDR: 1533Mhz/2133MT/s
-12100017 15000000 00000000 00000000
-6c000002 00008000 68104000 c1000000
-00000000 00000000 00000000 000307fc
-00000000 00000000 00000000 00000004
diff --git a/board/freescale/t208xqds/t2081_spi_rcw.cfg b/board/freescale/t208xqds/t2081_spi_rcw.cfg
deleted file mode 100644
index 79ba1f1ab7..0000000000
--- a/board/freescale/t208xqds/t2081_spi_rcw.cfg
+++ /dev/null
@@ -1,8 +0,0 @@
-#PBL preamble and RCW header
-aa55aa55 010e0100
-#Default SerDes Protocol: 0x6C
-#Core/DDR: 1533Mhz/2133MT/s
-12100017 15000000 00000000 00000000
-6c000002 00008000 58104000 c1000000
-00000000 00000000 00000000 000307fc
-00000000 00000000 00000000 00000004
diff --git a/board/freescale/t208xqds/t208x_pbi.cfg b/board/freescale/t208xqds/t208x_pbi.cfg
deleted file mode 100644
index 43be8a864e..0000000000
--- a/board/freescale/t208xqds/t208x_pbi.cfg
+++ /dev/null
@@ -1,40 +0,0 @@
-#
-# Copyright 2013 Freescale Semiconductor, Inc.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Refer doc/README.pblimage for more details about how-to configure
-# and create PBL boot image
-#
-
-#PBI commands
-#Initialize CPC1
-09010000 00200400
-09138000 00000000
-091380c0 00000100
-#512KB SRAM
-09010100 00000000
-09010104 fff80009
-09010f00 08000000
-#enable CPC1
-09010000 80000000
-#Configure LAW for CPC1
-09000d00 00000000
-09000d04 fff80000
-09000d08 81000012
-#Initialize eSPI controller, default configuration is slow for eSPI to
-#load data, this configuration comes from u-boot eSPI driver.
-09110000 80000403
-09110020 2d170008
-09110024 00100008
-09110028 00100008
-0911002c 00100008
-#Errata for slowing down the MDC clock to make it <= 2.5 MHZ
-094fc030 00008148
-094fd030 00008148
-#Configure alternate space
-09000010 00000000
-09000014 ff000000
-09000018 81000000
-#Flush PBL data
-091380c0 00100000
diff --git a/board/freescale/t208xqds/t208xqds.c b/board/freescale/t208xqds/t208xqds.c
deleted file mode 100644
index 4979085e19..0000000000
--- a/board/freescale/t208xqds/t208xqds.c
+++ /dev/null
@@ -1,489 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2009-2013 Freescale Semiconductor, Inc.
- * Copyright 2020 NXP
- */
-
-#include <common.h>
-#include <command.h>
-#include <env.h>
-#include <fdt_support.h>
-#include <i2c.h>
-#include <image.h>
-#include <init.h>
-#include <log.h>
-#include <netdev.h>
-#include <linux/compiler.h>
-#include <asm/mmu.h>
-#include <asm/processor.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_law.h>
-#include <asm/fsl_serdes.h>
-#include <asm/fsl_liodn.h>
-#include <fm_eth.h>
-
-#include "../common/qixis.h"
-#include "../common/vsc3316_3308.h"
-#include "../common/vid.h"
-#include "t208xqds.h"
-#include "t208xqds_qixis.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
- char buf[64];
- u8 sw;
- struct cpu_type *cpu = gd->arch.cpu;
- static const char *freq[4] = {
- "100.00MHZ(from 8T49N222A)", "125.00MHz",
- "156.25MHZ", "100.00MHz"
- };
-
- printf("Board: %sQDS, ", cpu->name);
- sw = QIXIS_READ(arch);
- printf("Sys ID: 0x%02x, Board Arch: V%d, ", QIXIS_READ(id), sw >> 4);
- printf("Board Version: %c, boot from ", (sw & 0xf) + 'A' - 1);
-
-#ifdef CONFIG_SDCARD
- puts("SD/MMC\n");
-#elif CONFIG_SPIFLASH
- puts("SPI\n");
-#else
- sw = QIXIS_READ(brdcfg[0]);
- sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
-
- if (sw < 0x8)
- printf("vBank%d\n", sw);
- else if (sw == 0x8)
- puts("Promjet\n");
- else if (sw == 0x9)
- puts("NAND\n");
- else
- printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
-#endif
-
- printf("FPGA: v%d (%s), build %d", (int)QIXIS_READ(scver),
- qixis_read_tag(buf), (int)qixis_read_minor());
- /* the timestamp string contains "\n"@the end */
- printf(" on %s", qixis_read_time(buf));
-
- puts("SERDES Reference Clocks:\n");
- sw = QIXIS_READ(brdcfg[2]);
- printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[sw >> 6],
- freq[(sw >> 4) & 0x3]);
- printf("SD2_CLK1=%s, SD2_CLK2=%s\n", freq[(sw & 0xf) >> 2],
- freq[sw & 0x3]);
-
- return 0;
-}
-
-int select_i2c_ch_pca9547(u8 ch, int bus_num)
-{
- int ret;
-
-#ifdef CONFIG_DM_I2C
- struct udevice *dev;
-
- ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
- if (ret) {
- printf("%s: Cannot find udev for a bus %d\n", __func__,
- bus_num);
- return ret;
- }
- ret = dm_i2c_write(dev, 0, &ch, 1);
-#else
- ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
-#endif
- if (ret) {
- puts("PCA: failed to select proper channel\n");
- return ret;
- }
-
- return 0;
-}
-
-int i2c_multiplexer_select_vid_channel(u8 channel)
-{
- return select_i2c_ch_pca9547(channel, 0);
-}
-
-int brd_mux_lane_to_slot(void)
-{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- u32 srds_prtcl_s1;
-
- srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
- FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
- srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
-#if defined(CONFIG_TARGET_T2080QDS)
- u32 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
- FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
- srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
-#endif
-
- switch (srds_prtcl_s1) {
- case 0:
- /* SerDes1 is not enabled */
- break;
-#if defined(CONFIG_TARGET_T2080QDS)
- case 0x1b:
- case 0x1c:
- case 0xa2:
- /* SD1(A:D) => SLOT3 SGMII
- * SD1(G:H) => SLOT1 SGMII
- */
- QIXIS_WRITE(brdcfg[12], 0x1a);
- break;
- case 0x94:
- case 0x95:
- /* SD1(A:B) => SLOT3 SGMII at 1.25bps
- * SD1(C:D) => SFP Module, SGMII at 3.125bps
- * SD1(E:H) => SLOT1 SGMII at 1.25bps
- */
- case 0x96:
- /* SD1(A:B) => SLOT3 SGMII at 1.25bps
- * SD1(C) => SFP Module, SGMII at 3.125bps
- * SD1(D) => SFP Module, SGMII at 1.25bps
- * SD1(E:H) => SLOT1 PCIe4 x4
- */
- QIXIS_WRITE(brdcfg[12], 0x3a);
- break;
- case 0x50:
- case 0x51:
- /* SD1(A:D) => SLOT3 XAUI
- * SD1(E) => SLOT1 PCIe4
- * SD1(F:H) => SLOT2 SGMII
- */
- QIXIS_WRITE(brdcfg[12], 0x15);
- break;
- case 0x66:
- case 0x67:
- /* SD1(A:D) => XFI cage
- * SD1(E:H) => SLOT1 PCIe4
- */
- QIXIS_WRITE(brdcfg[12], 0xfe);
- break;
- case 0x6a:
- case 0x6b:
- /* SD1(A:D) => XFI cage
- * SD1(E) => SLOT1 PCIe4
- * SD1(F:H) => SLOT2 SGMII
- */
- QIXIS_WRITE(brdcfg[12], 0xf1);
- break;
- case 0x6c:
- case 0x6d:
- /* SD1(A:B) => XFI cage
- * SD1(C:D) => SLOT3 SGMII
- * SD1(E:H) => SLOT1 PCIe4
- */
- QIXIS_WRITE(brdcfg[12], 0xda);
- break;
- case 0x6e:
- /* SD1(A:B) => SFP Module, XFI
- * SD1(C:D) => SLOT3 SGMII
- * SD1(E:F) => SLOT1 PCIe4 x2
- * SD1(G:H) => SLOT2 SGMII
- */
- QIXIS_WRITE(brdcfg[12], 0xd9);
- break;
- case 0xda:
- /* SD1(A:H) => SLOT3 PCIe3 x8
- */
- QIXIS_WRITE(brdcfg[12], 0x0);
- break;
- case 0xc8:
- /* SD1(A) => SLOT3 PCIe3 x1
- * SD1(B) => SFP Module, SGMII at 1.25bps
- * SD1(C:D) => SFP Module, SGMII at 3.125bps
- * SD1(E:F) => SLOT1 PCIe4 x2
- * SD1(G:H) => SLOT2 SGMII
- */
- QIXIS_WRITE(brdcfg[12], 0x79);
- break;
- case 0xab:
- /* SD1(A:D) => SLOT3 PCIe3 x4
- * SD1(E:H) => SLOT1 PCIe4 x4
- */
- QIXIS_WRITE(brdcfg[12], 0x1a);
- break;
-#elif defined(CONFIG_TARGET_T2081QDS)
- case 0x50:
- case 0x51:
- /* SD1(A:D) => SLOT2 XAUI
- * SD1(E) => SLOT1 PCIe4 x1
- * SD1(F:H) => SLOT3 SGMII
- */
- QIXIS_WRITE(brdcfg[12], 0x98);
- QIXIS_WRITE(brdcfg[13], 0x70);
- break;
- case 0x6a:
- case 0x6b:
- /* SD1(A:D) => XFI SFP Module
- * SD1(E) => SLOT1 PCIe4 x1
- * SD1(F:H) => SLOT3 SGMII
- */
- QIXIS_WRITE(brdcfg[12], 0x80);
- QIXIS_WRITE(brdcfg[13], 0x70);
- break;
- case 0x6c:
- case 0x6d:
- /* SD1(A:B) => XFI SFP Module
- * SD1(C:D) => SLOT2 SGMII
- * SD1(E:H) => SLOT1 PCIe4 x4
- */
- QIXIS_WRITE(brdcfg[12], 0xe8);
- QIXIS_WRITE(brdcfg[13], 0x0);
- break;
- case 0xaa:
- case 0xab:
- /* SD1(A:D) => SLOT2 PCIe3 x4
- * SD1(F:H) => SLOT1 SGMI4 x4
- */
- QIXIS_WRITE(brdcfg[12], 0xf8);
- QIXIS_WRITE(brdcfg[13], 0x0);
- break;
- case 0xca:
- case 0xcb:
- /* SD1(A) => SLOT2 PCIe3 x1
- * SD1(B) => SLOT7 SGMII
- * SD1(C) => SLOT6 SGMII
- * SD1(D) => SLOT5 SGMII
- * SD1(E) => SLOT1 PCIe4 x1
- * SD1(F:H) => SLOT3 SGMII
- */
- QIXIS_WRITE(brdcfg[12], 0x80);
- QIXIS_WRITE(brdcfg[13], 0x70);
- break;
- case 0xde:
- case 0xdf:
- /* SD1(A:D) => SLOT2 PCIe3 x4
- * SD1(E) => SLOT1 PCIe4 x1
- * SD1(F) => SLOT4 PCIe1 x1
- * SD1(G) => SLOT3 PCIe2 x1
- * SD1(H) => SLOT7 SGMII
- */
- QIXIS_WRITE(brdcfg[12], 0x98);
- QIXIS_WRITE(brdcfg[13], 0x25);
- break;
- case 0xf2:
- /* SD1(A) => SLOT2 PCIe3 x1
- * SD1(B:D) => SLOT7 SGMII
- * SD1(E) => SLOT1 PCIe4 x1
- * SD1(F) => SLOT4 PCIe1 x1
- * SD1(G) => SLOT3 PCIe2 x1
- * SD1(H) => SLOT7 SGMII
- */
- QIXIS_WRITE(brdcfg[12], 0x81);
- QIXIS_WRITE(brdcfg[13], 0xa5);
- break;
-#endif
- default:
- printf("WARNING: unsupported for SerDes1 Protocol %d\n",
- srds_prtcl_s1);
- return -1;
- }
-
-#ifdef CONFIG_TARGET_T2080QDS
- switch (srds_prtcl_s2) {
- case 0:
- /* SerDes2 is not enabled */
- break;
- case 0x01:
- case 0x02:
- /* SD2(A:H) => SLOT4 PCIe1 */
- QIXIS_WRITE(brdcfg[13], 0x10);
- break;
- case 0x15:
- case 0x16:
- /*
- * SD2(A:D) => SLOT4 PCIe1
- * SD2(E:F) => SLOT5 PCIe2
- * SD2(G:H) => SATA1,SATA2
- */
- QIXIS_WRITE(brdcfg[13], 0xb0);
- break;
- case 0x18:
- /*
- * SD2(A:D) => SLOT4 PCIe1
- * SD2(E:F) => SLOT5 Aurora
- * SD2(G:H) => SATA1,SATA2
- */
- QIXIS_WRITE(brdcfg[13], 0x78);
- break;
- case 0x1f:
- /*
- * SD2(A:D) => SLOT4 PCIe1
- * SD2(E:H) => SLOT5 PCIe2
- */
- QIXIS_WRITE(brdcfg[13], 0xa0);
- break;
- case 0x29:
- case 0x2d:
- case 0x2e:
- /*
- * SD2(A:D) => SLOT4 SRIO2
- * SD2(E:H) => SLOT5 SRIO1
- */
- QIXIS_WRITE(brdcfg[13], 0xa0);
- break;
- case 0x36:
- /*
- * SD2(A:D) => SLOT4 SRIO2
- * SD2(E:F) => Aurora
- * SD2(G:H) => SATA1,SATA2
- */
- QIXIS_WRITE(brdcfg[13], 0x78);
- break;
- default:
- printf("WARNING: unsupported for SerDes2 Protocol %d\n",
- srds_prtcl_s2);
- return -1;
- }
-#endif
- return 0;
-}
-
-int board_early_init_r(void)
-{
- const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
- int flash_esel = find_tlb_idx((void *)flashbase, 1);
-
- /*
- * Remap Boot flash + PROMJET region to caching-inhibited
- * so that flash can be erased properly.
- */
-
- /* Flush d-cache and invalidate i-cache of any FLASH data */
- flush_dcache();
- invalidate_icache();
-
- if (flash_esel == -1) {
- /* very unlikely unless something is messed up */
- puts("Error: Could not find TLB for FLASH BASE\n");
- flash_esel = 2; /* give our best effort to continue */
- } else {
- /* invalidate existing TLB entry for flash + promjet */
- disable_tlb(flash_esel);
- }
-
- set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, flash_esel, BOOKE_PAGESZ_256M, 1);
-
- /* Disable remote I2C connection to qixis fpga */
- QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE);
-
- /*
- * Adjust core voltage according to voltage ID
- * This function changes I2C mux to channel 2.
- */
- if (adjust_vdd(0))
- printf("Warning: Adjusting core voltage failed.\n");
-
- brd_mux_lane_to_slot();
- select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
-
- return 0;
-}
-
-unsigned long get_board_sys_clk(void)
-{
- u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
-#ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
- /* use accurate clock measurement */
- int freq = QIXIS_READ(clk_freq[0]) << 8 | QIXIS_READ(clk_freq[1]);
- int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
- u32 val;
-
- val = freq * base;
- if (val) {
- debug("SYS Clock measurement is: %d\n", val);
- return val;
- } else {
- printf("Warning: SYS clock measurement is invalid, ");
- printf("using value from brdcfg1.\n");
- }
-#endif
-
- switch (sysclk_conf & 0x0F) {
- case QIXIS_SYSCLK_83:
- return 83333333;
- case QIXIS_SYSCLK_100:
- return 100000000;
- case QIXIS_SYSCLK_125:
- return 125000000;
- case QIXIS_SYSCLK_133:
- return 133333333;
- case QIXIS_SYSCLK_150:
- return 150000000;
- case QIXIS_SYSCLK_160:
- return 160000000;
- case QIXIS_SYSCLK_166:
- return 166666666;
- }
- return 66666666;
-}
-
-unsigned long get_board_ddr_clk(void)
-{
- u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
-#ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
- /* use accurate clock measurement */
- int freq = QIXIS_READ(clk_freq[2]) << 8 | QIXIS_READ(clk_freq[3]);
- int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
- u32 val;
-
- val = freq * base;
- if (val) {
- debug("DDR Clock measurement is: %d\n", val);
- return val;
- } else {
- printf("Warning: DDR clock measurement is invalid, ");
- printf("using value from brdcfg1.\n");
- }
-#endif
-
- switch ((ddrclk_conf & 0x30) >> 4) {
- case QIXIS_DDRCLK_100:
- return 100000000;
- case QIXIS_DDRCLK_125:
- return 125000000;
- case QIXIS_DDRCLK_133:
- return 133333333;
- }
- return 66666666;
-}
-
-int misc_init_r(void)
-{
- return 0;
-}
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
- phys_addr_t base;
- phys_size_t size;
-
- ft_cpu_setup(blob, bd);
-
- base = env_get_bootm_low();
- size = env_get_bootm_size();
-
- fdt_fixup_memory(blob, (u64)base, (u64)size);
-
-#ifdef CONFIG_PCI
- pci_of_setup(blob, bd);
-#endif
-
- fdt_fixup_liodn(blob);
- fsl_fdt_fixup_dr_usb(blob, bd);
-
-#ifdef CONFIG_SYS_DPAA_FMAN
- fdt_fixup_fman_ethernet(blob);
- fdt_fixup_board_enet(blob);
-#endif
-
- return 0;
-}
diff --git a/board/freescale/t208xqds/t208xqds.h b/board/freescale/t208xqds/t208xqds.h
deleted file mode 100644
index 68c758f723..0000000000
--- a/board/freescale/t208xqds/t208xqds.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2011-2013 Freescale Semiconductor, Inc.
- */
-
-#ifndef __CORENET_DS_H__
-#define __CORENET_DS_H__
-
-void fdt_fixup_board_enet(void *blob);
-void pci_of_setup(void *blob, bd_t *bd);
-
-#endif
diff --git a/board/freescale/t208xqds/t208xqds_qixis.h b/board/freescale/t208xqds/t208xqds_qixis.h
deleted file mode 100644
index 0f9a45a6fd..0000000000
--- a/board/freescale/t208xqds/t208xqds_qixis.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#ifndef __T208xQDS_QIXIS_H__
-#define __T208xQDS_QIXIS_H__
-
-/* Definitions of QIXIS Registers for T208xQDS */
-
-#define QIXIS_SRDS1CLK_122 0x5a
-#define QIXIS_SRDS1CLK_125 0x5e
-
-
-/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */
-#define BRDCFG4_EMISEL_MASK 0xE0
-#define BRDCFG4_EMISEL_SHIFT 5
-
-/* SYSCLK */
-#define QIXIS_SYSCLK_66 0x0
-#define QIXIS_SYSCLK_83 0x1
-#define QIXIS_SYSCLK_100 0x2
-#define QIXIS_SYSCLK_125 0x3
-#define QIXIS_SYSCLK_133 0x4
-#define QIXIS_SYSCLK_150 0x5
-#define QIXIS_SYSCLK_160 0x6
-#define QIXIS_SYSCLK_166 0x7
-
-/* DDRCLK */
-#define QIXIS_DDRCLK_66 0x0
-#define QIXIS_DDRCLK_100 0x1
-#define QIXIS_DDRCLK_125 0x2
-#define QIXIS_DDRCLK_133 0x3
-
-#define BRDCFG5_IRE 0x20 /* i2c Remote i2c1 enable */
-
-#define BRDCFG9_SFP_TX_EN 0x10
-
-#define BRDCFG12_SD3EN_MASK 0x20
-#define BRDCFG12_SD3MX_MASK 0x08
-#define BRDCFG12_SD3MX_SLOT5 0x08
-#define BRDCFG12_SD3MX_SLOT6 0x00
-#define BRDCFG12_SD4EN_MASK 0x04
-#define BRDCFG12_SD4MX_MASK 0x03
-#define BRDCFG12_SD4MX_SLOT7 0x02
-#define BRDCFG12_SD4MX_SLOT8 0x01
-#define BRDCFG12_SD4MX_AURO_SATA 0x00
-#endif
diff --git a/board/freescale/t208xqds/tlb.c b/board/freescale/t208xqds/tlb.c
deleted file mode 100644
index 1e501da363..0000000000
--- a/board/freescale/t208xqds/tlb.c
+++ /dev/null
@@ -1,152 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008-2013 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
- /* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
-
- /* TLB 1 */
- /* *I*** - Covers boot page */
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
- /*
- * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
- * SRAM is at 0xfff00000, it covered the 0xfffff000.
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_1M, 1),
-#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
- /*
- * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the
- * space is at 0xfff00000, it covered the 0xfffff000.
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR,
- CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
- 0, 0, BOOKE_PAGESZ_1M, 1),
-#else
- SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_4K, 1),
-#endif
-
- /* *I*G* - CCSRBAR */
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 1, BOOKE_PAGESZ_16M, 1),
-
- /* *I*G* - Flash, localbus */
- /* This will be changed to *I*G* after relocation to RAM. */
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
- MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
- 0, 2, BOOKE_PAGESZ_256M, 1),
-
-#ifndef CONFIG_SPL_BUILD
- /* *I*G* - PCIe 1, 0x80000000 */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 3, BOOKE_PAGESZ_512M, 1),
-
- /* *I*G* - PCIe 2, 0xa0000000 */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_VIRT, CONFIG_SYS_PCIE2_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 4, BOOKE_PAGESZ_256M, 1),
-
- /* *I*G* - PCIe 3, 0xb0000000 */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 5, BOOKE_PAGESZ_256M, 1),
-
-
- /* *I*G* - PCIe 4, 0xc0000000 */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE4_MEM_VIRT, CONFIG_SYS_PCIE4_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 6, BOOKE_PAGESZ_256M, 1),
-
- /* *I*G* - PCI I/O */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 7, BOOKE_PAGESZ_256K, 1),
-
- /* Bman/Qman */
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
- SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 9, BOOKE_PAGESZ_16M, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
- CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 10, BOOKE_PAGESZ_16M, 1),
-#endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
- SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 11, BOOKE_PAGESZ_16M, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
- CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 12, BOOKE_PAGESZ_16M, 1),
-#endif
-#endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
- SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 13, BOOKE_PAGESZ_32M, 1),
-#endif
-#ifdef CONFIG_SYS_NAND_BASE
- /*
- * *I*G - NAND
- * entry 14 and 15 has been used hard coded, they will be disabled
- * in cpu_init_f, so we use entry 16 for nand.
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 16, BOOKE_PAGESZ_64K, 1),
-#endif
-#ifdef QIXIS_BASE_PHYS
- SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 17, BOOKE_PAGESZ_4K, 1),
-#endif
-#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
- /*
- * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for
- * fetching ucode and ENV from master
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR,
- CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
- 0, 18, BOOKE_PAGESZ_1M, 1),
-#endif
-
-#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
- SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
- 0, 19, BOOKE_PAGESZ_2G, 1)
-#endif
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/configs/T2080QDS_NAND_defconfig b/configs/T2080QDS_NAND_defconfig
deleted file mode 100644
index 52255ed120..0000000000
--- a/configs/T2080QDS_NAND_defconfig
+++ /dev/null
@@ -1,83 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x00201000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x140000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T2080QDS=y
-CONFIG_SYS_CUSTOM_LDSCRIPT=y
-CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_NAND_BOOT=y
-CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_AQUANTIA=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_STORAGE=y
diff --git a/configs/T2080QDS_SDCARD_defconfig b/configs/T2080QDS_SDCARD_defconfig
deleted file mode 100644
index ba57ea33b1..0000000000
--- a/configs/T2080QDS_SDCARD_defconfig
+++ /dev/null
@@ -1,80 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x00201000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T2080QDS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_MMC_BOOT=y
-CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_AQUANTIA=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_STORAGE=y
diff --git a/configs/T2080QDS_SECURE_BOOT_defconfig b/configs/T2080QDS_SECURE_BOOT_defconfig
deleted file mode 100644
index 9b3f709c87..0000000000
--- a/configs/T2080QDS_SECURE_BOOT_defconfig
+++ /dev/null
@@ -1,70 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T2080QDS=y
-CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_AQUANTIA=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
diff --git a/configs/T2080QDS_SPIFLASH_defconfig b/configs/T2080QDS_SPIFLASH_defconfig
deleted file mode 100644
index 5aa45f5a89..0000000000
--- a/configs/T2080QDS_SPIFLASH_defconfig
+++ /dev/null
@@ -1,83 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x00201000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T2080QDS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_SPI_BOOT=y
-CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_ADDR=0xFFFC9000
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_AQUANTIA=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_STORAGE=y
diff --git a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
deleted file mode 100644
index 4958435ef4..0000000000
--- a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
+++ /dev/null
@@ -1,60 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T2080QDS=y
-CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_GREPENV=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
-CONFIG_ENV_IS_IN_REMOTE=y
-CONFIG_ENV_ADDR=0xFFE20000
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_AQUANTIA=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_SYS_QE_FMAN_FW_IN_REMOTE=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_STORAGE=y
diff --git a/configs/T2080QDS_defconfig b/configs/T2080QDS_defconfig
deleted file mode 100644
index 602bf577e0..0000000000
--- a/configs/T2080QDS_defconfig
+++ /dev/null
@@ -1,68 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T2080QDS=y
-CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_AQUANTIA=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_STORAGE=y
diff --git a/configs/T2081QDS_NAND_defconfig b/configs/T2081QDS_NAND_defconfig
deleted file mode 100644
index 85381c60ef..0000000000
--- a/configs/T2081QDS_NAND_defconfig
+++ /dev/null
@@ -1,75 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x00201000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x140000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T2081QDS=y
-CONFIG_SYS_CUSTOM_LDSCRIPT=y
-CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_NAND_BOOT=y
-CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_AQUANTIA=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T2081QDS_SDCARD_defconfig b/configs/T2081QDS_SDCARD_defconfig
deleted file mode 100644
index bbc8b7666e..0000000000
--- a/configs/T2081QDS_SDCARD_defconfig
+++ /dev/null
@@ -1,72 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x00201000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T2081QDS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_MMC_BOOT=y
-CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_AQUANTIA=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T2081QDS_SPIFLASH_defconfig b/configs/T2081QDS_SPIFLASH_defconfig
deleted file mode 100644
index b02505be21..0000000000
--- a/configs/T2081QDS_SPIFLASH_defconfig
+++ /dev/null
@@ -1,75 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x00201000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T2081QDS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_SPI_BOOT=y
-CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_ADDR=0xFFFC9000
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_AQUANTIA=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig
deleted file mode 100644
index a10f39b336..0000000000
--- a/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig
+++ /dev/null
@@ -1,51 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T2081QDS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_GREPENV=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_IS_IN_REMOTE=y
-CONFIG_ENV_ADDR=0xFFE20000
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_AQUANTIA=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_REMOTE=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T2081QDS_defconfig b/configs/T2081QDS_defconfig
deleted file mode 100644
index 22ca08363c..0000000000
--- a/configs/T2081QDS_defconfig
+++ /dev/null
@@ -1,59 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T2081QDS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_AQUANTIA=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h
deleted file mode 100644
index c54f7f53e5..0000000000
--- a/include/configs/T208xQDS.h
+++ /dev/null
@@ -1,771 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2011-2013 Freescale Semiconductor, Inc.
- * Copyright 2020 NXP
- */
-
-/*
- * T2080/T2081 QDS board configuration file
- */
-
-#ifndef __T208xQDS_H
-#define __T208xQDS_H
-
-#include <linux/stringify.h>
-
-#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
-#if defined(CONFIG_ARCH_T2080)
-#define CONFIG_FSL_SATA_V2
-#define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */
-#define CONFIG_SRIO1 /* SRIO port 1 */
-#define CONFIG_SRIO2 /* SRIO port 2 */
-#elif defined(CONFIG_ARCH_T2081)
-#endif
-
-/* High Level Configuration Options */
-#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
-#define CONFIG_ENABLE_36BIT_PHYS
-
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_ADDR_MAP 1
-#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
-#endif
-
-#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
-#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
-#define CONFIG_ENV_OVERWRITE
-
-#ifdef CONFIG_RAMBOOT_PBL
-#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xqds/t208x_pbi.cfg
-
-#define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_PAD_TO 0x40000
-#define CONFIG_SPL_MAX_SIZE 0x28000
-#define RESET_VECTOR_OFFSET 0x27FFC
-#define BOOT_PAGE_OFFSET 0x27000
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SPL_SKIP_RELOCATE
-#define CONFIG_SPL_COMMON_INIT_DDR
-#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
-#endif
-
-#ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
-#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
-#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
-#if defined(CONFIG_ARCH_T2080)
-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_nand_rcw.cfg
-#elif defined(CONFIG_ARCH_T2081)
-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_nand_rcw.cfg
-#endif
-#endif
-
-#ifdef CONFIG_SPIFLASH
-#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
-#define CONFIG_SPL_SPI_FLASH_MINIMAL
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_SYS_MPC85XX_NO_RESETVEC
-#endif
-#if defined(CONFIG_ARCH_T2080)
-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_spi_rcw.cfg
-#elif defined(CONFIG_ARCH_T2081)
-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_spi_rcw.cfg
-#endif
-#endif
-
-#ifdef CONFIG_SDCARD
-#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
-#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
-#define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
-#define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
-#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_SYS_MPC85XX_NO_RESETVEC
-#endif
-#if defined(CONFIG_ARCH_T2080)
-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_sd_rcw.cfg
-#elif defined(CONFIG_ARCH_T2081)
-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_sd_rcw.cfg
-#endif
-#endif
-
-#endif /* CONFIG_RAMBOOT_PBL */
-
-#define CONFIG_SRIO_PCIE_BOOT_MASTER
-#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
-/* Set 1M boot space */
-#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
-#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
- (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
-#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
-#endif
-
-#ifndef CONFIG_RESET_VECTOR_ADDRESS
-#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
-#endif
-
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_SYS_CACHE_STASHING
-#define CONFIG_BTB /* toggle branch predition */
-#define CONFIG_DDR_ECC
-#ifdef CONFIG_DDR_ECC
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
-#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
-#endif
-
-#if defined(CONFIG_SPIFLASH)
-#elif defined(CONFIG_SDCARD)
-#define CONFIG_SYS_MMC_ENV_DEV 0
-#endif
-
-#ifndef __ASSEMBLY__
-unsigned long get_board_sys_clk(void);
-unsigned long get_board_ddr_clk(void);
-#endif
-
-#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
-#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
-
-/*
- * Config the L3 Cache as L3 SRAM
- */
-#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
-#define CONFIG_SYS_L3_SIZE (512 << 10)
-#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
-#define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
-#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
-#define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
-#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
-
-#define CONFIG_SYS_DCSRBAR 0xf0000000
-#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
-
-/* EEPROM */
-#define CONFIG_ID_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#define CONFIG_SYS_EEPROM_BUS_NUM 0
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-
-/*
- * DDR Setup
- */
-#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_DIMM_SLOTS_PER_CTLR 2
-#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
-#define CONFIG_DDR_SPD
-#define CONFIG_SYS_SPD_BUS_NUM 0
-#define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
-#define SPD_EEPROM_ADDRESS1 0x51
-#define SPD_EEPROM_ADDRESS2 0x52
-#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
-#define CTRL_INTLV_PREFERED cacheline
-
-/*
- * IFC Definitions
- */
-#define CONFIG_SYS_FLASH_BASE 0xe0000000
-#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
-#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
- + 0x8000000) | \
- CSPR_PORT_SIZE_16 | \
- CSPR_MSEL_NOR | \
- CSPR_V)
-#define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
-#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
- CSPR_PORT_SIZE_16 | \
- CSPR_MSEL_NOR | \
- CSPR_V)
-#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
-/* NOR Flash Timing Params */
-#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
-
-#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
- FTIM0_NOR_TEADC(0x5) | \
- FTIM0_NOR_TEAHC(0x5))
-#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
- FTIM1_NOR_TRAD_NOR(0x1A) |\
- FTIM1_NOR_TSEQRAD_NOR(0x13))
-#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
- FTIM2_NOR_TCH(0x4) | \
- FTIM2_NOR_TWPH(0x0E) | \
- FTIM2_NOR_TWP(0x1c))
-#define CONFIG_SYS_NOR_FTIM3 0x0
-
-#define CONFIG_SYS_FLASH_QUIET_TEST
-#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
- + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
-
-#define CONFIG_FSL_QIXIS /* use common QIXIS code */
-#define QIXIS_BASE 0xffdf0000
-#define QIXIS_LBMAP_SWITCH 6
-#define QIXIS_LBMAP_MASK 0x0f
-#define QIXIS_LBMAP_SHIFT 0
-#define QIXIS_LBMAP_DFLTBANK 0x00
-#define QIXIS_LBMAP_ALTBANK 0x04
-#define QIXIS_LBMAP_NAND 0x09
-#define QIXIS_LBMAP_SD 0x00
-#define QIXIS_RCW_SRC_NAND 0x104
-#define QIXIS_RCW_SRC_SD 0x040
-#define QIXIS_RST_CTL_RESET 0x83
-#define QIXIS_RST_FORCE_MEM 0x1
-#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
-#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
-#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
-#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
-
-#define CONFIG_SYS_CSPR3_EXT (0xf)
-#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
- | CSPR_PORT_SIZE_8 \
- | CSPR_MSEL_GPCM \
- | CSPR_V)
-#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_CSOR3 0x0
-/* QIXIS Timing parameters for IFC CS3 */
-#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
- FTIM0_GPCM_TEADC(0x0e) | \
- FTIM0_GPCM_TEAHC(0x0e))
-#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
- FTIM1_GPCM_TRAD(0x3f))
-#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
- FTIM2_GPCM_TCH(0x8) | \
- FTIM2_GPCM_TWP(0x1f))
-#define CONFIG_SYS_CS3_FTIM3 0x0
-
-/* NAND Flash on IFC */
-#define CONFIG_NAND_FSL_IFC
-#define CONFIG_SYS_NAND_BASE 0xff800000
-#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
-
-#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
-#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
- | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
- | CSPR_MSEL_NAND /* MSEL = NAND */ \
- | CSPR_V)
-#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
-
-#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
- | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
- | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
- | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
- | CSOR_NAND_PGS_2K /* Page Size = 2K */\
- | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\
- | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
-
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-
-/* ONFI NAND Flash mode0 Timing Params */
-#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
- FTIM0_NAND_TWP(0x18) | \
- FTIM0_NAND_TWCHT(0x07) | \
- FTIM0_NAND_TWH(0x0a))
-#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
- FTIM1_NAND_TWBE(0x39) | \
- FTIM1_NAND_TRR(0x0e) | \
- FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
- FTIM2_NAND_TREH(0x0a) | \
- FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3 0x0
-
-#define CONFIG_SYS_NAND_DDR_LAW 11
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
-
-#if defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
-#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
-#else
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
-#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
-#endif
-
-#if defined(CONFIG_RAMBOOT_PBL)
-#define CONFIG_SYS_RAMBOOT
-#endif
-
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
-#else
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-#endif
-
-#define CONFIG_HWCONFIG
-
-/* define to use L1 as initial stack */
-#define CONFIG_L1_INIT_RAM
-#define CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
-/* The assembler doesn't like typecast */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
- ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
- CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
-#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
-
-/*
- * Serial Port
- */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
-#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
-#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
-
-/*
- * I2C
- */
-#ifndef CONFIG_DM_I2C
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
-#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
-#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
-#define CONFIG_SYS_FSL_I2C_SPEED 100000
-#define CONFIG_SYS_FSL_I2C2_SPEED 100000
-#define CONFIG_SYS_FSL_I2C3_SPEED 100000
-#define CONFIG_SYS_FSL_I2C4_SPEED 100000
-#endif
-
-#define CONFIG_SYS_I2C_FSL
-
-#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
-#define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */
-#define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */
-#define I2C_MUX_CH_DEFAULT 0x8
-
-#define I2C_MUX_CH_VOL_MONITOR 0xa
-
-/* Voltage monitor on channel 2*/
-#define I2C_VOL_MONITOR_ADDR 0x40
-#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
-#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
-#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
-
-#define CONFIG_VID_FLS_ENV "t208xqds_vdd_mv"
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_VID
-#endif
-#define CONFIG_VOL_MONITOR_IR36021_SET
-#define CONFIG_VOL_MONITOR_IR36021_READ
-/* The lowest and highest voltage allowed for T208xQDS */
-#define VDD_MV_MIN 819
-#define VDD_MV_MAX 1212
-
-/*
- * RapidIO
- */
-#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
-#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
-#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
-#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
-#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
-/*
- * for slave u-boot IMAGE instored in master memory space,
- * PHYS must be aligned based on the SIZE
- */
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
-/*
- * for slave UCODE and ENV instored in master memory space,
- * PHYS must be aligned based on the SIZE
- */
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
-
-/* slave core release by master*/
-#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
-#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
-
-/*
- * SRIO_PCIE_BOOT - SLAVE
- */
-#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
-#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
-#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
- (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
-#endif
-
-/*
- * eSPI - Enhanced SPI
- */
-
-/*
- * General PCI
- * Memory space is mapped 1-1, but I/O space must start from 0.
- */
-#define CONFIG_PCIE1 /* PCIE controller 1 */
-#define CONFIG_PCIE2 /* PCIE controller 2 */
-#define CONFIG_PCIE3 /* PCIE controller 3 */
-#define CONFIG_PCIE4 /* PCIE controller 4 */
-#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
-/* controller 1, direct to uli, tgtid 3, Base address 20000 */
-#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
-#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
-
-/* controller 2, Slot 2, tgtid 2, Base address 201000 */
-#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
-#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
-#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
-
-/* controller 3, Slot 1, tgtid 1, Base address 202000 */
-#define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull
-#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
-#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
-
-/* controller 4, Base address 203000 */
-#define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000
-#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull
-#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
-
-#ifdef CONFIG_PCI
-#if !defined(CONFIG_DM_PCI)
-#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
-#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
-#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#endif
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#endif
-
-/* Qman/Bman */
-#ifndef CONFIG_NOBQFMAN
-#define CONFIG_SYS_BMAN_NUM_PORTALS 18
-#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
-#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
-#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
-#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
-#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
-#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
-#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
- CONFIG_SYS_BMAN_CENA_SIZE)
-#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
-#define CONFIG_SYS_QMAN_NUM_PORTALS 18
-#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
-#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
-#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
-#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
-#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
-#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
-#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
- CONFIG_SYS_QMAN_CENA_SIZE)
-#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
-
-#define CONFIG_SYS_DPAA_FMAN
-#define CONFIG_SYS_DPAA_PME
-#define CONFIG_SYS_PMAN
-#define CONFIG_SYS_DPAA_DCE
-#define CONFIG_SYS_DPAA_RMAN /* RMan */
-#define CONFIG_SYS_INTERLAKEN
-
-/* Default address of microcode for the Linux Fman driver */
-#if defined(CONFIG_SPIFLASH)
-/*
- * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
- * env, so we got 0x110000.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
-#elif defined(CONFIG_SDCARD)
-/*
- * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
- * about 1MB (2048 blocks), Env is stored after the image, and the env size is
- * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
-#elif defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
-#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
-/*
- * Slave has no ucode locally, it can fetch this from remote. When implementing
- * in two corenet boards, slave's ucode could be stored in master's memory
- * space, the address can be mapped from slave TLB->slave LAW->
- * slave SRIO or PCIE outbound window->master inbound window->
- * master LAW->the ucode address in master's memory space.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
-#else
-#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
-#endif
-#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
-#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
-#endif /* CONFIG_NOBQFMAN */
-
-#ifdef CONFIG_SYS_DPAA_FMAN
-#define RGMII_PHY1_ADDR 0x1
-#define RGMII_PHY2_ADDR 0x2
-#define FM1_10GEC1_PHY_ADDR 0x3
-#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
-#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
-#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
-#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
-#endif
-
-#ifdef CONFIG_FMAN_ENET
-#define CONFIG_ETHPRIME "FM1 at DTSEC3"
-#endif
-
-/*
- * SATA
- */
-#ifdef CONFIG_FSL_SATA_V2
-#define CONFIG_SYS_SATA_MAX_DEVICE 2
-#define CONFIG_SATA1
-#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
-#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
-#define CONFIG_SATA2
-#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
-#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
-#define CONFIG_LBA48
-#endif
-
-/*
- * USB
- */
-#ifdef CONFIG_USB_EHCI_HCD
-#define CONFIG_USB_EHCI_FSL
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_HAS_FSL_DR_USB
-#endif
-
-/*
- * SDHC
- */
-#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
-#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
-#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
-#define CONFIG_FSL_ESDHC_ADAPTER_IDENT
-#endif
-
-/*
- * Dynamic MTD Partition support with mtdparts
- */
-
-/*
- * Environment
- */
-#define CONFIG_LOADS_ECHO /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 64 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
-#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
-#endif
-
-/*
- * Environment Configuration
- */
-#define CONFIG_ROOTPATH "/opt/nfsroot"
-#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
-
-/* default location for tftp and bootm */
-#define CONFIG_LOADADDR 1000000
-#define __USB_PHY_TYPE utmi
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "hwconfig=fsl_ddr:" \
- "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
- "bank_intlv=auto;" \
- "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
- "netdev=eth0\0" \
- "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
- "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
- "tftpflash=tftpboot $loadaddr $uboot && " \
- "protect off $ubootaddr +$filesize && " \
- "erase $ubootaddr +$filesize && " \
- "cp.b $loadaddr $ubootaddr $filesize && " \
- "protect on $ubootaddr +$filesize && " \
- "cmp.b $loadaddr $ubootaddr $filesize\0" \
- "consoledev=ttyS0\0" \
- "ramdiskaddr=2000000\0" \
- "ramdiskfile=t2080qds/ramdisk.uboot\0" \
- "fdtaddr=1e00000\0" \
- "fdtfile=t2080qds/t2080qds.dtb\0" \
- "bdev=sda3\0"
-
-/*
- * For emulation this causes u-boot to jump to the start of the
- * proof point app code automatically
- */
-#define CONFIG_PROOF_POINTS \
- "setenv bootargs root=/dev/$bdev rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "cpu 1 release 0x29000000 - - -;" \
- "cpu 2 release 0x29000000 - - -;" \
- "cpu 3 release 0x29000000 - - -;" \
- "cpu 4 release 0x29000000 - - -;" \
- "cpu 5 release 0x29000000 - - -;" \
- "cpu 6 release 0x29000000 - - -;" \
- "cpu 7 release 0x29000000 - - -;" \
- "go 0x29000000"
-
-#define CONFIG_HVBOOT \
- "setenv bootargs config-addr=0x60000000; " \
- "bootm 0x01000000 - 0x00f00000"
-
-#define CONFIG_ALU \
- "setenv bootargs root=/dev/$bdev rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "cpu 1 release 0x01000000 - - -;" \
- "cpu 2 release 0x01000000 - - -;" \
- "cpu 3 release 0x01000000 - - -;" \
- "cpu 4 release 0x01000000 - - -;" \
- "cpu 5 release 0x01000000 - - -;" \
- "cpu 6 release 0x01000000 - - -;" \
- "cpu 7 release 0x01000000 - - -;" \
- "go 0x01000000"
-
-#define CONFIG_LINUX \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "setenv ramdiskaddr 0x02000000;" \
- "setenv fdtaddr 0x00c00000;" \
- "setenv loadaddr 0x1000000;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_HDBOOT \
- "setenv bootargs root=/dev/$bdev rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND CONFIG_LINUX
-
-#include <asm/fsl_secure_boot.h>
-
-#endif /* __T208xQDS_H */
--
2.25.1
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 17/24] arm: Remove configs/T2080RDB_NAND_defconfig board
2020-05-27 16:46 [PATCH 00/24] spi: dm-conversion (part2) Jagan Teki
` (15 preceding siblings ...)
2020-05-27 16:46 ` [PATCH 16/24] arm: Remove configs/T2080QDS_NAND_defconfig board Jagan Teki
@ 2020-05-27 16:46 ` Jagan Teki
2020-05-28 7:02 ` Priyanka Jain
2020-05-27 16:46 ` [PATCH 18/24] arm: Remove configs/T4160QDS_NAND_defconfig board Jagan Teki
` (5 subsequent siblings)
22 siblings, 1 reply; 59+ messages in thread
From: Jagan Teki @ 2020-05-27 16:46 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_SPI by the deadline.
Remove it.
Patch-cc: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Patch-cc: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
arch/powerpc/cpu/mpc85xx/Kconfig | 1 -
board/freescale/t208xrdb/Kconfig | 14 -
board/freescale/t208xrdb/MAINTAINERS | 15 -
board/freescale/t208xrdb/Makefile | 16 -
board/freescale/t208xrdb/README | 283 --------
board/freescale/t208xrdb/cpld.c | 70 --
board/freescale/t208xrdb/cpld.h | 44 --
board/freescale/t208xrdb/ddr.c | 118 ----
board/freescale/t208xrdb/ddr.h | 46 --
board/freescale/t208xrdb/eth_t208xrdb.c | 107 ---
board/freescale/t208xrdb/law.c | 33 -
board/freescale/t208xrdb/pci.c | 25 -
board/freescale/t208xrdb/spl.c | 112 ---
board/freescale/t208xrdb/t2080_nand_rcw.cfg | 19 -
board/freescale/t208xrdb/t2080_pbi.cfg | 40 --
board/freescale/t208xrdb/t2080_sd_rcw.cfg | 19 -
board/freescale/t208xrdb/t2080_spi_rcw.cfg | 19 -
board/freescale/t208xrdb/t208xrdb.c | 142 ----
board/freescale/t208xrdb/t208xrdb.h | 12 -
board/freescale/t208xrdb/tlb.c | 152 -----
configs/T2080RDB_NAND_defconfig | 84 ---
configs/T2080RDB_SDCARD_defconfig | 81 ---
configs/T2080RDB_SECURE_BOOT_defconfig | 63 --
configs/T2080RDB_SPIFLASH_defconfig | 84 ---
configs/T2080RDB_SRIO_PCIE_BOOT_defconfig | 53 --
configs/T2080RDB_defconfig | 68 --
include/configs/T208xRDB.h | 717 --------------------
27 files changed, 2437 deletions(-)
delete mode 100644 board/freescale/t208xrdb/Kconfig
delete mode 100644 board/freescale/t208xrdb/MAINTAINERS
delete mode 100644 board/freescale/t208xrdb/Makefile
delete mode 100644 board/freescale/t208xrdb/README
delete mode 100644 board/freescale/t208xrdb/cpld.c
delete mode 100644 board/freescale/t208xrdb/cpld.h
delete mode 100644 board/freescale/t208xrdb/ddr.c
delete mode 100644 board/freescale/t208xrdb/ddr.h
delete mode 100644 board/freescale/t208xrdb/eth_t208xrdb.c
delete mode 100644 board/freescale/t208xrdb/law.c
delete mode 100644 board/freescale/t208xrdb/pci.c
delete mode 100644 board/freescale/t208xrdb/spl.c
delete mode 100644 board/freescale/t208xrdb/t2080_nand_rcw.cfg
delete mode 100644 board/freescale/t208xrdb/t2080_pbi.cfg
delete mode 100644 board/freescale/t208xrdb/t2080_sd_rcw.cfg
delete mode 100644 board/freescale/t208xrdb/t2080_spi_rcw.cfg
delete mode 100644 board/freescale/t208xrdb/t208xrdb.c
delete mode 100644 board/freescale/t208xrdb/t208xrdb.h
delete mode 100644 board/freescale/t208xrdb/tlb.c
delete mode 100644 configs/T2080RDB_NAND_defconfig
delete mode 100644 configs/T2080RDB_SDCARD_defconfig
delete mode 100644 configs/T2080RDB_SECURE_BOOT_defconfig
delete mode 100644 configs/T2080RDB_SPIFLASH_defconfig
delete mode 100644 configs/T2080RDB_SRIO_PCIE_BOOT_defconfig
delete mode 100644 configs/T2080RDB_defconfig
delete mode 100644 include/configs/T208xRDB.h
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index edccf3698c..82c5a51f48 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -1599,7 +1599,6 @@ source "board/freescale/mpc8572ds/Kconfig"
source "board/freescale/p1023rdb/Kconfig"
source "board/freescale/p1_twr/Kconfig"
source "board/freescale/qemu-ppce500/Kconfig"
-source "board/freescale/t208xrdb/Kconfig"
source "board/freescale/t4qds/Kconfig"
source "board/freescale/t4rdb/Kconfig"
source "board/gdsys/p1022/Kconfig"
diff --git a/board/freescale/t208xrdb/Kconfig b/board/freescale/t208xrdb/Kconfig
deleted file mode 100644
index 6f0b012bab..0000000000
--- a/board/freescale/t208xrdb/Kconfig
+++ /dev/null
@@ -1,14 +0,0 @@
-if TARGET_T2080RDB
-
-config SYS_BOARD
- default "t208xrdb"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "T208xRDB"
-
-source "board/freescale/common/Kconfig"
-
-endif
diff --git a/board/freescale/t208xrdb/MAINTAINERS b/board/freescale/t208xrdb/MAINTAINERS
deleted file mode 100644
index f894f77b73..0000000000
--- a/board/freescale/t208xrdb/MAINTAINERS
+++ /dev/null
@@ -1,15 +0,0 @@
-T208XRDB BOARD
-M: Shengzhou Liu <Shengzhou.Liu@nxp.com>
-S: Maintained
-F: board/freescale/t208xrdb/
-F: include/configs/T208xRDB.h
-F: configs/T2080RDB_defconfig
-F: configs/T2080RDB_NAND_defconfig
-F: configs/T2080RDB_SDCARD_defconfig
-F: configs/T2080RDB_SPIFLASH_defconfig
-F: configs/T2080RDB_SRIO_PCIE_BOOT_defconfig
-
-T2080RDB_SECURE_BOOT BOARD
-M: Ruchika Gupta <ruchika.gupta@nxp.com>
-S: Maintained
-F: configs/T2080RDB_SECURE_BOOT_defconfig
diff --git a/board/freescale/t208xrdb/Makefile b/board/freescale/t208xrdb/Makefile
deleted file mode 100644
index 25ea66a024..0000000000
--- a/board/freescale/t208xrdb/Makefile
+++ /dev/null
@@ -1,16 +0,0 @@
-#
-# Copyright 2014 Freescale Semiconductor, Inc.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-ifdef CONFIG_SPL_BUILD
-obj-y += spl.o
-else
-obj-$(CONFIG_TARGET_T2080RDB) += t208xrdb.o eth_t208xrdb.o cpld.o
-obj-$(CONFIG_PCI) += pci.o
-endif
-
-obj-y += ddr.o
-obj-y += law.o
-obj-y += tlb.o
diff --git a/board/freescale/t208xrdb/README b/board/freescale/t208xrdb/README
deleted file mode 100644
index 9e4b28faf4..0000000000
--- a/board/freescale/t208xrdb/README
+++ /dev/null
@@ -1,283 +0,0 @@
-T2080PCIe-RDB is a Freescale Reference Design Board that hosts the T2080 SoC.
-It can work in two mode: standalone mode and PCIe endpoint mode.
-
-T2080 SoC Overview
-------------------
-The T2080 QorIQ multicore processor combines four dual-threaded e6500 Power
-Architecture processor cores with high-performance datapath acceleration
-logic and network and peripheral bus interfaces required for networking,
-telecom/datacom, wireless infrastructure, and mil/aerospace applications.
-
-T2080 includes the following functions and features:
- - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz
- - 2MB L2 cache and 512KB CoreNet platform cache (CPC)
- - Hierarchical interconnect fabric
- - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
- - Data Path Acceleration Architecture (DPAA) incorporating acceleration
- - 16 SerDes lanes up to 10.3125 GHz
- - 8 Ethernet interfaces, supporting combinations of the following:
- - Up to four 10 Gbps Ethernet MACs
- - Up to eight 1 Gbps Ethernet MACs
- - Up to four 2.5 Gbps Ethernet MACs
- - High-speed peripheral interfaces
- - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
- - Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz
- - Additional peripheral interfaces
- - Two serial ATA (SATA 2.0) controllers
- - Two high-speed USB 2.0 controllers with integrated PHY
- - Enhanced secure digital host controller (SD/SDHC/SDXC/eMMC)
- - Enhanced serial peripheral interface (eSPI)
- - Four I2C controllers
- - Four 2-pin UARTs or two 4-pin UARTs
- - Integrated Flash Controller supporting NAND and NOR flash
- - Three eight-channel DMA engines
- - Support for hardware virtualization and partitioning enforcement
- - QorIQ Platform's Trust Architecture 2.0
-
-Differences between T2080 and T2081
------------------------------------
- Feature T2080 T2081
- 1G Ethernet numbers: 8 6
- 10G Ethernet numbers: 4 2
- SerDes lanes: 16 8
- Serial RapidIO,RMan: 2 no
- SATA Controller: 2 no
- Aurora: yes no
- SoC Package: 896-pins 780-pins
-
-
-T2080PCIe-RDB board Overview
-----------------------------
- - SERDES Configuration
- - SerDes-1 Lane A-B: to two 10G XFI fiber (MAC9 & MAC10)
- - SerDes-1 Lane C-D: to two 10G Base-T (MAC1 & MAC2)
- - SerDes-1 Lane E-H: to PCIe Goldfinger (PCIe4 x4, Gen3)
- - SerDes-2 Lane A-D: to PCIe Slot (PCIe1 x4, Gen2)
- - SerDes-2 Lane E-F: to C293 secure co-processor (PCIe2 x2)
- - SerDes-2 Lane G-H: to SATA1 & SATA2
- - Ethernet
- - Two on-board 10M/100M/1G RGMII ethernet ports
- - Two on-board 10Gbps XFI fiber ports
- - Two on-board 10Gbps Base-T copper ports
- - DDR Memory
- - Supports 72bit 4GB DDR3-LP SODIMM
- - PCIe
- - One PCIe x4 gold-finger
- - One PCIe x4 connector
- - One PCIe x2 end-point device (C293 Crypto co-processor)
- - IFC/Local Bus
- - NOR: 128MB 16-bit NOR Flash
- - NAND: 1GB 8-bit NAND flash
- - CPLD: for system controlling with programable header on-board
- - SATA
- - Two SATA 2.0 onnectors on-board
- - USB
- - Supports two USB 2.0 ports with integrated PHYs
- - Two type A ports with 5V at 1.5A per port.
- - SDHC
- - one TF-card connector on-board
- - SPI
- - On-board 64MB SPI flash
- - Other
- - Two Serial ports
- - Four I2C ports
-
-
-System Memory map
------------------
-Start Address End Address Description Size
-0xF_FFDF_0000 0xF_FFDF_0FFF IFC - CPLD 4KB
-0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB
-0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB
-0xF_F803_0000 0xF_F803_FFFF PCI Express 4 I/O Space 64KB
-0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB
-0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB
-0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB
-0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB
-0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB
-0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB
-0xF_0000_0000 0xF_003F_FFFF DCSR 4MB
-0xC_4000_0000 0xC_4FFF_FFFF PCI Express 4 Mem Space 256MB
-0xC_3000_0000 0xC_3FFF_FFFF PCI Express 3 Mem Space 256MB
-0xC_2000_0000 0xC_2FFF_FFFF PCI Express 2 Mem Space 256MB
-0xC_0000_0000 0xC_1FFF_FFFF PCI Express 1 Mem Space 512MB
-0x0_0000_0000 0x0_ffff_ffff DDR 4GB
-
-
-128M NOR Flash memory Map
--------------------------
-Start Address End Address Definition Max size
-0xEFF40000 0xEFFFFFFF U-Boot (current bank) 768KB
-0xEFF20000 0xEFF3FFFF U-Boot env (current bank) 128KB
-0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB
-0xEFE00000 0xEFE3FFFF PHY CS4315 firmware 256KB
-0xED300000 0xEFEFFFFF rootfs (alt bank) 44MB
-0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB
-0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB
-0xEC000000 0xEC01FFFF RCW (alt bank) 128KB
-0xEBF40000 0xEBFFFFFF U-Boot (alt bank) 768KB
-0xEBF20000 0xEBF3FFFF U-Boot env (alt bank) 128KB
-0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB
-0xEBE00000 0xEBE3FFFF PHY CS4315 firmware (alt bank) 256KB
-0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB
-0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 1MB
-0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB
-0xE8000000 0xE801FFFF RCW (current bank) 128KB
-
-
-T2080PCIe-RDB Ethernet Port Map
--------------------------------
-Label In Uboot In Linux FMan Address Comments PHY
-ETH0 FM1 at GTEC1 fm1-mac9 0xfe4f0000 10G SFP+ (CS4315)
-ETH1 FM1 at GTEC2 fm1-mac10 0xfe4f2000 10G SFP+ (CS4315)
-ETH2 FM1 at GTEC3 fm1-mac1 0xfe4e0000 10G Base-T (AQ1202)
-ETH3 FM1 at GTEC4 fm1-mac2 0xfe4e2000 10G Base-T (AQ1202)
-ETH4 FM1 at DTSEC3 fm1-mac3 0xfe4e4000 1G RGMII (RTL8211E)
-ETH5 FM1 at DTSEC4 fm1-mac4 0xfe4e6000 1G RGMII (RTL8211E)
-
-
-T2080PCIe-RDB Default DIP-Switch setting
-----------------------------------------
-SW1[1:8] = '00010011'
-SW2[1:8] = '10111111'
-SW3[1:8] = '11100001'
-
-Software configurations and board settings
-------------------------------------------
-1. NOR boot:
- a. build NOR boot image
- $ make T2080RDB_config
- $ make
- b. program u-boot.bin image to NOR flash
- => tftp 1000000 u-boot.bin
- => pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize
- set SW1[1:8] = '00010011', SW2[1] = '1', SW3[4] = '0' for NOR boot
-
- Switching between default bank and alternate bank on NOR flash
- To change boot source to vbank4:
- via software: run command 'cpld reset altbank' in U-Boot.
- via DIP-switch: set SW3[5:7] = '100'
-
- To change boot source to vbank0:
- via software: run command 'cpld reset' in U-Boot.
- via DIP-Switch: set SW3[5:7] = '000'
-
-2. NAND Boot:
- a. build PBL image for NAND boot
- $ make T2080RDB_NAND_config
- $ make
- b. program u-boot-with-spl-pbl.bin to NAND flash
- => tftp 1000000 u-boot-with-spl-pbl.bin
- => nand erase 0 d0000
- => nand write 1000000 0 $filesize
- set SW1[1:8] = '10000010', SW2[1] = '1', SW3[4] = '1' for NAND boot
-
-3. SPI Boot:
- a. build PBL image for SPI boot
- $ make T2080RDB_SPIFLASH_config
- $ make
- b. program u-boot-with-spl-pbl.bin to SPI flash
- => tftp 1000000 u-boot-with-spl-pbl.bin
- => sf probe 0
- => sf erase 0 d0000
- => sf write 1000000 0 $filesize
- set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot
-
-4. SD Boot:
- a. build PBL image for SD boot
- $ make T2080RDB_SDCARD_config
- $ make
- b. program u-boot-with-spl-pbl.bin to micro-SD/TF card
- => tftp 1000000 u-boot-with-spl-pbl.bin
- => mmc write 1000000 8 0x800
- set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot
-
-
-2-stage NAND/SPI/SD boot loader
--------------------------------
-PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM.
-SPL further initializes DDR using SPD and environment variables
-and copy U-Boot(768 KB) from NAND/SPI/SD device to DDR.
-Finally SPL transers control to U-Boot for futher booting.
-
-SPL has following features:
- - Executes within 256K
- - No relocation required
-
-Run time view of SPL framework
--------------------------------------------------
-|Area | Address |
--------------------------------------------------
-|SecureBoot header | 0xFFFC0000 (32KB) |
--------------------------------------------------
-|GD, BD | 0xFFFC8000 (4KB) |
--------------------------------------------------
-|ENV | 0xFFFC9000 (8KB) |
--------------------------------------------------
-|HEAP | 0xFFFCB000 (50KB) |
--------------------------------------------------
-|STACK | 0xFFFD8000 (22KB) |
--------------------------------------------------
-|U-Boot SPL | 0xFFFD8000 (160KB) |
--------------------------------------------------
-
-NAND Flash memory Map on T2080RDB
---------------------------------------------------------------
-Start End Definition Size
-0x000000 0x0FFFFF U-Boot img 1MB (2 blocks)
-0x100000 0x17FFFF U-Boot env 512KB (1 block)
-0x180000 0x1FFFFF FMAN ucode 512KB (1 block)
-0x200000 0x27FFFF CS4315 ucode 512KB (1 block)
-
-
-Micro SD Card memory Map on T2080RDB
-----------------------------------------------------
-Block #blocks Definition Size
-0x008 2048 U-Boot img 1MB
-0x800 0016 U-Boot env 8KB
-0x820 0128 FMAN ucode 64KB
-0x8a0 0512 CS4315 ucode 256KB
-
-
-SPI Flash memory Map on T2080RDB
-----------------------------------------------------
-Start End Definition Size
-0x000000 0x0FFFFF U-Boot img 1MB
-0x100000 0x101FFF U-Boot env 8KB
-0x110000 0x11FFFF FMAN ucode 64KB
-0x120000 0x15FFFF CS4315 ucode 256KB
-
-
-How to update the ucode of Cortina CS4315/CS4340 10G PHY
---------------------------------------------------------
-=> tftp 1000000 CS4315-CS4340-PHY-ucode.txt
-=> pro off all;era 0xefe00000 0xefefffff;cp.b 1000000 0xefe00000 $filesize
-
-
-How to update the ucode of Freescale FMAN
------------------------------------------
-=> tftp 1000000 fsl_fman_ucode_t2080_r1.0.bin
-=> pro off all;erase 0xeff00000 0xeff1ffff;cp 1000000 0xeff00000 $filesize
-
-
-For more details, please refer to T2080PCIe-RDB User Guide and access
-website www.freescale.com and Freescale QorIQ SDK Infocenter document.
-
-Device tree support and how to enable it for different configs
---------------------------------------------------------------
-Device tree support is available for t2080rdb for below mentioned boot,
-1. NOR Boot
-2. NAND Boot
-3. SD Boot
-4. SPIFLASH Boot
-
-To enable device tree support for other boot, below configs need to be
-enabled in relative defconfig file,
-1. CONFIG_DEFAULT_DEVICE_TREE="t2080rdb" (Change default device tree name if required)
-2. CONFIG_OF_CONTROL
-3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at
- CONFIG_RESET_VECTOR_ADDRESS - 0xffc
-
-If device tree support is enabled in defconfig,
-1. use 'u-boot-with-dtb.bin' for NOR boot.
-2. use 'u-boot-with-spl-pbl.bin' for other boot.
diff --git a/board/freescale/t208xrdb/cpld.c b/board/freescale/t208xrdb/cpld.c
deleted file mode 100644
index b9ba62adff..0000000000
--- a/board/freescale/t208xrdb/cpld.c
+++ /dev/null
@@ -1,70 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2014 Freescale Semiconductor
- *
- * Freescale T2080RDB board-specific CPLD controlling supports.
- */
-
-#include <common.h>
-#include <command.h>
-#include "cpld.h"
-
-u8 cpld_read(unsigned int reg)
-{
- void *p = (void *)CONFIG_SYS_CPLD_BASE;
-
- return in_8(p + reg);
-}
-
-void cpld_write(unsigned int reg, u8 value)
-{
- void *p = (void *)CONFIG_SYS_CPLD_BASE;
-
- out_8(p + reg, value);
-}
-
-/* Set the boot bank to the alternate bank */
-void cpld_set_altbank(void)
-{
- u8 reg = CPLD_READ(flash_csr);
-
- reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_ALTBANK;
- CPLD_WRITE(flash_csr, reg);
- CPLD_WRITE(reset_ctl, CPLD_LBMAP_RESET);
-}
-
-/* Set the boot bank to the default bank */
-void cpld_set_defbank(void)
-{
- u8 reg = CPLD_READ(flash_csr);
-
- reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_DFLTBANK;
- CPLD_WRITE(flash_csr, reg);
- CPLD_WRITE(reset_ctl, CPLD_LBMAP_RESET);
-}
-
-int do_cpld(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
-{
- int rc = 0;
-
- if (argc <= 1)
- return cmd_usage(cmdtp);
-
- if (strcmp(argv[1], "reset") == 0) {
- if (strcmp(argv[2], "altbank") == 0)
- cpld_set_altbank();
- else
- cpld_set_defbank();
- } else {
- rc = cmd_usage(cmdtp);
- }
-
- return rc;
-}
-
-U_BOOT_CMD(
- cpld, CONFIG_SYS_MAXARGS, 1, do_cpld,
- "Reset the board or alternate bank",
- "reset: reset to default bank\n"
- "cpld reset altbank: reset to alternate bank\n"
-);
diff --git a/board/freescale/t208xrdb/cpld.h b/board/freescale/t208xrdb/cpld.h
deleted file mode 100644
index bd6c203742..0000000000
--- a/board/freescale/t208xrdb/cpld.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2014 Freescale Semiconductor
- */
-
-/*
- * CPLD register set of T2080RDB board-specific.
- */
-struct cpld_data {
- u8 chip_id1; /* 0x00 - Chip ID1 register */
- u8 chip_id2; /* 0x01 - Chip ID2 register */
- u8 hw_ver; /* 0x02 - Hardware Revision Register */
- u8 sw_ver; /* 0x03 - Software Revision register */
- u8 res0[12]; /* 0x04 - 0x0F - not used */
- u8 reset_ctl; /* 0x10 - Reset control Register */
- u8 flash_csr; /* 0x11 - Flash control and status register */
- u8 thermal_csr; /* 0x12 - Thermal control and status register */
- u8 led_csr; /* 0x13 - LED control and status register */
- u8 sfp_csr; /* 0x14 - SFP+ control and status register */
- u8 misc_csr; /* 0x15 - Misc control and status register */
- u8 boot_or; /* 0x16 - Boot config override register */
- u8 boot_cfg1; /* 0x17 - Boot configuration register 1 */
- u8 boot_cfg2; /* 0x18 - Boot configuration register 2 */
-} cpld_data_t;
-
-u8 cpld_read(unsigned int reg);
-void cpld_write(unsigned int reg, u8 value);
-
-#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg))
-#define CPLD_WRITE(reg, value) \
- cpld_write(offsetof(struct cpld_data, reg), value)
-
-/* CPLD on IFC */
-#define CPLD_LBMAP_MASK 0x3F
-#define CPLD_BANK_SEL_MASK 0x07
-#define CPLD_BANK_OVERRIDE 0x40
-#define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */
-#define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK 0 */
-#define CPLD_LBMAP_RESET 0xFF
-#define CPLD_LBMAP_SHIFT 0x03
-#define CPLD_BOOT_SEL 0x80
-
-/* RSTCON Register */
-#define CPLD_RSTCON_EDC_RST 0x04
diff --git a/board/freescale/t208xrdb/ddr.c b/board/freescale/t208xrdb/ddr.c
deleted file mode 100644
index 6a09d1cd22..0000000000
--- a/board/freescale/t208xrdb/ddr.c
+++ /dev/null
@@ -1,118 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <hwconfig.h>
-#include <init.h>
-#include <log.h>
-#include <asm/mmu.h>
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-#include <asm/fsl_law.h>
-#include "ddr.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
- ulong ddr_freq;
-
- if (ctrl_num > 1) {
- printf("Not supported controller number %d\n", ctrl_num);
- return;
- }
- if (!pdimm->n_ranks)
- return;
-
- pbsp = udimms[0];
-
- /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
- * freqency and n_banks specified in board_specific_parameters table.
- */
- ddr_freq = get_ddr_freq(0) / 1000000;
- while (pbsp->datarate_mhz_high) {
- if (pbsp->n_ranks == pdimm->n_ranks &&
- (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
- if (ddr_freq <= pbsp->datarate_mhz_high) {
- popts->clk_adjust = pbsp->clk_adjust;
- popts->wrlvl_start = pbsp->wrlvl_start;
- popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
- popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
- goto found;
- }
- pbsp_highest = pbsp;
- }
- pbsp++;
- }
-
- if (pbsp_highest) {
- printf("Error: board specific timing not found");
- printf("for data rate %lu MT/s\n", ddr_freq);
- printf("Trying to use the highest speed (%u) parameters\n",
- pbsp_highest->datarate_mhz_high);
- popts->clk_adjust = pbsp_highest->clk_adjust;
- popts->wrlvl_start = pbsp_highest->wrlvl_start;
- popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
- popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
- } else {
- panic("DIMM is not supported by this board");
- }
-found:
- debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
- "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
- "wrlvl_ctrl_3 0x%x\n",
- pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
- pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
- pbsp->wrlvl_ctl_3);
-
- /*
- * Factors to consider for half-strength driver enable:
- * - number of DIMMs installed
- */
- popts->half_strength_driver_enable = 0;
- /*
- * Write leveling override
- */
- popts->wrlvl_override = 1;
- popts->wrlvl_sample = 0xf;
-
- /*
- * Rtt and Rtt_WR override
- */
- popts->rtt_override = 0;
-
- /* Enable ZQ calibration */
- popts->zq_en = 1;
-
- /* DHC_EN =1, ODT = 75 Ohm */
- popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
- popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
-
- /* optimize cpo for erratum A-009942 */
- popts->cpo_sample = 0x54;
-}
-
-int dram_init(void)
-{
- phys_size_t dram_size;
-
-#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
- puts("Initializing....using SPD\n");
- dram_size = fsl_ddr_sdram();
-#else
- /* DDR has been initialised by first stage boot loader */
- dram_size = fsl_ddr_sdram_size();
-#endif
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
-
- gd->ram_size = dram_size;
-
- return 0;
-}
diff --git a/board/freescale/t208xrdb/ddr.h b/board/freescale/t208xrdb/ddr.h
deleted file mode 100644
index c00f178166..0000000000
--- a/board/freescale/t208xrdb/ddr.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- */
-
-#ifndef __DDR_H__
-#define __DDR_H__
-struct board_specific_parameters {
- u32 n_ranks;
- u32 datarate_mhz_high;
- u32 rank_gb;
- u32 clk_adjust;
- u32 wrlvl_start;
- u32 wrlvl_ctl_2;
- u32 wrlvl_ctl_3;
-};
-
-/*
- * These tables contain all valid speeds we want to override with board
- * specific parameters. datarate_mhz_high values need to be in ascending order
- * for each n_ranks group.
- */
-
-static const struct board_specific_parameters udimm0[] = {
- /*
- * memory controller 0
- * num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
- * ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
- */
- {2, 1200, 2, 10, 7, 0x0808090a, 0x0b0c0c0a},
- {2, 1500, 2, 10, 6, 0x07070809, 0x0a0b0b09},
- {2, 1600, 2, 10, 8, 0x0808070b, 0x0c0d0e0a},
- {2, 1700, 2, 8, 7, 0x080a0a0c, 0x0c0d0e0a},
- {2, 1900, 0, 10, 7, 0x0808080c, 0x0b0c0c09},
- {1, 1200, 2, 10, 7, 0x0808090a, 0x0b0c0c0a},
- {1, 1500, 2, 10, 6, 0x07070809, 0x0a0b0b09},
- {1, 1600, 2, 10, 8, 0x0808070b, 0x0c0d0e0a},
- {1, 1700, 2, 8, 7, 0x080a0a0c, 0x0c0d0e0a},
- {1, 1900, 0, 10, 7, 0x0808080c, 0x0b0c0c09},
- {}
-};
-
-static const struct board_specific_parameters *udimms[] = {
- udimm0,
-};
-#endif
diff --git a/board/freescale/t208xrdb/eth_t208xrdb.c b/board/freescale/t208xrdb/eth_t208xrdb.c
deleted file mode 100644
index db4718128d..0000000000
--- a/board/freescale/t208xrdb/eth_t208xrdb.c
+++ /dev/null
@@ -1,107 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- *
- * Shengzhou Liu <Shengzhou.Liu@freescale.com>
- */
-
-#include <common.h>
-#include <command.h>
-#include <fdt_support.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/mmu.h>
-#include <asm/processor.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_law.h>
-#include <asm/fsl_serdes.h>
-#include <asm/fsl_portals.h>
-#include <asm/fsl_liodn.h>
-#include <malloc.h>
-#include <fm_eth.h>
-#include <fsl_mdio.h>
-#include <miiphy.h>
-#include <phy.h>
-#include <fsl_dtsec.h>
-#include <asm/fsl_serdes.h>
-
-int board_eth_init(bd_t *bis)
-{
-#if defined(CONFIG_FMAN_ENET)
- int i, interface;
- struct memac_mdio_info dtsec_mdio_info;
- struct memac_mdio_info tgec_mdio_info;
- struct mii_dev *dev;
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- u32 srds_s1;
-
- srds_s1 = in_be32(&gur->rcwsr[4]) &
- FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
- srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
-
- dtsec_mdio_info.regs =
- (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
-
- dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
-
- /* Register the 1G MDIO bus */
- fm_memac_mdio_init(bis, &dtsec_mdio_info);
-
- tgec_mdio_info.regs =
- (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
- tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
-
- /* Register the 10G MDIO bus */
- fm_memac_mdio_init(bis, &tgec_mdio_info);
-
- /* Set the two on-board RGMII PHY address */
- fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
- fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
-
- switch (srds_s1) {
- case 0x66:
- case 0x6b:
- fm_info_set_phy_address(FM1_10GEC1, CORTINA_PHY_ADDR1);
- fm_info_set_phy_address(FM1_10GEC2, CORTINA_PHY_ADDR2);
- fm_info_set_phy_address(FM1_10GEC3, FM1_10GEC3_PHY_ADDR);
- fm_info_set_phy_address(FM1_10GEC4, FM1_10GEC4_PHY_ADDR);
- break;
- default:
- printf("SerDes1 protocol 0x%x is not supported on T208xRDB\n",
- srds_s1);
- break;
- }
-
- for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
- interface = fm_info_get_enet_if(i);
- switch (interface) {
- case PHY_INTERFACE_MODE_RGMII:
- dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
- fm_info_set_mdio(i, dev);
- break;
- default:
- break;
- }
- }
-
- for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
- switch (fm_info_get_enet_if(i)) {
- case PHY_INTERFACE_MODE_XGMII:
- dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
- fm_info_set_mdio(i, dev);
- break;
- default:
- break;
- }
- }
-
- cpu_eth_init(bis);
-#endif /* CONFIG_FMAN_ENET */
-
- return pci_eth_init(bis);
-}
-
-void fdt_fixup_board_enet(void *fdt)
-{
- return;
-}
diff --git a/board/freescale/t208xrdb/law.c b/board/freescale/t208xrdb/law.c
deleted file mode 100644
index d3b263f59d..0000000000
--- a/board/freescale/t208xrdb/law.c
+++ /dev/null
@@ -1,33 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008-2014 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-struct law_entry law_table[] = {
- SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
- SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
-#endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
- SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
-#endif
-#ifdef CONFIG_SYS_CPLD_BASE_PHYS
- SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
-#endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
- /* Limit DCSR to 32M to access NPC Trace Buffer */
- SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
-#endif
-#ifdef CONFIG_SYS_NAND_BASE_PHYS
- SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
-#endif
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/t208xrdb/pci.c b/board/freescale/t208xrdb/pci.c
deleted file mode 100644
index bd0e29744c..0000000000
--- a/board/freescale/t208xrdb/pci.c
+++ /dev/null
@@ -1,25 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2007-2014 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <init.h>
-#include <pci.h>
-#include <asm/fsl_pci.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <asm/fsl_serdes.h>
-
-#if !defined(CONFIG_DM_PCI)
-void pci_init_board(void)
-{
- fsl_pcie_init_board(0);
-}
-
-void pci_of_setup(void *blob, bd_t *bd)
-{
- FT_FSL_PCI_SETUP;
-}
-#endif
diff --git a/board/freescale/t208xrdb/spl.c b/board/freescale/t208xrdb/spl.c
deleted file mode 100644
index 27e87da409..0000000000
--- a/board/freescale/t208xrdb/spl.c
+++ /dev/null
@@ -1,112 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/* Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <clock_legacy.h>
-#include <console.h>
-#include <env_internal.h>
-#include <init.h>
-#include <malloc.h>
-#include <ns16550.h>
-#include <nand.h>
-#include <i2c.h>
-#include <mmc.h>
-#include <fsl_esdhc.h>
-#include <spi_flash.h>
-#include "../common/spl.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-phys_size_t get_effective_memsize(void)
-{
- return CONFIG_SYS_L3_SIZE;
-}
-
-unsigned long get_board_sys_clk(void)
-{
- return CONFIG_SYS_CLK_FREQ;
-}
-
-unsigned long get_board_ddr_clk(void)
-{
- return CONFIG_DDR_CLK_FREQ;
-}
-
-void board_init_f(ulong bootflag)
-{
- u32 plat_ratio, sys_clk, ccb_clk;
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
- /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
- memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
-
- /* Update GD pointer */
- gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
-
- console_init_f();
-
- /* initialize selected port with appropriate baud rate */
- sys_clk = get_board_sys_clk();
- plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
- ccb_clk = sys_clk * plat_ratio / 2;
-
- NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
- ccb_clk / 16 / CONFIG_BAUDRATE);
-
-#if defined(CONFIG_SPL_MMC_BOOT)
- puts("\nSD boot...\n");
-#elif defined(CONFIG_SPL_SPI_BOOT)
- puts("\nSPI boot...\n");
-#elif defined(CONFIG_SPL_NAND_BOOT)
- puts("\nNAND boot...\n");
-#endif
-
- relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
- bd_t *bd;
-
- bd = (bd_t *)(gd + sizeof(gd_t));
- memset(bd, 0, sizeof(bd_t));
- gd->bd = bd;
- bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
- bd->bi_memsize = CONFIG_SYS_L3_SIZE;
-
- arch_cpu_init();
- get_clocks();
- mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
- CONFIG_SPL_RELOC_MALLOC_SIZE);
- gd->flags |= GD_FLG_FULL_MALLOC_INIT;
-
-#ifdef CONFIG_SPL_NAND_BOOT
- nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
- (uchar *)SPL_ENV_ADDR);
-#endif
-#ifdef CONFIG_SPL_MMC_BOOT
- mmc_initialize(bd);
- mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
- (uchar *)SPL_ENV_ADDR);
-#endif
-#ifdef CONFIG_SPL_SPI_BOOT
- fsl_spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
- (uchar *)SPL_ENV_ADDR);
-#endif
-
- gd->env_addr = (ulong)(SPL_ENV_ADDR);
- gd->env_valid = ENV_VALID;
-
- i2c_init_all();
-
- dram_init();
-
-#ifdef CONFIG_SPL_MMC_BOOT
- mmc_boot();
-#elif defined(CONFIG_SPL_SPI_BOOT)
- fsl_spi_boot();
-#elif defined(CONFIG_SPL_NAND_BOOT)
- nand_boot();
-#endif
-}
diff --git a/board/freescale/t208xrdb/t2080_nand_rcw.cfg b/board/freescale/t208xrdb/t2080_nand_rcw.cfg
deleted file mode 100644
index 8096ff9f37..0000000000
--- a/board/freescale/t208xrdb/t2080_nand_rcw.cfg
+++ /dev/null
@@ -1,19 +0,0 @@
-#PBL preamble and RCW header
-aa55aa55 010e0100
-
-#For T2080 v1.0
-#SerDes=0x66_0x16, Core=1533MHz, DDR=1600MT/s
-#120c0017 15000000 00000000 00000000
-#66150002 00008400 ec104000 c1000000
-#00000000 00000000 00000000 000307fc
-#00000000 00000000 00000000 00000004
-
-#For T2080 v1.1
-#SerDes=0x66_0x15, Core:1800MHz, DDR:1600MT/s
-#1206001b 15000000 00000000 00000000
-
-#SerDes=0x66_0x15, Core:1800MHz, DDR:1867MT/s
-1207001b 15000000 00000000 00000000
-66150002 00000000 e8104000 c1000000
-00800000 00000000 00000000 000307fc
-00000000 00000000 00000000 00000004
diff --git a/board/freescale/t208xrdb/t2080_pbi.cfg b/board/freescale/t208xrdb/t2080_pbi.cfg
deleted file mode 100644
index 43be8a864e..0000000000
--- a/board/freescale/t208xrdb/t2080_pbi.cfg
+++ /dev/null
@@ -1,40 +0,0 @@
-#
-# Copyright 2013 Freescale Semiconductor, Inc.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Refer doc/README.pblimage for more details about how-to configure
-# and create PBL boot image
-#
-
-#PBI commands
-#Initialize CPC1
-09010000 00200400
-09138000 00000000
-091380c0 00000100
-#512KB SRAM
-09010100 00000000
-09010104 fff80009
-09010f00 08000000
-#enable CPC1
-09010000 80000000
-#Configure LAW for CPC1
-09000d00 00000000
-09000d04 fff80000
-09000d08 81000012
-#Initialize eSPI controller, default configuration is slow for eSPI to
-#load data, this configuration comes from u-boot eSPI driver.
-09110000 80000403
-09110020 2d170008
-09110024 00100008
-09110028 00100008
-0911002c 00100008
-#Errata for slowing down the MDC clock to make it <= 2.5 MHZ
-094fc030 00008148
-094fd030 00008148
-#Configure alternate space
-09000010 00000000
-09000014 ff000000
-09000018 81000000
-#Flush PBL data
-091380c0 00100000
diff --git a/board/freescale/t208xrdb/t2080_sd_rcw.cfg b/board/freescale/t208xrdb/t2080_sd_rcw.cfg
deleted file mode 100644
index 6309b1d220..0000000000
--- a/board/freescale/t208xrdb/t2080_sd_rcw.cfg
+++ /dev/null
@@ -1,19 +0,0 @@
-#PBL preamble and RCW header
-aa55aa55 010e0100
-
-#For T2080 v1.0
-#SerDes=0x66_0x16, Core=1533MHz, DDR=1600MT/s
-#120c0017 15000000 00000000 00000000
-#66150002 00008400 ec104000 c1000000
-#00000000 00000000 00000000 000307fc
-#00000000 00000000 00000000 00000004
-
-#For T2080 v1.1
-#SerDes=0x66_0x15, Core:1800MHz, DDR:1600MT/s
-#1206001b 15000000 00000000 00000000
-
-#SerDes=0x66_0x15, Core:1800MHz, DDR:1867MT/s
-1207001b 15000000 00000000 00000000
-66150002 00000000 68104000 c1000000
-00800000 00000000 00000000 000307fc
-00000000 00000000 00000000 00000004
diff --git a/board/freescale/t208xrdb/t2080_spi_rcw.cfg b/board/freescale/t208xrdb/t2080_spi_rcw.cfg
deleted file mode 100644
index f167495887..0000000000
--- a/board/freescale/t208xrdb/t2080_spi_rcw.cfg
+++ /dev/null
@@ -1,19 +0,0 @@
-#PBL preamble and RCW header
-aa55aa55 010e0100
-
-#For T2080 v1.0
-#SerDes=0x66_0x16, Core=1533MHz, DDR=1600MT/s
-#120c0017 15000000 00000000 00000000
-#66150002 00008400 ec104000 c1000000
-#00000000 00000000 00000000 000307fc
-#00000000 00000000 00000000 00000004
-
-#For T2080 v1.1
-#SerDes=0x66_0x15, Core:1800MHz, DDR:1600MT/s
-#1206001b 15000000 00000000 00000000
-
-#SerDes=0x66_0x15, Core:1800MHz, DDR:1867MT/s
-1207001b 15000000 00000000 00000000
-66150002 00000000 58104000 c1000000
-00800000 00000000 00000000 000307fc
-00000000 00000000 00000000 00000004
diff --git a/board/freescale/t208xrdb/t208xrdb.c b/board/freescale/t208xrdb/t208xrdb.c
deleted file mode 100644
index 24f0d0764c..0000000000
--- a/board/freescale/t208xrdb/t208xrdb.c
+++ /dev/null
@@ -1,142 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2009-2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <env.h>
-#include <fdt_support.h>
-#include <i2c.h>
-#include <image.h>
-#include <init.h>
-#include <netdev.h>
-#include <linux/compiler.h>
-#include <asm/mmu.h>
-#include <asm/processor.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_law.h>
-#include <asm/fsl_serdes.h>
-#include <asm/fsl_liodn.h>
-#include <fm_eth.h>
-#include "t208xrdb.h"
-#include "cpld.h"
-#include "../common/vid.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
- struct cpu_type *cpu = gd->arch.cpu;
- static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"};
-
- printf("Board: %sRDB, ", cpu->name);
- printf("Board rev: 0x%02x CPLD ver: 0x%02x, boot from ",
- CPLD_READ(hw_ver), CPLD_READ(sw_ver));
-
-#ifdef CONFIG_SDCARD
- puts("SD/MMC\n");
-#elif CONFIG_SPIFLASH
- puts("SPI\n");
-#else
- u8 reg;
-
- reg = CPLD_READ(flash_csr);
-
- if (reg & CPLD_BOOT_SEL) {
- puts("NAND\n");
- } else {
- reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
- printf("NOR vBank%d\n", reg);
- }
-#endif
-
- puts("SERDES Reference Clocks:\n");
- printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]);
- printf("SD2_CLK1=%s, SD2_CLK2=%s\n", freq[0], freq[0]);
-
- return 0;
-}
-
-int board_early_init_r(void)
-{
- const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
- int flash_esel = find_tlb_idx((void *)flashbase, 1);
- /*
- * Remap Boot flash + PROMJET region to caching-inhibited
- * so that flash can be erased properly.
- */
-
- /* Flush d-cache and invalidate i-cache of any FLASH data */
- flush_dcache();
- invalidate_icache();
- if (flash_esel == -1) {
- /* very unlikely unless something is messed up */
- puts("Error: Could not find TLB for FLASH BASE\n");
- flash_esel = 2; /* give our best effort to continue */
- } else {
- /* invalidate existing TLB entry for flash + promjet */
- disable_tlb(flash_esel);
- }
-
- set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, flash_esel, BOOKE_PAGESZ_256M, 1);
-
- /*
- * Adjust core voltage according to voltage ID
- * This function changes I2C mux to channel 2.
- */
- if (adjust_vdd(0))
- printf("Warning: Adjusting core voltage failed.\n");
- return 0;
-}
-
-unsigned long get_board_sys_clk(void)
-{
- return CONFIG_SYS_CLK_FREQ;
-}
-
-unsigned long get_board_ddr_clk(void)
-{
- return CONFIG_DDR_CLK_FREQ;
-}
-
-int misc_init_r(void)
-{
- u8 reg;
-
- /* Reset CS4315 PHY */
- reg = CPLD_READ(reset_ctl);
- reg |= CPLD_RSTCON_EDC_RST;
- CPLD_WRITE(reset_ctl, reg);
-
- return 0;
-}
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
- phys_addr_t base;
- phys_size_t size;
-
- ft_cpu_setup(blob, bd);
-
- base = env_get_bootm_low();
- size = env_get_bootm_size();
-
- fdt_fixup_memory(blob, (u64)base, (u64)size);
-
-#ifdef CONFIG_PCI
- pci_of_setup(blob, bd);
-#endif
-
- fdt_fixup_liodn(blob);
- fsl_fdt_fixup_dr_usb(blob, bd);
-
-#ifdef CONFIG_SYS_DPAA_FMAN
- fdt_fixup_fman_ethernet(blob);
- fdt_fixup_board_enet(blob);
-#endif
-
- return 0;
-}
diff --git a/board/freescale/t208xrdb/t208xrdb.h b/board/freescale/t208xrdb/t208xrdb.h
deleted file mode 100644
index 2f630ef1ca..0000000000
--- a/board/freescale/t208xrdb/t208xrdb.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- */
-
-#ifndef __CORENET_DS_H__
-#define __CORENET_DS_H__
-
-void fdt_fixup_board_enet(void *blob);
-void pci_of_setup(void *blob, bd_t *bd);
-
-#endif
diff --git a/board/freescale/t208xrdb/tlb.c b/board/freescale/t208xrdb/tlb.c
deleted file mode 100644
index 542ab1e034..0000000000
--- a/board/freescale/t208xrdb/tlb.c
+++ /dev/null
@@ -1,152 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008-2014 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
- /* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
-
- /* TLB 1 */
- /* *I*** - Covers boot page */
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
- /*
- * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
- * SRAM is at 0xfff00000, it covered the 0xfffff000.
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_1M, 1),
-#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
- /*
- * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the
- * space is at 0xfff00000, it covered the 0xfffff000.
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR,
- CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
- 0, 0, BOOKE_PAGESZ_1M, 1),
-#else
- SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_4K, 1),
-#endif
-
- /* *I*G* - CCSRBAR */
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 1, BOOKE_PAGESZ_16M, 1),
-
- /* *I*G* - Flash, localbus */
- /* This will be changed to *I*G* after relocation to RAM. */
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
- MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
- 0, 2, BOOKE_PAGESZ_256M, 1),
-
-#ifndef CONFIG_SPL_BUILD
- /* *I*G* - PCIe 1, 0x80000000 */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 3, BOOKE_PAGESZ_512M, 1),
-
- /* *I*G* - PCIe 2, 0xa0000000 */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_VIRT, CONFIG_SYS_PCIE2_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 4, BOOKE_PAGESZ_256M, 1),
-
- /* *I*G* - PCIe 3, 0xb0000000 */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 5, BOOKE_PAGESZ_256M, 1),
-
-
- /* *I*G* - PCIe 4, 0xc0000000 */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE4_MEM_VIRT, CONFIG_SYS_PCIE4_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 6, BOOKE_PAGESZ_256M, 1),
-
- /* *I*G* - PCI I/O */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 7, BOOKE_PAGESZ_256K, 1),
-
- /* Bman/Qman */
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
- SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 9, BOOKE_PAGESZ_16M, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
- CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 10, BOOKE_PAGESZ_16M, 1),
-#endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
- SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 11, BOOKE_PAGESZ_16M, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
- CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 12, BOOKE_PAGESZ_16M, 1),
-#endif
-#endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
- SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 13, BOOKE_PAGESZ_32M, 1),
-#endif
-#ifdef CONFIG_SYS_NAND_BASE
- /*
- * *I*G - NAND
- * entry 14 and 15 has been used hard coded, they will be disabled
- * in cpu_init_f, so we use entry 16 for nand.
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 16, BOOKE_PAGESZ_64K, 1),
-#endif
-#ifdef CONFIG_SYS_CPLD_BASE
- SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 17, BOOKE_PAGESZ_4K, 1),
-#endif
-#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
- /*
- * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for
- * fetching ucode and ENV from master
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR,
- CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
- 0, 18, BOOKE_PAGESZ_1M, 1),
-#endif
-#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
- SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
- 0, 19, BOOKE_PAGESZ_2G, 1)
-#endif
-
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/configs/T2080RDB_NAND_defconfig b/configs/T2080RDB_NAND_defconfig
deleted file mode 100644
index 81baa5dbdd..0000000000
--- a/configs/T2080RDB_NAND_defconfig
+++ /dev/null
@@ -1,84 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x00201000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T2080RDB=y
-CONFIG_SYS_CUSTOM_LDSCRIPT=y
-CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_NAND_BOOT=y
-CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_SYS_ALT_MEMTEST=y
-CONFIG_SYS_MEMTEST_START=0x00200000
-CONFIG_SYS_MEMTEST_END=0x00400000
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.1"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.1:1m(uboot),5m(kernel),128k(dtb),-(user)"
-# CONFIG_CMD_IRQ is not set
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="t2080rdb"
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_AQUANTIA=y
-CONFIG_PHY_CORTINA=y
-CONFIG_SYS_CORTINA_FW_IN_NAND=y
-CONFIG_PHY_REALTEK=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
diff --git a/configs/T2080RDB_SDCARD_defconfig b/configs/T2080RDB_SDCARD_defconfig
deleted file mode 100644
index a1d7d87b60..0000000000
--- a/configs/T2080RDB_SDCARD_defconfig
+++ /dev/null
@@ -1,81 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x00201000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T2080RDB=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_MMC_BOOT=y
-CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_SYS_ALT_MEMTEST=y
-CONFIG_SYS_MEMTEST_START=0x00200000
-CONFIG_SYS_MEMTEST_END=0x00400000
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.1"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.1:1m(uboot),5m(kernel),128k(dtb),-(user)"
-# CONFIG_CMD_IRQ is not set
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="t2080rdb"
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_AQUANTIA=y
-CONFIG_PHY_CORTINA=y
-CONFIG_SYS_CORTINA_FW_IN_MMC=y
-CONFIG_PHY_REALTEK=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
diff --git a/configs/T2080RDB_SECURE_BOOT_defconfig b/configs/T2080RDB_SECURE_BOOT_defconfig
deleted file mode 100644
index 7d04a94116..0000000000
--- a/configs/T2080RDB_SECURE_BOOT_defconfig
+++ /dev/null
@@ -1,63 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T2080RDB=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_SYS_ALT_MEMTEST=y
-CONFIG_SYS_MEMTEST_START=0x00200000
-CONFIG_SYS_MEMTEST_END=0x00400000
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.1"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.1:1m(uboot),5m(kernel),128k(dtb),-(user)"
-# CONFIG_CMD_IRQ is not set
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_AQUANTIA=y
-CONFIG_PHY_CORTINA=y
-CONFIG_PHY_REALTEK=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T2080RDB_SPIFLASH_defconfig b/configs/T2080RDB_SPIFLASH_defconfig
deleted file mode 100644
index c433a922e6..0000000000
--- a/configs/T2080RDB_SPIFLASH_defconfig
+++ /dev/null
@@ -1,84 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x00201000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T2080RDB=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_SPI_BOOT=y
-CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_SYS_ALT_MEMTEST=y
-CONFIG_SYS_MEMTEST_START=0x00200000
-CONFIG_SYS_MEMTEST_END=0x00400000
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.1"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.1:1m(uboot),5m(kernel),128k(dtb),-(user)"
-# CONFIG_CMD_IRQ is not set
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="t2080rdb"
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_ADDR=0xFFFC9000
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_AQUANTIA=y
-CONFIG_PHY_CORTINA=y
-CONFIG_SYS_CORTINA_FW_IN_SPIFLASH=y
-CONFIG_PHY_REALTEK=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
diff --git a/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig b/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig
deleted file mode 100644
index a8f0a965c1..0000000000
--- a/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig
+++ /dev/null
@@ -1,53 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T2080RDB=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_SYS_ALT_MEMTEST=y
-CONFIG_SYS_MEMTEST_START=0x00200000
-CONFIG_SYS_MEMTEST_END=0x00400000
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-# CONFIG_CMD_IRQ is not set
-CONFIG_ENV_IS_IN_REMOTE=y
-CONFIG_ENV_ADDR=0xFFE20000
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_AQUANTIA=y
-CONFIG_PHY_CORTINA=y
-CONFIG_SYS_CORTINA_FW_IN_REMOTE=y
-CONFIG_PHY_REALTEK=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_REMOTE=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T2080RDB_defconfig b/configs/T2080RDB_defconfig
deleted file mode 100644
index 85e3b64ad3..0000000000
--- a/configs/T2080RDB_defconfig
+++ /dev/null
@@ -1,68 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T2080RDB=y
-CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_SYS_ALT_MEMTEST=y
-CONFIG_SYS_MEMTEST_START=0x00200000
-CONFIG_SYS_MEMTEST_END=0x00400000
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.1"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.1:1m(uboot),5m(kernel),128k(dtb),-(user)"
-# CONFIG_CMD_IRQ is not set
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="t2080rdb"
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_AQUANTIA=y
-CONFIG_PHY_CORTINA=y
-CONFIG_PHY_REALTEK=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h
deleted file mode 100644
index 70eafc3e28..0000000000
--- a/include/configs/T208xRDB.h
+++ /dev/null
@@ -1,717 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2020 NXP
- */
-
-/*
- * T2080 RDB/PCIe board configuration file
- */
-
-#ifndef __T2080RDB_H
-#define __T2080RDB_H
-
-#include <linux/stringify.h>
-
-#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
-#define CONFIG_FSL_SATA_V2
-
-/* High Level Configuration Options */
-#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
-#define CONFIG_ENABLE_36BIT_PHYS
-
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_ADDR_MAP 1
-#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
-#endif
-
-#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
-#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
-#define CONFIG_ENV_OVERWRITE
-
-#ifdef CONFIG_RAMBOOT_PBL
-#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg
-
-#define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_PAD_TO 0x40000
-#define CONFIG_SPL_MAX_SIZE 0x28000
-#define RESET_VECTOR_OFFSET 0x27FFC
-#define BOOT_PAGE_OFFSET 0x27000
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SPL_SKIP_RELOCATE
-#define CONFIG_SPL_COMMON_INIT_DDR
-#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
-#endif
-
-#ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
-#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
-#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_nand_rcw.cfg
-#endif
-
-#ifdef CONFIG_SPIFLASH
-#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
-#define CONFIG_SPL_SPI_FLASH_MINIMAL
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_SYS_MPC85XX_NO_RESETVEC
-#endif
-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_spi_rcw.cfg
-#endif
-
-#ifdef CONFIG_SDCARD
-#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
-#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
-#define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
-#define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
-#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_SYS_MPC85XX_NO_RESETVEC
-#endif
-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_sd_rcw.cfg
-#endif
-
-#endif /* CONFIG_RAMBOOT_PBL */
-
-#define CONFIG_SRIO_PCIE_BOOT_MASTER
-#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
-/* Set 1M boot space */
-#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
-#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
- (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
-#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
-#endif
-
-#ifndef CONFIG_RESET_VECTOR_ADDRESS
-#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
-#endif
-
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_SYS_CACHE_STASHING
-#define CONFIG_BTB /* toggle branch predition */
-#define CONFIG_DDR_ECC
-#ifdef CONFIG_DDR_ECC
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
-#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
-#endif
-
-#if defined(CONFIG_SPIFLASH)
-#elif defined(CONFIG_SDCARD)
-#define CONFIG_SYS_MMC_ENV_DEV 0
-#endif
-
-#ifndef __ASSEMBLY__
-unsigned long get_board_sys_clk(void);
-unsigned long get_board_ddr_clk(void);
-#endif
-
-#define CONFIG_SYS_CLK_FREQ 66660000
-#define CONFIG_DDR_CLK_FREQ 133330000
-
-/*
- * Config the L3 Cache as L3 SRAM
- */
-#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
-#define CONFIG_SYS_L3_SIZE (512 << 10)
-#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
-#define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
-#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
-#define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
-#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
-
-#define CONFIG_SYS_DCSRBAR 0xf0000000
-#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
-
-/* EEPROM */
-#define CONFIG_ID_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#define CONFIG_SYS_EEPROM_BUS_NUM 0
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-
-/*
- * DDR Setup
- */
-#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
-#define CONFIG_DDR_SPD
-#define CONFIG_SYS_SPD_BUS_NUM 0
-#define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
-#define SPD_EEPROM_ADDRESS1 0x51
-#define SPD_EEPROM_ADDRESS2 0x52
-#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
-#define CTRL_INTLV_PREFERED cacheline
-
-/*
- * IFC Definitions
- */
-#define CONFIG_SYS_FLASH_BASE 0xe8000000
-#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
-#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
- CSPR_PORT_SIZE_16 | \
- CSPR_MSEL_NOR | \
- CSPR_V)
-#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
-
-/* NOR Flash Timing Params */
-#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
-
-#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
- FTIM0_NOR_TEADC(0x5) | \
- FTIM0_NOR_TEAHC(0x5))
-#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
- FTIM1_NOR_TRAD_NOR(0x1A) |\
- FTIM1_NOR_TSEQRAD_NOR(0x13))
-#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
- FTIM2_NOR_TCH(0x4) | \
- FTIM2_NOR_TWPH(0x0E) | \
- FTIM2_NOR_TWP(0x1c))
-#define CONFIG_SYS_NOR_FTIM3 0x0
-
-#define CONFIG_SYS_FLASH_QUIET_TEST
-#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS }
-
-/* CPLD on IFC */
-#define CONFIG_SYS_CPLD_BASE 0xffdf0000
-#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
-#define CONFIG_SYS_CSPR2_EXT (0xf)
-#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
- | CSPR_PORT_SIZE_8 \
- | CSPR_MSEL_GPCM \
- | CSPR_V)
-#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
-#define CONFIG_SYS_CSOR2 0x0
-
-/* CPLD Timing parameters for IFC CS2 */
-#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
- FTIM0_GPCM_TEADC(0x0e) | \
- FTIM0_GPCM_TEAHC(0x0e))
-#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
- FTIM1_GPCM_TRAD(0x1f))
-#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
- FTIM2_GPCM_TCH(0x8) | \
- FTIM2_GPCM_TWP(0x1f))
-#define CONFIG_SYS_CS2_FTIM3 0x0
-
-/* NAND Flash on IFC */
-#define CONFIG_NAND_FSL_IFC
-#define CONFIG_SYS_NAND_BASE 0xff800000
-#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
-
-#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
-#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
- | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
- | CSPR_MSEL_NAND /* MSEL = NAND */ \
- | CSPR_V)
-#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
-
-#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
- | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
- | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
- | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
- | CSOR_NAND_PGS_2K /* Page Size = 2K */\
- | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\
- | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
-
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-
-/* ONFI NAND Flash mode0 Timing Params */
-#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
- FTIM0_NAND_TWP(0x18) | \
- FTIM0_NAND_TWCHT(0x07) | \
- FTIM0_NAND_TWH(0x0a))
-#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
- FTIM1_NAND_TWBE(0x39) | \
- FTIM1_NAND_TRR(0x0e) | \
- FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
- FTIM2_NAND_TREH(0x0a) | \
- FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3 0x0
-
-#define CONFIG_SYS_NAND_DDR_LAW 11
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
-
-#if defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
-#else
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
-#endif
-
-#if defined(CONFIG_RAMBOOT_PBL)
-#define CONFIG_SYS_RAMBOOT
-#endif
-
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
-#else
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-#endif
-
-#define CONFIG_HWCONFIG
-
-/* define to use L1 as initial stack */
-#define CONFIG_L1_INIT_RAM
-#define CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
-/* The assembler doesn't like typecast */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
- ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
- CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
-#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
-
-/*
- * Serial Port
- */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
-#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
-#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
-
-/*
- * I2C
- */
-#ifndef CONFIG_DM_I2C
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
-#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
-#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
-#define CONFIG_SYS_FSL_I2C_SPEED 100000
-#define CONFIG_SYS_FSL_I2C2_SPEED 100000
-#define CONFIG_SYS_FSL_I2C3_SPEED 100000
-#define CONFIG_SYS_FSL_I2C4_SPEED 100000
-#else
-#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
-#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
-#endif
-
-#define CONFIG_SYS_I2C_FSL
-
-#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
-#define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */
-#define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */
-#define I2C_MUX_CH_DEFAULT 0x8
-
-#define I2C_MUX_CH_VOL_MONITOR 0xa
-
-#define CONFIG_VID_FLS_ENV "t208xrdb_vdd_mv"
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_VID
-#endif
-#define CONFIG_VOL_MONITOR_IR36021_SET
-#define CONFIG_VOL_MONITOR_IR36021_READ
-/* The lowest and highest voltage allowed for T208xRDB */
-#define VDD_MV_MIN 819
-#define VDD_MV_MAX 1212
-
-/*
- * RapidIO
- */
-#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
-#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
-#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
-#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
-#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
-/*
- * for slave u-boot IMAGE instored in master memory space,
- * PHYS must be aligned based on the SIZE
- */
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
-/*
- * for slave UCODE and ENV instored in master memory space,
- * PHYS must be aligned based on the SIZE
- */
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
-
-/* slave core release by master*/
-#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
-#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
-
-/*
- * SRIO_PCIE_BOOT - SLAVE
- */
-#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
-#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
-#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
- (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
-#endif
-
-/*
- * eSPI - Enhanced SPI
- */
-
-/*
- * General PCI
- * Memory space is mapped 1-1, but I/O space must start from 0.
- */
-#define CONFIG_PCIE1 /* PCIE controller 1 */
-#define CONFIG_PCIE2 /* PCIE controller 2 */
-#define CONFIG_PCIE3 /* PCIE controller 3 */
-#define CONFIG_PCIE4 /* PCIE controller 4 */
-#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
-/* controller 1, direct to uli, tgtid 3, Base address 20000 */
-#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
-#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
-
-/* controller 2, Slot 2, tgtid 2, Base address 201000 */
-#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
-#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
-#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
-
-/* controller 3, Slot 1, tgtid 1, Base address 202000 */
-#define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull
-#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
-#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
-
-/* controller 4, Base address 203000 */
-#define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000
-#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull
-#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
-
-#ifdef CONFIG_PCI
-#if !defined(CONFIG_DM_PCI)
-#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
-#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
-#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#endif
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#endif
-
-/* Qman/Bman */
-#ifndef CONFIG_NOBQFMAN
-#define CONFIG_SYS_BMAN_NUM_PORTALS 18
-#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
-#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
-#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
-#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
-#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
-#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
-#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
- CONFIG_SYS_BMAN_CENA_SIZE)
-#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
-#define CONFIG_SYS_QMAN_NUM_PORTALS 18
-#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
-#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
-#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
-#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
-#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
-#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
-#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
- CONFIG_SYS_QMAN_CENA_SIZE)
-#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
-
-#define CONFIG_SYS_DPAA_FMAN
-#define CONFIG_SYS_DPAA_PME
-#define CONFIG_SYS_PMAN
-#define CONFIG_SYS_DPAA_DCE
-#define CONFIG_SYS_DPAA_RMAN /* RMan */
-#define CONFIG_SYS_INTERLAKEN
-
-/* Default address of microcode for the Linux Fman driver */
-#if defined(CONFIG_SPIFLASH)
-/*
- * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
- * env, so we got 0x110000.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
-#define CONFIG_CORTINA_FW_ADDR 0x120000
-
-#elif defined(CONFIG_SDCARD)
-/*
- * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
- * about 1MB (2048 blocks), Env is stored after the image, and the env size is
- * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
-#define CONFIG_CORTINA_FW_ADDR (512 * 0x8a0)
-
-#elif defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
-#define CONFIG_CORTINA_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
-#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
-/*
- * Slave has no ucode locally, it can fetch this from remote. When implementing
- * in two corenet boards, slave's ucode could be stored in master's memory
- * space, the address can be mapped from slave TLB->slave LAW->
- * slave SRIO or PCIE outbound window->master inbound window->
- * master LAW->the ucode address in master's memory space.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
-#define CONFIG_CORTINA_FW_ADDR 0xFFE10000
-#else
-#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
-#define CONFIG_CORTINA_FW_ADDR 0xEFE00000
-#endif
-#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
-#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
-#endif /* CONFIG_NOBQFMAN */
-
-#ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_CORTINA_FW_LENGTH 0x40000
-#define RGMII_PHY1_ADDR 0x01 /* RealTek RTL8211E */
-#define RGMII_PHY2_ADDR 0x02
-#define CORTINA_PHY_ADDR1 0x0c /* Cortina CS4315 */
-#define CORTINA_PHY_ADDR2 0x0d
-#define FM1_10GEC3_PHY_ADDR 0x00 /* Aquantia AQ1202 10G Base-T */
-#define FM1_10GEC4_PHY_ADDR 0x01
-#endif
-
-#ifdef CONFIG_FMAN_ENET
-#define CONFIG_ETHPRIME "FM1 at DTSEC3"
-#endif
-
-/*
- * SATA
- */
-#ifdef CONFIG_FSL_SATA_V2
-#define CONFIG_SYS_SATA_MAX_DEVICE 2
-#define CONFIG_SATA1
-#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
-#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
-#define CONFIG_SATA2
-#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
-#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
-#define CONFIG_LBA48
-#endif
-
-/*
- * USB
- */
-#ifdef CONFIG_USB_EHCI_HCD
-#define CONFIG_USB_EHCI_FSL
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_HAS_FSL_DR_USB
-#endif
-
-/*
- * SDHC
- */
-#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
-#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
-#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
-#endif
-
-/*
- * Dynamic MTD Partition support with mtdparts
- */
-
-/*
- * Environment
- */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 64 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
-#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
-#endif
-
-/*
- * Environment Configuration
- */
-#define CONFIG_ROOTPATH "/opt/nfsroot"
-#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
-
-/* default location for tftp and bootm */
-#define CONFIG_LOADADDR 1000000
-#define __USB_PHY_TYPE utmi
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "hwconfig=fsl_ddr:" \
- "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
- "bank_intlv=auto;" \
- "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
- "netdev=eth0\0" \
- "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
- "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
- "tftpflash=tftpboot $loadaddr $uboot && " \
- "protect off $ubootaddr +$filesize && " \
- "erase $ubootaddr +$filesize && " \
- "cp.b $loadaddr $ubootaddr $filesize && " \
- "protect on $ubootaddr +$filesize && " \
- "cmp.b $loadaddr $ubootaddr $filesize\0" \
- "consoledev=ttyS0\0" \
- "ramdiskaddr=2000000\0" \
- "ramdiskfile=t2080rdb/ramdisk.uboot\0" \
- "fdtaddr=1e00000\0" \
- "fdtfile=t2080rdb/t2080rdb.dtb\0" \
- "bdev=sda3\0"
-
-/*
- * For emulation this causes u-boot to jump to the start of the
- * proof point app code automatically
- */
-#define CONFIG_PROOF_POINTS \
- "setenv bootargs root=/dev/$bdev rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "cpu 1 release 0x29000000 - - -;" \
- "cpu 2 release 0x29000000 - - -;" \
- "cpu 3 release 0x29000000 - - -;" \
- "cpu 4 release 0x29000000 - - -;" \
- "cpu 5 release 0x29000000 - - -;" \
- "cpu 6 release 0x29000000 - - -;" \
- "cpu 7 release 0x29000000 - - -;" \
- "go 0x29000000"
-
-#define CONFIG_HVBOOT \
- "setenv bootargs config-addr=0x60000000; " \
- "bootm 0x01000000 - 0x00f00000"
-
-#define CONFIG_ALU \
- "setenv bootargs root=/dev/$bdev rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "cpu 1 release 0x01000000 - - -;" \
- "cpu 2 release 0x01000000 - - -;" \
- "cpu 3 release 0x01000000 - - -;" \
- "cpu 4 release 0x01000000 - - -;" \
- "cpu 5 release 0x01000000 - - -;" \
- "cpu 6 release 0x01000000 - - -;" \
- "cpu 7 release 0x01000000 - - -;" \
- "go 0x01000000"
-
-#define CONFIG_LINUX \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "setenv ramdiskaddr 0x02000000;" \
- "setenv fdtaddr 0x00c00000;" \
- "setenv loadaddr 0x1000000;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_HDBOOT \
- "setenv bootargs root=/dev/$bdev rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND CONFIG_LINUX
-
-#include <asm/fsl_secure_boot.h>
-
-#endif /* __T2080RDB_H */
--
2.25.1
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 18/24] arm: Remove configs/T4160QDS_NAND_defconfig board
2020-05-27 16:46 [PATCH 00/24] spi: dm-conversion (part2) Jagan Teki
` (16 preceding siblings ...)
2020-05-27 16:46 ` [PATCH 17/24] arm: Remove configs/T2080RDB_NAND_defconfig board Jagan Teki
@ 2020-05-27 16:46 ` Jagan Teki
2020-05-28 7:15 ` Priyanka Jain
2020-05-27 16:46 ` [PATCH 19/24] arm: Remove configs/T4160RDB_defconfig board Jagan Teki
` (4 subsequent siblings)
22 siblings, 1 reply; 59+ messages in thread
From: Jagan Teki @ 2020-05-27 16:46 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_SPI by the deadline.
Remove it.
Patch-cc: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
arch/powerpc/cpu/mpc85xx/Kconfig | 1 -
board/freescale/t4qds/Kconfig | 14 -
board/freescale/t4qds/MAINTAINERS | 18 -
board/freescale/t4qds/Makefile | 15 -
board/freescale/t4qds/README | 194 -----
board/freescale/t4qds/ddr.c | 134 ----
board/freescale/t4qds/ddr.h | 81 --
board/freescale/t4qds/eth.c | 869 --------------------
board/freescale/t4qds/law.c | 33 -
board/freescale/t4qds/pci.c | 23 -
board/freescale/t4qds/spl.c | 145 ----
board/freescale/t4qds/t4240emu.c | 85 --
board/freescale/t4qds/t4240qds.c | 927 ----------------------
board/freescale/t4qds/t4240qds_qixis.h | 42 -
board/freescale/t4qds/t4_nand_rcw.cfg | 7 -
board/freescale/t4qds/t4_pbi.cfg | 21 -
board/freescale/t4qds/t4_sd_rcw.cfg | 7 -
board/freescale/t4qds/t4qds.h | 12 -
board/freescale/t4qds/tlb.c | 146 ----
configs/T4160QDS_NAND_defconfig | 69 --
configs/T4160QDS_SDCARD_defconfig | 66 --
configs/T4160QDS_SECURE_BOOT_defconfig | 56 --
configs/T4160QDS_defconfig | 53 --
configs/T4240QDS_NAND_defconfig | 69 --
configs/T4240QDS_SDCARD_defconfig | 66 --
configs/T4240QDS_SECURE_BOOT_defconfig | 56 --
configs/T4240QDS_SRIO_PCIE_BOOT_defconfig | 49 --
configs/T4240QDS_defconfig | 53 --
include/configs/T4240QDS.h | 555 -------------
29 files changed, 3866 deletions(-)
delete mode 100644 board/freescale/t4qds/Kconfig
delete mode 100644 board/freescale/t4qds/MAINTAINERS
delete mode 100644 board/freescale/t4qds/Makefile
delete mode 100644 board/freescale/t4qds/README
delete mode 100644 board/freescale/t4qds/ddr.c
delete mode 100644 board/freescale/t4qds/ddr.h
delete mode 100644 board/freescale/t4qds/eth.c
delete mode 100644 board/freescale/t4qds/law.c
delete mode 100644 board/freescale/t4qds/pci.c
delete mode 100644 board/freescale/t4qds/spl.c
delete mode 100644 board/freescale/t4qds/t4240emu.c
delete mode 100644 board/freescale/t4qds/t4240qds.c
delete mode 100644 board/freescale/t4qds/t4240qds_qixis.h
delete mode 100644 board/freescale/t4qds/t4_nand_rcw.cfg
delete mode 100644 board/freescale/t4qds/t4_pbi.cfg
delete mode 100644 board/freescale/t4qds/t4_sd_rcw.cfg
delete mode 100644 board/freescale/t4qds/t4qds.h
delete mode 100644 board/freescale/t4qds/tlb.c
delete mode 100644 configs/T4160QDS_NAND_defconfig
delete mode 100644 configs/T4160QDS_SDCARD_defconfig
delete mode 100644 configs/T4160QDS_SECURE_BOOT_defconfig
delete mode 100644 configs/T4160QDS_defconfig
delete mode 100644 configs/T4240QDS_NAND_defconfig
delete mode 100644 configs/T4240QDS_SDCARD_defconfig
delete mode 100644 configs/T4240QDS_SECURE_BOOT_defconfig
delete mode 100644 configs/T4240QDS_SRIO_PCIE_BOOT_defconfig
delete mode 100644 configs/T4240QDS_defconfig
delete mode 100644 include/configs/T4240QDS.h
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 82c5a51f48..b429e41515 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -1599,7 +1599,6 @@ source "board/freescale/mpc8572ds/Kconfig"
source "board/freescale/p1023rdb/Kconfig"
source "board/freescale/p1_twr/Kconfig"
source "board/freescale/qemu-ppce500/Kconfig"
-source "board/freescale/t4qds/Kconfig"
source "board/freescale/t4rdb/Kconfig"
source "board/gdsys/p1022/Kconfig"
source "board/keymile/Kconfig"
diff --git a/board/freescale/t4qds/Kconfig b/board/freescale/t4qds/Kconfig
deleted file mode 100644
index f7c1a0c15d..0000000000
--- a/board/freescale/t4qds/Kconfig
+++ /dev/null
@@ -1,14 +0,0 @@
-if TARGET_T4160QDS || TARGET_T4240QDS
-
-config SYS_BOARD
- default "t4qds"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "T4240QDS"
-
-source "board/freescale/common/Kconfig"
-
-endif
diff --git a/board/freescale/t4qds/MAINTAINERS b/board/freescale/t4qds/MAINTAINERS
deleted file mode 100644
index 44bb2f5c6d..0000000000
--- a/board/freescale/t4qds/MAINTAINERS
+++ /dev/null
@@ -1,18 +0,0 @@
-T4QDS BOARD
-#M: Shaohui Xie <Shaohui.Xie@freescale.com>
-S: Orphan (since 2018-05)
-F: board/freescale/t4qds/
-F: include/configs/T4240QDS.h
-F: configs/T4160QDS_defconfig
-F: configs/T4160QDS_NAND_defconfig
-F: configs/T4160QDS_SDCARD_defconfig
-F: configs/T4240QDS_defconfig
-F: configs/T4240QDS_NAND_defconfig
-F: configs/T4240QDS_SDCARD_defconfig
-F: configs/T4240QDS_SRIO_PCIE_BOOT_defconfig
-
-T4160QDS_SECURE_BOOT BOARD
-M: Ruchika Gupta <ruchika.gupta@nxp.com>
-S: Maintained
-F: configs/T4160QDS_SECURE_BOOT_defconfig
-F: configs/T4240QDS_SECURE_BOOT_defconfig
diff --git a/board/freescale/t4qds/Makefile b/board/freescale/t4qds/Makefile
deleted file mode 100644
index 11144222d3..0000000000
--- a/board/freescale/t4qds/Makefile
+++ /dev/null
@@ -1,15 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2012 Freescale Semiconductor, Inc.
-
-ifdef CONFIG_SPL_BUILD
-obj-y += spl.o
-else
-obj-$(CONFIG_TARGET_T4160QDS) += t4240qds.o eth.o
-obj-$(CONFIG_TARGET_T4240QDS) += t4240qds.o eth.o
-obj-$(CONFIG_PCI) += pci.o
-endif
-
-obj-y += ddr.o
-obj-y += law.o
-obj-y += tlb.o
diff --git a/board/freescale/t4qds/README b/board/freescale/t4qds/README
deleted file mode 100644
index bf238146db..0000000000
--- a/board/freescale/t4qds/README
+++ /dev/null
@@ -1,194 +0,0 @@
-Overview
---------
-The T4240QDS is a high-performance computing evaluation, development and test
-platform supporting the T4240 QorIQ? Power Architecture? processor. T4240QDS is
-optimized to support the high-bandwidth DDR3 memory ports, as well as the
-highly-configurable SerDes ports. The system is lead-free and RoHS-compliant.
-
-Board Features
- SERDES Connections
- 32 lanes grouped into four 8-lane banks
- Two ?front side? banks dedicated to Ethernet
- - High-speed crosspoint switch fabric on selected lanes
- - Two PCI Express slots with side-band connector supporting
- - SGMII
- - XAUI
- - HiGig
- - I-pass connectors allow board-to-board and loopback support
- Two ?back side? banks dedicated to other protocols
- - High-speed crosspoint switch fabric on all lanes
- - Four PCI Express slots with side-band connector supporting
- - PCI Express 3.0
- - SATA 2.0
- - SRIO 2.0
- - Supports 4X Aurora debug with two connectors
- DDR Controllers
- Three independant 64-bit DDR3 controllers
- Supports rates of 1866 up to 2133 MHz data-rate
- Supports two DDR3/DDR3LP UDIMM/RDIMMs per controller
- DDR power supplies 1.5V to all devices with automatic tracking of VTT.
- Power software-switchable to 1.35V if software detects all DDR3LP devices.
- MT9JSF25672AZ-2G1KZESZF has been tested at 1333, 1600, 1867, 2000 and
- 2133MT/s speeds. For 1867MT/s and above, read-to-write turnaround time
- increases by 1 clock.
-
- IFC/Local Bus
- NAND flash: 8-bit, async or sync, up to 2GB.
- NOR: 16-bit, Address/Data Multiplexed (ADM), up to 128 MB
- NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB
- - NOR devices support 16 virtual banks
- GASIC: Minimal target within Qixis FPGA
- PromJET rapid memory download support
- Address demultiplexing handled within FPGA.
- - Flexible demux allows 8 or 16 bit evaluation.
- IFC Debug/Development card
- - Support for 32-bit devices
- Ethernet
- Support two on-board RGMII 10/100/1G ethernet ports.
- SGMII and XAUI support via SERDES block (see above).
- 1588 support via Symmetricom board.
- QIXIS System Logic FPGA
- Manages system power and reset sequencing
- Manages DUT, board, clock, etc. configuration for dynamic shmoo
- Collects V-I-T data in background for code/power profiling.
- Supports legacy TMT test features (POSt, IRS, SYSCLK-synchronous assertion)
- General fault monitoring and logging
- Runs from ATX ?hot? power rails allowing operation while system is off.
- Clocks
- System and DDR clock (SYSCLK, ?DDRCLK?)
- - Switch selectable to one of 16 common settings in the interval 33MHz-166MHz.
- - Software selectable in 1MHz increments from 1-200MHz.
- SERDES clocks
- - Provides clocks to all SerDes blocks and slots
- - 100, 125 and 156.25 MHz
- Power Supplies
- Dedicated regulators for VDD
- - Adjustable from (0.7V to 1.3V at 80A
- - Regulators can be controlled by VID and/or software
- Dedicated regulator for GVDD_PL: 1.35/1.5V at 22A
- - VTT/MVREF automatically track operating voltage
- Dedicated regulators/filters for AVDD supplies
- Dedicated regulators for other supplies: OVDD, BVDD, DVDD, LVDD, POVDD, etc.
- USB
- Supports two USB 2.0 ports with integrated PHYs
- - One type A, one type micro-AB with 1.0A power per port.
- Other IO
- eSDHC/MMC
- - SDHC card slot
- eSPI port
- - High-speed serial flash
- Two Serial port
- Four I2C ports
- XFI
- XFI is supported on T4QDS-XFI board which removed slot3 and routed
- four Lanes A/B/C/D to a SFP+ cages, which to house fiber cable or
- direct attach cable(copper), the copper cable is used to emulate
- 10GBASE-KR scenario.
- So, for XFI usage, there are two scenarios, one will use fiber cable,
- another will use copper cable. An hwconfig env "fsl_10gkr_copper" is
- introduced to indicate a XFI port will use copper cable, and U-Boot
- will fixup the dtb accordingly.
- It's used as: fsl_10gkr_copper:<10g_mac_name>
- The <10g_mac_name> can be fm1_10g1, fm1_10g2, fm2_10g1, fm2_10g2, they
- do not have to be coexist in hwconfig. If a MAC is listed in the env
- "fsl_10gkr_copper", it will use copper cable, otherwise, fiber cable
- will be used by default.
- for ex. set "fsl_10gkr_copper:fm1_10g1,fm1_10g2,fm2_10g1,fm2_10g2" in
- hwconfig, then both four XFI ports will use copper cable.
- set "fsl_10gkr_copper:fm1_10g1,fm1_10g2" in hwconfig, then first two
- XFI ports will use copper cable, the other two XFI ports will use fiber
- cable.
-
-Memory map
-----------
-The addresses in brackets are physical addresses.
-
-0x0_0000_0000 (0x0_0000_0000) - 0x0_7fff_ffff 2GB DDR (more than 2GB is initialized but not mapped under with TLB)
-0x0_8000_0000 (0xc_0000_0000) - 0x0_dfff_ffff 1.5GB PCIE memory
-0x0_f000_0000 (0xf_0000_0000) - 0x0_f1ff_ffff 32MB DCSR (includes trace buffers)
-0x0_f400_0000 (0xf_f400_0000) - 0x0_f5ff_ffff 32MB BMan
-0x0_f600_0000 (0xf_f600_0000) - 0x0_f7ff_ffff 32MB QMan
-0x0_f800_0000 (0xf_f800_0000) - 0x0_f803_ffff 256KB PCIE IO
-0x0_e000_0000 (0xf_e000_0000) - 0x0_efff_ffff 256MB NOR flash
-0x0_fe00_0000 (0xf_fe00_0000) - 0x0_feff_ffff 16MB CCSR
-0x0_ffdf_0000 (0xf_ffdf_0000) - 0x0_ffdf_03ff 4KB QIXIS
-0x0_ffff_f000 (0x0_7fff_fff0) - 0x0_ffff_ffff 4KB Boot page translation for secondary cores
-
-The physical address of the last (boot page translation) varies with the actual DDR size.
-
-Voltage ID and VDD override
---------------------
-T4240 has a VID feature. U-Boot reads the VID efuses and adjust the voltage
-accordingly. The voltage can also be override by command vdd_override. The
-syntax is
-
-vdd_override <voltage in mV>, eg. 1050 is for 1.050v.
-
-Upon success, the actual voltage will be read back. The value is checked
-for safety and any invalid value will not adjust the voltage.
-
-Another way to override VDD is to use environmental variable, in case of using
-command is too late for some debugging. The syntax is
-
-setenv t4240qds_vdd_mv <voltage in mV>
-saveenv
-reset
-
-The override voltage takes effect when booting.
-
-Note: voltage adjustment needs to be done step by step. Changing voltage too
-rapidly may cause current surge. The voltage stepping is done by software.
-Users can set the final voltage directly.
-
-2-stage NAND/SD boot loader
--------------------------------
-PBL initializes the internal SRAM and copy SPL(160K) in SRAM.
-SPL further initialise DDR using SPD and environment variables
-and copy U-Boot(768 KB) from NAND/SD device to DDR.
-Finally SPL transers control to U-Boot for futher booting.
-
-SPL has following features:
- - Executes within 256K
- - No relocation required
-
-Run time view of SPL framework
--------------------------------------------------
-|Area | Address |
--------------------------------------------------
-|SecureBoot header | 0xFFFC0000 (32KB) |
--------------------------------------------------
-|GD, BD | 0xFFFC8000 (4KB) |
--------------------------------------------------
-|ENV | 0xFFFC9000 (8KB) |
--------------------------------------------------
-|HEAP | 0xFFFCB000 (50KB) |
--------------------------------------------------
-|STACK | 0xFFFD8000 (22KB) |
--------------------------------------------------
-|U-Boot SPL | 0xFFFD8000 (160KB) |
--------------------------------------------------
-
-NAND Flash memory Map on T4QDS
---------------------------------------------------------------
-Start End Definition Size
-0x000000 0x0FFFFF U-Boot img 1MB
-0x140000 0x15FFFF U-Boot env 128KB
-0x160000 0x17FFFF FMAN Ucode 128KB
-
-Micro SD Card memory Map on T4QDS
-----------------------------------------------------
-Block #blocks Definition Size
-0x008 2048 U-Boot img 1MB
-0x800 0016 U-Boot env 8KB
-0x820 0128 FMAN ucode 64KB
-
-Switch Settings: (ON is 1, OFF is 0)
-===============
-NAND boot SW setting:
-SW1[1:8] = 10000010
-SW2[1.1] = 0
-SW6[1:4] = 1001
-
-SD boot SW setting:
-SW1[1:8] = 00100000
-SW2[1.1] = 0
diff --git a/board/freescale/t4qds/ddr.c b/board/freescale/t4qds/ddr.c
deleted file mode 100644
index 4fdd69d424..0000000000
--- a/board/freescale/t4qds/ddr.c
+++ /dev/null
@@ -1,134 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright 2012 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <hwconfig.h>
-#include <init.h>
-#include <log.h>
-#include <asm/mmu.h>
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-#include <asm/fsl_law.h>
-#include "ddr.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
- ulong ddr_freq;
-
- if (ctrl_num > 2) {
- printf("Not supported controller number %d\n", ctrl_num);
- return;
- }
- if (!pdimm->n_ranks)
- return;
-
- /*
- * we use identical timing for all slots. If needed, change the code
- * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
- */
- if (popts->registered_dimm_en)
- pbsp = rdimms[0];
- else
- pbsp = udimms[0];
-
-
- /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
- * freqency and n_banks specified in board_specific_parameters table.
- */
- ddr_freq = get_ddr_freq(0) / 1000000;
- while (pbsp->datarate_mhz_high) {
- if (pbsp->n_ranks == pdimm->n_ranks &&
- (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
- if (ddr_freq <= pbsp->datarate_mhz_high) {
- popts->cpo_override = pbsp->cpo;
- popts->write_data_delay =
- pbsp->write_data_delay;
- popts->clk_adjust = pbsp->clk_adjust;
- popts->wrlvl_start = pbsp->wrlvl_start;
- popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
- popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
- popts->twot_en = pbsp->force_2t;
- goto found;
- }
- pbsp_highest = pbsp;
- }
- pbsp++;
- }
-
- if (pbsp_highest) {
- printf("Error: board specific timing not found "
- "for data rate %lu MT/s\n"
- "Trying to use the highest speed (%u) parameters\n",
- ddr_freq, pbsp_highest->datarate_mhz_high);
- popts->cpo_override = pbsp_highest->cpo;
- popts->write_data_delay = pbsp_highest->write_data_delay;
- popts->clk_adjust = pbsp_highest->clk_adjust;
- popts->wrlvl_start = pbsp_highest->wrlvl_start;
- popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
- popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
- popts->twot_en = pbsp_highest->force_2t;
- } else {
- panic("DIMM is not supported by this board");
- }
-found:
- debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
- "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
- "wrlvl_ctrl_3 0x%x\n",
- pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
- pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
- pbsp->wrlvl_ctl_3);
-
- /*
- * Factors to consider for half-strength driver enable:
- * - number of DIMMs installed
- */
- popts->half_strength_driver_enable = 0;
- /*
- * Write leveling override
- */
- popts->wrlvl_override = 1;
- popts->wrlvl_sample = 0xf;
-
- /*
- * Rtt and Rtt_WR override
- */
- popts->rtt_override = 0;
-
- /* Enable ZQ calibration */
- popts->zq_en = 1;
-
- /* DHC_EN =1, ODT = 75 Ohm */
- popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
- popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
-
- /* optimize cpo for erratum A-009942 */
- popts->cpo_sample = 0x63;
-}
-
-int dram_init(void)
-{
- phys_size_t dram_size;
-
- puts("Initializing....using SPD\n");
-
-#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
- dram_size = fsl_ddr_sdram();
-#else
- /* DDR has been initialised by first stage boot loader */
- dram_size = fsl_ddr_sdram_size();
-#endif
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
-
- gd->ram_size = dram_size;
-
- return 0;
-}
diff --git a/board/freescale/t4qds/ddr.h b/board/freescale/t4qds/ddr.h
deleted file mode 100644
index a28d4314da..0000000000
--- a/board/freescale/t4qds/ddr.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#ifndef __DDR_H__
-#define __DDR_H__
-struct board_specific_parameters {
- u32 n_ranks;
- u32 datarate_mhz_high;
- u32 rank_gb;
- u32 clk_adjust;
- u32 wrlvl_start;
- u32 wrlvl_ctl_2;
- u32 wrlvl_ctl_3;
- u32 cpo;
- u32 write_data_delay;
- u32 force_2t;
-};
-
-/*
- * These tables contain all valid speeds we want to override with board
- * specific parameters. datarate_mhz_high values need to be in ascending order
- * for each n_ranks group.
- */
-
-static const struct board_specific_parameters udimm0[] = {
- /*
- * memory controller 0
- * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
- * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
- */
- {2, 1350, 4, 8, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0},
- {2, 1350, 0, 10, 7, 0x0709090b, 0x0c0c0d09, 0xff, 2, 0},
- {2, 1666, 4, 8, 8, 0x080a0a0d, 0x0d10100b, 0xff, 2, 0},
- {2, 1666, 0, 10, 7, 0x080a0a0c, 0x0d0d0e0a, 0xff, 2, 0},
- {2, 1900, 0, 8, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0},
- {2, 2140, 0, 8, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0},
- {1, 1350, 0, 10, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0},
- {1, 1700, 0, 10, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0},
- {1, 1900, 0, 8, 8, 0x080a0a0c, 0x0e0e0f0a, 0xff, 2, 0},
- {1, 2140, 0, 8, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0},
- {}
-};
-
-static const struct board_specific_parameters rdimm0[] = {
- /*
- * memory controller 0
- * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
- * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
- */
- {4, 1350, 0, 10, 9, 0x08070605, 0x06070806, 0xff, 2, 0},
- {4, 1666, 0, 10, 11, 0x0a080706, 0x07090906, 0xff, 2, 0},
- {4, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0},
- {2, 1350, 0, 10, 9, 0x08070605, 0x06070806, 0xff, 2, 0},
- {2, 1666, 0, 10, 11, 0x0a090806, 0x08090a06, 0xff, 2, 0},
- {2, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0},
- {1, 1350, 0, 10, 9, 0x08070605, 0x06070806, 0xff, 2, 0},
- {1, 1666, 0, 10, 11, 0x0a090806, 0x08090a06, 0xff, 2, 0},
- {1, 2140, 0, 8, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0},
- {}
-};
-
-/*
- * The three slots have slightly different timing. The center values are good
- * for all slots. We use identical speed tables for them. In future use, if
- * DIMMs require separated tables, make more entries as needed.
- */
-static const struct board_specific_parameters *udimms[] = {
- udimm0,
-};
-
-/*
- * The three slots have slightly different timing. See comments above.
- */
-static const struct board_specific_parameters *rdimms[] = {
- rdimm0,
-};
-
-
-#endif
diff --git a/board/freescale/t4qds/eth.c b/board/freescale/t4qds/eth.c
deleted file mode 100644
index 810868ff39..0000000000
--- a/board/freescale/t4qds/eth.c
+++ /dev/null
@@ -1,869 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2012 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <fdt_support.h>
-#include <log.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/mmu.h>
-#include <asm/processor.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_law.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/fsl_serdes.h>
-#include <asm/fsl_portals.h>
-#include <asm/fsl_liodn.h>
-#include <malloc.h>
-#include <fm_eth.h>
-#include <fsl_mdio.h>
-#include <miiphy.h>
-#include <phy.h>
-#include <fsl_dtsec.h>
-#include <asm/fsl_serdes.h>
-#include <hwconfig.h>
-#include "../common/qixis.h"
-#include "../common/fman.h"
-#include <linux/libfdt.h>
-
-#include "t4240qds_qixis.h"
-
-#define EMI_NONE 0xFFFFFFFF
-#define EMI1_RGMII 0
-#define EMI1_SLOT1 1
-#define EMI1_SLOT2 2
-#define EMI1_SLOT3 3
-#define EMI1_SLOT4 4
-#define EMI1_SLOT5 5
-#define EMI1_SLOT7 7
-#define EMI2 8
-/* Slot6 and Slot8 do not have EMI connections */
-
-static int mdio_mux[NUM_FM_PORTS];
-
-static const char *mdio_names[] = {
- "T4240QDS_MDIO0",
- "T4240QDS_MDIO1",
- "T4240QDS_MDIO2",
- "T4240QDS_MDIO3",
- "T4240QDS_MDIO4",
- "T4240QDS_MDIO5",
- "NULL",
- "T4240QDS_MDIO7",
- "T4240QDS_10GC",
-};
-
-static u8 lane_to_slot_fsm1[] = {1, 1, 1, 1, 2, 2, 2, 2};
-static u8 lane_to_slot_fsm2[] = {3, 3, 3, 3, 4, 4, 4, 4};
-static u8 slot_qsgmii_phyaddr[5][4] = {
- {0, 0, 0, 0},/* not used, to make index match slot No. */
- {0, 1, 2, 3},
- {4, 5, 6, 7},
- {8, 9, 0xa, 0xb},
- {0xc, 0xd, 0xe, 0xf},
-};
-static u8 qsgmiiphy_fix[NUM_FM_PORTS] = {0};
-
-static const char *t4240qds_mdio_name_for_muxval(u8 muxval)
-{
- return mdio_names[muxval];
-}
-
-struct mii_dev *mii_dev_for_muxval(u8 muxval)
-{
- struct mii_dev *bus;
- const char *name = t4240qds_mdio_name_for_muxval(muxval);
-
- if (!name) {
- printf("No bus for muxval %x\n", muxval);
- return NULL;
- }
-
- bus = miiphy_get_dev_by_name(name);
-
- if (!bus) {
- printf("No bus by name %s\n", name);
- return NULL;
- }
-
- return bus;
-}
-
-struct t4240qds_mdio {
- u8 muxval;
- struct mii_dev *realbus;
-};
-
-static void t4240qds_mux_mdio(u8 muxval)
-{
- u8 brdcfg4;
- if ((muxval < 6) || (muxval == 7)) {
- brdcfg4 = QIXIS_READ(brdcfg[4]);
- brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
- brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
- QIXIS_WRITE(brdcfg[4], brdcfg4);
- }
-}
-
-static int t4240qds_mdio_read(struct mii_dev *bus, int addr, int devad,
- int regnum)
-{
- struct t4240qds_mdio *priv = bus->priv;
-
- t4240qds_mux_mdio(priv->muxval);
-
- return priv->realbus->read(priv->realbus, addr, devad, regnum);
-}
-
-static int t4240qds_mdio_write(struct mii_dev *bus, int addr, int devad,
- int regnum, u16 value)
-{
- struct t4240qds_mdio *priv = bus->priv;
-
- t4240qds_mux_mdio(priv->muxval);
-
- return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
-}
-
-static int t4240qds_mdio_reset(struct mii_dev *bus)
-{
- struct t4240qds_mdio *priv = bus->priv;
-
- return priv->realbus->reset(priv->realbus);
-}
-
-static int t4240qds_mdio_init(char *realbusname, u8 muxval)
-{
- struct t4240qds_mdio *pmdio;
- struct mii_dev *bus = mdio_alloc();
-
- if (!bus) {
- printf("Failed to allocate T4240QDS MDIO bus\n");
- return -1;
- }
-
- pmdio = malloc(sizeof(*pmdio));
- if (!pmdio) {
- printf("Failed to allocate T4240QDS private data\n");
- free(bus);
- return -1;
- }
-
- bus->read = t4240qds_mdio_read;
- bus->write = t4240qds_mdio_write;
- bus->reset = t4240qds_mdio_reset;
- strcpy(bus->name, t4240qds_mdio_name_for_muxval(muxval));
-
- pmdio->realbus = miiphy_get_dev_by_name(realbusname);
-
- if (!pmdio->realbus) {
- printf("No bus with name %s\n", realbusname);
- free(bus);
- free(pmdio);
- return -1;
- }
-
- pmdio->muxval = muxval;
- bus->priv = pmdio;
-
- return mdio_register(bus);
-}
-
-void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa,
- enum fm_port port, int offset)
-{
- int interface = fm_info_get_enet_if(port);
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- u32 prtcl2 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
-
- prtcl2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
-
- if (interface == PHY_INTERFACE_MODE_SGMII ||
- interface == PHY_INTERFACE_MODE_QSGMII) {
- switch (port) {
- case FM1_DTSEC1:
- if (qsgmiiphy_fix[port])
- fdt_set_phy_handle(blob, prop, pa,
- "sgmii_phy21");
- break;
- case FM1_DTSEC2:
- if (qsgmiiphy_fix[port])
- fdt_set_phy_handle(blob, prop, pa,
- "sgmii_phy22");
- break;
- case FM1_DTSEC3:
- if (qsgmiiphy_fix[port])
- fdt_set_phy_handle(blob, prop, pa,
- "sgmii_phy23");
- break;
- case FM1_DTSEC4:
- if (qsgmiiphy_fix[port])
- fdt_set_phy_handle(blob, prop, pa,
- "sgmii_phy24");
- break;
- case FM1_DTSEC6:
- if (qsgmiiphy_fix[port])
- fdt_set_phy_handle(blob, prop, pa,
- "sgmii_phy12");
- break;
- case FM1_DTSEC9:
- if (qsgmiiphy_fix[port])
- fdt_set_phy_handle(blob, prop, pa,
- "sgmii_phy14");
- else
- fdt_set_phy_handle(blob, prop, pa,
- "phy_sgmii4");
- break;
- case FM1_DTSEC10:
- if (qsgmiiphy_fix[port])
- fdt_set_phy_handle(blob, prop, pa,
- "sgmii_phy13");
- else
- fdt_set_phy_handle(blob, prop, pa,
- "phy_sgmii3");
- break;
- case FM2_DTSEC1:
- if (qsgmiiphy_fix[port])
- fdt_set_phy_handle(blob, prop, pa,
- "sgmii_phy41");
- break;
- case FM2_DTSEC2:
- if (qsgmiiphy_fix[port])
- fdt_set_phy_handle(blob, prop, pa,
- "sgmii_phy42");
- break;
- case FM2_DTSEC3:
- if (qsgmiiphy_fix[port])
- fdt_set_phy_handle(blob, prop, pa,
- "sgmii_phy43");
- break;
- case FM2_DTSEC4:
- if (qsgmiiphy_fix[port])
- fdt_set_phy_handle(blob, prop, pa,
- "sgmii_phy44");
- break;
- case FM2_DTSEC6:
- if (qsgmiiphy_fix[port])
- fdt_set_phy_handle(blob, prop, pa,
- "sgmii_phy32");
- break;
- case FM2_DTSEC9:
- if (qsgmiiphy_fix[port])
- fdt_set_phy_handle(blob, prop, pa,
- "sgmii_phy34");
- else
- fdt_set_phy_handle(blob, prop, pa,
- "phy_sgmii12");
- break;
- case FM2_DTSEC10:
- if (qsgmiiphy_fix[port])
- fdt_set_phy_handle(blob, prop, pa,
- "sgmii_phy33");
- else
- fdt_set_phy_handle(blob, prop, pa,
- "phy_sgmii11");
- break;
- default:
- break;
- }
- } else if (interface == PHY_INTERFACE_MODE_XGMII &&
- ((prtcl2 == 55) || (prtcl2 == 57))) {
- /*
- * if the 10G is XFI, check hwconfig to see what is the
- * media type, there are two types, fiber or copper,
- * fix the dtb accordingly.
- */
- int media_type = 0;
- struct fixed_link f_link;
- char lane_mode[20] = {"10GBASE-KR"};
- char buf[32] = "serdes-2,";
- int off;
-
- switch (port) {
- case FM1_10GEC1:
- if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g1")) {
- media_type = 1;
- fdt_set_phy_handle(blob, prop, pa,
- "phy_xfi1");
- sprintf(buf, "%s%s%s", buf, "lane-a,",
- (char *)lane_mode);
- }
- break;
- case FM1_10GEC2:
- if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g2")) {
- media_type = 1;
- fdt_set_phy_handle(blob, prop, pa,
- "phy_xfi2");
- sprintf(buf, "%s%s%s", buf, "lane-b,",
- (char *)lane_mode);
- }
- break;
- case FM2_10GEC1:
- if (hwconfig_sub("fsl_10gkr_copper", "fm2_10g1")) {
- media_type = 1;
- fdt_set_phy_handle(blob, prop, pa,
- "phy_xfi3");
- sprintf(buf, "%s%s%s", buf, "lane-d,",
- (char *)lane_mode);
- }
- break;
- case FM2_10GEC2:
- if (hwconfig_sub("fsl_10gkr_copper", "fm2_10g2")) {
- media_type = 1;
- fdt_set_phy_handle(blob, prop, pa,
- "phy_xfi4");
- sprintf(buf, "%s%s%s", buf, "lane-c,",
- (char *)lane_mode);
- }
- break;
- default:
- return;
- }
-
- if (!media_type) {
- /* fixed-link is used for XFI fiber cable */
- fdt_delprop(blob, offset, "phy-handle");
- f_link.phy_id = port;
- f_link.duplex = 1;
- f_link.link_speed = 10000;
- f_link.pause = 0;
- f_link.asym_pause = 0;
- fdt_setprop(blob, offset, "fixed-link", &f_link,
- sizeof(f_link));
- } else {
- /* set property for copper cable */
- off = fdt_node_offset_by_compat_reg(blob,
- "fsl,fman-memac-mdio", pa + 0x1000);
- fdt_setprop_string(blob, off, "lane-instance", buf);
- }
- }
-}
-
-void fdt_fixup_board_enet(void *fdt)
-{
- int i;
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- u32 prtcl2 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
-
- prtcl2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
- for (i = FM1_DTSEC1; i < NUM_FM_PORTS; i++) {
- switch (fm_info_get_enet_if(i)) {
- case PHY_INTERFACE_MODE_SGMII:
- case PHY_INTERFACE_MODE_QSGMII:
- switch (mdio_mux[i]) {
- case EMI1_SLOT1:
- fdt_status_okay_by_alias(fdt, "emi1_slot1");
- break;
- case EMI1_SLOT2:
- fdt_status_okay_by_alias(fdt, "emi1_slot2");
- break;
- case EMI1_SLOT3:
- fdt_status_okay_by_alias(fdt, "emi1_slot3");
- break;
- case EMI1_SLOT4:
- fdt_status_okay_by_alias(fdt, "emi1_slot4");
- break;
- default:
- break;
- }
- break;
- case PHY_INTERFACE_MODE_XGMII:
- /* check if it's XFI interface for 10g */
- if ((prtcl2 == 55) || (prtcl2 == 57)) {
- if (i == FM1_10GEC1 && hwconfig_sub(
- "fsl_10gkr_copper", "fm1_10g1"))
- fdt_status_okay_by_alias(
- fdt, "xfi_pcs_mdio1");
- if (i == FM1_10GEC2 && hwconfig_sub(
- "fsl_10gkr_copper", "fm1_10g2"))
- fdt_status_okay_by_alias(
- fdt, "xfi_pcs_mdio2");
- if (i == FM2_10GEC1 && hwconfig_sub(
- "fsl_10gkr_copper", "fm2_10g1"))
- fdt_status_okay_by_alias(
- fdt, "xfi_pcs_mdio3");
- if (i == FM2_10GEC2 && hwconfig_sub(
- "fsl_10gkr_copper", "fm2_10g2"))
- fdt_status_okay_by_alias(
- fdt, "xfi_pcs_mdio4");
- break;
- }
- switch (i) {
- case FM1_10GEC1:
- fdt_status_okay_by_alias(fdt, "emi2_xauislot1");
- break;
- case FM1_10GEC2:
- fdt_status_okay_by_alias(fdt, "emi2_xauislot2");
- break;
- case FM2_10GEC1:
- fdt_status_okay_by_alias(fdt, "emi2_xauislot3");
- break;
- case FM2_10GEC2:
- fdt_status_okay_by_alias(fdt, "emi2_xauislot4");
- break;
- default:
- break;
- }
- break;
- default:
- break;
- }
- }
-}
-
-static void initialize_qsgmiiphy_fix(void)
-{
- int i;
- unsigned short reg;
-
- for (i = 1; i <= 4; i++) {
- /*
- * Try to read if a SGMII card is used, we do it slot by slot.
- * if a SGMII PHY address is valid on a slot, then we mark
- * all ports on the slot, then fix the PHY address for the
- * marked port when doing dtb fixup.
- */
- if (miiphy_read(mdio_names[i],
- SGMII_CARD_PORT1_PHY_ADDR, MII_PHYSID2, ®) != 0) {
- debug("Slot%d PHY ID register 2 read failed\n", i);
- continue;
- }
-
- debug("Slot%d MII_PHYSID2 @ 0x1c= 0x%04x\n", i, reg);
-
- if (reg == 0xFFFF) {
- /* No physical device present@this address */
- continue;
- }
-
- switch (i) {
- case 1:
- qsgmiiphy_fix[FM1_DTSEC5] = 1;
- qsgmiiphy_fix[FM1_DTSEC6] = 1;
- qsgmiiphy_fix[FM1_DTSEC9] = 1;
- qsgmiiphy_fix[FM1_DTSEC10] = 1;
- slot_qsgmii_phyaddr[1][0] = SGMII_CARD_PORT1_PHY_ADDR;
- slot_qsgmii_phyaddr[1][1] = SGMII_CARD_PORT2_PHY_ADDR;
- slot_qsgmii_phyaddr[1][2] = SGMII_CARD_PORT3_PHY_ADDR;
- slot_qsgmii_phyaddr[1][3] = SGMII_CARD_PORT4_PHY_ADDR;
- break;
- case 2:
- qsgmiiphy_fix[FM1_DTSEC1] = 1;
- qsgmiiphy_fix[FM1_DTSEC2] = 1;
- qsgmiiphy_fix[FM1_DTSEC3] = 1;
- qsgmiiphy_fix[FM1_DTSEC4] = 1;
- slot_qsgmii_phyaddr[2][0] = SGMII_CARD_PORT1_PHY_ADDR;
- slot_qsgmii_phyaddr[2][1] = SGMII_CARD_PORT2_PHY_ADDR;
- slot_qsgmii_phyaddr[2][2] = SGMII_CARD_PORT3_PHY_ADDR;
- slot_qsgmii_phyaddr[2][3] = SGMII_CARD_PORT4_PHY_ADDR;
- break;
- case 3:
- qsgmiiphy_fix[FM2_DTSEC5] = 1;
- qsgmiiphy_fix[FM2_DTSEC6] = 1;
- qsgmiiphy_fix[FM2_DTSEC9] = 1;
- qsgmiiphy_fix[FM2_DTSEC10] = 1;
- slot_qsgmii_phyaddr[3][0] = SGMII_CARD_PORT1_PHY_ADDR;
- slot_qsgmii_phyaddr[3][1] = SGMII_CARD_PORT2_PHY_ADDR;
- slot_qsgmii_phyaddr[3][2] = SGMII_CARD_PORT3_PHY_ADDR;
- slot_qsgmii_phyaddr[3][3] = SGMII_CARD_PORT4_PHY_ADDR;
- break;
- case 4:
- qsgmiiphy_fix[FM2_DTSEC1] = 1;
- qsgmiiphy_fix[FM2_DTSEC2] = 1;
- qsgmiiphy_fix[FM2_DTSEC3] = 1;
- qsgmiiphy_fix[FM2_DTSEC4] = 1;
- slot_qsgmii_phyaddr[4][0] = SGMII_CARD_PORT1_PHY_ADDR;
- slot_qsgmii_phyaddr[4][1] = SGMII_CARD_PORT2_PHY_ADDR;
- slot_qsgmii_phyaddr[4][2] = SGMII_CARD_PORT3_PHY_ADDR;
- slot_qsgmii_phyaddr[4][3] = SGMII_CARD_PORT4_PHY_ADDR;
- break;
- default:
- break;
- }
- }
-}
-
-int board_eth_init(bd_t *bis)
-{
-#if defined(CONFIG_FMAN_ENET)
- int i, idx, lane, slot, interface;
- struct memac_mdio_info dtsec_mdio_info;
- struct memac_mdio_info tgec_mdio_info;
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- u32 srds_prtcl_s1, srds_prtcl_s2;
-
- srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
- FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
- srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
- srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
- FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
- srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
-
- /* Initialize the mdio_mux array so we can recognize empty elements */
- for (i = 0; i < NUM_FM_PORTS; i++)
- mdio_mux[i] = EMI_NONE;
-
- dtsec_mdio_info.regs =
- (struct memac_mdio_controller *)CONFIG_SYS_FM2_DTSEC_MDIO_ADDR;
-
- dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
-
- /* Register the 1G MDIO bus */
- fm_memac_mdio_init(bis, &dtsec_mdio_info);
-
- tgec_mdio_info.regs =
- (struct memac_mdio_controller *)CONFIG_SYS_FM2_TGEC_MDIO_ADDR;
- tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
-
- /* Register the 10G MDIO bus */
- fm_memac_mdio_init(bis, &tgec_mdio_info);
-
- /* Register the muxing front-ends to the MDIO buses */
- t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII);
- t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
- t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
- t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
- t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
- t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
- t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7);
- t4240qds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
-
- initialize_qsgmiiphy_fix();
-
- switch (srds_prtcl_s1) {
- case 1:
- case 2:
- case 4:
- /* XAUI/HiGig in Slot1 and Slot2 */
- fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
- fm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR);
- break;
- case 27:
- case 28:
- case 35:
- case 36:
- /* SGMII in Slot1 and Slot2 */
- fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
- fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
- fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]);
- fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]);
- fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
- fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
- if ((srds_prtcl_s2 != 55) && (srds_prtcl_s2 != 57)) {
- fm_info_set_phy_address(FM1_DTSEC9,
- slot_qsgmii_phyaddr[1][3]);
- fm_info_set_phy_address(FM1_DTSEC10,
- slot_qsgmii_phyaddr[1][2]);
- }
- break;
- case 37:
- case 38:
- fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
- fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
- fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]);
- fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]);
- fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
- fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
- if ((srds_prtcl_s2 != 55) && (srds_prtcl_s2 != 57)) {
- fm_info_set_phy_address(FM1_DTSEC9,
- slot_qsgmii_phyaddr[1][2]);
- fm_info_set_phy_address(FM1_DTSEC10,
- slot_qsgmii_phyaddr[1][3]);
- }
- break;
- case 39:
- case 40:
- case 45:
- case 46:
- case 47:
- case 48:
- fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
- fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
- if ((srds_prtcl_s2 != 55) && (srds_prtcl_s2 != 57)) {
- fm_info_set_phy_address(FM1_DTSEC10,
- slot_qsgmii_phyaddr[1][2]);
- fm_info_set_phy_address(FM1_DTSEC9,
- slot_qsgmii_phyaddr[1][3]);
- }
- fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
- fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
- fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]);
- fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]);
- break;
- default:
- puts("Invalid SerDes1 protocol for T4240QDS\n");
- break;
- }
-
- for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
- idx = i - FM1_DTSEC1;
- interface = fm_info_get_enet_if(i);
- switch (interface) {
- case PHY_INTERFACE_MODE_SGMII:
- case PHY_INTERFACE_MODE_QSGMII:
- if (interface == PHY_INTERFACE_MODE_QSGMII) {
- if (idx <= 3)
- lane = serdes_get_first_lane(FSL_SRDS_1,
- QSGMII_FM1_A);
- else
- lane = serdes_get_first_lane(FSL_SRDS_1,
- QSGMII_FM1_B);
- if (lane < 0)
- break;
- slot = lane_to_slot_fsm1[lane];
- debug("FM1 at DTSEC%u expects QSGMII in slot %u\n",
- idx + 1, slot);
- } else {
- lane = serdes_get_first_lane(FSL_SRDS_1,
- SGMII_FM1_DTSEC1 + idx);
- if (lane < 0)
- break;
- slot = lane_to_slot_fsm1[lane];
- debug("FM1 at DTSEC%u expects SGMII in slot %u\n",
- idx + 1, slot);
- }
- if (QIXIS_READ(present2) & (1 << (slot - 1)))
- fm_disable_port(i);
- switch (slot) {
- case 1:
- mdio_mux[i] = EMI1_SLOT1;
- fm_info_set_mdio(i,
- mii_dev_for_muxval(mdio_mux[i]));
- break;
- case 2:
- mdio_mux[i] = EMI1_SLOT2;
- fm_info_set_mdio(i,
- mii_dev_for_muxval(mdio_mux[i]));
- break;
- };
- break;
- case PHY_INTERFACE_MODE_RGMII:
- /* FM1 DTSEC5 routes to RGMII with EC2 */
- debug("FM1 at DTSEC%u is RGMII at address %u\n",
- idx + 1, 2);
- if (i == FM1_DTSEC5)
- fm_info_set_phy_address(i, 2);
- mdio_mux[i] = EMI1_RGMII;
- fm_info_set_mdio(i,
- mii_dev_for_muxval(mdio_mux[i]));
- break;
- default:
- break;
- }
- }
-
- for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
- idx = i - FM1_10GEC1;
- switch (fm_info_get_enet_if(i)) {
- case PHY_INTERFACE_MODE_XGMII:
- if ((srds_prtcl_s2 == 55) || (srds_prtcl_s2 == 57)) {
- /* A fake PHY address to make U-Boot happy */
- fm_info_set_phy_address(i, i);
- } else {
- lane = serdes_get_first_lane(FSL_SRDS_1,
- XAUI_FM1_MAC9 + idx);
- if (lane < 0)
- break;
- slot = lane_to_slot_fsm1[lane];
- if (QIXIS_READ(present2) & (1 << (slot - 1)))
- fm_disable_port(i);
- }
- mdio_mux[i] = EMI2;
- fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
- break;
- default:
- break;
- }
- }
-
-#if (CONFIG_SYS_NUM_FMAN == 2)
- switch (srds_prtcl_s2) {
- case 1:
- case 2:
- case 4:
- /* XAUI/HiGig in Slot3 and Slot4 */
- fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
- fm_info_set_phy_address(FM2_10GEC2, FM2_10GEC2_PHY_ADDR);
- break;
- case 6:
- case 7:
- case 12:
- case 13:
- case 14:
- case 15:
- case 16:
- case 21:
- case 22:
- case 23:
- case 24:
- case 25:
- case 26:
- /* XAUI/HiGig in Slot3, SGMII in Slot4 */
- fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
- fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
- fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
- fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
- fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
- break;
- case 27:
- case 28:
- case 35:
- case 36:
- /* SGMII in Slot3 and Slot4 */
- fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
- fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
- fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
- fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
- fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
- fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]);
- fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]);
- fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]);
- break;
- case 37:
- case 38:
- /* QSGMII in Slot3 and Slot4 */
- fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
- fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
- fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
- fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
- fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
- fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]);
- fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][2]);
- fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][3]);
- break;
- case 39:
- case 40:
- case 45:
- case 46:
- case 47:
- case 48:
- /* SGMII in Slot3 */
- fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
- fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]);
- fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]);
- fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]);
- /* QSGMII in Slot4 */
- fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
- fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
- fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
- fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
- break;
- case 49:
- case 50:
- case 51:
- case 52:
- case 53:
- case 54:
- fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
- fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
- fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
- fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
- fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
- break;
- case 55:
- case 57:
- /* XFI in Slot3, SGMII in Slot4 */
- fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
- fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
- fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
- fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
- break;
- default:
- puts("Invalid SerDes2 protocol for T4240QDS\n");
- break;
- }
-
- for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
- idx = i - FM2_DTSEC1;
- interface = fm_info_get_enet_if(i);
- switch (interface) {
- case PHY_INTERFACE_MODE_SGMII:
- case PHY_INTERFACE_MODE_QSGMII:
- if (interface == PHY_INTERFACE_MODE_QSGMII) {
- if (idx <= 3)
- lane = serdes_get_first_lane(FSL_SRDS_2,
- QSGMII_FM2_A);
- else
- lane = serdes_get_first_lane(FSL_SRDS_2,
- QSGMII_FM2_B);
- if (lane < 0)
- break;
- slot = lane_to_slot_fsm2[lane];
- debug("FM2 at DTSEC%u expects QSGMII in slot %u\n",
- idx + 1, slot);
- } else {
- lane = serdes_get_first_lane(FSL_SRDS_2,
- SGMII_FM2_DTSEC1 + idx);
- if (lane < 0)
- break;
- slot = lane_to_slot_fsm2[lane];
- debug("FM2 at DTSEC%u expects SGMII in slot %u\n",
- idx + 1, slot);
- }
- if (QIXIS_READ(present2) & (1 << (slot - 1)))
- fm_disable_port(i);
- switch (slot) {
- case 3:
- mdio_mux[i] = EMI1_SLOT3;
- fm_info_set_mdio(i,
- mii_dev_for_muxval(mdio_mux[i]));
- break;
- case 4:
- mdio_mux[i] = EMI1_SLOT4;
- fm_info_set_mdio(i,
- mii_dev_for_muxval(mdio_mux[i]));
- break;
- };
- break;
- case PHY_INTERFACE_MODE_RGMII:
- /*
- * If DTSEC5 is RGMII, then it's routed via via EC1 to
- * the first on-board RGMII port. If DTSEC6 is RGMII,
- * then it's routed via via EC2 to the second on-board
- * RGMII port.
- */
- debug("FM2 at DTSEC%u is RGMII at address %u\n",
- idx + 1, i == FM2_DTSEC5 ? 1 : 2);
- fm_info_set_phy_address(i, i == FM2_DTSEC5 ? 1 : 2);
- mdio_mux[i] = EMI1_RGMII;
- fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
- break;
- default:
- break;
- }
- }
-
- for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) {
- idx = i - FM2_10GEC1;
- switch (fm_info_get_enet_if(i)) {
- case PHY_INTERFACE_MODE_XGMII:
- if ((srds_prtcl_s2 == 55) || (srds_prtcl_s2 == 57)) {
- /* A fake PHY address to make U-Boot happy */
- fm_info_set_phy_address(i, i);
- } else {
- lane = serdes_get_first_lane(FSL_SRDS_2,
- XAUI_FM2_MAC9 + idx);
- if (lane < 0)
- break;
- slot = lane_to_slot_fsm2[lane];
- if (QIXIS_READ(present2) & (1 << (slot - 1)))
- fm_disable_port(i);
- }
- mdio_mux[i] = EMI2;
- fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
- break;
- default:
- break;
- }
- }
-#endif /* CONFIG_SYS_NUM_FMAN */
-
- cpu_eth_init(bis);
-#endif /* CONFIG_FMAN_ENET */
-
- return pci_eth_init(bis);
-}
diff --git a/board/freescale/t4qds/law.c b/board/freescale/t4qds/law.c
deleted file mode 100644
index cb7bdf391b..0000000000
--- a/board/freescale/t4qds/law.c
+++ /dev/null
@@ -1,33 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008-2012 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-struct law_entry law_table[] = {
- SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
- SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
-#endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
- SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
-#endif
-#ifdef QIXIS_BASE_PHYS
- SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
-#endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
- /* Limit DCSR to 32M to access NPC Trace Buffer */
- SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
-#endif
-#ifdef CONFIG_SYS_NAND_BASE_PHYS
- SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
-#endif
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/t4qds/pci.c b/board/freescale/t4qds/pci.c
deleted file mode 100644
index 26e2a0af4a..0000000000
--- a/board/freescale/t4qds/pci.c
+++ /dev/null
@@ -1,23 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2007-2012 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <init.h>
-#include <pci.h>
-#include <asm/fsl_pci.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <asm/fsl_serdes.h>
-
-void pci_init_board(void)
-{
- fsl_pcie_init_board(0);
-}
-
-void pci_of_setup(void *blob, bd_t *bd)
-{
- FT_FSL_PCI_SETUP;
-}
diff --git a/board/freescale/t4qds/spl.c b/board/freescale/t4qds/spl.c
deleted file mode 100644
index d72d207a76..0000000000
--- a/board/freescale/t4qds/spl.c
+++ /dev/null
@@ -1,145 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/* Copyright 2014 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <clock_legacy.h>
-#include <console.h>
-#include <env_internal.h>
-#include <init.h>
-#include <asm/spl.h>
-#include <malloc.h>
-#include <ns16550.h>
-#include <nand.h>
-#include <mmc.h>
-#include <fsl_esdhc.h>
-#include <i2c.h>
-#include "../common/qixis.h"
-#include "t4240qds_qixis.h"
-
-#define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000
-
-DECLARE_GLOBAL_DATA_PTR;
-
-phys_size_t get_effective_memsize(void)
-{
- return CONFIG_SYS_L3_SIZE;
-}
-
-unsigned long get_board_sys_clk(void)
-{
- u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
-
- switch (sysclk_conf & 0x0F) {
- case QIXIS_SYSCLK_83:
- return 83333333;
- case QIXIS_SYSCLK_100:
- return 100000000;
- case QIXIS_SYSCLK_125:
- return 125000000;
- case QIXIS_SYSCLK_133:
- return 133333333;
- case QIXIS_SYSCLK_150:
- return 150000000;
- case QIXIS_SYSCLK_160:
- return 160000000;
- case QIXIS_SYSCLK_166:
- return 166666666;
- }
- return 66666666;
-}
-
-unsigned long get_board_ddr_clk(void)
-{
- u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
-
- switch ((ddrclk_conf & 0x30) >> 4) {
- case QIXIS_DDRCLK_100:
- return 100000000;
- case QIXIS_DDRCLK_125:
- return 125000000;
- case QIXIS_DDRCLK_133:
- return 133333333;
- }
- return 66666666;
-}
-
-void board_init_f(ulong bootflag)
-{
- u32 plat_ratio, sys_clk, ccb_clk;
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-#ifdef CONFIG_SPL_NAND_BOOT
- u32 porsr1, pinctl;
-#endif
-
-#ifdef CONFIG_SPL_NAND_BOOT
- porsr1 = in_be32(&gur->porsr1);
- pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK)) | 0x24800000);
- out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000), pinctl);
-#endif
- /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
- memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
-
- /* Update GD pointer */
- gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
-
- /* compiler optimization barrier needed for GCC >= 3.4 */
- __asm__ __volatile__("" : : : "memory");
-
- console_init_f();
-
- /* initialize selected port with appropriate baud rate */
- sys_clk = get_board_sys_clk();
- plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
- ccb_clk = sys_clk * plat_ratio / 2;
-
- NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
- ccb_clk / 16 / CONFIG_BAUDRATE);
-
-#ifdef CONFIG_SPL_MMC_BOOT
- puts("\nSD boot...\n");
-#elif defined(CONFIG_SPL_NAND_BOOT)
- puts("\nNAND boot...\n");
-#endif
- relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
- bd_t *bd;
-
- bd = (bd_t *)(gd + sizeof(gd_t));
- memset(bd, 0, sizeof(bd_t));
- gd->bd = bd;
- bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
- bd->bi_memsize = CONFIG_SYS_L3_SIZE;
-
- arch_cpu_init();
- get_clocks();
- mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
- CONFIG_SPL_RELOC_MALLOC_SIZE);
- gd->flags |= GD_FLG_FULL_MALLOC_INIT;
-
-#ifdef CONFIG_SPL_NAND_BOOT
- nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
- (uchar *)SPL_ENV_ADDR);
-#endif
-#ifdef CONFIG_SPL_MMC_BOOT
- mmc_initialize(bd);
- mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
- (uchar *)SPL_ENV_ADDR);
-#endif
-
- gd->env_addr = (ulong)(SPL_ENV_ADDR);
- gd->env_valid = ENV_VALID;
-
- i2c_init_all();
-
- dram_init();
-
-#ifdef CONFIG_SPL_MMC_BOOT
- mmc_boot();
-#elif defined(CONFIG_SPL_NAND_BOOT)
- nand_boot();
-#endif
-}
diff --git a/board/freescale/t4qds/t4240emu.c b/board/freescale/t4qds/t4240emu.c
deleted file mode 100644
index 8f2032acc7..0000000000
--- a/board/freescale/t4qds/t4240emu.c
+++ /dev/null
@@ -1,85 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <env.h>
-#include <fdt_support.h>
-#include <i2c.h>
-#include <image.h>
-#include <init.h>
-#include <netdev.h>
-#include <linux/compiler.h>
-#include <asm/mmu.h>
-#include <asm/processor.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_law.h>
-#include <asm/fsl_serdes.h>
-#include <asm/fsl_liodn.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
- struct cpu_type *cpu = gd->arch.cpu;
-
- printf("Board: %sEMU\n", cpu->name);
-
- return 0;
-}
-
-int board_early_init_r(void)
-{
- const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
- int flash_esel = find_tlb_idx((void *)flashbase, 1);
-
- /*
- * Remap Boot flash + PROMJET region to caching-inhibited
- * so that flash can be erased properly.
- */
-
- /* Flush d-cache and invalidate i-cache of any FLASH data */
- flush_dcache();
- invalidate_icache();
-
- if (flash_esel == -1) {
- /* very unlikely unless something is messed up */
- puts("Error: Could not find TLB for FLASH BASE\n");
- flash_esel = 2; /* give our best effort to continue */
- } else {
- /* invalidate existing TLB entry for flash */
- disable_tlb(flash_esel);
- }
-
- set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, flash_esel, BOOKE_PAGESZ_256M, 1);
-
- return 0;
-}
-
-int misc_init_r(void)
-{
- return 0;
-}
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
- phys_addr_t base;
- phys_size_t size;
-
- ft_cpu_setup(blob, bd);
-
- base = env_get_bootm_low();
- size = env_get_bootm_size();
-
- fdt_fixup_memory(blob, (u64)base, (u64)size);
-
- fdt_fixup_liodn(blob);
- fsl_fdt_fixup_dr_usb(blob, bd);
-
- return 0;
-}
diff --git a/board/freescale/t4qds/t4240qds.c b/board/freescale/t4qds/t4240qds.c
deleted file mode 100644
index 8d1a66f223..0000000000
--- a/board/freescale/t4qds/t4240qds.c
+++ /dev/null
@@ -1,927 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2009-2012 Freescale Semiconductor, Inc.
- * Copyright 2020 NXP
- */
-
-#include <common.h>
-#include <command.h>
-#include <env.h>
-#include <fdt_support.h>
-#include <i2c.h>
-#include <image.h>
-#include <init.h>
-#include <irq_func.h>
-#include <log.h>
-#include <netdev.h>
-#include <linux/compiler.h>
-#include <asm/mmu.h>
-#include <asm/processor.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_law.h>
-#include <asm/fsl_serdes.h>
-#include <asm/fsl_liodn.h>
-#include <fm_eth.h>
-#include <linux/delay.h>
-
-#include "../common/qixis.h"
-#include "../common/vsc3316_3308.h"
-#include "t4qds.h"
-#include "t4240qds_qixis.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static int8_t vsc3316_fsm1_tx[8][2] = { {0, 0}, {1, 1}, {6, 6}, {7, 7},
- {8, 8}, {9, 9}, {14, 14}, {15, 15} };
-
-static int8_t vsc3316_fsm2_tx[8][2] = { {2, 2}, {3, 3}, {4, 4}, {5, 5},
- {10, 10}, {11, 11}, {12, 12}, {13, 13} };
-
-static int8_t vsc3316_fsm1_rx[8][2] = { {2, 12}, {3, 13}, {4, 5}, {5, 4},
- {10, 11}, {11, 10}, {12, 2}, {13, 3} };
-
-static int8_t vsc3316_fsm2_rx[8][2] = { {0, 15}, {1, 14}, {6, 7}, {7, 6},
- {8, 9}, {9, 8}, {14, 1}, {15, 0} };
-
-int checkboard(void)
-{
- char buf[64];
- u8 sw;
- struct cpu_type *cpu = gd->arch.cpu;
- unsigned int i;
-
- printf("Board: %sQDS, ", cpu->name);
- printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ",
- QIXIS_READ(id), QIXIS_READ(arch));
-
- sw = QIXIS_READ(brdcfg[0]);
- sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
-
- if (sw < 0x8)
- printf("vBank: %d\n", sw);
- else if (sw == 0x8)
- puts("Promjet\n");
- else if (sw == 0x9)
- puts("NAND\n");
- else
- printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
-
- printf("FPGA: v%d (%s), build %d",
- (int)QIXIS_READ(scver), qixis_read_tag(buf),
- (int)qixis_read_minor());
- /* the timestamp string contains "\n"@the end */
- printf(" on %s", qixis_read_time(buf));
-
- /*
- * Display the actual SERDES reference clocks as configured by the
- * dip switches on the board. Note that the SWx registers could
- * technically be set to force the reference clocks to match the
- * values that the SERDES expects (or vice versa). For now, however,
- * we just display both values and hope the user notices when they
- * don't match.
- */
- puts("SERDES Reference Clocks: ");
- sw = QIXIS_READ(brdcfg[2]);
- for (i = 0; i < MAX_SERDES; i++) {
- static const char * const freq[] = {
- "100", "125", "156.25", "161.1328125"};
- unsigned int clock = (sw >> (6 - 2 * i)) & 3;
-
- printf("SERDES%u=%sMHz ", i+1, freq[clock]);
- }
- puts("\n");
-
- return 0;
-}
-
-int select_i2c_ch_pca9547(u8 ch, int bus_num)
-{
- int ret;
-
-#ifdef CONFIG_DM_I2C
- struct udevice *dev;
-
- ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
- 1, &dev);
- if (ret) {
- printf("%s: Cannot find udev for a bus %d\n", __func__,
- bus_num);
- return ret;
- }
-
- ret = dm_i2c_write(dev, 0, &ch, 1);
-#else
- ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
-#endif
- if (ret) {
- puts("PCA: failed to select proper channel\n");
- return ret;
- }
-
- return 0;
-}
-
-/*
- * read_voltage from sensor on I2C bus
- * We use average of 4 readings, waiting for 532us befor another reading
- */
-#define NUM_READINGS 4 /* prefer to be power of 2 for efficiency */
-#define WAIT_FOR_ADC 532 /* wait for 532 microseconds for ADC */
-
-static inline int read_voltage(void)
-{
- int i, ret, voltage_read = 0;
- u16 vol_mon;
-#ifdef CONFIG_DM_I2C
- struct udevice *dev;
- int bus_num = 0;
-#endif
-
- for (i = 0; i < NUM_READINGS; i++) {
-#ifdef CONFIG_DM_I2C
- ret = i2c_get_chip_for_busnum(bus_num, I2C_VOL_MONITOR_ADDR,
- 1, &dev);
- if (ret) {
- printf("%s: Cannot find udev for a bus %d\n", __func__,
- bus_num);
- return ret;
- }
-
- ret = dm_i2c_read(dev,
- I2C_VOL_MONITOR_BUS_V_OFFSET,
- (void *)&vol_mon, 2);
-#else
- ret = i2c_read(I2C_VOL_MONITOR_ADDR,
- I2C_VOL_MONITOR_BUS_V_OFFSET, 1, (void *)&vol_mon, 2);
-#endif
- if (ret) {
- printf("VID: failed to read core voltage\n");
- return ret;
- }
- if (vol_mon & I2C_VOL_MONITOR_BUS_V_OVF) {
- printf("VID: Core voltage sensor error\n");
- return -1;
- }
- debug("VID: bus voltage reads 0x%04x\n", vol_mon);
- /* LSB = 4mv */
- voltage_read += (vol_mon >> I2C_VOL_MONITOR_BUS_V_SHIFT) * 4;
- udelay(WAIT_FOR_ADC);
- }
- /* calculate the average */
- voltage_read /= NUM_READINGS;
-
- return voltage_read;
-}
-
-/*
- * We need to calculate how long before the voltage starts to drop or increase
- * It returns with the loop count. Each loop takes several readings (532us)
- */
-static inline int wait_for_voltage_change(int vdd_last)
-{
- int timeout, vdd_current;
-
- vdd_current = read_voltage();
- /* wait until voltage starts to drop */
- for (timeout = 0; abs(vdd_last - vdd_current) <= 4 &&
- timeout < 100; timeout++) {
- vdd_current = read_voltage();
- }
- if (timeout >= 100) {
- printf("VID: Voltage adjustment timeout\n");
- return -1;
- }
- return timeout;
-}
-
-/*
- * argument 'wait' is the time we know the voltage difference can be measured
- * this function keeps reading the voltage until it is stable
- */
-static inline int wait_for_voltage_stable(int wait)
-{
- int timeout, vdd_current, vdd_last;
-
- vdd_last = read_voltage();
- udelay(wait * NUM_READINGS * WAIT_FOR_ADC);
- /* wait until voltage is stable */
- vdd_current = read_voltage();
- for (timeout = 0; abs(vdd_last - vdd_current) >= 4 &&
- timeout < 100; timeout++) {
- vdd_last = vdd_current;
- udelay(wait * NUM_READINGS * WAIT_FOR_ADC);
- vdd_current = read_voltage();
- }
- if (timeout >= 100) {
- printf("VID: Voltage adjustment timeout\n");
- return -1;
- }
-
- return vdd_current;
-}
-
-static inline int set_voltage(u8 vid)
-{
- int wait, vdd_last;
-
- vdd_last = read_voltage();
- QIXIS_WRITE(brdcfg[6], vid);
- wait = wait_for_voltage_change(vdd_last);
- if (wait < 0)
- return -1;
- debug("VID: Waited %d us\n", wait * NUM_READINGS * WAIT_FOR_ADC);
- wait = wait ? wait : 1;
-
- vdd_last = wait_for_voltage_stable(wait);
- if (vdd_last < 0)
- return -1;
- debug("VID: Current voltage is %d mV\n", vdd_last);
-
- return vdd_last;
-}
-
-
-static int adjust_vdd(ulong vdd_override)
-{
- int re_enable = disable_interrupts();
- ccsr_gur_t __iomem *gur =
- (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- u32 fusesr;
- u8 vid, vid_current;
- int vdd_target, vdd_current, vdd_last;
- int ret;
- unsigned long vdd_string_override;
- char *vdd_string;
- static const uint16_t vdd[32] = {
- 0, /* unused */
- 9875, /* 0.9875V */
- 9750,
- 9625,
- 9500,
- 9375,
- 9250,
- 9125,
- 9000,
- 8875,
- 8750,
- 8625,
- 8500,
- 8375,
- 8250,
- 8125,
- 10000, /* 1.0000V */
- 10125,
- 10250,
- 10375,
- 10500,
- 10625,
- 10750,
- 10875,
- 11000,
- 0, /* reserved */
- };
- struct vdd_drive {
- u8 vid;
- unsigned voltage;
- };
-
- ret = select_i2c_ch_pca9547(I2C_MUX_CH_VOL_MONITOR, 0);
- if (ret) {
- debug("VID: I2c failed to switch channel\n");
- ret = -1;
- goto exit;
- }
-
- /* get the voltage ID from fuse status register */
- fusesr = in_be32(&gur->dcfg_fusesr);
- vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_VID_SHIFT) &
- FSL_CORENET_DCFG_FUSESR_VID_MASK;
- if (vid == FSL_CORENET_DCFG_FUSESR_VID_MASK) {
- vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) &
- FSL_CORENET_DCFG_FUSESR_ALTVID_MASK;
- }
- vdd_target = vdd[vid];
-
- /* check override variable for overriding VDD */
- vdd_string = env_get("t4240qds_vdd_mv");
- if (vdd_override == 0 && vdd_string &&
- !strict_strtoul(vdd_string, 10, &vdd_string_override))
- vdd_override = vdd_string_override;
- if (vdd_override >= 819 && vdd_override <= 1212) {
- vdd_target = vdd_override * 10; /* convert to 1/10 mV */
- debug("VDD override is %lu\n", vdd_override);
- } else if (vdd_override != 0) {
- printf("Invalid value.\n");
- }
-
- if (vdd_target == 0) {
- debug("VID: VID not used\n");
- ret = 0;
- goto exit;
- } else {
- /* round up and divice by 10 to get a value in mV */
- vdd_target = DIV_ROUND_UP(vdd_target, 10);
- debug("VID: vid = %d mV\n", vdd_target);
- }
-
- /*
- * Check current board VID setting
- * Voltage regulator support output to 6.250mv step
- * The highes voltage allowed for this board is (vid=0x40) 1.21250V
- * the lowest is (vid=0x7f) 0.81875V
- */
- vid_current = QIXIS_READ(brdcfg[6]);
- vdd_current = 121250 - (vid_current - 0x40) * 625;
- debug("VID: Current vid setting is (0x%x) %d mV\n",
- vid_current, vdd_current/100);
-
- /*
- * Read voltage monitor to check real voltage.
- * Voltage monitor LSB is 4mv.
- */
- vdd_last = read_voltage();
- if (vdd_last < 0) {
- printf("VID: Could not read voltage sensor abort VID adjustment\n");
- ret = -1;
- goto exit;
- }
- debug("VID: Core voltage is at %d mV\n", vdd_last);
- /*
- * Adjust voltage to@or 8mV above target.
- * Each step of adjustment is 6.25mV.
- * Stepping down too fast may cause over current.
- */
- while (vdd_last > 0 && vid_current < 0x80 &&
- vdd_last > (vdd_target + 8)) {
- vid_current++;
- vdd_last = set_voltage(vid_current);
- }
- /*
- * Check if we need to step up
- * This happens when board voltage switch was set too low
- */
- while (vdd_last > 0 && vid_current >= 0x40 &&
- vdd_last < vdd_target + 2) {
- vid_current--;
- vdd_last = set_voltage(vid_current);
- }
- if (vdd_last > 0)
- printf("VID: Core voltage %d mV\n", vdd_last);
- else
- ret = -1;
-
-exit:
- if (re_enable)
- enable_interrupts();
- return ret;
-}
-
-/* Configure Crossbar switches for Front-Side SerDes Ports */
-int config_frontside_crossbar_vsc3316(void)
-{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- u32 srds_prtcl_s1, srds_prtcl_s2;
- int ret;
-
- ret = select_i2c_ch_pca9547(I2C_MUX_CH_VSC3316_FS, 0);
- if (ret)
- return ret;
-
- srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
- FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
- srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
- switch (srds_prtcl_s1) {
- case 37:
- case 38:
- /* swap first lane and third lane on slot1 */
- vsc3316_fsm1_tx[0][1] = 14;
- vsc3316_fsm1_tx[6][1] = 0;
- vsc3316_fsm1_rx[1][1] = 2;
- vsc3316_fsm1_rx[6][1] = 13;
- case 39:
- case 40:
- case 45:
- case 46:
- case 47:
- case 48:
- /* swap first lane and third lane on slot2 */
- vsc3316_fsm1_tx[2][1] = 8;
- vsc3316_fsm1_tx[4][1] = 6;
- vsc3316_fsm1_rx[2][1] = 10;
- vsc3316_fsm1_rx[5][1] = 5;
- default:
- ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm1_tx, 8);
- if (ret)
- return ret;
- ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm1_rx, 8);
- if (ret)
- return ret;
- break;
- }
-
- srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
- FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
- srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
- switch (srds_prtcl_s2) {
- case 37:
- case 38:
- /* swap first lane and third lane on slot3 */
- vsc3316_fsm2_tx[2][1] = 11;
- vsc3316_fsm2_tx[5][1] = 4;
- vsc3316_fsm2_rx[2][1] = 9;
- vsc3316_fsm2_rx[4][1] = 7;
- case 39:
- case 40:
- case 45:
- case 46:
- case 47:
- case 48:
- case 49:
- case 50:
- case 51:
- case 52:
- case 53:
- case 54:
- /* swap first lane and third lane on slot4 */
- vsc3316_fsm2_tx[6][1] = 3;
- vsc3316_fsm2_tx[1][1] = 12;
- vsc3316_fsm2_rx[0][1] = 1;
- vsc3316_fsm2_rx[6][1] = 15;
- default:
- ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm2_tx, 8);
- if (ret)
- return ret;
- ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm2_rx, 8);
- if (ret)
- return ret;
- break;
- }
-
- return 0;
-}
-
-int config_backside_crossbar_mux(void)
-{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- u32 srds_prtcl_s3, srds_prtcl_s4;
- u8 brdcfg;
-
- srds_prtcl_s3 = in_be32(&gur->rcwsr[4]) &
- FSL_CORENET2_RCWSR4_SRDS3_PRTCL;
- srds_prtcl_s3 >>= FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT;
- switch (srds_prtcl_s3) {
- case 0:
- /* SerDes3 is not enabled */
- break;
- case 1:
- case 2:
- case 9:
- case 10:
- /* SD3(0:7) => SLOT5(0:7) */
- brdcfg = QIXIS_READ(brdcfg[12]);
- brdcfg &= ~BRDCFG12_SD3MX_MASK;
- brdcfg |= BRDCFG12_SD3MX_SLOT5;
- QIXIS_WRITE(brdcfg[12], brdcfg);
- break;
- case 3:
- case 4:
- case 5:
- case 6:
- case 7:
- case 8:
- case 11:
- case 12:
- case 13:
- case 14:
- case 15:
- case 16:
- case 17:
- case 18:
- case 19:
- case 20:
- /* SD3(4:7) => SLOT6(0:3) */
- brdcfg = QIXIS_READ(brdcfg[12]);
- brdcfg &= ~BRDCFG12_SD3MX_MASK;
- brdcfg |= BRDCFG12_SD3MX_SLOT6;
- QIXIS_WRITE(brdcfg[12], brdcfg);
- break;
- default:
- printf("WARNING: unsupported for SerDes3 Protocol %d\n",
- srds_prtcl_s3);
- return -1;
- }
-
- srds_prtcl_s4 = in_be32(&gur->rcwsr[4]) &
- FSL_CORENET2_RCWSR4_SRDS4_PRTCL;
- srds_prtcl_s4 >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT;
- switch (srds_prtcl_s4) {
- case 0:
- /* SerDes4 is not enabled */
- break;
- case 1:
- case 2:
- /* 10b, SD4(0:7) => SLOT7(0:7) */
- brdcfg = QIXIS_READ(brdcfg[12]);
- brdcfg &= ~BRDCFG12_SD4MX_MASK;
- brdcfg |= BRDCFG12_SD4MX_SLOT7;
- QIXIS_WRITE(brdcfg[12], brdcfg);
- break;
- case 3:
- case 4:
- case 5:
- case 6:
- case 7:
- case 8:
- /* x1b, SD4(4:7) => SLOT8(0:3) */
- brdcfg = QIXIS_READ(brdcfg[12]);
- brdcfg &= ~BRDCFG12_SD4MX_MASK;
- brdcfg |= BRDCFG12_SD4MX_SLOT8;
- QIXIS_WRITE(brdcfg[12], brdcfg);
- break;
- case 9:
- case 10:
- case 11:
- case 12:
- case 13:
- case 14:
- case 15:
- case 16:
- case 18:
- /* 00b, SD4(4:5) => AURORA, SD4(6:7) => SATA */
- brdcfg = QIXIS_READ(brdcfg[12]);
- brdcfg &= ~BRDCFG12_SD4MX_MASK;
- brdcfg |= BRDCFG12_SD4MX_AURO_SATA;
- QIXIS_WRITE(brdcfg[12], brdcfg);
- break;
- default:
- printf("WARNING: unsupported for SerDes4 Protocol %d\n",
- srds_prtcl_s4);
- return -1;
- }
-
- return 0;
-}
-
-int board_early_init_r(void)
-{
- const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
- int flash_esel = find_tlb_idx((void *)flashbase, 1);
-
- /*
- * Remap Boot flash + PROMJET region to caching-inhibited
- * so that flash can be erased properly.
- */
-
- /* Flush d-cache and invalidate i-cache of any FLASH data */
- flush_dcache();
- invalidate_icache();
-
- if (flash_esel == -1) {
- /* very unlikely unless something is messed up */
- puts("Error: Could not find TLB for FLASH BASE\n");
- flash_esel = 2; /* give our best effort to continue */
- } else {
- /* invalidate existing TLB entry for flash + promjet */
- disable_tlb(flash_esel);
- }
-
- set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, flash_esel, BOOKE_PAGESZ_256M, 1);
-
- /* Disable remote I2C connection to qixis fpga */
- QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE);
-
- /*
- * Adjust core voltage according to voltage ID
- * This function changes I2C mux to channel 2.
- */
- if (adjust_vdd(0))
- printf("Warning: Adjusting core voltage failed.\n");
-
- /* Configure board SERDES ports crossbar */
- config_frontside_crossbar_vsc3316();
- config_backside_crossbar_mux();
- select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
-
- return 0;
-}
-
-unsigned long get_board_sys_clk(void)
-{
- u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
-#ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
- /* use accurate clock measurement */
- int freq = QIXIS_READ(clk_freq[0]) << 8 | QIXIS_READ(clk_freq[1]);
- int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
- u32 val;
-
- val = freq * base;
- if (val) {
- debug("SYS Clock measurement is: %d\n", val);
- return val;
- } else {
- printf("Warning: SYS clock measurement is invalid, using value from brdcfg1.\n");
- }
-#endif
-
- switch (sysclk_conf & 0x0F) {
- case QIXIS_SYSCLK_83:
- return 83333333;
- case QIXIS_SYSCLK_100:
- return 100000000;
- case QIXIS_SYSCLK_125:
- return 125000000;
- case QIXIS_SYSCLK_133:
- return 133333333;
- case QIXIS_SYSCLK_150:
- return 150000000;
- case QIXIS_SYSCLK_160:
- return 160000000;
- case QIXIS_SYSCLK_166:
- return 166666666;
- }
- return 66666666;
-}
-
-unsigned long get_board_ddr_clk(void)
-{
- u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
-#ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
- /* use accurate clock measurement */
- int freq = QIXIS_READ(clk_freq[2]) << 8 | QIXIS_READ(clk_freq[3]);
- int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
- u32 val;
-
- val = freq * base;
- if (val) {
- debug("DDR Clock measurement is: %d\n", val);
- return val;
- } else {
- printf("Warning: DDR clock measurement is invalid, using value from brdcfg1.\n");
- }
-#endif
-
- switch ((ddrclk_conf & 0x30) >> 4) {
- case QIXIS_DDRCLK_100:
- return 100000000;
- case QIXIS_DDRCLK_125:
- return 125000000;
- case QIXIS_DDRCLK_133:
- return 133333333;
- }
- return 66666666;
-}
-
-int misc_init_r(void)
-{
- u8 sw;
- void *srds_base = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
- serdes_corenet_t *srds_regs;
- u32 actual[MAX_SERDES];
- u32 pllcr0, expected;
- unsigned int i;
-
- sw = QIXIS_READ(brdcfg[2]);
- for (i = 0; i < MAX_SERDES; i++) {
- unsigned int clock = (sw >> (6 - 2 * i)) & 3;
- switch (clock) {
- case 0:
- actual[i] = SRDS_PLLCR0_RFCK_SEL_100;
- break;
- case 1:
- actual[i] = SRDS_PLLCR0_RFCK_SEL_125;
- break;
- case 2:
- actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25;
- break;
- case 3:
- actual[i] = SRDS_PLLCR0_RFCK_SEL_161_13;
- break;
- }
- }
-
- for (i = 0; i < MAX_SERDES; i++) {
- srds_regs = srds_base + i * 0x1000;
- pllcr0 = srds_regs->bank[0].pllcr0;
- expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
- if (expected != actual[i]) {
- printf("Warning: SERDES%u expects reference clock %sMHz, but actual is %sMHz\n",
- i + 1, serdes_clock_to_string(expected),
- serdes_clock_to_string(actual[i]));
- }
- }
-
- return 0;
-}
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
- phys_addr_t base;
- phys_size_t size;
-
- ft_cpu_setup(blob, bd);
-
- base = env_get_bootm_low();
- size = env_get_bootm_size();
-
- fdt_fixup_memory(blob, (u64)base, (u64)size);
-
-#ifdef CONFIG_PCI
- pci_of_setup(blob, bd);
-#endif
-
- fdt_fixup_liodn(blob);
- fsl_fdt_fixup_dr_usb(blob, bd);
-
-#ifdef CONFIG_SYS_DPAA_FMAN
- fdt_fixup_fman_ethernet(blob);
- fdt_fixup_board_enet(blob);
-#endif
-
- return 0;
-}
-
-/*
- * This function is called by bdinfo to print detail board information.
- * As an exmaple for future board, we organize the messages into
- * several sections. If applicable, the message is in the format of
- * <name> = <value>
- * It should aligned with normal output of bdinfo command.
- *
- * Voltage: Core, DDR and another configurable voltages
- * Clock : Critical clocks which are not printed already
- * RCW : RCW source if not printed already
- * Misc : Other important information not in above catagories
- */
-void board_detail(void)
-{
- int i;
- u8 brdcfg[16], dutcfg[16], rst_ctl;
- int vdd, rcwsrc;
- static const char * const clk[] = {"66.67", "100", "125", "133.33"};
-
- for (i = 0; i < 16; i++) {
- brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i);
- dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i);
- }
-
- /* Voltage secion */
- if (!select_i2c_ch_pca9547(I2C_MUX_CH_VOL_MONITOR, 0)) {
- vdd = read_voltage();
- if (vdd > 0)
- printf("Core voltage= %d mV\n", vdd);
- select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
- }
-
- printf("XVDD = 1.%d V\n", ((brdcfg[8] & 0xf) - 4) * 5 + 25);
-
- /* clock section */
- printf("SYSCLK = %s MHz\nDDRCLK = %s MHz\n",
- clk[(brdcfg[11] >> 2) & 0x3], clk[brdcfg[11] & 3]);
-
- /* RCW section */
- rcwsrc = (dutcfg[0] << 1) + (dutcfg[1] & 1);
- puts("RCW source = ");
- switch (rcwsrc) {
- case 0x017:
- case 0x01f:
- puts("8-bit NOR\n");
- break;
- case 0x027:
- case 0x02F:
- puts("16-bit NOR\n");
- break;
- case 0x040:
- puts("SDHC/eMMC\n");
- break;
- case 0x044:
- puts("SPI 16-bit addressing\n");
- break;
- case 0x045:
- puts("SPI 24-bit addressing\n");
- break;
- case 0x048:
- puts("I2C normal addressing\n");
- break;
- case 0x049:
- puts("I2C extended addressing\n");
- break;
- case 0x108:
- case 0x109:
- case 0x10a:
- case 0x10b:
- puts("8-bit NAND, 2KB\n");
- break;
- default:
- if ((rcwsrc >= 0x080) && (rcwsrc <= 0x09f))
- puts("Hard-coded RCW\n");
- else if ((rcwsrc >= 0x110) && (rcwsrc <= 0x11f))
- puts("8-bit NAND, 4KB\n");
- else
- puts("unknown\n");
- break;
- }
-
- /* Misc section */
- rst_ctl = QIXIS_READ(rst_ctl);
- puts("HRESET_REQ = ");
- switch (rst_ctl & 0x30) {
- case 0x00:
- puts("Ignored\n");
- break;
- case 0x10:
- puts("Assert HRESET\n");
- break;
- case 0x30:
- puts("Reset system\n");
- break;
- default:
- puts("N/A\n");
- break;
- }
-}
-
-/*
- * Reverse engineering switch settings.
- * Some bits cannot be figured out. They will be displayed as
- * underscore in binary format. mask[] has those bits.
- * Some bits are calculated differently than the actual switches
- * if booting with overriding by FPGA.
- */
-void qixis_dump_switch(void)
-{
- int i;
- u8 sw[9];
-
- /*
- * Any bit with 1 means that bit cannot be reverse engineered.
- * It will be displayed as _ in binary format.
- */
- static const u8 mask[] = {0, 0, 0, 0, 0, 0x1, 0xcf, 0x3f, 0x1f};
- char buf[10];
- u8 brdcfg[16], dutcfg[16];
-
- for (i = 0; i < 16; i++) {
- brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i);
- dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i);
- }
-
- sw[0] = dutcfg[0];
- sw[1] = (dutcfg[1] << 0x07) |
- ((dutcfg[12] & 0xC0) >> 1) |
- ((dutcfg[11] & 0xE0) >> 3) |
- ((dutcfg[6] & 0x80) >> 6) |
- ((dutcfg[1] & 0x80) >> 7);
- sw[2] = ((brdcfg[1] & 0x0f) << 4) |
- ((brdcfg[1] & 0x30) >> 2) |
- ((brdcfg[1] & 0x40) >> 5) |
- ((brdcfg[1] & 0x80) >> 7);
- sw[3] = brdcfg[2];
- sw[4] = ((dutcfg[2] & 0x01) << 7) |
- ((dutcfg[2] & 0x06) << 4) |
- ((~QIXIS_READ(present)) & 0x10) |
- ((brdcfg[3] & 0x80) >> 4) |
- ((brdcfg[3] & 0x01) << 2) |
- ((brdcfg[6] == 0x62) ? 3 :
- ((brdcfg[6] == 0x5a) ? 2 :
- ((brdcfg[6] == 0x5e) ? 1 : 0)));
- sw[5] = ((brdcfg[0] & 0x0f) << 4) |
- ((QIXIS_READ(rst_ctl) & 0x30) >> 2) |
- ((brdcfg[0] & 0x40) >> 5);
- sw[6] = (brdcfg[11] & 0x20) |
- ((brdcfg[5] & 0x02) << 3);
- sw[7] = (((~QIXIS_READ(rst_ctl)) & 0x40) << 1) |
- ((brdcfg[5] & 0x10) << 2);
- sw[8] = ((brdcfg[12] & 0x08) << 4) |
- ((brdcfg[12] & 0x03) << 5);
-
- puts("DIP switch (reverse-engineering)\n");
- for (i = 0; i < 9; i++) {
- printf("SW%d = 0b%s (0x%02x)\n",
- i + 1, byte_to_binary_mask(sw[i], mask[i], buf), sw[i]);
- }
-}
-
-static int do_vdd_adjust(struct cmd_tbl *cmdtp,
- int flag, int argc,
- char *const argv[])
-{
- ulong override;
-
- if (argc < 2)
- return CMD_RET_USAGE;
- if (!strict_strtoul(argv[1], 10, &override))
- adjust_vdd(override); /* the value is checked by callee */
- else
- return CMD_RET_USAGE;
-
- return 0;
-}
-
-U_BOOT_CMD(
- vdd_override, 2, 0, do_vdd_adjust,
- "Override VDD",
- "- override with the voltage specified in mV, eg. 1050"
-);
diff --git a/board/freescale/t4qds/t4240qds_qixis.h b/board/freescale/t4qds/t4240qds_qixis.h
deleted file mode 100644
index 52e8d5a7be..0000000000
--- a/board/freescale/t4qds/t4240qds_qixis.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2012 Freescale Semiconductor, Inc.
- */
-
-#ifndef __T4020QDS_QIXIS_H__
-#define __T4020QDS_QIXIS_H__
-
-/* Definitions of QIXIS Registers for T4020QDS */
-
-/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */
-#define BRDCFG4_EMISEL_MASK 0xE0
-#define BRDCFG4_EMISEL_SHIFT 5
-
-/* SYSCLK */
-#define QIXIS_SYSCLK_66 0x0
-#define QIXIS_SYSCLK_83 0x1
-#define QIXIS_SYSCLK_100 0x2
-#define QIXIS_SYSCLK_125 0x3
-#define QIXIS_SYSCLK_133 0x4
-#define QIXIS_SYSCLK_150 0x5
-#define QIXIS_SYSCLK_160 0x6
-#define QIXIS_SYSCLK_166 0x7
-
-/* DDRCLK */
-#define QIXIS_DDRCLK_66 0x0
-#define QIXIS_DDRCLK_100 0x1
-#define QIXIS_DDRCLK_125 0x2
-#define QIXIS_DDRCLK_133 0x3
-
-#define BRDCFG5_IRE 0x20 /* i2c Remote i2c1 enable */
-
-#define BRDCFG12_SD3EN_MASK 0x20
-#define BRDCFG12_SD3MX_MASK 0x08
-#define BRDCFG12_SD3MX_SLOT5 0x08
-#define BRDCFG12_SD3MX_SLOT6 0x00
-#define BRDCFG12_SD4EN_MASK 0x04
-#define BRDCFG12_SD4MX_MASK 0x03
-#define BRDCFG12_SD4MX_SLOT7 0x02
-#define BRDCFG12_SD4MX_SLOT8 0x01
-#define BRDCFG12_SD4MX_AURO_SATA 0x00
-#endif
diff --git a/board/freescale/t4qds/t4_nand_rcw.cfg b/board/freescale/t4qds/t4_nand_rcw.cfg
deleted file mode 100644
index 9386be0faa..0000000000
--- a/board/freescale/t4qds/t4_nand_rcw.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-#PBL preamble and RCW header
-aa55aa55 010e0100
-#serdes protocol 1_27_5_11
-1607001b 18101b16 00000000 00000000
-04362858 30548c00 e8020000 f5000000
-00000000 ee0000ee 00000000 000307fc
-00000000 00000000 00000000 00000028
diff --git a/board/freescale/t4qds/t4_pbi.cfg b/board/freescale/t4qds/t4_pbi.cfg
deleted file mode 100644
index 8d460039bf..0000000000
--- a/board/freescale/t4qds/t4_pbi.cfg
+++ /dev/null
@@ -1,21 +0,0 @@
-#PBI commands
-#Initialize CPC1
-09010000 00200400
-09138000 00000000
-091380c0 00000100
-#512KB SRAM
-09010100 00000000
-09010104 fff80009
-09010f00 08000000
-#enable CPC1
-09010000 80000000
-#Configure LAW for CPC1
-09000d00 00000000
-09000d04 fff80000
-09000d08 81000012
-#Configure alternate space
-09000010 00000000
-09000014 ff000000
-09000018 81000000
-#Flush PBL data
-091380c0 00100000
diff --git a/board/freescale/t4qds/t4_sd_rcw.cfg b/board/freescale/t4qds/t4_sd_rcw.cfg
deleted file mode 100644
index 54beb6783d..0000000000
--- a/board/freescale/t4qds/t4_sd_rcw.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-#PBL preamble and RCW header
-aa55aa55 010e0100
-#serdes protocol 1_27_5_11
-1607001b 18101b16 00000000 00000000
-04362858 30548c00 68020000 f5000000
-00000000 ee0000ee 00000000 000307fc
-00000000 00000000 00000000 00000028
diff --git a/board/freescale/t4qds/t4qds.h b/board/freescale/t4qds/t4qds.h
deleted file mode 100644
index 4a8e91b58f..0000000000
--- a/board/freescale/t4qds/t4qds.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2011-2012 Freescale Semiconductor, Inc.
- */
-
-#ifndef __CORENET_DS_H__
-#define __CORENET_DS_H__
-
-void fdt_fixup_board_enet(void *blob);
-void pci_of_setup(void *blob, bd_t *bd);
-
-#endif
diff --git a/board/freescale/t4qds/tlb.c b/board/freescale/t4qds/tlb.c
deleted file mode 100644
index cd5cf48def..0000000000
--- a/board/freescale/t4qds/tlb.c
+++ /dev/null
@@ -1,146 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008-2012 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
- /* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
-
- /* TLB 1 */
- /* *I*** - Covers boot page */
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
- /*
- * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
- * SRAM is at 0xfff00000, it covered the 0xfffff000.
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_1M, 1),
-#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
- /*
- * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the
- * space is at 0xfff00000, it covered the 0xfffff000.
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR,
- CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
- 0, 0, BOOKE_PAGESZ_1M, 1),
-#else
- SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_4K, 1),
-#endif
-
- /* *I*G* - CCSRBAR */
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 1, BOOKE_PAGESZ_16M, 1),
-
- /* *I*G* - Flash, localbus */
- /* This will be changed to *I*G* after relocation to RAM. */
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
- MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
- 0, 2, BOOKE_PAGESZ_256M, 1),
-#ifndef CONFIG_SPL_BUILD
- /* *I*G* - PCI */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 3, BOOKE_PAGESZ_1G, 1),
-
- /* *I*G* - PCI */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000,
- CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 4, BOOKE_PAGESZ_256M, 1),
-
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000,
- CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 5, BOOKE_PAGESZ_256M, 1),
-
- /* *I*G* - PCI I/O */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 6, BOOKE_PAGESZ_256K, 1),
-
- /* Bman/Qman */
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
- SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 9, BOOKE_PAGESZ_16M, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
- CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 10, BOOKE_PAGESZ_16M, 1),
-#endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
- SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 11, BOOKE_PAGESZ_16M, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
- CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 12, BOOKE_PAGESZ_16M, 1),
-#endif
-#endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
- SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 13, BOOKE_PAGESZ_32M, 1),
-#endif
-#ifdef CONFIG_SYS_NAND_BASE
- /*
- * *I*G - NAND
- * entry 14 and 15 has been used hard coded, they will be disabled
- * in cpu_init_f, so we use entry 16 for nand.
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 16, BOOKE_PAGESZ_64K, 1),
-#endif
-#ifdef QIXIS_BASE_PHYS
- SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 17, BOOKE_PAGESZ_4K, 1),
-#endif
-#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
- /*
- * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for
- * fetching ucode and ENV from master
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR,
- CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
- 0, 18, BOOKE_PAGESZ_1M, 1),
-#endif
-
-#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
- SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
- 0, 19, BOOKE_PAGESZ_2G, 1)
-#endif
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/configs/T4160QDS_NAND_defconfig b/configs/T4160QDS_NAND_defconfig
deleted file mode 100644
index ddff89602f..0000000000
--- a/configs/T4160QDS_NAND_defconfig
+++ /dev/null
@@ -1,69 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x00201000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x140000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T4160QDS=y
-CONFIG_SYS_CUSTOM_LDSCRIPT=y
-CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_NAND_BOOT=y
-CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T4160QDS_SDCARD_defconfig b/configs/T4160QDS_SDCARD_defconfig
deleted file mode 100644
index 5d253534ca..0000000000
--- a/configs/T4160QDS_SDCARD_defconfig
+++ /dev/null
@@ -1,66 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x00201000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T4160QDS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_MMC_BOOT=y
-CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T4160QDS_SECURE_BOOT_defconfig b/configs/T4160QDS_SECURE_BOOT_defconfig
deleted file mode 100644
index 8934c3edf0..0000000000
--- a/configs/T4160QDS_SECURE_BOOT_defconfig
+++ /dev/null
@@ -1,56 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T4160QDS=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T4160QDS_defconfig b/configs/T4160QDS_defconfig
deleted file mode 100644
index d0d1290631..0000000000
--- a/configs/T4160QDS_defconfig
+++ /dev/null
@@ -1,53 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T4160QDS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T4240QDS_NAND_defconfig b/configs/T4240QDS_NAND_defconfig
deleted file mode 100644
index f971cee3b0..0000000000
--- a/configs/T4240QDS_NAND_defconfig
+++ /dev/null
@@ -1,69 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x00201000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x140000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T4240QDS=y
-CONFIG_SYS_CUSTOM_LDSCRIPT=y
-CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_NAND_BOOT=y
-CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T4240QDS_SDCARD_defconfig b/configs/T4240QDS_SDCARD_defconfig
deleted file mode 100644
index 5e662be1d7..0000000000
--- a/configs/T4240QDS_SDCARD_defconfig
+++ /dev/null
@@ -1,66 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x00201000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T4240QDS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_MMC_BOOT=y
-CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T4240QDS_SECURE_BOOT_defconfig b/configs/T4240QDS_SECURE_BOOT_defconfig
deleted file mode 100644
index 807d5b5895..0000000000
--- a/configs/T4240QDS_SECURE_BOOT_defconfig
+++ /dev/null
@@ -1,56 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T4240QDS=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T4240QDS_SRIO_PCIE_BOOT_defconfig b/configs/T4240QDS_SRIO_PCIE_BOOT_defconfig
deleted file mode 100644
index 2bc30bbf9e..0000000000
--- a/configs/T4240QDS_SRIO_PCIE_BOOT_defconfig
+++ /dev/null
@@ -1,49 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T4240QDS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_GREPENV=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_IS_IN_REMOTE=y
-CONFIG_ENV_ADDR=0xFFE20000
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_REMOTE=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T4240QDS_defconfig b/configs/T4240QDS_defconfig
deleted file mode 100644
index 84341f7579..0000000000
--- a/configs/T4240QDS_defconfig
+++ /dev/null
@@ -1,53 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T4240QDS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h
deleted file mode 100644
index d92af7202b..0000000000
--- a/include/configs/T4240QDS.h
+++ /dev/null
@@ -1,555 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2011-2012 Freescale Semiconductor, Inc.
- */
-
-/*
- * T4240 QDS board configuration file
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <linux/stringify.h>
-
-#define CONFIG_FSL_SATA_V2
-#define CONFIG_PCIE4
-
-#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
-
-#ifdef CONFIG_RAMBOOT_PBL
-#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t4qds/t4_pbi.cfg
-#if !defined(CONFIG_MTD_RAW_NAND) && !defined(CONFIG_SDCARD)
-#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
-#else
-#define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_PAD_TO 0x40000
-#define CONFIG_SPL_MAX_SIZE 0x28000
-#define RESET_VECTOR_OFFSET 0x27FFC
-#define BOOT_PAGE_OFFSET 0x27000
-
-#ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
-#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
-#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_nand_rcw.cfg
-#endif
-
-#ifdef CONFIG_SDCARD
-#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
-#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
-#define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000
-#define CONFIG_SYS_MMC_U_BOOT_START 0x00200000
-#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_SYS_MPC85XX_NO_RESETVEC
-#endif
-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_sd_rcw.cfg
-#endif
-
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SPL_SKIP_RELOCATE
-#define CONFIG_SPL_COMMON_INIT_DDR
-#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
-#endif
-
-#endif
-#endif /* CONFIG_RAMBOOT_PBL */
-
-#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
-/* Set 1M boot space */
-#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
-#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
- (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
-#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
-#endif
-
-#define CONFIG_SRIO_PCIE_BOOT_MASTER
-#define CONFIG_DDR_ECC
-
-#include "t4qds.h"
-
-#if defined(CONFIG_SPIFLASH)
-#elif defined(CONFIG_SDCARD)
-#define CONFIG_SYS_MMC_ENV_DEV 0
-#endif
-
-#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
-#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
-
-#ifndef __ASSEMBLY__
-unsigned long get_board_sys_clk(void);
-unsigned long get_board_ddr_clk(void);
-#endif
-
-/* EEPROM */
-#define CONFIG_ID_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#define CONFIG_SYS_EEPROM_BUS_NUM 0
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-
-/*
- * DDR Setup
- */
-#define CONFIG_SYS_SPD_BUS_NUM 0
-#define SPD_EEPROM_ADDRESS1 0x51
-#define SPD_EEPROM_ADDRESS2 0x52
-#define SPD_EEPROM_ADDRESS3 0x53
-#define SPD_EEPROM_ADDRESS4 0x54
-#define SPD_EEPROM_ADDRESS5 0x55
-#define SPD_EEPROM_ADDRESS6 0x56
-#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
-#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
-
-/*
- * IFC Definitions
- */
-#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
-#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
- + 0x8000000) | \
- CSPR_PORT_SIZE_16 | \
- CSPR_MSEL_NOR | \
- CSPR_V)
-#define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
-#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
- CSPR_PORT_SIZE_16 | \
- CSPR_MSEL_NOR | \
- CSPR_V)
-#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
-/* NOR Flash Timing Params */
-#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
-
-#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
- FTIM0_NOR_TEADC(0x5) | \
- FTIM0_NOR_TEAHC(0x5))
-#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
- FTIM1_NOR_TRAD_NOR(0x1A) |\
- FTIM1_NOR_TSEQRAD_NOR(0x13))
-#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
- FTIM2_NOR_TCH(0x4) | \
- FTIM2_NOR_TWPH(0x0E) | \
- FTIM2_NOR_TWP(0x1c))
-#define CONFIG_SYS_NOR_FTIM3 0x0
-
-#define CONFIG_SYS_FLASH_QUIET_TEST
-#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
- + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
-
-#define CONFIG_FSL_QIXIS /* use common QIXIS code */
-#define QIXIS_BASE 0xffdf0000
-#define QIXIS_LBMAP_SWITCH 6
-#define QIXIS_LBMAP_MASK 0x0f
-#define QIXIS_LBMAP_SHIFT 0
-#define QIXIS_LBMAP_DFLTBANK 0x00
-#define QIXIS_LBMAP_ALTBANK 0x04
-#define QIXIS_RST_CTL_RESET 0x83
-#define QIXIS_RST_FORCE_MEM 0x1
-#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
-#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
-#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
-#define QIXIS_BRDCFG5 0x55
-#define QIXIS_MUX_SDHC 2
-#define QIXIS_MUX_SDHC_WIDTH8 1
-#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
-
-#define CONFIG_SYS_CSPR3_EXT (0xf)
-#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
- | CSPR_PORT_SIZE_8 \
- | CSPR_MSEL_GPCM \
- | CSPR_V)
-#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_CSOR3 0x0
-/* QIXIS Timing parameters for IFC CS3 */
-#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
- FTIM0_GPCM_TEADC(0x0e) | \
- FTIM0_GPCM_TEAHC(0x0e))
-#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
- FTIM1_GPCM_TRAD(0x3f))
-#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
- FTIM2_GPCM_TCH(0x8) | \
- FTIM2_GPCM_TWP(0x1f))
-#define CONFIG_SYS_CS3_FTIM3 0x0
-
-/* NAND Flash on IFC */
-#define CONFIG_NAND_FSL_IFC
-#define CONFIG_SYS_NAND_BASE 0xff800000
-#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
-
-#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
-#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
- | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
- | CSPR_MSEL_NAND /* MSEL = NAND */ \
- | CSPR_V)
-#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
-
-#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
- | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
- | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
- | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
- | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
- | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
- | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
-
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-
-/* ONFI NAND Flash mode0 Timing Params */
-#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
- FTIM0_NAND_TWP(0x18) | \
- FTIM0_NAND_TWCHT(0x07) | \
- FTIM0_NAND_TWH(0x0a))
-#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
- FTIM1_NAND_TWBE(0x39) | \
- FTIM1_NAND_TRR(0x0e) | \
- FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
- FTIM2_NAND_TREH(0x0a) | \
- FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3 0x0
-
-#define CONFIG_SYS_NAND_DDR_LAW 11
-
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
-#define CONFIG_SYS_NAND_MAX_OOBFREE 2
-#define CONFIG_SYS_NAND_MAX_ECCPOS 256
-
-#if defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
-#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
-#else
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
-#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
-#endif
-
-#if defined(CONFIG_RAMBOOT_PBL)
-#define CONFIG_SYS_RAMBOOT
-#endif
-
-/* I2C */
-#ifndef CONFIG_DM_I2C
-#define CONFIG_SYS_I2C
-#else
-#undef CONFIG_SYS_I2C
-#undef CONFIG_SYS_FSL_I2C2_OFFSET
-#undef CONFIG_SYS_FSL_I2C2_SLAVE
-#undef CONFIG_SYS_FSL_I2C2_SPEED
-#undef CONFIG_SYS_FSL_I2C_SLAVE
-#undef CONFIG_SYS_FSL_I2C_SPEED
-#undef CONFIG_SYS_FSL_I2C_OFFSET
-#endif
-
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */
-#define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */
-#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
-#define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */
-
-#define I2C_MUX_CH_DEFAULT 0x8
-#define I2C_MUX_CH_VOL_MONITOR 0xa
-#define I2C_MUX_CH_VSC3316_FS 0xc
-#define I2C_MUX_CH_VSC3316_BS 0xd
-
-/* Voltage monitor on channel 2*/
-#define I2C_VOL_MONITOR_ADDR 0x40
-#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
-#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
-#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
-
-/* VSC Crossbar switches */
-#define CONFIG_VSC_CROSSBAR
-#define VSC3316_FSM_TX_ADDR 0x70
-#define VSC3316_FSM_RX_ADDR 0x71
-
-/*
- * RapidIO
- */
-
-/*
- * for slave u-boot IMAGE instored in master memory space,
- * PHYS must be aligned based on the SIZE
- */
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
-/*
- * for slave UCODE and ENV instored in master memory space,
- * PHYS must be aligned based on the SIZE
- */
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
-
-/* slave core release by master*/
-#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
-#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
-
-/*
- * SRIO_PCIE_BOOT - SLAVE
- */
-#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
-#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
-#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
- (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
-#endif
-/*
- * eSPI - Enhanced SPI
- */
-
-/* Qman/Bman */
-#ifndef CONFIG_NOBQFMAN
-#define CONFIG_SYS_BMAN_NUM_PORTALS 50
-#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
-#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
-#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
-#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
-#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
-#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
-#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
- CONFIG_SYS_BMAN_CENA_SIZE)
-#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
-#define CONFIG_SYS_QMAN_NUM_PORTALS 50
-#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
-#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
-#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
-#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
-#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
-#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
-#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
- CONFIG_SYS_QMAN_CENA_SIZE)
-#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
-
-#define CONFIG_SYS_DPAA_FMAN
-#define CONFIG_SYS_DPAA_PME
-#define CONFIG_SYS_PMAN
-#define CONFIG_SYS_DPAA_DCE
-#define CONFIG_SYS_DPAA_RMAN
-#define CONFIG_SYS_INTERLAKEN
-
-/* Default address of microcode for the Linux Fman driver */
-#if defined(CONFIG_SPIFLASH)
-/*
- * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
- * env, so we got 0x110000.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
-#elif defined(CONFIG_SDCARD)
-/*
- * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
- * about 1MB (2048 blocks), Env is stored after the image, and the env size is
- * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
-#elif defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
-#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
-/*
- * Slave has no ucode locally, it can fetch this from remote. When implementing
- * in two corenet boards, slave's ucode could be stored in master's memory
- * space, the address can be mapped from slave TLB->slave LAW->
- * slave SRIO or PCIE outbound window->master inbound window->
- * master LAW->the ucode address in master's memory space.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
-#else
-#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
-#endif
-#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
-#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
-#endif /* CONFIG_NOBQFMAN */
-
-#ifdef CONFIG_SYS_DPAA_FMAN
-#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
-#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
-#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
-#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
-#define FM1_10GEC1_PHY_ADDR 0x0
-#define FM1_10GEC2_PHY_ADDR 0x1
-#define FM2_10GEC1_PHY_ADDR 0x2
-#define FM2_10GEC2_PHY_ADDR 0x3
-#endif
-
-/* SATA */
-#ifdef CONFIG_FSL_SATA_V2
-#define CONFIG_SYS_SATA_MAX_DEVICE 2
-#define CONFIG_SATA1
-#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
-#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
-#define CONFIG_SATA2
-#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
-#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
-
-#define CONFIG_LBA48
-#endif
-
-#ifdef CONFIG_FMAN_ENET
-#define CONFIG_ETHPRIME "FM1 at DTSEC1"
-#endif
-
-/*
-* USB
-*/
-#define CONFIG_USB_EHCI_FSL
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_HAS_FSL_DR_USB
-
-#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
-#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
-#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
-#define CONFIG_ESDHC_DETECT_QUIRK \
- (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC) || \
- IS_SVR_REV(get_svr(), 1, 0))
-#define CONFIG_ESDHC_DETECT_8_BIT_QUIRK \
- (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC_WIDTH8))
-#endif
-
-
-#define __USB_PHY_TYPE utmi
-
-/*
- * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
- * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
- * interleaving. It can be cacheline, page, bank, superbank.
- * See doc/README.fsl-ddr for details.
- */
-#ifdef CONFIG_ARCH_T4240
-#define CTRL_INTLV_PREFERED 3way_4KB
-#else
-#define CTRL_INTLV_PREFERED cacheline
-#endif
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "hwconfig=fsl_ddr:" \
- "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
- "bank_intlv=auto;" \
- "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
- "netdev=eth0\0" \
- "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
- "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
- "tftpflash=tftpboot $loadaddr $uboot && " \
- "protect off $ubootaddr +$filesize && " \
- "erase $ubootaddr +$filesize && " \
- "cp.b $loadaddr $ubootaddr $filesize && " \
- "protect on $ubootaddr +$filesize && " \
- "cmp.b $loadaddr $ubootaddr $filesize\0" \
- "consoledev=ttyS0\0" \
- "ramdiskaddr=2000000\0" \
- "ramdiskfile=t4240qds/ramdisk.uboot\0" \
- "fdtaddr=1e00000\0" \
- "fdtfile=t4240qds/t4240qds.dtb\0" \
- "bdev=sda3\0"
-
-#define CONFIG_HVBOOT \
- "setenv bootargs config-addr=0x60000000; " \
- "bootm 0x01000000 - 0x00f00000"
-
-#define CONFIG_ALU \
- "setenv bootargs root=/dev/$bdev rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "cpu 1 release 0x01000000 - - -;" \
- "cpu 2 release 0x01000000 - - -;" \
- "cpu 3 release 0x01000000 - - -;" \
- "cpu 4 release 0x01000000 - - -;" \
- "cpu 5 release 0x01000000 - - -;" \
- "cpu 6 release 0x01000000 - - -;" \
- "cpu 7 release 0x01000000 - - -;" \
- "go 0x01000000"
-
-#define CONFIG_LINUX \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "setenv ramdiskaddr 0x02000000;" \
- "setenv fdtaddr 0x00c00000;" \
- "setenv loadaddr 0x1000000;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_HDBOOT \
- "setenv bootargs root=/dev/$bdev rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND CONFIG_LINUX
-
-#include <asm/fsl_secure_boot.h>
-
-#endif /* __CONFIG_H */
--
2.25.1
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 19/24] arm: Remove configs/T4160RDB_defconfig board
2020-05-27 16:46 [PATCH 00/24] spi: dm-conversion (part2) Jagan Teki
` (17 preceding siblings ...)
2020-05-27 16:46 ` [PATCH 18/24] arm: Remove configs/T4160QDS_NAND_defconfig board Jagan Teki
@ 2020-05-27 16:46 ` Jagan Teki
2020-05-28 7:04 ` Priyanka Jain
2020-05-27 16:46 ` [PATCH 20/24] arm: Remove configs/TWR-P1025_defconfig board Jagan Teki
` (3 subsequent siblings)
22 siblings, 1 reply; 59+ messages in thread
From: Jagan Teki @ 2020-05-27 16:46 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_SPI by the deadline.
Remove it.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
arch/powerpc/cpu/mpc85xx/Kconfig | 1 -
board/freescale/t4rdb/Kconfig | 14 -
board/freescale/t4rdb/MAINTAINERS | 8 -
board/freescale/t4rdb/Makefile | 19 -
board/freescale/t4rdb/cpld.c | 129 ------
board/freescale/t4rdb/cpld.h | 48 --
board/freescale/t4rdb/ddr.c | 127 ------
board/freescale/t4rdb/ddr.h | 77 ----
board/freescale/t4rdb/eth.c | 152 -------
board/freescale/t4rdb/law.c | 30 --
board/freescale/t4rdb/pci.c | 25 -
board/freescale/t4rdb/spl.c | 99 ----
board/freescale/t4rdb/t4240rdb.c | 150 ------
board/freescale/t4rdb/t4_pbi.cfg | 27 --
board/freescale/t4rdb/t4_sd_rcw.cfg | 7 -
board/freescale/t4rdb/t4rdb.h | 17 -
board/freescale/t4rdb/tlb.c | 123 -----
configs/T4160RDB_defconfig | 54 ---
configs/T4240RDB_SDCARD_defconfig | 74 ---
configs/T4240RDB_defconfig | 62 ---
include/configs/T4240RDB.h | 681 ----------------------------
21 files changed, 1924 deletions(-)
delete mode 100644 board/freescale/t4rdb/Kconfig
delete mode 100644 board/freescale/t4rdb/MAINTAINERS
delete mode 100644 board/freescale/t4rdb/Makefile
delete mode 100644 board/freescale/t4rdb/cpld.c
delete mode 100644 board/freescale/t4rdb/cpld.h
delete mode 100644 board/freescale/t4rdb/ddr.c
delete mode 100644 board/freescale/t4rdb/ddr.h
delete mode 100644 board/freescale/t4rdb/eth.c
delete mode 100644 board/freescale/t4rdb/law.c
delete mode 100644 board/freescale/t4rdb/pci.c
delete mode 100644 board/freescale/t4rdb/spl.c
delete mode 100644 board/freescale/t4rdb/t4240rdb.c
delete mode 100644 board/freescale/t4rdb/t4_pbi.cfg
delete mode 100644 board/freescale/t4rdb/t4_sd_rcw.cfg
delete mode 100644 board/freescale/t4rdb/t4rdb.h
delete mode 100644 board/freescale/t4rdb/tlb.c
delete mode 100644 configs/T4160RDB_defconfig
delete mode 100644 configs/T4240RDB_SDCARD_defconfig
delete mode 100644 configs/T4240RDB_defconfig
delete mode 100644 include/configs/T4240RDB.h
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index b429e41515..337bf83835 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -1599,7 +1599,6 @@ source "board/freescale/mpc8572ds/Kconfig"
source "board/freescale/p1023rdb/Kconfig"
source "board/freescale/p1_twr/Kconfig"
source "board/freescale/qemu-ppce500/Kconfig"
-source "board/freescale/t4rdb/Kconfig"
source "board/gdsys/p1022/Kconfig"
source "board/keymile/Kconfig"
source "board/sbc8548/Kconfig"
diff --git a/board/freescale/t4rdb/Kconfig b/board/freescale/t4rdb/Kconfig
deleted file mode 100644
index a94a57e7fe..0000000000
--- a/board/freescale/t4rdb/Kconfig
+++ /dev/null
@@ -1,14 +0,0 @@
-if TARGET_T4160RDB || TARGET_T4240RDB
-
-config SYS_BOARD
- default "t4rdb"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "T4240RDB"
-
-source "board/freescale/common/Kconfig"
-
-endif
diff --git a/board/freescale/t4rdb/MAINTAINERS b/board/freescale/t4rdb/MAINTAINERS
deleted file mode 100644
index 4ba5c3a546..0000000000
--- a/board/freescale/t4rdb/MAINTAINERS
+++ /dev/null
@@ -1,8 +0,0 @@
-T4RDB BOARD
-#M: Chunhe Lan <Chunhe.Lan@freescale.com>
-S: Orphan (since 2018-05)
-F: board/freescale/t4rdb/
-F: include/configs/T4240RDB.h
-F: configs/T4160RDB_defconfig
-F: configs/T4240RDB_defconfig
-F: configs/T4240RDB_SDCARD_defconfig
diff --git a/board/freescale/t4rdb/Makefile b/board/freescale/t4rdb/Makefile
deleted file mode 100644
index 209983a24b..0000000000
--- a/board/freescale/t4rdb/Makefile
+++ /dev/null
@@ -1,19 +0,0 @@
-#
-# Copyright 2014 Freescale Semiconductor, Inc.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-ifdef CONFIG_SPL_BUILD
-obj-y += spl.o
-else
-obj-$(CONFIG_TARGET_T4160RDB) += t4240rdb.o
-obj-$(CONFIG_TARGET_T4240RDB) += t4240rdb.o
-obj-y += cpld.o
-obj-y += eth.o
-obj-$(CONFIG_PCI) += pci.o
-endif
-
-obj-y += ddr.o
-obj-y += law.o
-obj-y += tlb.o
diff --git a/board/freescale/t4rdb/cpld.c b/board/freescale/t4rdb/cpld.c
deleted file mode 100644
index d484509bc2..0000000000
--- a/board/freescale/t4rdb/cpld.c
+++ /dev/null
@@ -1,129 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/**
- * Copyright 2014 Freescale Semiconductor
- *
- * Author: Chunhe Lan <Chunhe.Lan@freescale.com>
- *
- * This file provides support for the board-specific CPLD used on some Freescale
- * reference boards.
- *
- * The following macros need to be defined:
- *
- * CONFIG_SYS_CPLD_BASE - The virtual address of the base of the
- * CPLD register map
- *
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/io.h>
-
-#include "cpld.h"
-
-u8 cpld_read(unsigned int reg)
-{
- void *p = (void *)CONFIG_SYS_CPLD_BASE;
-
- return in_8(p + reg);
-}
-
-void cpld_write(unsigned int reg, u8 value)
-{
- void *p = (void *)CONFIG_SYS_CPLD_BASE;
-
- out_8(p + reg, value);
-}
-
-/**
- * Set the boot bank to the alternate bank
- */
-void cpld_set_altbank(void)
-{
- u8 val, curbank, altbank, override;
-
- val = CPLD_READ(vbank);
- curbank = val & CPLD_BANK_SEL_MASK;
-
- switch (curbank) {
- case CPLD_SELECT_BANK0:
- case CPLD_SELECT_BANK4:
- altbank = CPLD_SELECT_BANK4;
- CPLD_WRITE(vbank, altbank);
- override = CPLD_READ(software_on);
- CPLD_WRITE(software_on, override | CPLD_BANK_SEL_EN);
- CPLD_WRITE(sys_reset, CPLD_SYSTEM_RESET);
- break;
- default:
- printf("CPLD Altbank Fail: Invalid value!\n");
- return;
- }
-}
-
-/**
- * Set the boot bank to the default bank
- */
-void cpld_set_defbank(void)
-{
- u8 val;
-
- val = CPLD_DEFAULT_BANK;
-
- CPLD_WRITE(global_reset, val);
-}
-
-#ifdef DEBUG
-static void cpld_dump_regs(void)
-{
- printf("chip_id1 = 0x%02x\n", CPLD_READ(chip_id1));
- printf("chip_id2 = 0x%02x\n", CPLD_READ(chip_id2));
- printf("sw_maj_ver = 0x%02x\n", CPLD_READ(sw_maj_ver));
- printf("sw_min_ver = 0x%02x\n", CPLD_READ(sw_min_ver));
- printf("hw_ver = 0x%02x\n", CPLD_READ(hw_ver));
- printf("software_on = 0x%02x\n", CPLD_READ(software_on));
- printf("cfg_rcw_src = 0x%02x\n", CPLD_READ(cfg_rcw_src));
- printf("res0 = 0x%02x\n", CPLD_READ(res0));
- printf("vbank = 0x%02x\n", CPLD_READ(vbank));
- printf("sw1_sysclk = 0x%02x\n", CPLD_READ(sw1_sysclk));
- printf("sw2_status = 0x%02x\n", CPLD_READ(sw2_status));
- printf("sw3_status = 0x%02x\n", CPLD_READ(sw3_status));
- printf("sw4_status = 0x%02x\n", CPLD_READ(sw4_status));
- printf("sys_reset = 0x%02x\n", CPLD_READ(sys_reset));
- printf("global_reset = 0x%02x\n", CPLD_READ(global_reset));
- printf("res1 = 0x%02x\n", CPLD_READ(res1));
- putc('\n');
-}
-#endif
-
-#ifndef CONFIG_SPL_BUILD
-int do_cpld(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
-{
- int rc = 0;
-
- if (argc <= 1)
- return cmd_usage(cmdtp);
-
- if (strcmp(argv[1], "reset") == 0) {
- if (strcmp(argv[2], "altbank") == 0)
- cpld_set_altbank();
- else
- cpld_set_defbank();
-#ifdef DEBUG
- } else if (strcmp(argv[1], "dump") == 0) {
- cpld_dump_regs();
-#endif
- } else
- rc = cmd_usage(cmdtp);
-
- return rc;
-}
-
-U_BOOT_CMD(
- cpld, CONFIG_SYS_MAXARGS, 1, do_cpld,
- "Reset the board or alternate bank",
- "reset - reset to default bank\n"
- "cpld reset altbank - reset to alternate bank\n"
-#ifdef DEBUG
- "cpld dump - display the CPLD registers\n"
-#endif
- );
-#endif
diff --git a/board/freescale/t4rdb/cpld.h b/board/freescale/t4rdb/cpld.h
deleted file mode 100644
index dc3f9f3c26..0000000000
--- a/board/freescale/t4rdb/cpld.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/**
- * Copyright 2014 Freescale Semiconductor
- *
- * Author: Chunhe Lan <Chunhe.Lan@freescale.com>
- *
- * This file provides support for the ngPIXIS, a board-specific FPGA used on
- * some Freescale reference boards.
- */
-
-/*
- * CPLD register set. Feel free to add board-specific #ifdefs where necessary.
- */
-struct cpld_data {
- u8 chip_id1; /* 0x00 - CPLD Chip ID1 Register */
- u8 chip_id2; /* 0x01 - CPLD Chip ID2 Register */
- u8 sw_maj_ver; /* 0x02 - CPLD Code Major Version Register */
- u8 sw_min_ver; /* 0x03 - CPLD Code Minor Version Register */
- u8 hw_ver; /* 0x04 - PCBA Version Register */
- u8 software_on; /* 0x05 - Override Physical Switch Enable Register */
- u8 cfg_rcw_src; /* 0x06 - RCW Source Location Control Register */
- u8 res0; /* 0x07 - not used */
- u8 vbank; /* 0x08 - Flash Bank Selection Control Register */
- u8 sw1_sysclk; /* 0x09 - SW1 Status Read Back Register */
- u8 sw2_status; /* 0x0a - SW2 Status Read Back Register */
- u8 sw3_status; /* 0x0b - SW3 Status Read Back Register */
- u8 sw4_status; /* 0x0c - SW4 Status Read Back Register */
- u8 sys_reset; /* 0x0d - Reset System With Reserving Registers Value*/
- u8 global_reset;/* 0x0e - Reset System With Default Registers Value */
- u8 res1; /* 0x0f - not used */
-};
-
-#define CPLD_BANK_SEL_MASK 0x07
-#define CPLD_BANK_SEL_EN 0x04
-#define CPLD_SYSTEM_RESET 0x01
-#define CPLD_SELECT_BANK0 0x00
-#define CPLD_SELECT_BANK4 0x04
-#define CPLD_DEFAULT_BANK 0x01
-
-/* Pointer to the CPLD register set */
-
-u8 cpld_read(unsigned int reg);
-void cpld_write(unsigned int reg, u8 value);
-
-#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg))
-#define CPLD_WRITE(reg, value) \
- cpld_write(offsetof(struct cpld_data, reg), value)
-
diff --git a/board/freescale/t4rdb/ddr.c b/board/freescale/t4rdb/ddr.c
deleted file mode 100644
index 5b7d10c979..0000000000
--- a/board/freescale/t4rdb/ddr.c
+++ /dev/null
@@ -1,127 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <hwconfig.h>
-#include <init.h>
-#include <log.h>
-#include <asm/mmu.h>
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-#include <asm/fsl_law.h>
-#include "ddr.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
- ulong ddr_freq;
-
- if (ctrl_num > 2) {
- printf("Not supported controller number %d\n", ctrl_num);
- return;
- }
- if (!pdimm->n_ranks)
- return;
-
- /*
- * we use identical timing for all slots. If needed, change the code
- * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
- */
- if (popts->registered_dimm_en)
- pbsp = rdimms[0];
- else
- pbsp = udimms[0];
-
-
- /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
- * freqency and n_banks specified in board_specific_parameters table.
- */
- ddr_freq = get_ddr_freq(0) / 1000000;
- while (pbsp->datarate_mhz_high) {
- if (pbsp->n_ranks == pdimm->n_ranks &&
- (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
- if (ddr_freq <= pbsp->datarate_mhz_high) {
- popts->clk_adjust = pbsp->clk_adjust;
- popts->wrlvl_start = pbsp->wrlvl_start;
- popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
- popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
- goto found;
- }
- pbsp_highest = pbsp;
- }
- pbsp++;
- }
-
- if (pbsp_highest) {
- printf("Error: board specific timing not found for data\n"
- "rate %lu MT/s\n"
- "Trying to use the highest speed (%u) parameters\n",
- ddr_freq, pbsp_highest->datarate_mhz_high);
- popts->clk_adjust = pbsp_highest->clk_adjust;
- popts->wrlvl_start = pbsp_highest->wrlvl_start;
- popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
- popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
- } else {
- panic("DIMM is not supported by this board");
- }
-found:
- debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
- "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x,\n"
- "wrlvl_ctrl_3 0x%x\n",
- pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
- pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
- pbsp->wrlvl_ctl_3);
-
- /*
- * Factors to consider for half-strength driver enable:
- * - number of DIMMs installed
- */
- popts->half_strength_driver_enable = 0;
- /*
- * Write leveling override
- */
- popts->wrlvl_override = 1;
- popts->wrlvl_sample = 0xf;
-
- /*
- * Rtt and Rtt_WR override
- */
- popts->rtt_override = 0;
-
- /* Enable ZQ calibration */
- popts->zq_en = 1;
-
- /* DHC_EN =1, ODT = 75 Ohm */
- popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
- popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
-
- /* optimize cpo for erratum A-009942 */
- popts->cpo_sample = 0x64;
-}
-
-int dram_init(void)
-{
- phys_size_t dram_size;
-
- puts("Initializing....using SPD\n");
-
-#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
- dram_size = fsl_ddr_sdram();
-#else
- /* DDR has been initialised by first stage boot loader */
- dram_size = fsl_ddr_sdram_size();
-#endif
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
-
- gd->ram_size = dram_size;
-
- return 0;
-}
diff --git a/board/freescale/t4rdb/ddr.h b/board/freescale/t4rdb/ddr.h
deleted file mode 100644
index 74a2779611..0000000000
--- a/board/freescale/t4rdb/ddr.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- */
-
-#ifndef __DDR_H__
-#define __DDR_H__
-struct board_specific_parameters {
- u32 n_ranks;
- u32 datarate_mhz_high;
- u32 rank_gb;
- u32 clk_adjust;
- u32 wrlvl_start;
- u32 wrlvl_ctl_2;
- u32 wrlvl_ctl_3;
-};
-
-/*
- * These tables contain all valid speeds we want to override with board
- * specific parameters. datarate_mhz_high values need to be in ascending order
- * for each n_ranks group.
- */
-static const struct board_specific_parameters udimm0[] = {
- /*
- * memory controller 0
- * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
- * ranks| mhz| GB |adjst| start | ctl2 | ctl3
- */
- {2, 1350, 4, 8, 8, 0x0809090b, 0x0c0c0d0a},
- {2, 1350, 0, 10, 7, 0x0709090b, 0x0c0c0d09},
- {2, 1666, 4, 8, 8, 0x080a0a0d, 0x0d10100b},
- {2, 1666, 0, 10, 7, 0x080a0a0c, 0x0d0d0e0a},
- {2, 1900, 0, 8, 8, 0x090a0b0e, 0x0f11120c},
- {2, 2140, 0, 8, 8, 0x090a0b0e, 0x0f11120c},
- {1, 1350, 0, 10, 8, 0x0809090b, 0x0c0c0d0a},
- {1, 1700, 0, 10, 8, 0x080a0a0c, 0x0c0d0e0a},
- {1, 1900, 0, 8, 8, 0x080a0a0c, 0x0e0e0f0a},
- {1, 2140, 0, 8, 8, 0x090a0b0c, 0x0e0f100b},
- {}
-};
-
-static const struct board_specific_parameters rdimm0[] = {
- /*
- * memory controller 0
- * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
- * ranks| mhz| GB |adjst| start | ctl2 | ctl3
- */
- {4, 1350, 0, 10, 9, 0x08070605, 0x06070806},
- {4, 1666, 0, 10, 11, 0x0a080706, 0x07090906},
- {4, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07},
- {2, 1350, 0, 10, 9, 0x08070605, 0x06070806},
- {2, 1666, 0, 10, 11, 0x0a090806, 0x08090a06},
- {2, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07},
- {1, 1350, 0, 10, 9, 0x08070605, 0x06070806},
- {1, 1666, 0, 10, 11, 0x0a090806, 0x08090a06},
- {1, 2140, 0, 8, 12, 0x0b090807, 0x080a0b07},
- {}
-};
-
-/*
- * The three slots have slightly different timing. The center values are good
- * for all slots. We use identical speed tables for them. In future use, if
- * DIMMs require separated tables, make more entries as needed.
- */
-static const struct board_specific_parameters *udimms[] = {
- udimm0,
-};
-
-/*
- * The three slots have slightly different timing. See comments above.
- */
-static const struct board_specific_parameters *rdimms[] = {
- rdimm0,
-};
-
-
-#endif
diff --git a/board/freescale/t4rdb/eth.c b/board/freescale/t4rdb/eth.c
deleted file mode 100644
index 4c896c8a90..0000000000
--- a/board/freescale/t4rdb/eth.c
+++ /dev/null
@@ -1,152 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- *
- * Chunhe Lan <Chunhe.Lan@freescale.com>
- */
-
-#include <common.h>
-#include <command.h>
-#include <fdt_support.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/mmu.h>
-#include <asm/processor.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_law.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/fsl_serdes.h>
-#include <asm/fsl_portals.h>
-#include <asm/fsl_liodn.h>
-#include <malloc.h>
-#include <fm_eth.h>
-#include <fsl_mdio.h>
-#include <miiphy.h>
-#include <phy.h>
-#include <fsl_dtsec.h>
-#include <asm/fsl_serdes.h>
-#include <hwconfig.h>
-
-#include "../common/fman.h"
-#include "t4rdb.h"
-
-void fdt_fixup_board_enet(void *fdt)
-{
- return;
-}
-
-int board_eth_init(bd_t *bis)
-{
-#if defined(CONFIG_FMAN_ENET)
- int i, interface;
- struct memac_mdio_info dtsec_mdio_info;
- struct memac_mdio_info tgec_mdio_info;
- struct mii_dev *dev;
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- u32 srds_prtcl_s1, srds_prtcl_s2;
-
- srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
- FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
- srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
- srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
- FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
- srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
-
- dtsec_mdio_info.regs =
- (struct memac_mdio_controller *)CONFIG_SYS_FM2_DTSEC_MDIO_ADDR;
-
- dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
-
- /* Register the 1G MDIO bus */
- fm_memac_mdio_init(bis, &dtsec_mdio_info);
-
- tgec_mdio_info.regs =
- (struct memac_mdio_controller *)CONFIG_SYS_FM2_TGEC_MDIO_ADDR;
- tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
-
- /* Register the 10G MDIO bus */
- fm_memac_mdio_init(bis, &tgec_mdio_info);
-
- if ((srds_prtcl_s1 == 28) || (srds_prtcl_s1 == 27)) {
- /* SGMII */
- fm_info_set_phy_address(FM1_DTSEC1, SGMII_PHY_ADDR1);
- fm_info_set_phy_address(FM1_DTSEC2, SGMII_PHY_ADDR2);
- fm_info_set_phy_address(FM1_DTSEC3, SGMII_PHY_ADDR3);
- fm_info_set_phy_address(FM1_DTSEC4, SGMII_PHY_ADDR4);
- } else {
- puts("Invalid SerDes1 protocol for T4240RDB\n");
- }
-
- fm_disable_port(FM1_DTSEC5);
- fm_disable_port(FM1_DTSEC6);
-
- for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
- interface = fm_info_get_enet_if(i);
- switch (interface) {
- case PHY_INTERFACE_MODE_SGMII:
- dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
- fm_info_set_mdio(i, dev);
- break;
- default:
- break;
- }
- }
-
- for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
- switch (fm_info_get_enet_if(i)) {
- case PHY_INTERFACE_MODE_XGMII:
- dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
- fm_info_set_mdio(i, dev);
- break;
- default:
- break;
- }
- }
-
-#if (CONFIG_SYS_NUM_FMAN == 2)
- if ((srds_prtcl_s2 == 56) || (srds_prtcl_s2 == 55)) {
- /* SGMII && XFI */
- fm_info_set_phy_address(FM2_DTSEC1, SGMII_PHY_ADDR5);
- fm_info_set_phy_address(FM2_DTSEC2, SGMII_PHY_ADDR6);
- fm_info_set_phy_address(FM2_DTSEC3, SGMII_PHY_ADDR7);
- fm_info_set_phy_address(FM2_DTSEC4, SGMII_PHY_ADDR8);
- fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
- fm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR);
- fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC2_PHY_ADDR);
- fm_info_set_phy_address(FM2_10GEC2, FM2_10GEC1_PHY_ADDR);
- } else {
- puts("Invalid SerDes2 protocol for T4240RDB\n");
- }
-
- fm_disable_port(FM2_DTSEC5);
- fm_disable_port(FM2_DTSEC6);
- for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
- interface = fm_info_get_enet_if(i);
- switch (interface) {
- case PHY_INTERFACE_MODE_SGMII:
- dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
- fm_info_set_mdio(i, dev);
- break;
- default:
- break;
- }
- }
-
- for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) {
- switch (fm_info_get_enet_if(i)) {
- case PHY_INTERFACE_MODE_XGMII:
- dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
- fm_info_set_mdio(i, dev);
- break;
- default:
- break;
- }
- }
-#endif /* CONFIG_SYS_NUM_FMAN */
-
- cpu_eth_init(bis);
-#endif /* CONFIG_FMAN_ENET */
-
- return pci_eth_init(bis);
-}
diff --git a/board/freescale/t4rdb/law.c b/board/freescale/t4rdb/law.c
deleted file mode 100644
index 038f60565f..0000000000
--- a/board/freescale/t4rdb/law.c
+++ /dev/null
@@ -1,30 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-struct law_entry law_table[] = {
- SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
- SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
-#endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
- SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
-#endif
-#ifdef CONFIG_SYS_CPLD_BASE_PHYS
- SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
-#endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
- /* Limit DCSR to 32M to access NPC Trace Buffer */
- SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
-#endif
-#ifdef CONFIG_SYS_NAND_BASE_PHYS
- SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
-#endif
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/t4rdb/pci.c b/board/freescale/t4rdb/pci.c
deleted file mode 100644
index ac0c95687a..0000000000
--- a/board/freescale/t4rdb/pci.c
+++ /dev/null
@@ -1,25 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <init.h>
-#include <pci.h>
-#include <asm/fsl_pci.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <asm/fsl_serdes.h>
-
-#if !defined(CONFIG_DM_PCI)
-void pci_init_board(void)
-{
- fsl_pcie_init_board(0);
-}
-
-void pci_of_setup(void *blob, bd_t *bd)
-{
- FT_FSL_PCI_SETUP;
-}
-#endif
diff --git a/board/freescale/t4rdb/spl.c b/board/freescale/t4rdb/spl.c
deleted file mode 100644
index 5d018c316c..0000000000
--- a/board/freescale/t4rdb/spl.c
+++ /dev/null
@@ -1,99 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2015 Freescale Semiconductor, Inc.
- *
- * Author: Chunhe Lan <Chunhe.Lan@freescale.com>
- */
-
-#include <common.h>
-#include <clock_legacy.h>
-#include <console.h>
-#include <env_internal.h>
-#include <init.h>
-#include <asm/spl.h>
-#include <malloc.h>
-#include <ns16550.h>
-#include <nand.h>
-#include <mmc.h>
-#include <fsl_esdhc.h>
-#include <i2c.h>
-
-#include "t4rdb.h"
-
-#define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000
-
-DECLARE_GLOBAL_DATA_PTR;
-
-phys_size_t get_effective_memsize(void)
-{
- return CONFIG_SYS_L3_SIZE;
-}
-
-unsigned long get_board_sys_clk(void)
-{
- return CONFIG_SYS_CLK_FREQ;
-}
-
-unsigned long get_board_ddr_clk(void)
-{
- return CONFIG_DDR_CLK_FREQ;
-}
-
-void board_init_f(ulong bootflag)
-{
- u32 plat_ratio, sys_clk, ccb_clk;
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
- /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
- memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
-
- /* Update GD pointer */
- gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
-
- /* compiler optimization barrier needed for GCC >= 3.4 */
- __asm__ __volatile__("" : : : "memory");
-
- console_init_f();
-
- /* initialize selected port with appropriate baud rate */
- sys_clk = get_board_sys_clk();
- plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
- ccb_clk = sys_clk * plat_ratio / 2;
-
- NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
- ccb_clk / 16 / CONFIG_BAUDRATE);
-
- puts("\nSD boot...\n");
-
- relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
- bd_t *bd;
-
- bd = (bd_t *)(gd + sizeof(gd_t));
- memset(bd, 0, sizeof(bd_t));
- gd->bd = bd;
- bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
- bd->bi_memsize = CONFIG_SYS_L3_SIZE;
-
- arch_cpu_init();
- get_clocks();
- mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
- CONFIG_SPL_RELOC_MALLOC_SIZE);
- gd->flags |= GD_FLG_FULL_MALLOC_INIT;
-
- mmc_initialize(bd);
- mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
- (uchar *)SPL_ENV_ADDR);
-
- gd->env_addr = (ulong)(SPL_ENV_ADDR);
- gd->env_valid = ENV_VALID;
-
- i2c_init_all();
-
- dram_init();
-
- mmc_boot();
-}
diff --git a/board/freescale/t4rdb/t4240rdb.c b/board/freescale/t4rdb/t4240rdb.c
deleted file mode 100644
index d801f2c7a1..0000000000
--- a/board/freescale/t4rdb/t4240rdb.c
+++ /dev/null
@@ -1,150 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <env.h>
-#include <fdt_support.h>
-#include <i2c.h>
-#include <image.h>
-#include <init.h>
-#include <netdev.h>
-#include <linux/compiler.h>
-#include <asm/mmu.h>
-#include <asm/processor.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_law.h>
-#include <asm/fsl_serdes.h>
-#include <asm/fsl_liodn.h>
-#include <fm_eth.h>
-
-#include "t4rdb.h"
-#include "cpld.h"
-#include "../common/vid.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
- struct cpu_type *cpu = gd->arch.cpu;
- u8 sw;
-
- printf("Board: %sRDB, ", cpu->name);
- printf("Board rev: 0x%02x CPLD ver: 0x%02x%02x, ",
- CPLD_READ(hw_ver), CPLD_READ(sw_maj_ver), CPLD_READ(sw_min_ver));
-
- sw = CPLD_READ(vbank);
- sw = sw & CPLD_BANK_SEL_MASK;
-
- if (sw <= 7)
- printf("vBank: %d\n", sw);
- else
- printf("Unsupported Bank=%x\n", sw);
-
- puts("SERDES Reference Clocks:\n");
- printf(" SERDES1=100MHz SERDES2=156.25MHz\n"
- " SERDES3=100MHz SERDES4=100MHz\n");
-
- return 0;
-}
-
-int board_early_init_r(void)
-{
- const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
- int flash_esel = find_tlb_idx((void *)flashbase, 1);
-
- /*
- * Remap Boot flash + PROMJET region to caching-inhibited
- * so that flash can be erased properly.
- */
-
- /* Flush d-cache and invalidate i-cache of any FLASH data */
- flush_dcache();
- invalidate_icache();
-
- if (flash_esel == -1) {
- /* very unlikely unless something is messed up */
- puts("Error: Could not find TLB for FLASH BASE\n");
- flash_esel = 2; /* give our best effort to continue */
- } else {
- /* invalidate existing TLB entry for flash + promjet */
- disable_tlb(flash_esel);
- }
-
- set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, flash_esel, BOOKE_PAGESZ_256M, 1);
-
- /*
- * Adjust core voltage according to voltage ID
- * This function changes I2C mux to channel 2.
- */
- if (adjust_vdd(0))
- printf("Warning: Adjusting core voltage failed.\n");
-
- return 0;
-}
-
-int misc_init_r(void)
-{
- return 0;
-}
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
- phys_addr_t base;
- phys_size_t size;
-
- ft_cpu_setup(blob, bd);
-
- base = env_get_bootm_low();
- size = env_get_bootm_size();
-
- fdt_fixup_memory(blob, (u64)base, (u64)size);
-
-#ifdef CONFIG_PCI
- pci_of_setup(blob, bd);
-#endif
-
- fdt_fixup_liodn(blob);
- fsl_fdt_fixup_dr_usb(blob, bd);
-
-#ifdef CONFIG_SYS_DPAA_FMAN
- fdt_fixup_fman_ethernet(blob);
- fdt_fixup_board_enet(blob);
-#endif
-
- return 0;
-}
-
-/*
- * This function is called by bdinfo to print detail board information.
- * As an exmaple for future board, we organize the messages into
- * several sections. If applicable, the message is in the format of
- * <name> = <value>
- * It should aligned with normal output of bdinfo command.
- *
- * Voltage: Core, DDR and another configurable voltages
- * Clock : Critical clocks which are not printed already
- * RCW : RCW source if not printed already
- * Misc : Other important information not in above catagories
- */
-void board_detail(void)
-{
- int rcwsrc;
-
- /* RCW section SW3[4] */
- rcwsrc = 0x0;
- puts("RCW source = ");
- switch (rcwsrc & 0x1) {
- case 0x1:
- puts("SDHC/eMMC\n");
- break;
- default:
- puts("I2C normal addressing\n");
- break;
- }
-}
diff --git a/board/freescale/t4rdb/t4_pbi.cfg b/board/freescale/t4rdb/t4_pbi.cfg
deleted file mode 100644
index 0b326fa163..0000000000
--- a/board/freescale/t4rdb/t4_pbi.cfg
+++ /dev/null
@@ -1,27 +0,0 @@
-#
-# Copyright 2014 Freescale Semiconductor, Inc.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-#PBI commands
-#Initialize CPC1
-09010000 00200400
-09138000 00000000
-091380c0 00000100
-#512KB SRAM
-09010100 00000000
-09010104 fff80009
-09010f00 08000000
-#enable CPC1
-09010000 80000000
-#Configure LAW for CPC1
-09000d00 00000000
-09000d04 fff80000
-09000d08 81000012
-#Configure alternate space
-09000010 00000000
-09000014 ff000000
-09000018 81000000
-#Flush PBL data
-091380c0 00100000
diff --git a/board/freescale/t4rdb/t4_sd_rcw.cfg b/board/freescale/t4rdb/t4_sd_rcw.cfg
deleted file mode 100644
index cc2bff6826..0000000000
--- a/board/freescale/t4rdb/t4_sd_rcw.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-#PBL preamble and RCW header
-aa55aa55 010e0100
-#serdes protocol 27_55_1_9
-16070019 18101916 00000000 00000000
-6c6e0848 00448c00 6c020000 f5000000
-00000000 ee0000ee 00000000 000307fc
-00000000 00000000 00000000 00000028
diff --git a/board/freescale/t4rdb/t4rdb.h b/board/freescale/t4rdb/t4rdb.h
deleted file mode 100644
index 6e04bf0710..0000000000
--- a/board/freescale/t4rdb/t4rdb.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- */
-
-#ifndef __T4RDB_H__
-#define __T4RDB_H__
-
-#undef CONFIG_SYS_NUM_FM1_DTSEC
-#undef CONFIG_SYS_NUM_FM2_DTSEC
-#define CONFIG_SYS_NUM_FM1_DTSEC 4
-#define CONFIG_SYS_NUM_FM2_DTSEC 4
-
-void fdt_fixup_board_enet(void *blob);
-void pci_of_setup(void *blob, bd_t *bd);
-
-#endif
diff --git a/board/freescale/t4rdb/tlb.c b/board/freescale/t4rdb/tlb.c
deleted file mode 100644
index b927dd8484..0000000000
--- a/board/freescale/t4rdb/tlb.c
+++ /dev/null
@@ -1,123 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
- /* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
-
- /* TLB 1 */
- /* *I*** - Covers boot page */
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
- /*
- * *I*G - L3SRAM. When L3 is used as 512K SRAM */
- SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_512K, 1),
-#else
- SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_4K, 1),
-#endif
-
- /* *I*G* - CCSRBAR */
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 1, BOOKE_PAGESZ_16M, 1),
-
- /* *I*G* - Flash, localbus */
- /* This will be changed to *I*G* after relocation to RAM. */
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
- MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
- 0, 2, BOOKE_PAGESZ_256M, 1),
-
-#ifndef CONFIG_SPL_BUILD
- /* *I*G* - PCI */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 3, BOOKE_PAGESZ_1G, 1),
-
- /* *I*G* - PCI */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000,
- CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 4, BOOKE_PAGESZ_256M, 1),
-
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000,
- CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 5, BOOKE_PAGESZ_256M, 1),
-
- /* *I*G* - PCI I/O */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 6, BOOKE_PAGESZ_256K, 1),
-
- /* Bman/Qman */
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
- SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 9, BOOKE_PAGESZ_16M, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
- CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 10, BOOKE_PAGESZ_16M, 1),
-#endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
- SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 11, BOOKE_PAGESZ_16M, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
- CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 12, BOOKE_PAGESZ_16M, 1),
-#endif
-#endif
-
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
- SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 13, BOOKE_PAGESZ_32M, 1),
-#endif
-#ifdef CONFIG_SYS_NAND_BASE
- /*
- * *I*G - NAND
- * entry 14 and 15 has been used hard coded, they will be disabled
- * in cpu_init_f, so we use entry 16 for nand.
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 16, BOOKE_PAGESZ_64K, 1),
-#endif
-#ifdef CONFIG_SYS_CPLD_BASE
- SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
- MAS3_SW|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 17, BOOKE_PAGESZ_4K, 1),
-#endif
-#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
- SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
- 0, 18, BOOKE_PAGESZ_2G, 1)
-#endif
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/configs/T4160RDB_defconfig b/configs/T4160RDB_defconfig
deleted file mode 100644
index f3c7e1ec57..0000000000
--- a/configs/T4160RDB_defconfig
+++ /dev/null
@@ -1,54 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T4160RDB=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_CORTINA=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T4240RDB_SDCARD_defconfig b/configs/T4240RDB_SDCARD_defconfig
deleted file mode 100644
index 14e366358b..0000000000
--- a/configs/T4240RDB_SDCARD_defconfig
+++ /dev/null
@@ -1,74 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x00201000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T4240RDB=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_MMC_BOOT=y
-CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="t4240rdb"
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_CORTINA=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
diff --git a/configs/T4240RDB_defconfig b/configs/T4240RDB_defconfig
deleted file mode 100644
index dfe8953af7..0000000000
--- a/configs/T4240RDB_defconfig
+++ /dev/null
@@ -1,62 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T4240RDB=y
-CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="t4240rdb"
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_CORTINA=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h
deleted file mode 100644
index fcfd3b0b4b..0000000000
--- a/include/configs/T4240RDB.h
+++ /dev/null
@@ -1,681 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2020 NXP
- */
-
-/*
- * T4240 RDB board configuration file
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <linux/stringify.h>
-
-#define CONFIG_FSL_SATA_V2
-#define CONFIG_PCIE4
-
-#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
-
-#ifdef CONFIG_RAMBOOT_PBL
-#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg
-#ifndef CONFIG_SDCARD
-#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
-#else
-#define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_PAD_TO 0x40000
-#define CONFIG_SPL_MAX_SIZE 0x28000
-#define RESET_VECTOR_OFFSET 0x27FFC
-#define BOOT_PAGE_OFFSET 0x27000
-
-#ifdef CONFIG_SDCARD
-#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
-#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
-#define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000
-#define CONFIG_SYS_MMC_U_BOOT_START 0x00200000
-#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_SYS_MPC85XX_NO_RESETVEC
-#endif
-#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_sd_rcw.cfg
-#endif
-
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SPL_SKIP_RELOCATE
-#define CONFIG_SPL_COMMON_INIT_DDR
-#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
-#endif
-
-#endif
-#endif /* CONFIG_RAMBOOT_PBL */
-
-#define CONFIG_DDR_ECC
-
-/* High Level Configuration Options */
-#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
-
-#ifndef CONFIG_RESET_VECTOR_ADDRESS
-#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
-#endif
-
-#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
-#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
-#define CONFIG_PCIE1 /* PCIE controller 1 */
-#define CONFIG_PCIE2 /* PCIE controller 2 */
-#define CONFIG_PCIE3 /* PCIE controller 3 */
-#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
-
-#define CONFIG_ENV_OVERWRITE
-
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_SYS_CACHE_STASHING
-#define CONFIG_BTB /* toggle branch predition */
-#ifdef CONFIG_DDR_ECC
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
-#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
-#endif
-
-#define CONFIG_ENABLE_36BIT_PHYS
-
-#define CONFIG_ADDR_MAP
-#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
-
-/*
- * Config the L3 Cache as L3 SRAM
- */
-#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
-#define CONFIG_SYS_L3_SIZE (512 << 10)
-#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
-#define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
-#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
-#define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
-#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
-
-#define CONFIG_SYS_DCSRBAR 0xf0000000
-#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
-
-/*
- * DDR Setup
- */
-#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_CHIP_SELECTS_PER_CTRL 4
-
-#define CONFIG_DDR_SPD
-
-/*
- * IFC Definitions
- */
-#define CONFIG_SYS_FLASH_BASE 0xe0000000
-#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
-
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
-#else
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#endif
-
-#define CONFIG_HWCONFIG
-
-/* define to use L1 as initial stack */
-#define CONFIG_L1_INIT_RAM
-#define CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
-/* The assembler doesn't like typecast */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
- ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
- CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
-#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
-
-/* Serial Port - controlled on board with jumper J8
- * open - index 2
- * shorted - index 1
- */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
-#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
-#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
-
-/* I2C */
-#ifndef CONFIG_DM_I2C
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
-#else
-#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
-#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
-#endif
-
-#define CONFIG_SYS_I2C_FSL
-
-/*
- * General PCI
- * Memory space is mapped 1-1, but I/O space must start from 0.
- */
-
-/* controller 1, direct to uli, tgtid 3, Base address 20000 */
-#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
-#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
-
-/* controller 2, Slot 2, tgtid 2, Base address 201000 */
-#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
-#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
-#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
-
-/* controller 3, Slot 1, tgtid 1, Base address 202000 */
-#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
-#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
-#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
-
-/* controller 4, Base address 203000 */
-#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
-#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
-
-#ifdef CONFIG_PCI
-#if !defined(CONFIG_DM_PCI)
-#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
-#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
-#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#endif
-
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#endif /* CONFIG_PCI */
-
-/* SATA */
-#ifdef CONFIG_FSL_SATA_V2
-#define CONFIG_SYS_SATA_MAX_DEVICE 2
-#define CONFIG_SATA1
-#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
-#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
-#define CONFIG_SATA2
-#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
-#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
-
-#define CONFIG_LBA48
-#endif
-
-#ifdef CONFIG_FMAN_ENET
-#define CONFIG_ETHPRIME "FM1@DTSEC1"
-#endif
-
-/*
- * Environment
- */
-#define CONFIG_LOADS_ECHO /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
-
-/*
- * Command line configuration.
- */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 64 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
-#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-#define CONFIG_ROOTPATH "/opt/nfsroot"
-#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
-
-/* default location for tftp and bootm */
-#define CONFIG_LOADADDR 1000000
-
-#define CONFIG_HVBOOT \
- "setenv bootargs config-addr=0x60000000; " \
- "bootm 0x01000000 - 0x00f00000"
-
-#if defined(CONFIG_SPIFLASH)
-#elif defined(CONFIG_SDCARD)
-#define CONFIG_SYS_MMC_ENV_DEV 0
-#endif
-
-#define CONFIG_SYS_CLK_FREQ 66666666
-#define CONFIG_DDR_CLK_FREQ 133333333
-
-#ifndef __ASSEMBLY__
-unsigned long get_board_sys_clk(void);
-unsigned long get_board_ddr_clk(void);
-#endif
-
-/*
- * DDR Setup
- */
-#define CONFIG_SYS_SPD_BUS_NUM 0
-#define SPD_EEPROM_ADDRESS1 0x52
-#define SPD_EEPROM_ADDRESS2 0x54
-#define SPD_EEPROM_ADDRESS3 0x56
-#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
-#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
-
-/*
- * IFC Definitions
- */
-#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
-#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
- + 0x8000000) | \
- CSPR_PORT_SIZE_16 | \
- CSPR_MSEL_NOR | \
- CSPR_V)
-#define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
-#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
- CSPR_PORT_SIZE_16 | \
- CSPR_MSEL_NOR | \
- CSPR_V)
-#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
-/* NOR Flash Timing Params */
-#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
-
-#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
- FTIM0_NOR_TEADC(0x5) | \
- FTIM0_NOR_TEAHC(0x5))
-#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
- FTIM1_NOR_TRAD_NOR(0x1A) |\
- FTIM1_NOR_TSEQRAD_NOR(0x13))
-#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
- FTIM2_NOR_TCH(0x4) | \
- FTIM2_NOR_TWPH(0x0E) | \
- FTIM2_NOR_TWP(0x1c))
-#define CONFIG_SYS_NOR_FTIM3 0x0
-
-#define CONFIG_SYS_FLASH_QUIET_TEST
-#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
- + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
-
-/* NAND Flash on IFC */
-#define CONFIG_NAND_FSL_IFC
-#define CONFIG_SYS_NAND_MAX_ECCPOS 256
-#define CONFIG_SYS_NAND_MAX_OOBFREE 2
-#define CONFIG_SYS_NAND_BASE 0xff800000
-#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
-
-#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
-#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
- | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
- | CSPR_MSEL_NAND /* MSEL = NAND */ \
- | CSPR_V)
-#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
-
-#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
- | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
- | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
- | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
- | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
- | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
- | CSOR_NAND_PB(128)) /*Page Per Block = 128*/
-
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-
-/* ONFI NAND Flash mode0 Timing Params */
-#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
- FTIM0_NAND_TWP(0x18) | \
- FTIM0_NAND_TWCHT(0x07) | \
- FTIM0_NAND_TWH(0x0a))
-#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
- FTIM1_NAND_TWBE(0x39) | \
- FTIM1_NAND_TRR(0x0e) | \
- FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
- FTIM2_NAND_TREH(0x0a) | \
- FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3 0x0
-
-#define CONFIG_SYS_NAND_DDR_LAW 11
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-
-#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
-
-#if defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
-#else
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
-#endif
-#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
-#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
-
-/* CPLD on IFC */
-#define CONFIG_SYS_CPLD_BASE 0xffdf0000
-#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
-#define CONFIG_SYS_CSPR3_EXT (0xf)
-#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
- | CSPR_PORT_SIZE_8 \
- | CSPR_MSEL_GPCM \
- | CSPR_V)
-
-#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_CSOR3 0x0
-
-/* CPLD Timing parameters for IFC CS3 */
-#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
- FTIM0_GPCM_TEADC(0x0e) | \
- FTIM0_GPCM_TEAHC(0x0e))
-#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
- FTIM1_GPCM_TRAD(0x1f))
-#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
- FTIM2_GPCM_TCH(0x8) | \
- FTIM2_GPCM_TWP(0x1f))
-#define CONFIG_SYS_CS3_FTIM3 0x0
-
-#if defined(CONFIG_RAMBOOT_PBL)
-#define CONFIG_SYS_RAMBOOT
-#endif
-
-/* I2C */
-#define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */
-#define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */
-#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
-#define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */
-
-#define I2C_MUX_CH_DEFAULT 0x8
-#define I2C_MUX_CH_VOL_MONITOR 0xa
-#define I2C_MUX_CH_VSC3316_FS 0xc
-#define I2C_MUX_CH_VSC3316_BS 0xd
-
-/* Voltage monitor on channel 2*/
-#define I2C_VOL_MONITOR_ADDR 0x40
-#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
-#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
-#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
-
-#define CONFIG_VID_FLS_ENV "t4240rdb_vdd_mv"
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_VID
-#endif
-#define CONFIG_VOL_MONITOR_IR36021_SET
-#define CONFIG_VOL_MONITOR_IR36021_READ
-/* The lowest and highest voltage allowed for T4240RDB */
-#define VDD_MV_MIN 819
-#define VDD_MV_MAX 1212
-
-/*
- * eSPI - Enhanced SPI
- */
-
-/* Qman/Bman */
-#ifndef CONFIG_NOBQFMAN
-#define CONFIG_SYS_BMAN_NUM_PORTALS 50
-#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
-#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
-#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
-#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
-#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
-#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
-#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
- CONFIG_SYS_BMAN_CENA_SIZE)
-#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
-#define CONFIG_SYS_QMAN_NUM_PORTALS 50
-#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
-#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
-#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
-#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
-#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
-#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
-#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
- CONFIG_SYS_QMAN_CENA_SIZE)
-#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
-
-#define CONFIG_SYS_DPAA_FMAN
-#define CONFIG_SYS_DPAA_PME
-#define CONFIG_SYS_PMAN
-#define CONFIG_SYS_DPAA_DCE
-#define CONFIG_SYS_DPAA_RMAN
-#define CONFIG_SYS_INTERLAKEN
-
-/* Default address of microcode for the Linux Fman driver */
-#if defined(CONFIG_SPIFLASH)
-/*
- * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
- * env, so we got 0x110000.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
-#elif defined(CONFIG_SDCARD)
-/*
- * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
- * about 1MB (2048 blocks), Env is stored after the image, and the env size is
- * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
-#elif defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
-#else
-#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
-#endif
-#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
-#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
-#endif /* CONFIG_NOBQFMAN */
-
-#ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_CORTINA_FW_ADDR 0xefe00000
-#define CONFIG_CORTINA_FW_LENGTH 0x40000
-#define SGMII_PHY_ADDR1 0x0
-#define SGMII_PHY_ADDR2 0x1
-#define SGMII_PHY_ADDR3 0x2
-#define SGMII_PHY_ADDR4 0x3
-#define SGMII_PHY_ADDR5 0x4
-#define SGMII_PHY_ADDR6 0x5
-#define SGMII_PHY_ADDR7 0x6
-#define SGMII_PHY_ADDR8 0x7
-#define FM1_10GEC1_PHY_ADDR 0x10
-#define FM1_10GEC2_PHY_ADDR 0x11
-#define FM2_10GEC1_PHY_ADDR 0x12
-#define FM2_10GEC2_PHY_ADDR 0x13
-#define CORTINA_PHY_ADDR1 FM1_10GEC1_PHY_ADDR
-#define CORTINA_PHY_ADDR2 FM1_10GEC2_PHY_ADDR
-#define CORTINA_PHY_ADDR3 FM2_10GEC1_PHY_ADDR
-#define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR
-#endif
-
-/* SATA */
-#ifdef CONFIG_FSL_SATA_V2
-#define CONFIG_SYS_SATA_MAX_DEVICE 2
-#define CONFIG_SATA1
-#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
-#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
-#define CONFIG_SATA2
-#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
-#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
-
-#define CONFIG_LBA48
-#endif
-
-#ifdef CONFIG_FMAN_ENET
-#define CONFIG_ETHPRIME "FM1 at DTSEC1"
-#endif
-
-/*
-* USB
-*/
-#define CONFIG_USB_EHCI_FSL
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_HAS_FSL_DR_USB
-
-#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
-#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
-#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
-#endif
-
-
-#define __USB_PHY_TYPE utmi
-
-/*
- * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
- * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
- * interleaving. It can be cacheline, page, bank, superbank.
- * See doc/README.fsl-ddr for details.
- */
-#ifdef CONFIG_ARCH_T4240
-#define CTRL_INTLV_PREFERED 3way_4KB
-#else
-#define CTRL_INTLV_PREFERED cacheline
-#endif
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "hwconfig=fsl_ddr:" \
- "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
- "bank_intlv=auto;" \
- "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
- "netdev=eth0\0" \
- "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
- "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
- "tftpflash=tftpboot $loadaddr $uboot && " \
- "protect off $ubootaddr +$filesize && " \
- "erase $ubootaddr +$filesize && " \
- "cp.b $loadaddr $ubootaddr $filesize && " \
- "protect on $ubootaddr +$filesize && " \
- "cmp.b $loadaddr $ubootaddr $filesize\0" \
- "consoledev=ttyS0\0" \
- "ramdiskaddr=2000000\0" \
- "ramdiskfile=t4240rdb/ramdisk.uboot\0" \
- "fdtaddr=1e00000\0" \
- "fdtfile=t4240rdb/t4240rdb.dtb\0" \
- "bdev=sda3\0"
-
-#define CONFIG_HVBOOT \
- "setenv bootargs config-addr=0x60000000; " \
- "bootm 0x01000000 - 0x00f00000"
-
-#define CONFIG_LINUX \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "setenv ramdiskaddr 0x02000000;" \
- "setenv fdtaddr 0x00c00000;" \
- "setenv loadaddr 0x1000000;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_HDBOOT \
- "setenv bootargs root=/dev/$bdev rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND CONFIG_LINUX
-
-#include <asm/fsl_secure_boot.h>
-
-#endif /* __CONFIG_H */
--
2.25.1
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 20/24] arm: Remove configs/TWR-P1025_defconfig board
2020-05-27 16:46 [PATCH 00/24] spi: dm-conversion (part2) Jagan Teki
` (18 preceding siblings ...)
2020-05-27 16:46 ` [PATCH 19/24] arm: Remove configs/T4160RDB_defconfig board Jagan Teki
@ 2020-05-27 16:46 ` Jagan Teki
2020-05-28 7:12 ` Priyanka Jain
2020-05-27 18:38 ` [PATCH 00/24] spi: dm-conversion (part2) Joakim Tjernlund
` (2 subsequent siblings)
22 siblings, 1 reply; 59+ messages in thread
From: Jagan Teki @ 2020-05-27 16:46 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_SPI by the deadline.
Remove it.
Patch-cc: Xiaobo Xie <xiaobo.xie@nxp.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
arch/powerpc/cpu/mpc85xx/Kconfig | 1 -
board/freescale/p1_twr/Kconfig | 12 -
board/freescale/p1_twr/MAINTAINERS | 6 -
board/freescale/p1_twr/Makefile | 9 -
board/freescale/p1_twr/ddr.c | 69 -----
board/freescale/p1_twr/law.c | 15 -
board/freescale/p1_twr/p1_twr.c | 292 ------------------
board/freescale/p1_twr/tlb.c | 75 -----
configs/TWR-P1025_defconfig | 64 ----
include/configs/p1_twr.h | 480 -----------------------------
10 files changed, 1023 deletions(-)
delete mode 100644 board/freescale/p1_twr/Kconfig
delete mode 100644 board/freescale/p1_twr/MAINTAINERS
delete mode 100644 board/freescale/p1_twr/Makefile
delete mode 100644 board/freescale/p1_twr/ddr.c
delete mode 100644 board/freescale/p1_twr/law.c
delete mode 100644 board/freescale/p1_twr/p1_twr.c
delete mode 100644 board/freescale/p1_twr/tlb.c
delete mode 100644 configs/TWR-P1025_defconfig
delete mode 100644 include/configs/p1_twr.h
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 337bf83835..4041973578 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -1597,7 +1597,6 @@ source "board/freescale/mpc8568mds/Kconfig"
source "board/freescale/mpc8569mds/Kconfig"
source "board/freescale/mpc8572ds/Kconfig"
source "board/freescale/p1023rdb/Kconfig"
-source "board/freescale/p1_twr/Kconfig"
source "board/freescale/qemu-ppce500/Kconfig"
source "board/gdsys/p1022/Kconfig"
source "board/keymile/Kconfig"
diff --git a/board/freescale/p1_twr/Kconfig b/board/freescale/p1_twr/Kconfig
deleted file mode 100644
index 8f9a8d4415..0000000000
--- a/board/freescale/p1_twr/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_P1_TWR
-
-config SYS_BOARD
- default "p1_twr"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "p1_twr"
-
-endif
diff --git a/board/freescale/p1_twr/MAINTAINERS b/board/freescale/p1_twr/MAINTAINERS
deleted file mode 100644
index 0f9f98f459..0000000000
--- a/board/freescale/p1_twr/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-P1_TWR BOARD
-M: Xiaobo Xie <xiaobo.xie@nxp.com>
-S: Maintained
-F: board/freescale/p1_twr/
-F: include/configs/p1_twr.h
-F: configs/TWR-P1025_defconfig
diff --git a/board/freescale/p1_twr/Makefile b/board/freescale/p1_twr/Makefile
deleted file mode 100644
index 5e6c658551..0000000000
--- a/board/freescale/p1_twr/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2013 Freescale Semiconductor, Inc.
-#
-
-obj-y += p1_twr.o
-obj-y += ddr.o
-obj-y += law.o
-obj-y += tlb.o
diff --git a/board/freescale/p1_twr/ddr.c b/board/freescale/p1_twr/ddr.c
deleted file mode 100644
index 85f1f6344a..0000000000
--- a/board/freescale/p1_twr/ddr.c
+++ /dev/null
@@ -1,69 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <vsprintf.h>
-#include <asm/mmu.h>
-#include <asm/immap_85xx.h>
-#include <asm/processor.h>
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-#include <asm/io.h>
-#include <asm/fsl_law.h>
-
-/* Fixed sdram init -- doesn't use serial presence detect. */
-phys_size_t fixed_sdram(void)
-{
- sys_info_t sysinfo;
- char buf[32];
- size_t ddr_size;
- fsl_ddr_cfg_regs_t ddr_cfg_regs = {
- .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
- .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
- .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
-#if CONFIG_CHIP_SELECTS_PER_CTRL > 1
- .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
- .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
- .cs[1].config_2 = CONFIG_SYS_DDR_CS1_CONFIG_2,
-#endif
- .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3,
- .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0,
- .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1,
- .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2,
- .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
- .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
- .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1,
- .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2,
- .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
- .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL,
- .ddr_data_init = CONFIG_SYS_DDR_DATA_INIT,
- .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL,
- .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
- .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
- .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
- .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
- .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
- .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
- .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
- .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
- .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
- };
-
- get_sys_info(&sysinfo);
- printf("Configuring DDR for %s MT/s data rate\n",
- strmhz(buf, sysinfo.freq_ddrbus));
-
- ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
-
- fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
-
- if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
- ddr_size, LAW_TRGT_IF_DDR_1) < 0) {
- printf("ERROR setting Local Access Windows for DDR\n");
- return 0;
- };
-
- return ddr_size;
-}
diff --git a/board/freescale/p1_twr/law.c b/board/freescale/p1_twr/law.c
deleted file mode 100644
index 45721f6140..0000000000
--- a/board/freescale/p1_twr/law.c
+++ /dev/null
@@ -1,15 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-struct law_entry law_table[] = {
- SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
- SET_LAW(CONFIG_SYS_SSD_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC)
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/p1_twr/p1_twr.c b/board/freescale/p1_twr/p1_twr.c
deleted file mode 100644
index 8e1522a604..0000000000
--- a/board/freescale/p1_twr/p1_twr.c
+++ /dev/null
@@ -1,292 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <env.h>
-#include <hwconfig.h>
-#include <image.h>
-#include <init.h>
-#include <net.h>
-#include <pci.h>
-#include <i2c.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_pci.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/io.h>
-#include <asm/fsl_law.h>
-#include <asm/fsl_lbc.h>
-#include <asm/mp.h>
-#include <miiphy.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <fsl_mdio.h>
-#include <tsec.h>
-#include <ioports.h>
-#include <asm/fsl_serdes.h>
-#include <netdev.h>
-
-#define SYSCLK_64 64000000
-#define SYSCLK_66 66666666
-
-unsigned long get_board_sys_clk(ulong dummy)
-{
- ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- par_io_t *par_io = (par_io_t *) &(gur->qe_par_io);
- unsigned int cpdat_val = 0;
-
- /* Set-up up pin muxing based on board switch settings */
- cpdat_val = par_io[1].cpdat;
-
- /* Check switch setting for SYSCLK select (PB3) */
- if (cpdat_val & 0x10000000)
- return SYSCLK_64;
- else
- return SYSCLK_66;
-
- return 0;
-}
-
-#ifdef CONFIG_QE
-
-#define PCA_IOPORT_I2C_ADDR 0x23
-#define PCA_IOPORT_OUTPUT_CMD 0x2
-#define PCA_IOPORT_CFG_CMD 0x6
-
-const qe_iop_conf_t qe_iop_conf_tab[] = {
-
-#ifdef CONFIG_TWR_P1025
- /* GPIO */
- {1, 0, 1, 0, 0},
- {1, 18, 1, 0, 0},
-
- /* GPIO for switch options */
- {1, 2, 2, 0, 0}, /* PROFIBUS_MODE_SEL */
- {1, 3, 2, 0, 0}, /* SYS_CLK_SELECT */
- {1, 29, 2, 0, 0}, /* LOCALBUS_QE_MUXSEL */
- {1, 30, 2, 0, 0}, /* ETH_TDM_SEL */
-
- /* QE_MUX_MDC */
- {1, 19, 1, 0, 1}, /* QE_MUX_MDC */
-
- /* QE_MUX_MDIO */
- {1, 20, 3, 0, 1}, /* QE_MUX_MDIO */
-
- /* UCC_1_MII */
- {0, 23, 2, 0, 2}, /* CLK12 */
- {0, 24, 2, 0, 1}, /* CLK9 */
- {0, 7, 1, 0, 2}, /* ENET1_TXD0_SER1_TXD0 */
- {0, 9, 1, 0, 2}, /* ENET1_TXD1_SER1_TXD1 */
- {0, 11, 1, 0, 2}, /* ENET1_TXD2_SER1_TXD2 */
- {0, 12, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3 */
- {0, 6, 2, 0, 2}, /* ENET1_RXD0_SER1_RXD0 */
- {0, 10, 2, 0, 2}, /* ENET1_RXD1_SER1_RXD1 */
- {0, 14, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2 */
- {0, 15, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3 */
- {0, 5, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */
- {0, 13, 1, 0, 2}, /* ENET1_TX_ER */
- {0, 4, 2, 0, 2}, /* ENET1_RX_DV_SER1_CTS_B */
- {0, 8, 2, 0, 2}, /* ENET1_RX_ER_SER1_CD_B */
- {0, 17, 2, 0, 2}, /* ENET1_CRS */
- {0, 16, 2, 0, 2}, /* ENET1_COL */
-
- /* UCC_5_RMII */
- {1, 11, 2, 0, 1}, /* CLK13 */
- {1, 7, 1, 0, 2}, /* ENET5_TXD0_SER5_TXD0 */
- {1, 10, 1, 0, 2}, /* ENET5_TXD1_SER5_TXD1 */
- {1, 6, 2, 0, 2}, /* ENET5_RXD0_SER5_RXD0 */
- {1, 9, 2, 0, 2}, /* ENET5_RXD1_SER5_RXD1 */
- {1, 5, 1, 0, 2}, /* ENET5_TX_EN_SER5_RTS_B */
- {1, 4, 2, 0, 2}, /* ENET5_RX_DV_SER5_CTS_B */
- {1, 8, 2, 0, 2}, /* ENET5_RX_ER_SER5_CD_B */
-
- /* TDMA - clock option is configured in OS based on board setting */
- {1, 23, 2, 0, 2}, /* TDMA_TXD */
- {1, 25, 2, 0, 2}, /* TDMA_RXD */
- {1, 26, 1, 0, 2}, /* TDMA_SYNC */
-#endif
-
- {0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */
-};
-#endif
-
-int board_early_init_f(void)
-{
- ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-
- setbits_be32(&gur->pmuxcr,
- (MPC85xx_PMUXCR_SDHC_CD | MPC85xx_PMUXCR_SDHC_WP));
-
- /* SDHC_DAT[4:7] not exposed to pins (use as SPI) */
- clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
-
- return 0;
-}
-
-int checkboard(void)
-{
- ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- u8 boot_status;
-
- printf("Board: %s\n", CONFIG_BOARDNAME);
-
- boot_status = ((gur->porbmsr) >> MPC85xx_PORBMSR_ROMLOC_SHIFT) & 0xf;
- puts("rom_loc: ");
- if (boot_status == PORBMSR_ROMLOC_NOR)
- puts("nor flash");
- else if (boot_status == PORBMSR_ROMLOC_SDHC)
- puts("sd");
- else
- puts("unknown");
- puts("\n");
-
- return 0;
-}
-
-#ifdef CONFIG_PCI
-void pci_init_board(void)
-{
- fsl_pcie_init_board(0);
-}
-#endif
-
-int board_early_init_r(void)
-{
- const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
- int flash_esel = find_tlb_idx((void *)flashbase, 1);
-
- /*
- * Remap Boot flash region to caching-inhibited
- * so that flash can be erased properly.
- */
-
- /* Flush d-cache and invalidate i-cache of any FLASH data */
- flush_dcache();
- invalidate_icache();
-
- if (flash_esel == -1) {
- /* very unlikely unless something is messed up */
- puts("Error: Could not find TLB for FLASH BASE\n");
- flash_esel = 2; /* give our best effort to continue */
- } else {
- /* invalidate existing TLB entry for flash */
- disable_tlb(flash_esel);
- }
-
- set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
- 0, flash_esel, BOOKE_PAGESZ_64M, 1);/* ts, esel, tsize, iprot */
- return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
- struct fsl_pq_mdio_info mdio_info;
- struct tsec_info_struct tsec_info[4];
- ccsr_gur_t *gur __attribute__((unused)) =
- (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- int num = 0;
-
-#ifdef CONFIG_TSEC1
- SET_STD_TSEC_INFO(tsec_info[num], 1);
- num++;
-#endif
-#ifdef CONFIG_TSEC2
- SET_STD_TSEC_INFO(tsec_info[num], 2);
- if (is_serdes_configured(SGMII_TSEC2)) {
- printf("eTSEC2 is in sgmii mode.\n");
- tsec_info[num].flags |= TSEC_SGMII;
- }
- num++;
-#endif
-#ifdef CONFIG_TSEC3
- SET_STD_TSEC_INFO(tsec_info[num], 3);
- num++;
-#endif
-
- if (!num) {
- printf("No TSECs initialized\n");
- return 0;
- }
-
- mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
- mdio_info.name = DEFAULT_MII_NAME;
-
- fsl_pq_mdio_init(bis, &mdio_info);
-
- tsec_eth_init(bis, tsec_info, num);
-
-#if defined(CONFIG_UEC_ETH)
- /* QE0 and QE3 need to be exposed for UCC1
- * and UCC5 Eth mode (in PMUXCR register).
- * Currently QE/LBC muxed pins assumed to be
- * LBC for U-Boot and PMUXCR updated by OS if required */
-
- uec_standard_init(bis);
-#endif
-
- return pci_eth_init(bis);
-}
-
-#if defined(CONFIG_QE)
-static void fdt_board_fixup_qe_pins(void *blob)
-{
- int node;
-
- if (!hwconfig("qe")) {
- /* For QE and eLBC pins multiplexing,
- * When don't use QE function, remove
- * qe node from dt blob.
- */
- node = fdt_path_offset(blob, "/qe");
- if (node >= 0)
- fdt_del_node(blob, node);
- } else {
- /* For TWR Peripheral Modules - TWR-SER2
- * board only can support Signal Port MII,
- * so delete one UEC node when use MII port.
- */
- if (hwconfig("mii"))
- node = fdt_path_offset(blob, "/qe/ucc at 2400");
- else
- node = fdt_path_offset(blob, "/qe/ucc at 2000");
- if (node >= 0)
- fdt_del_node(blob, node);
- }
-
- return;
-}
-#endif
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int ft_board_setup(void *blob, bd_t *bd)
-{
- phys_addr_t base;
- phys_size_t size;
-
- ft_cpu_setup(blob, bd);
-
- base = env_get_bootm_low();
- size = env_get_bootm_size();
-
- fdt_fixup_memory(blob, (u64)base, (u64)size);
-
- FT_FSL_PCI_SETUP;
-
-#ifdef CONFIG_QE
- do_fixup_by_compat(blob, "fsl,qe", "status", "okay",
- sizeof("okay"), 0);
-#endif
-#if defined(CONFIG_TWR_P1025)
- fdt_board_fixup_qe_pins(blob);
-#endif
- fsl_fdt_fixup_dr_usb(blob, bd);
-
- return 0;
-}
-#endif
diff --git a/board/freescale/p1_twr/tlb.c b/board/freescale/p1_twr/tlb.c
deleted file mode 100644
index 8e403e3e44..0000000000
--- a/board/freescale/p1_twr/tlb.c
+++ /dev/null
@@ -1,75 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
- /* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
-
- /* TLB 1 */
- /* *I*** - Covers boot page */
- SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I,
- 0, 0, BOOKE_PAGESZ_4K, 1),
-
- /* *I*G* - CCSRBAR */
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 1, BOOKE_PAGESZ_1M, 1),
-
-#ifndef CONFIG_SPL_BUILD
- /* W**G* - Flash, localbus */
- /* This will be changed to *I*G* after relocation to RAM. */
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
- MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
- 0, 2, BOOKE_PAGESZ_64M, 1),
-
- /* W**G* - Flash, localbus */
- /* This will be changed to *I*G* after relocation to RAM. */
- SET_TLB_ENTRY(1, CONFIG_SYS_SSD_BASE, CONFIG_SYS_SSD_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 5, BOOKE_PAGESZ_1M, 1),
-
-#ifdef CONFIG_PCI
- /* *I*G* - PCI memory 1.5G */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 3, BOOKE_PAGESZ_1G, 1),
-
- /* *I*G* - PCI I/O effective: 192K */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 4, BOOKE_PAGESZ_256K, 1),
-#endif
-
-#endif
-
-#ifdef CONFIG_SYS_RAMBOOT
- /* *I*G - eSDHC boot */
- SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
- 0, 8, BOOKE_PAGESZ_1G, 1),
-#endif
-
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/configs/TWR-P1025_defconfig b/configs/TWR-P1025_defconfig
deleted file mode 100644
index e48454aa6c..0000000000
--- a/configs/TWR-P1025_defconfig
+++ /dev/null
@@ -1,64 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P1_TWR=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="TWR_P1025"
-CONFIG_BOOTDELAY=10
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_EEPROM=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=ec000000.nor"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=ec000000.nor:256k(vsc7385-firmware),256k(dtb),5632k(kernel),57856k(fs),256k(qe-ucode-firmware),1280k(u-boot)"
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_SATA_SIL3114=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_PANIC_HANG=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/p1_twr.h b/include/configs/p1_twr.h
deleted file mode 100644
index d731f9c8fa..0000000000
--- a/include/configs/p1_twr.h
+++ /dev/null
@@ -1,480 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-/*
- * QorIQ P1 Tower boards configuration file
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <linux/stringify.h>
-
-#if defined(CONFIG_TWR_P1025)
-#define CONFIG_BOARDNAME "TWR-P1025"
-#define CONFIG_SYS_LBC_LBCR 0x00080000 /* Conversion of LBC addr */
-#define CONFIG_SYS_LBC_LCRR 0x80000002 /* LB clock ratio reg */
-#endif
-
-#ifdef CONFIG_SDCARD
-#define CONFIG_RAMBOOT_SDCARD
-#define CONFIG_SYS_RAMBOOT
-#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
-#endif
-
-#ifndef CONFIG_RESET_VECTOR_ADDRESS
-#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
-#endif
-
-#ifndef CONFIG_SYS_MONITOR_BASE
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-#endif
-
-#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
-#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
-#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
-
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_SYS_SATA_MAX_DEVICE 2
-#define CONFIG_LBA48
-
-#ifndef __ASSEMBLY__
-extern unsigned long get_board_sys_clk(unsigned long dummy);
-#endif
-#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /*sysclk for TWR-P1025 */
-
-#define CONFIG_DDR_CLK_FREQ 66666666
-
-#define CONFIG_HWCONFIG
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_L2_CACHE
-#define CONFIG_BTB
-
-#define CONFIG_SYS_CCSRBAR 0xffe00000
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
-
-/* DDR Setup */
-
-#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M
-#define CONFIG_CHIP_SELECTS_PER_CTRL 1
-
-#define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-
-/* Default settings for DDR3 */
-#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f
-#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
-#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
-#define CONFIG_SYS_DDR_CS1_BNDS 0x00000000
-#define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000
-#define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
-
-#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
-#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
-#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
-#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
-
-#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
-#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655a608
-#define CONFIG_SYS_DDR_SR_CNTR 0x00000000
-#define CONFIG_SYS_DDR_RCW_1 0x00000000
-#define CONFIG_SYS_DDR_RCW_2 0x00000000
-#define CONFIG_SYS_DDR_CONTROL 0xc70c0000 /* Type = DDR3 */
-#define CONFIG_SYS_DDR_CONTROL_2 0x04401050
-#define CONFIG_SYS_DDR_TIMING_4 0x00220001
-#define CONFIG_SYS_DDR_TIMING_5 0x03402400
-
-#define CONFIG_SYS_DDR_TIMING_3 0x00020000
-#define CONFIG_SYS_DDR_TIMING_0 0x00220004
-#define CONFIG_SYS_DDR_TIMING_1 0x5c5b6544
-#define CONFIG_SYS_DDR_TIMING_2 0x0fa880de
-#define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
-#define CONFIG_SYS_DDR_MODE_1 0x80461320
-#define CONFIG_SYS_DDR_MODE_2 0x00008000
-#define CONFIG_SYS_DDR_INTERVAL 0x09480000
-
-/*
- * Memory map
- *
- * 0x0000_0000 0x1fff_ffff DDR Up to 512MB cacheable
- * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3)
- * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
- *
- * Localbus
- * 0xe000_0000 0xe002_0000 SSD1289 128K non-cacheable
- * 0xec00_0000 0xefff_ffff FLASH Up to 64M non-cacheable
- *
- * 0xff90_0000 0xff97_ffff L2 SRAM Up to 512K cacheable
- * 0xffd0_0000 0xffd0_3fff init ram 16K Cacheable
- * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
- */
-
-/*
- * Local Bus Definitions
- */
-#define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
-#define CONFIG_SYS_FLASH_BASE 0xec000000
-
-#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
-
-#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS)) \
- | BR_PS_16 | BR_V)
-
-#define CONFIG_FLASH_OR_PRELIM 0xfc0000b1
-
-#define CONFIG_SYS_SSD_BASE 0xe0000000
-#define CONFIG_SYS_SSD_BASE_PHYS CONFIG_SYS_SSD_BASE
-#define CONFIG_SSD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_SSD_BASE_PHYS) | \
- BR_PS_16 | BR_V)
-#define CONFIG_SSD_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
- OR_GPCM_ACS_DIV2 | OR_GPCM_SCY | \
- OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
-
-#define CONFIG_SYS_BR2_PRELIM CONFIG_SSD_BR_PRELIM
-#define CONFIG_SYS_OR2_PRELIM CONFIG_SSD_OR_PRELIM
-
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
-#define CONFIG_SYS_FLASH_QUIET_TEST
-#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
-
-#undef CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
-#define CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000
-/* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
-/* Size of used area in RAM */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */
-
-#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
-#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
-
-/* Serial Port
- * open - index 2
- * shorted - index 1
- */
-#undef CONFIG_SERIAL_SOFTWARE_FIFO
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
-#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C spd and slave address */
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
-
-/*
- * I2C2 EEPROM
- */
-#define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C spd and slave address */
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
-
-#define CONFIG_SYS_I2C_PCA9555_ADDR 0x23
-
-/* enable read and write access to EEPROM */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
-
-#if defined(CONFIG_PCI)
-/*
- * General PCI
- * Memory space is mapped 1-1, but I/O space must start from 0.
- */
-
-/* controller 2, direct to uli, tgtid 2, Base address 9000 */
-#define CONFIG_SYS_PCIE2_NAME "TWR-ELEV PCIe SLOT"
-#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
-#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
-#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
-
-/* controller 1, tgtid 1, Base address a000 */
-#define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT"
-#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
-#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
-#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
-
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#endif /* CONFIG_PCI */
-
-#if defined(CONFIG_TSEC_ENET)
-
-#define CONFIG_TSEC1
-#define CONFIG_TSEC1_NAME "eTSEC1"
-#undef CONFIG_TSEC2
-#undef CONFIG_TSEC2_NAME
-#define CONFIG_TSEC3
-#define CONFIG_TSEC3_NAME "eTSEC3"
-
-#define TSEC1_PHY_ADDR 2
-#define TSEC2_PHY_ADDR 0
-#define TSEC3_PHY_ADDR 1
-
-#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-
-#define TSEC1_PHYIDX 0
-#define TSEC2_PHYIDX 0
-#define TSEC3_PHYIDX 0
-
-#define CONFIG_ETHPRIME "eTSEC1"
-
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#undef CONFIG_HAS_ETH2
-#endif /* CONFIG_TSEC_ENET */
-
-#ifdef CONFIG_QE
-/* QE microcode/firmware address */
-#define CONFIG_SYS_QE_FW_ADDR 0xefec0000
-#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
-#endif /* CONFIG_QE */
-
-#ifdef CONFIG_TWR_P1025
-/*
- * QE UEC ethernet configuration
- */
-#define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120)
-
-#undef CONFIG_UEC_ETH
-#define CONFIG_PHY_MODE_NEED_CHANGE
-
-#define CONFIG_UEC_ETH1 /* ETH1 */
-#define CONFIG_HAS_ETH0
-
-#ifdef CONFIG_UEC_ETH1
-#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
-#define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */
-#define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */
-#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
-#define CONFIG_SYS_UEC1_PHY_ADDR 0x18 /* 0x18 for MII */
-#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
-#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
-#endif /* CONFIG_UEC_ETH1 */
-
-#define CONFIG_UEC_ETH5 /* ETH5 */
-#define CONFIG_HAS_ETH1
-
-#ifdef CONFIG_UEC_ETH5
-#define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */
-#define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE
-#define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */
-#define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH
-#define CONFIG_SYS_UEC5_PHY_ADDR 0x19 /* 0x19 for RMII */
-#define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
-#define CONFIG_SYS_UEC5_INTERFACE_SPEED 100
-#endif /* CONFIG_UEC_ETH5 */
-#endif /* CONFIG_TWR-P1025 */
-
-/*
- * Dynamic MTD Partition support with mtdparts
- */
-
-/*
- * Environment
- */
-#ifdef CONFIG_SYS_RAMBOOT
-#ifdef CONFIG_RAMBOOT_SDCARD
-#define CONFIG_SYS_MMC_ENV_DEV 0
-#endif
-#endif
-
-#define CONFIG_LOADS_ECHO /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
-
-/*
- * USB
- */
-#define CONFIG_HAS_FSL_DR_USB
-
-#if defined(CONFIG_HAS_FSL_DR_USB)
-#ifdef CONFIG_USB_EHCI_HCD
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_USB_EHCI_FSL
-#endif
-#endif
-
-#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
-#endif
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 64 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
-#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-
-/*
- * Environment Configuration
- */
-#define CONFIG_HOSTNAME "unknown"
-#define CONFIG_ROOTPATH "/opt/nfsroot"
-#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
-
-/* default location for tftp and bootm */
-#define CONFIG_LOADADDR 1000000
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
-"netdev=eth0\0" \
-"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
-"loadaddr=1000000\0" \
-"bootfile=uImage\0" \
-"dtbfile=twr-p1025twr.dtb\0" \
-"ramdiskfile=rootfs.ext2.gz.uboot\0" \
-"qefirmwarefile=fsl_qe_ucode_1021_10_A.bin\0" \
-"tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
- "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
-"kernelflash=tftpboot $loadaddr $bootfile; " \
- "protect off 0xefa80000 +$filesize; " \
- "erase 0xefa80000 +$filesize; " \
- "cp.b $loadaddr 0xefa80000 $filesize; " \
- "protect on 0xefa80000 +$filesize; " \
- "cmp.b $loadaddr 0xefa80000 $filesize\0" \
-"dtbflash=tftpboot $loadaddr $dtbfile; " \
- "protect off 0xefe80000 +$filesize; " \
- "erase 0xefe80000 +$filesize; " \
- "cp.b $loadaddr 0xefe80000 $filesize; " \
- "protect on 0xefe80000 +$filesize; " \
- "cmp.b $loadaddr 0xefe80000 $filesize\0" \
-"ramdiskflash=tftpboot $loadaddr $ramdiskfile; " \
- "protect off 0xeeb80000 +$filesize; " \
- "erase 0xeeb80000 +$filesize; " \
- "cp.b $loadaddr 0xeeb80000 $filesize; " \
- "protect on 0xeeb80000 +$filesize; " \
- "cmp.b $loadaddr 0xeeb80000 $filesize\0" \
-"qefirmwareflash=tftpboot $loadaddr $qefirmwarefile; " \
- "protect off 0xefec0000 +$filesize; " \
- "erase 0xefec0000 +$filesize; " \
- "cp.b $loadaddr 0xefec0000 $filesize; " \
- "protect on 0xefec0000 +$filesize; " \
- "cmp.b $loadaddr 0xefec0000 $filesize\0" \
-"consoledev=ttyS0\0" \
-"ramdiskaddr=2000000\0" \
-"ramdiskfile=rootfs.ext2.gz.uboot\0" \
-"fdtaddr=1e00000\0" \
-"bdev=sda1\0" \
-"norbootaddr=ef080000\0" \
-"norfdtaddr=ef040000\0" \
-"ramdisk_size=120000\0" \
-"usbboot=setenv bootargs root=/dev/sda1 rw rootdelay=5 " \
-"console=$consoledev,$baudrate $othbootargs ; bootm 0xefa80000 - 0xefe80000"
-
-#define CONFIG_NFSBOOTCOMMAND \
-"setenv bootargs root=/dev/nfs rw " \
-"nfsroot=$serverip:$rootpath " \
-"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
-"console=$consoledev,$baudrate $othbootargs;" \
-"tftp $loadaddr $bootfile&&" \
-"tftp $fdtaddr $fdtfile&&" \
-"bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_HDBOOT \
-"setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
-"console=$consoledev,$baudrate $othbootargs;" \
-"usb start;" \
-"ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
-"ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
-"bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_USB_FAT_BOOT \
-"setenv bootargs root=/dev/ram rw " \
-"console=$consoledev,$baudrate $othbootargs " \
-"ramdisk_size=$ramdisk_size;" \
-"usb start;" \
-"fatload usb 0:2 $loadaddr $bootfile;" \
-"fatload usb 0:2 $fdtaddr $fdtfile;" \
-"fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
-"bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_USB_EXT2_BOOT \
-"setenv bootargs root=/dev/ram rw " \
-"console=$consoledev,$baudrate $othbootargs " \
-"ramdisk_size=$ramdisk_size;" \
-"usb start;" \
-"ext2load usb 0:4 $loadaddr $bootfile;" \
-"ext2load usb 0:4 $fdtaddr $fdtfile;" \
-"ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
-"bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_NORBOOT \
-"setenv bootargs root=/dev/mtdblock3 rw " \
-"console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
-"bootm $norbootaddr - $norfdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND_TFTP \
-"setenv bootargs root=/dev/ram rw " \
-"console=$consoledev,$baudrate $othbootargs " \
-"ramdisk_size=$ramdisk_size;" \
-"tftp $ramdiskaddr $ramdiskfile;" \
-"tftp $loadaddr $bootfile;" \
-"tftp $fdtaddr $fdtfile;" \
-"bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
-"setenv bootargs root=/dev/ram rw " \
-"console=$consoledev,$baudrate $othbootargs " \
-"ramdisk_size=$ramdisk_size;" \
-"bootm 0xefa80000 0xeeb80000 0xefe80000"
-
-#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
-
-#endif /* __CONFIG_H */
--
2.25.1
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 00/24] spi: dm-conversion (part2)
2020-05-27 16:46 [PATCH 00/24] spi: dm-conversion (part2) Jagan Teki
` (19 preceding siblings ...)
2020-05-27 16:46 ` [PATCH 20/24] arm: Remove configs/TWR-P1025_defconfig board Jagan Teki
@ 2020-05-27 18:38 ` Joakim Tjernlund
2020-05-27 18:49 ` Jagan Teki
2020-05-28 0:56 ` Bin Meng
2020-05-28 9:44 ` Priyanka Jain
22 siblings, 1 reply; 59+ messages in thread
From: Joakim Tjernlund @ 2020-05-27 18:38 UTC (permalink / raw)
To: u-boot
On Wed, 2020-05-27 at 22:16 +0530, Jagan Teki wrote:
> CAUTION: This email originated from outside of the organization. Do not click links or open attachments unless you recognize the sender and know the content is safe.
>
>
> I believe some boards can directly enable DM_SPI if it has
> OF_CONTROL enabled already, so now it's the last call for
> board maintainers to take care of this.
>
> Now all boards which are using fsl_espi are removed due to
> no action on dm conversion from years.
hmm, last I heard fsl_espi was beeing rewritten by NXP, is that not so anymore?
We use fsl_espi on our custom boards, but we are behind a bit ATM
Jocke
^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH 00/24] spi: dm-conversion (part2)
2020-05-27 18:38 ` [PATCH 00/24] spi: dm-conversion (part2) Joakim Tjernlund
@ 2020-05-27 18:49 ` Jagan Teki
0 siblings, 0 replies; 59+ messages in thread
From: Jagan Teki @ 2020-05-27 18:49 UTC (permalink / raw)
To: u-boot
On Thu, May 28, 2020 at 12:08 AM Joakim Tjernlund
<Joakim.Tjernlund@infinera.com> wrote:
>
> On Wed, 2020-05-27 at 22:16 +0530, Jagan Teki wrote:
> > CAUTION: This email originated from outside of the organization. Do not click links or open attachments unless you recognize the sender and know the content is safe.
> >
> >
> > I believe some boards can directly enable DM_SPI if it has
> > OF_CONTROL enabled already, so now it's the last call for
> > board maintainers to take care of this.
> >
> > Now all boards which are using fsl_espi are removed due to
> > no action on dm conversion from years.
>
> hmm, last I heard fsl_espi was being rewritten by NXP, is that not so anymore?
Do you mean the FlexSPI controller is a replacement?
> We use fsl_espi on our custom boards, but we are behind a bit ATM
So, then fsl_espi is no more requirement to use it in Mainline or
nobody care about it isn't it?
Jagan.
^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH 00/24] spi: dm-conversion (part2)
2020-05-27 16:46 [PATCH 00/24] spi: dm-conversion (part2) Jagan Teki
` (20 preceding siblings ...)
2020-05-27 18:38 ` [PATCH 00/24] spi: dm-conversion (part2) Joakim Tjernlund
@ 2020-05-28 0:56 ` Bin Meng
2020-05-28 9:46 ` Jagan Teki
2020-05-28 9:44 ` Priyanka Jain
22 siblings, 1 reply; 59+ messages in thread
From: Bin Meng @ 2020-05-28 0:56 UTC (permalink / raw)
To: u-boot
Hi Jagan,
On Thu, May 28, 2020 at 12:47 AM Jagan Teki <jagan@amarulasolutions.com> wrote:
>
> I believe some boards can directly enable DM_SPI if it has
> OF_CONTROL enabled already, so now it's the last call for
> board maintainers to take care of this.
>
> Now all boards which are using fsl_espi are removed due to
> no action on dm conversion from years.
>
> These will merge as soon as possible, based on the response.
>
> Travis-CI:
> https://travis-ci.org/github/openedev/u-boot-amarula/builds/691819005
>
> Any inputs?
> Jagan.
>
> Jagan Teki (24):
> arm: Remove configs/B4420QDS_NAND_defconfig board
> arm: Remove configs/BSC9131RDB_NAND_SYSCLK100_defconfig board
> arm: Remove configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig board
> arm: Remove configs/C29XPCIE_NAND_defconfig board
> arm: Remove configs/Cyrus_P5020_defconfig board
> arm: Remove configs/MPC8536DS_36BIT_defconfig board
> arm: Remove configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig board
> arm: Remove configs/P1020MBG-PC_36BIT_SDCARD_defconfig board
> arm: Remove configs/P1022DS_36BIT_NAND_defconfig board
> arm: Remove configs/P2041RDB_NAND_defconfig board
> arm: Remove configs/P3041DS_NAND_SECURE_BOOT_defconfig board
> arm: Remove configs/T1023RDB_NAND_defconfig board
> arm: Remove configs/T1024QDS_DDR4_SECURE_BOOT_defconfig board
> arm: Remove configs/T1040D4RDB_NAND_defconfig board
> arm: Remove configs/T1040QDS_DDR4_defconfig board
> arm: Remove configs/T2080QDS_NAND_defconfig board
> arm: Remove configs/T2080RDB_NAND_defconfig board
> arm: Remove configs/T4160QDS_NAND_defconfig board
> arm: Remove configs/T4160RDB_defconfig board
> arm: Remove configs/TWR-P1025_defconfig board
> arm: Remove configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig
> board
> arm: Remove configs/kmcoge4_defconfig board
> spi: Zap fsl_espi
> mtd: spi: Drop fsl_espi_spl
All these boards are powerpc, not arm. So the tag of these patches
should be fixed to use powerpc.
Regards,
Bin
^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH 02/24] arm: Remove configs/BSC9131RDB_NAND_SYSCLK100_defconfig board
2020-05-27 16:46 ` [PATCH 02/24] arm: Remove configs/BSC9131RDB_NAND_SYSCLK100_defconfig board Jagan Teki
@ 2020-05-28 4:17 ` Priyanka Jain
0 siblings, 0 replies; 59+ messages in thread
From: Priyanka Jain @ 2020-05-28 4:17 UTC (permalink / raw)
To: u-boot
>-----Original Message-----
>From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Jagan Teki
>Sent: Wednesday, May 27, 2020 10:17 PM
>To: Simon Glass <sjg@chromium.org>; Tom Rini <trini@konsulko.com>
>Cc: u-boot at lists.denx.de; linux-amarula at amarulasolutions.com; Jagan Teki
><jagan@amarulasolutions.com>
>Subject: [PATCH 02/24] arm: Remove
>configs/BSC9131RDB_NAND_SYSCLK100_defconfig board
>
>This board has not been converted to CONFIG_DM_SPI by the deadline.
>
>Remove it.
>
>Patch-cc: Poonam Aggrwal <poonam.aggrwal@nxp.com>
>Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
>---
> arch/powerpc/cpu/mpc85xx/Kconfig | 1 -
> board/freescale/bsc9131rdb/Kconfig | 12 -
> board/freescale/bsc9131rdb/MAINTAINERS | 9 -
> board/freescale/bsc9131rdb/Makefile | 21 --
> board/freescale/bsc9131rdb/README | 151 --------
> board/freescale/bsc9131rdb/bsc9131rdb.c | 82 -----
> board/freescale/bsc9131rdb/ddr.c | 170 ---------
> board/freescale/bsc9131rdb/law.c | 18 -
> board/freescale/bsc9131rdb/spl_minimal.c | 105 ------
> board/freescale/bsc9131rdb/tlb.c | 61 ----
> configs/BSC9131RDB_NAND_SYSCLK100_defconfig | 64 ----
> configs/BSC9131RDB_NAND_defconfig | 63 ----
> .../BSC9131RDB_SPIFLASH_SYSCLK100_defconfig | 56 ---
> configs/BSC9131RDB_SPIFLASH_defconfig | 56 ---
> include/configs/BSC9131RDB.h | 337 ------------------
> 15 files changed, 1206 deletions(-)
> delete mode 100644 board/freescale/bsc9131rdb/Kconfig
> delete mode 100644 board/freescale/bsc9131rdb/MAINTAINERS
> delete mode 100644 board/freescale/bsc9131rdb/Makefile
> delete mode 100644 board/freescale/bsc9131rdb/README delete mode
>100644 board/freescale/bsc9131rdb/bsc9131rdb.c
> delete mode 100644 board/freescale/bsc9131rdb/ddr.c delete mode 100644
>board/freescale/bsc9131rdb/law.c delete mode 100644
>board/freescale/bsc9131rdb/spl_minimal.c
> delete mode 100644 board/freescale/bsc9131rdb/tlb.c delete mode 100644
>configs/BSC9131RDB_NAND_SYSCLK100_defconfig
> delete mode 100644 configs/BSC9131RDB_NAND_defconfig delete mode
>100644 configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig
> delete mode 100644 configs/BSC9131RDB_SPIFLASH_defconfig
> delete mode 100644 include/configs/BSC9131RDB.h
>
<snip>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH 03/24] arm: Remove configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig board
2020-05-27 16:46 ` [PATCH 03/24] arm: Remove configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig board Jagan Teki
@ 2020-05-28 5:26 ` Priyanka Jain
0 siblings, 0 replies; 59+ messages in thread
From: Priyanka Jain @ 2020-05-28 5:26 UTC (permalink / raw)
To: u-boot
>-----Original Message-----
>From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Jagan Teki
>Sent: Wednesday, May 27, 2020 10:17 PM
>To: Simon Glass <sjg@chromium.org>; Tom Rini <trini@konsulko.com>
>Cc: u-boot at lists.denx.de; linux-amarula at amarulasolutions.com; Jagan Teki
><jagan@amarulasolutions.com>
>Subject: [PATCH 03/24] arm: Remove
>configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig board
>
>This board has not been converted to CONFIG_DM_SPI by the deadline.
>
>Remove it.
>
>Patch-cc: Naveen Burmi <naveen.burmi@nxp.com>
>Patch-cc: Ruchika Gupta <ruchika.gupta@nxp.com>
>Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
>---
> arch/powerpc/cpu/mpc85xx/Kconfig | 1 -
> board/freescale/bsc9132qds/Kconfig | 14 -
> board/freescale/bsc9132qds/MAINTAINERS | 25 -
> board/freescale/bsc9132qds/Makefile | 21 -
> board/freescale/bsc9132qds/README | 150 -----
> board/freescale/bsc9132qds/bsc9132qds.c | 432 --------------
> board/freescale/bsc9132qds/ddr.c | 191 ------
> board/freescale/bsc9132qds/law.c | 28 -
> board/freescale/bsc9132qds/spl_minimal.c | 117 ----
> board/freescale/bsc9132qds/tlb.c | 91 ---
> ...BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig | 66 ---
> configs/BSC9132QDS_NAND_DDRCLK100_defconfig | 72 ---
> ...BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig | 66 ---
> configs/BSC9132QDS_NAND_DDRCLK133_defconfig | 72 ---
> .../BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig | 65 ---
> configs/BSC9132QDS_NOR_DDRCLK100_defconfig | 63 --
> .../BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig | 65 ---
> configs/BSC9132QDS_NOR_DDRCLK133_defconfig | 63 --
> ...C9132QDS_SDCARD_DDRCLK100_SECURE_defconfig | 66 ---
> configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig | 63 --
> ...C9132QDS_SDCARD_DDRCLK133_SECURE_defconfig | 66 ---
> configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig | 63 --
> ...132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig | 66 ---
> .../BSC9132QDS_SPIFLASH_DDRCLK100_defconfig | 64 --
> ...132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig | 66 ---
> .../BSC9132QDS_SPIFLASH_DDRCLK133_defconfig | 64 --
> include/configs/BSC9132QDS.h | 548 ------------------
> 27 files changed, 2668 deletions(-)
> delete mode 100644 board/freescale/bsc9132qds/Kconfig
> delete mode 100644 board/freescale/bsc9132qds/MAINTAINERS
> delete mode 100644 board/freescale/bsc9132qds/Makefile
> delete mode 100644 board/freescale/bsc9132qds/README
> delete mode 100644 board/freescale/bsc9132qds/bsc9132qds.c
> delete mode 100644 board/freescale/bsc9132qds/ddr.c
> delete mode 100644 board/freescale/bsc9132qds/law.c
> delete mode 100644 board/freescale/bsc9132qds/spl_minimal.c
> delete mode 100644 board/freescale/bsc9132qds/tlb.c
> delete mode 100644
>configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig
> delete mode 100644 configs/BSC9132QDS_NAND_DDRCLK100_defconfig
> delete mode 100644
>configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig
> delete mode 100644 configs/BSC9132QDS_NAND_DDRCLK133_defconfig
> delete mode 100644
>configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig
> delete mode 100644 configs/BSC9132QDS_NOR_DDRCLK100_defconfig
> delete mode 100644
>configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig
> delete mode 100644 configs/BSC9132QDS_NOR_DDRCLK133_defconfig
> delete mode 100644
>configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig
> delete mode 100644 configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig
> delete mode 100644
>configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig
> delete mode 100644 configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig
> delete mode 100644
>configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig
> delete mode 100644 configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig
> delete mode 100644
>configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig
> delete mode 100644 configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig
> delete mode 100644 include/configs/BSC9132QDS.h
>
<snip>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH 04/24] arm: Remove configs/C29XPCIE_NAND_defconfig board
2020-05-27 16:46 ` [PATCH 04/24] arm: Remove configs/C29XPCIE_NAND_defconfig board Jagan Teki
@ 2020-05-28 5:28 ` Priyanka Jain
0 siblings, 0 replies; 59+ messages in thread
From: Priyanka Jain @ 2020-05-28 5:28 UTC (permalink / raw)
To: u-boot
>-----Original Message-----
>From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Jagan Teki
>Sent: Wednesday, May 27, 2020 10:17 PM
>To: Simon Glass <sjg@chromium.org>; Tom Rini <trini@konsulko.com>
>Cc: u-boot at lists.denx.de; linux-amarula at amarulasolutions.com; Jagan Teki
><jagan@amarulasolutions.com>
>Subject: [PATCH 04/24] arm: Remove configs/C29XPCIE_NAND_defconfig
>board
>
>This board has not been converted to CONFIG_DM_SPI by the deadline.
>
>Remove it.
>
>Patch-cc: Po Liu <po.liu@nxp.com>
>Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
>---
> arch/powerpc/cpu/mpc85xx/Kconfig | 1 -
> board/freescale/c29xpcie/Kconfig | 14 -
> board/freescale/c29xpcie/MAINTAINERS | 10 -
> board/freescale/c29xpcie/Makefile | 25 --
> board/freescale/c29xpcie/README | 100 -----
> board/freescale/c29xpcie/c29xpcie.c | 159 -------
> board/freescale/c29xpcie/cpld.c | 133 ------
> board/freescale/c29xpcie/cpld.h | 39 --
> board/freescale/c29xpcie/ddr.c | 106 -----
> board/freescale/c29xpcie/law.c | 18 -
> board/freescale/c29xpcie/spl.c | 81 ----
> board/freescale/c29xpcie/spl_minimal.c | 63 ---
> board/freescale/c29xpcie/tlb.c | 84 ----
> configs/C29XPCIE_NAND_defconfig | 70 ----
> configs/C29XPCIE_NOR_SECBOOT_defconfig | 55 ---
> configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig | 57 ---
> configs/C29XPCIE_SPIFLASH_defconfig | 55 ---
> configs/C29XPCIE_defconfig | 53 ---
> include/configs/C29XPCIE.h | 443 --------------------
> 19 files changed, 1566 deletions(-)
> delete mode 100644 board/freescale/c29xpcie/Kconfig
> delete mode 100644 board/freescale/c29xpcie/MAINTAINERS
> delete mode 100644 board/freescale/c29xpcie/Makefile
> delete mode 100644 board/freescale/c29xpcie/README
> delete mode 100644 board/freescale/c29xpcie/c29xpcie.c
> delete mode 100644 board/freescale/c29xpcie/cpld.c
> delete mode 100644 board/freescale/c29xpcie/cpld.h
> delete mode 100644 board/freescale/c29xpcie/ddr.c
> delete mode 100644 board/freescale/c29xpcie/law.c
> delete mode 100644 board/freescale/c29xpcie/spl.c
> delete mode 100644 board/freescale/c29xpcie/spl_minimal.c
> delete mode 100644 board/freescale/c29xpcie/tlb.c
> delete mode 100644 configs/C29XPCIE_NAND_defconfig
> delete mode 100644 configs/C29XPCIE_NOR_SECBOOT_defconfig
> delete mode 100644 configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig
> delete mode 100644 configs/C29XPCIE_SPIFLASH_defconfig
> delete mode 100644 configs/C29XPCIE_defconfig
> delete mode 100644 include/configs/C29XPCIE.h
>
<snip>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH 06/24] arm: Remove configs/MPC8536DS_36BIT_defconfig board
2020-05-27 16:46 ` [PATCH 06/24] arm: Remove configs/MPC8536DS_36BIT_defconfig board Jagan Teki
@ 2020-05-28 5:32 ` Priyanka Jain
0 siblings, 0 replies; 59+ messages in thread
From: Priyanka Jain @ 2020-05-28 5:32 UTC (permalink / raw)
To: u-boot
>-----Original Message-----
>From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Jagan Teki
>Sent: Wednesday, May 27, 2020 10:17 PM
>To: Simon Glass <sjg@chromium.org>; Tom Rini <trini@konsulko.com>
>Cc: u-boot at lists.denx.de; linux-amarula at amarulasolutions.com; Jagan Teki
><jagan@amarulasolutions.com>
>Subject: [PATCH 06/24] arm: Remove configs/MPC8536DS_36BIT_defconfig
>board
Please change prefix arm -> powerpc in the entire patch series
>
>This board has not been converted to CONFIG_DM_SPI by the deadline.
>
>Remove it.
>
>Patch-cc: Priyanka Jain <priyanka.jain@nxp.com>
>Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
>---
> arch/powerpc/cpu/mpc85xx/Kconfig | 1 -
> board/freescale/mpc8536ds/Kconfig | 12 -
> board/freescale/mpc8536ds/MAINTAINERS | 9 -
> board/freescale/mpc8536ds/Makefile | 10 -
> board/freescale/mpc8536ds/README | 127 -----
> board/freescale/mpc8536ds/ddr.c | 59 ---
> board/freescale/mpc8536ds/law.c | 19 -
> board/freescale/mpc8536ds/mpc8536ds.c | 293 ------------
> board/freescale/mpc8536ds/tlb.c | 70 ---
> configs/MPC8536DS_36BIT_defconfig | 61 ---
> configs/MPC8536DS_SDCARD_defconfig | 60 ---
> configs/MPC8536DS_SPIFLASH_defconfig | 61 ---
> configs/MPC8536DS_defconfig | 60 ---
> include/configs/MPC8536DS.h | 642 --------------------------
> 14 files changed, 1484 deletions(-)
> delete mode 100644 board/freescale/mpc8536ds/Kconfig delete mode
>100644 board/freescale/mpc8536ds/MAINTAINERS
> delete mode 100644 board/freescale/mpc8536ds/Makefile
> delete mode 100644 board/freescale/mpc8536ds/README delete mode
>100644 board/freescale/mpc8536ds/ddr.c delete mode 100644
>board/freescale/mpc8536ds/law.c delete mode 100644
>board/freescale/mpc8536ds/mpc8536ds.c
> delete mode 100644 board/freescale/mpc8536ds/tlb.c delete mode 100644
>configs/MPC8536DS_36BIT_defconfig delete mode 100644
>configs/MPC8536DS_SDCARD_defconfig
> delete mode 100644 configs/MPC8536DS_SPIFLASH_defconfig
> delete mode 100644 configs/MPC8536DS_defconfig delete mode 100644
>include/configs/MPC8536DS.h
>
<snip>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH 09/24] arm: Remove configs/P1022DS_36BIT_NAND_defconfig board
2020-05-27 16:46 ` [PATCH 09/24] arm: Remove configs/P1022DS_36BIT_NAND_defconfig board Jagan Teki
@ 2020-05-28 5:37 ` Priyanka Jain
0 siblings, 0 replies; 59+ messages in thread
From: Priyanka Jain @ 2020-05-28 5:37 UTC (permalink / raw)
To: u-boot
>-----Original Message-----
>From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Jagan Teki
>Sent: Wednesday, May 27, 2020 10:17 PM
>To: Simon Glass <sjg@chromium.org>; Tom Rini <trini@konsulko.com>
>Cc: u-boot at lists.denx.de; linux-amarula at amarulasolutions.com; Jagan Teki
><jagan@amarulasolutions.com>
>Subject: [PATCH 09/24] arm: Remove
>configs/P1022DS_36BIT_NAND_defconfig board
>
>This board has not been converted to CONFIG_DM_SPI by the deadline.
>
>Remove it.
>
>Patch-cc: Timur Tabi <timur@tabi.org>
>Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
>---
> arch/powerpc/cpu/mpc85xx/Kconfig | 1 -
> board/freescale/p1022ds/Kconfig | 12 -
> board/freescale/p1022ds/MAINTAINERS | 13 -
> board/freescale/p1022ds/Makefile | 25 -
> board/freescale/p1022ds/README | 23 -
> board/freescale/p1022ds/ddr.c | 106 ----
> board/freescale/p1022ds/diu.c | 478 ------------------
> board/freescale/p1022ds/law.c | 18 -
> board/freescale/p1022ds/p1022ds.c | 364 --------------
> board/freescale/p1022ds/spl.c | 131 -----
> board/freescale/p1022ds/spl_minimal.c | 71 ---
> board/freescale/p1022ds/tlb.c | 101 ----
> configs/P1022DS_36BIT_NAND_defconfig | 80 ---
> configs/P1022DS_36BIT_SDCARD_defconfig | 74 ---
> configs/P1022DS_36BIT_SPIFLASH_defconfig | 76 ---
> configs/P1022DS_36BIT_defconfig | 62 ---
> configs/P1022DS_NAND_defconfig | 79 ---
> configs/P1022DS_SDCARD_defconfig | 73 ---
> configs/P1022DS_SPIFLASH_defconfig | 75 ---
> configs/P1022DS_defconfig | 61 ---
> include/configs/P1022DS.h | 593 -----------------------
> 21 files changed, 2516 deletions(-)
> delete mode 100644 board/freescale/p1022ds/Kconfig
> delete mode 100644 board/freescale/p1022ds/MAINTAINERS
> delete mode 100644 board/freescale/p1022ds/Makefile
> delete mode 100644 board/freescale/p1022ds/README
> delete mode 100644 board/freescale/p1022ds/ddr.c
> delete mode 100644 board/freescale/p1022ds/diu.c
> delete mode 100644 board/freescale/p1022ds/law.c
> delete mode 100644 board/freescale/p1022ds/p1022ds.c
> delete mode 100644 board/freescale/p1022ds/spl.c
> delete mode 100644 board/freescale/p1022ds/spl_minimal.c
> delete mode 100644 board/freescale/p1022ds/tlb.c
> delete mode 100644 configs/P1022DS_36BIT_NAND_defconfig
> delete mode 100644 configs/P1022DS_36BIT_SDCARD_defconfig
> delete mode 100644 configs/P1022DS_36BIT_SPIFLASH_defconfig
> delete mode 100644 configs/P1022DS_36BIT_defconfig
> delete mode 100644 configs/P1022DS_NAND_defconfig
> delete mode 100644 configs/P1022DS_SDCARD_defconfig
> delete mode 100644 configs/P1022DS_SPIFLASH_defconfig
> delete mode 100644 configs/P1022DS_defconfig
> delete mode 100644 include/configs/P1022DS.h
>
<snip>
Please change prefix in subject arm->powerpc. Rest looks fine.
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH 10/24] arm: Remove configs/P2041RDB_NAND_defconfig board
2020-05-27 16:46 ` [PATCH 10/24] arm: Remove configs/P2041RDB_NAND_defconfig board Jagan Teki
@ 2020-05-28 5:43 ` Priyanka Jain
0 siblings, 0 replies; 59+ messages in thread
From: Priyanka Jain @ 2020-05-28 5:43 UTC (permalink / raw)
To: u-boot
>-----Original Message-----
>From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Jagan Teki
>Sent: Wednesday, May 27, 2020 10:17 PM
>To: Simon Glass <sjg@chromium.org>; Tom Rini <trini@konsulko.com>
>Cc: u-boot at lists.denx.de; linux-amarula at amarulasolutions.com; Jagan Teki
><jagan@amarulasolutions.com>
>Subject: [PATCH 10/24] arm: Remove configs/P2041RDB_NAND_defconfig
>board
>
>This board has not been converted to CONFIG_DM_SPI by the deadline.
>
>Remove it.
>
>Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
>---
> arch/powerpc/cpu/mpc85xx/Kconfig | 1 -
> board/freescale/p2041rdb/Kconfig | 14 -
> board/freescale/p2041rdb/MAINTAINERS | 11 -
> board/freescale/p2041rdb/Makefile | 10 -
> board/freescale/p2041rdb/README | 141 ------
> board/freescale/p2041rdb/cpld.c | 157 ------
> board/freescale/p2041rdb/cpld.h | 54 --
> board/freescale/p2041rdb/ddr.c | 143 ------
> board/freescale/p2041rdb/eth.c | 201 --------
> board/freescale/p2041rdb/p2041rdb.c | 244 ---------
> configs/P2041RDB_NAND_defconfig | 64 ---
> configs/P2041RDB_SDCARD_defconfig | 63 ---
> configs/P2041RDB_SECURE_BOOT_defconfig | 57 ---
> configs/P2041RDB_SPIFLASH_defconfig | 64 ---
> configs/P2041RDB_SRIO_PCIE_BOOT_defconfig | 50 --
> configs/P2041RDB_defconfig | 62 ---
> include/configs/P2041RDB.h | 585 ----------------------
> 17 files changed, 1921 deletions(-)
> delete mode 100644 board/freescale/p2041rdb/Kconfig
> delete mode 100644 board/freescale/p2041rdb/MAINTAINERS
> delete mode 100644 board/freescale/p2041rdb/Makefile
> delete mode 100644 board/freescale/p2041rdb/README
> delete mode 100644 board/freescale/p2041rdb/cpld.c
> delete mode 100644 board/freescale/p2041rdb/cpld.h
> delete mode 100644 board/freescale/p2041rdb/ddr.c
> delete mode 100644 board/freescale/p2041rdb/eth.c
> delete mode 100644 board/freescale/p2041rdb/p2041rdb.c
> delete mode 100644 configs/P2041RDB_NAND_defconfig
> delete mode 100644 configs/P2041RDB_SDCARD_defconfig
> delete mode 100644 configs/P2041RDB_SECURE_BOOT_defconfig
> delete mode 100644 configs/P2041RDB_SPIFLASH_defconfig
> delete mode 100644 configs/P2041RDB_SRIO_PCIE_BOOT_defconfig
> delete mode 100644 configs/P2041RDB_defconfig
> delete mode 100644 include/configs/P2041RDB.h
>
NXP plans to keep maintaining P2041RDB. Please don't merge this patch in master.
The espi series of patches for DM migration were in review since long, but could not be merged because of dependency.
NXP engineers are working on rebasing the DM espi migration patch series.
http://patchwork.ozlabs.org/project/uboot/list/?series=127282&state=*
http://patchwork.ozlabs.org/project/uboot/list/?series=138873
Nacked-by: Priyanka Jain <priyanka.jain@nxp.com>
^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH 01/24] arm: Remove configs/B4420QDS_NAND_defconfig board
2020-05-27 16:46 ` [PATCH 01/24] arm: Remove configs/B4420QDS_NAND_defconfig board Jagan Teki
@ 2020-05-28 7:00 ` Priyanka Jain
0 siblings, 0 replies; 59+ messages in thread
From: Priyanka Jain @ 2020-05-28 7:00 UTC (permalink / raw)
To: u-boot
>-----Original Message-----
>From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Jagan Teki
>Sent: Wednesday, May 27, 2020 10:17 PM
>To: Simon Glass <sjg@chromium.org>; Tom Rini <trini@konsulko.com>
>Cc: u-boot at lists.denx.de; linux-amarula at amarulasolutions.com; Jagan Teki
><jagan@amarulasolutions.com>
>Subject: [PATCH 01/24] arm: Remove configs/B4420QDS_NAND_defconfig
>board
>
>This board has not been converted to CONFIG_DM_SPI by the deadline.
>
>Remove it.
>
>Patch-cc: Ashish Kumar <ashish.kumar@nxp.com>
>Patch-cc: Ruchika Gupta <ruchika.gupta@nxp.com>
>Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
>---
> arch/powerpc/cpu/mpc85xx/Kconfig | 1 -
> board/freescale/b4860qds/Kconfig | 14 -
> board/freescale/b4860qds/MAINTAINERS | 17 -
> board/freescale/b4860qds/Makefile | 16 -
> board/freescale/b4860qds/b4860qds.c | 1274 -----------------
> board/freescale/b4860qds/b4860qds.h | 12 -
> .../b4860qds/b4860qds_crossbar_con.h | 72 -
> board/freescale/b4860qds/b4860qds_qixis.h | 28 -
> board/freescale/b4860qds/b4_pbi.cfg | 30 -
> board/freescale/b4860qds/b4_rcw.cfg | 7 -
> board/freescale/b4860qds/ddr.c | 267 ----
> board/freescale/b4860qds/eth_b4860qds.c | 454 ------
> board/freescale/b4860qds/law.c | 28 -
> board/freescale/b4860qds/pci.c | 23 -
> board/freescale/b4860qds/spl.c | 119 --
> board/freescale/b4860qds/tlb.c | 154 --
> configs/B4420QDS_NAND_defconfig | 69 -
> configs/B4420QDS_SPIFLASH_defconfig | 55 -
> configs/B4420QDS_defconfig | 53 -
> configs/B4860QDS_NAND_defconfig | 69 -
> configs/B4860QDS_SECURE_BOOT_defconfig | 56 -
> configs/B4860QDS_SPIFLASH_defconfig | 55 -
> configs/B4860QDS_SRIO_PCIE_BOOT_defconfig | 49 -
> configs/B4860QDS_defconfig | 53 -
> include/configs/B4860QDS.h | 759 ----------
> 25 files changed, 3734 deletions(-)
> delete mode 100644 board/freescale/b4860qds/Kconfig
> delete mode 100644 board/freescale/b4860qds/MAINTAINERS
> delete mode 100644 board/freescale/b4860qds/Makefile
> delete mode 100644 board/freescale/b4860qds/b4860qds.c
> delete mode 100644 board/freescale/b4860qds/b4860qds.h
> delete mode 100644 board/freescale/b4860qds/b4860qds_crossbar_con.h
> delete mode 100644 board/freescale/b4860qds/b4860qds_qixis.h
> delete mode 100644 board/freescale/b4860qds/b4_pbi.cfg
> delete mode 100644 board/freescale/b4860qds/b4_rcw.cfg
> delete mode 100644 board/freescale/b4860qds/ddr.c
> delete mode 100644 board/freescale/b4860qds/eth_b4860qds.c
> delete mode 100644 board/freescale/b4860qds/law.c
> delete mode 100644 board/freescale/b4860qds/pci.c
> delete mode 100644 board/freescale/b4860qds/spl.c
> delete mode 100644 board/freescale/b4860qds/tlb.c
> delete mode 100644 configs/B4420QDS_NAND_defconfig
> delete mode 100644 configs/B4420QDS_SPIFLASH_defconfig
> delete mode 100644 configs/B4420QDS_defconfig
> delete mode 100644 configs/B4860QDS_NAND_defconfig
> delete mode 100644 configs/B4860QDS_SECURE_BOOT_defconfig
> delete mode 100644 configs/B4860QDS_SPIFLASH_defconfig
> delete mode 100644 configs/B4860QDS_SRIO_PCIE_BOOT_defconfig
> delete mode 100644 configs/B4860QDS_defconfig
> delete mode 100644 include/configs/B4860QDS.h
>
<snip>
Please replace arm to powerpc in subject. Rest is fine
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH 15/24] arm: Remove configs/T1040QDS_DDR4_defconfig board
2020-05-27 16:46 ` [PATCH 15/24] arm: Remove configs/T1040QDS_DDR4_defconfig board Jagan Teki
@ 2020-05-28 7:01 ` Priyanka Jain
0 siblings, 0 replies; 59+ messages in thread
From: Priyanka Jain @ 2020-05-28 7:01 UTC (permalink / raw)
To: u-boot
>-----Original Message-----
>From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Jagan Teki
>Sent: Wednesday, May 27, 2020 10:17 PM
>To: Simon Glass <sjg@chromium.org>; Tom Rini <trini@konsulko.com>
>Cc: u-boot at lists.denx.de; linux-amarula at amarulasolutions.com; Jagan Teki
><jagan@amarulasolutions.com>
>Subject: [PATCH 15/24] arm: Remove configs/T1040QDS_DDR4_defconfig
>board
>
>This board has not been converted to CONFIG_DM_SPI by the deadline.
>
>Remove it.
>
>Patch-cc: Poonam Aggrwal <poonam.aggrwal@nxp.com>
>Patch-cc: Ruchika Gupta <ruchika.gupta@nxp.com>
>Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
>---
> arch/powerpc/cpu/mpc85xx/Kconfig | 1 -
> board/freescale/t1040qds/Kconfig | 14 -
> board/freescale/t1040qds/MAINTAINERS | 12 -
> board/freescale/t1040qds/Makefile | 11 -
> board/freescale/t1040qds/README | 169 ------
> board/freescale/t1040qds/ddr.c | 142 -----
> board/freescale/t1040qds/ddr.h | 52 --
> board/freescale/t1040qds/diu.c | 98 ----
> board/freescale/t1040qds/eth.c | 592 -------------------
> board/freescale/t1040qds/law.c | 31 -
> board/freescale/t1040qds/pci.c | 23 -
> board/freescale/t1040qds/t1040_pbi.cfg | 27 -
> board/freescale/t1040qds/t1040_rcw.cfg | 7 -
> board/freescale/t1040qds/t1040qds.c | 305 ----------
> board/freescale/t1040qds/t1040qds.h | 14 -
> board/freescale/t1040qds/t1040qds_qixis.h | 51 --
> board/freescale/t1040qds/tlb.c | 107 ----
> configs/T1040QDS_DDR4_defconfig | 67 ---
> configs/T1040QDS_SECURE_BOOT_defconfig | 70 ---
> configs/T1040QDS_defconfig | 68 ---
> include/configs/T1040QDS.h | 667 ----------------------
> 21 files changed, 2528 deletions(-)
> delete mode 100644 board/freescale/t1040qds/Kconfig
> delete mode 100644 board/freescale/t1040qds/MAINTAINERS
> delete mode 100644 board/freescale/t1040qds/Makefile
> delete mode 100644 board/freescale/t1040qds/README
> delete mode 100644 board/freescale/t1040qds/ddr.c
> delete mode 100644 board/freescale/t1040qds/ddr.h
> delete mode 100644 board/freescale/t1040qds/diu.c
> delete mode 100644 board/freescale/t1040qds/eth.c
> delete mode 100644 board/freescale/t1040qds/law.c
> delete mode 100644 board/freescale/t1040qds/pci.c
> delete mode 100644 board/freescale/t1040qds/t1040_pbi.cfg
> delete mode 100644 board/freescale/t1040qds/t1040_rcw.cfg
> delete mode 100644 board/freescale/t1040qds/t1040qds.c
> delete mode 100644 board/freescale/t1040qds/t1040qds.h
> delete mode 100644 board/freescale/t1040qds/t1040qds_qixis.h
> delete mode 100644 board/freescale/t1040qds/tlb.c
> delete mode 100644 configs/T1040QDS_DDR4_defconfig
> delete mode 100644 configs/T1040QDS_SECURE_BOOT_defconfig
> delete mode 100644 configs/T1040QDS_defconfig
> delete mode 100644 include/configs/T1040QDS.h
>
<snip>
Please replace arm to powerpc in subject. Rest is fine
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH 17/24] arm: Remove configs/T2080RDB_NAND_defconfig board
2020-05-27 16:46 ` [PATCH 17/24] arm: Remove configs/T2080RDB_NAND_defconfig board Jagan Teki
@ 2020-05-28 7:02 ` Priyanka Jain
0 siblings, 0 replies; 59+ messages in thread
From: Priyanka Jain @ 2020-05-28 7:02 UTC (permalink / raw)
To: u-boot
>-----Original Message-----
>From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Jagan Teki
>Sent: Wednesday, May 27, 2020 10:17 PM
>To: Simon Glass <sjg@chromium.org>; Tom Rini <trini@konsulko.com>
>Cc: u-boot at lists.denx.de; linux-amarula at amarulasolutions.com; Jagan Teki
><jagan@amarulasolutions.com>
>Subject: [PATCH 17/24] arm: Remove configs/T2080RDB_NAND_defconfig
>board
>
>This board has not been converted to CONFIG_DM_SPI by the deadline.
>
>Remove it.
>
>Patch-cc: Shengzhou Liu <Shengzhou.Liu@nxp.com>
>Patch-cc: Ruchika Gupta <ruchika.gupta@nxp.com>
>Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
>---
> arch/powerpc/cpu/mpc85xx/Kconfig | 1 -
> board/freescale/t208xrdb/Kconfig | 14 -
> board/freescale/t208xrdb/MAINTAINERS | 15 -
> board/freescale/t208xrdb/Makefile | 16 -
> board/freescale/t208xrdb/README | 283 --------
> board/freescale/t208xrdb/cpld.c | 70 --
> board/freescale/t208xrdb/cpld.h | 44 --
> board/freescale/t208xrdb/ddr.c | 118 ----
> board/freescale/t208xrdb/ddr.h | 46 --
> board/freescale/t208xrdb/eth_t208xrdb.c | 107 ---
> board/freescale/t208xrdb/law.c | 33 -
> board/freescale/t208xrdb/pci.c | 25 -
> board/freescale/t208xrdb/spl.c | 112 ---
> board/freescale/t208xrdb/t2080_nand_rcw.cfg | 19 -
> board/freescale/t208xrdb/t2080_pbi.cfg | 40 --
> board/freescale/t208xrdb/t2080_sd_rcw.cfg | 19 -
> board/freescale/t208xrdb/t2080_spi_rcw.cfg | 19 -
> board/freescale/t208xrdb/t208xrdb.c | 142 ----
> board/freescale/t208xrdb/t208xrdb.h | 12 -
> board/freescale/t208xrdb/tlb.c | 152 -----
> configs/T2080RDB_NAND_defconfig | 84 ---
> configs/T2080RDB_SDCARD_defconfig | 81 ---
> configs/T2080RDB_SECURE_BOOT_defconfig | 63 --
> configs/T2080RDB_SPIFLASH_defconfig | 84 ---
> configs/T2080RDB_SRIO_PCIE_BOOT_defconfig | 53 --
> configs/T2080RDB_defconfig | 68 --
> include/configs/T208xRDB.h | 717 --------------------
> 27 files changed, 2437 deletions(-)
> delete mode 100644 board/freescale/t208xrdb/Kconfig
> delete mode 100644 board/freescale/t208xrdb/MAINTAINERS
> delete mode 100644 board/freescale/t208xrdb/Makefile
> delete mode 100644 board/freescale/t208xrdb/README
> delete mode 100644 board/freescale/t208xrdb/cpld.c
> delete mode 100644 board/freescale/t208xrdb/cpld.h
> delete mode 100644 board/freescale/t208xrdb/ddr.c
> delete mode 100644 board/freescale/t208xrdb/ddr.h
> delete mode 100644 board/freescale/t208xrdb/eth_t208xrdb.c
> delete mode 100644 board/freescale/t208xrdb/law.c
> delete mode 100644 board/freescale/t208xrdb/pci.c
> delete mode 100644 board/freescale/t208xrdb/spl.c
> delete mode 100644 board/freescale/t208xrdb/t2080_nand_rcw.cfg
> delete mode 100644 board/freescale/t208xrdb/t2080_pbi.cfg
> delete mode 100644 board/freescale/t208xrdb/t2080_sd_rcw.cfg
> delete mode 100644 board/freescale/t208xrdb/t2080_spi_rcw.cfg
> delete mode 100644 board/freescale/t208xrdb/t208xrdb.c
> delete mode 100644 board/freescale/t208xrdb/t208xrdb.h
> delete mode 100644 board/freescale/t208xrdb/tlb.c
> delete mode 100644 configs/T2080RDB_NAND_defconfig
> delete mode 100644 configs/T2080RDB_SDCARD_defconfig
> delete mode 100644 configs/T2080RDB_SECURE_BOOT_defconfig
> delete mode 100644 configs/T2080RDB_SPIFLASH_defconfig
> delete mode 100644 configs/T2080RDB_SRIO_PCIE_BOOT_defconfig
> delete mode 100644 configs/T2080RDB_defconfig
> delete mode 100644 include/configs/T208xRDB.h
>
<snip>
NXP plans to keep maintaining T2080RDB board. Please don't merge this patch in master.
The espi series of patches for DM migration were in review since long, but could not be merged because of dependency.
NXP engineers are working on rebasing the DM espi migration series.
http://patchwork.ozlabs.org/project/uboot/list/?series=127282&state=*
http://patchwork.ozlabs.org/project/uboot/list/?series=138873
Nacked-by: Priyanka Jain <priyanka.jain@nxp.com>
^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH 19/24] arm: Remove configs/T4160RDB_defconfig board
2020-05-27 16:46 ` [PATCH 19/24] arm: Remove configs/T4160RDB_defconfig board Jagan Teki
@ 2020-05-28 7:04 ` Priyanka Jain
0 siblings, 0 replies; 59+ messages in thread
From: Priyanka Jain @ 2020-05-28 7:04 UTC (permalink / raw)
To: u-boot
>-----Original Message-----
>From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Jagan Teki
>Sent: Wednesday, May 27, 2020 10:17 PM
>To: Simon Glass <sjg@chromium.org>; Tom Rini <trini@konsulko.com>
>Cc: u-boot at lists.denx.de; linux-amarula at amarulasolutions.com; Jagan Teki
><jagan@amarulasolutions.com>
>Subject: [PATCH 19/24] arm: Remove configs/T4160RDB_defconfig board
>
>This board has not been converted to CONFIG_DM_SPI by the deadline.
>
>Remove it.
>
>Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
>---
> arch/powerpc/cpu/mpc85xx/Kconfig | 1 -
> board/freescale/t4rdb/Kconfig | 14 -
> board/freescale/t4rdb/MAINTAINERS | 8 -
> board/freescale/t4rdb/Makefile | 19 -
> board/freescale/t4rdb/cpld.c | 129 ------
> board/freescale/t4rdb/cpld.h | 48 --
> board/freescale/t4rdb/ddr.c | 127 ------
> board/freescale/t4rdb/ddr.h | 77 ----
> board/freescale/t4rdb/eth.c | 152 -------
> board/freescale/t4rdb/law.c | 30 --
> board/freescale/t4rdb/pci.c | 25 -
> board/freescale/t4rdb/spl.c | 99 ----
> board/freescale/t4rdb/t4240rdb.c | 150 ------
> board/freescale/t4rdb/t4_pbi.cfg | 27 --
> board/freescale/t4rdb/t4_sd_rcw.cfg | 7 -
> board/freescale/t4rdb/t4rdb.h | 17 -
> board/freescale/t4rdb/tlb.c | 123 -----
> configs/T4160RDB_defconfig | 54 ---
> configs/T4240RDB_SDCARD_defconfig | 74 ---
> configs/T4240RDB_defconfig | 62 ---
> include/configs/T4240RDB.h | 681 ----------------------------
> 21 files changed, 1924 deletions(-)
> delete mode 100644 board/freescale/t4rdb/Kconfig
> delete mode 100644 board/freescale/t4rdb/MAINTAINERS
> delete mode 100644 board/freescale/t4rdb/Makefile
> delete mode 100644 board/freescale/t4rdb/cpld.c
> delete mode 100644 board/freescale/t4rdb/cpld.h
> delete mode 100644 board/freescale/t4rdb/ddr.c
> delete mode 100644 board/freescale/t4rdb/ddr.h
> delete mode 100644 board/freescale/t4rdb/eth.c
> delete mode 100644 board/freescale/t4rdb/law.c
> delete mode 100644 board/freescale/t4rdb/pci.c
> delete mode 100644 board/freescale/t4rdb/spl.c
> delete mode 100644 board/freescale/t4rdb/t4240rdb.c
> delete mode 100644 board/freescale/t4rdb/t4_pbi.cfg
> delete mode 100644 board/freescale/t4rdb/t4_sd_rcw.cfg
> delete mode 100644 board/freescale/t4rdb/t4rdb.h
> delete mode 100644 board/freescale/t4rdb/tlb.c
> delete mode 100644 configs/T4160RDB_defconfig
> delete mode 100644 configs/T4240RDB_SDCARD_defconfig
> delete mode 100644 configs/T4240RDB_defconfig
> delete mode 100644 include/configs/T4240RDB.h
>
<snip>
NXP plans to keep maintaining T4240RDB board. Please don't merge this patch .
The espi series of patches for DM migration were in review since long, but could not be merged because of dependency.
NXP engineers are working on rebasing the DM espi migration series.
http://patchwork.ozlabs.org/project/uboot/list/?series=127282&state=*
http://patchwork.ozlabs.org/project/uboot/list/?series=138873
Nacked-by: Priyanka Jain <priyanka.jain@nxp.com>
^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH 07/24] arm: Remove configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig board
2020-05-27 16:46 ` [PATCH 07/24] arm: Remove configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig board Jagan Teki
@ 2020-05-28 7:05 ` Priyanka Jain
2020-05-28 20:02 ` Tom Rini
0 siblings, 1 reply; 59+ messages in thread
From: Priyanka Jain @ 2020-05-28 7:05 UTC (permalink / raw)
To: u-boot
>-----Original Message-----
>From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Jagan Teki
>Sent: Wednesday, May 27, 2020 10:17 PM
>To: Simon Glass <sjg@chromium.org>; Tom Rini <trini@konsulko.com>
>Cc: u-boot at lists.denx.de; linux-amarula at amarulasolutions.com; Jagan Teki
><jagan@amarulasolutions.com>
>Subject: [PATCH 07/24] arm: Remove configs/P1010RDB-
>PA_36BIT_NAND_SECBOOT_defconfig board
>
>This board has not been converted to CONFIG_DM_SPI by the deadline.
>
>Remove it.
>
>Patch-cc: Qiang Zhao <qiang.zhao@nxp.com>
>Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
>---
> arch/powerpc/cpu/mpc85xx/Kconfig | 1 -
> board/freescale/p1010rdb/Kconfig | 14 -
> board/freescale/p1010rdb/MAINTAINERS | 33 -
> board/freescale/p1010rdb/Makefile | 24 -
> board/freescale/p1010rdb/README.P1010RDB-PA | 208 -----
> board/freescale/p1010rdb/README.P1010RDB-PB | 188 -----
> board/freescale/p1010rdb/ddr.c | 235 ------
> board/freescale/p1010rdb/law.c | 16 -
> board/freescale/p1010rdb/p1010rdb.c | 731 -----------------
> board/freescale/p1010rdb/spl.c | 114 ---
> board/freescale/p1010rdb/spl_minimal.c | 65 --
> board/freescale/p1010rdb/tlb.c | 90 --
> .../P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig | 63 --
> configs/P1010RDB-PA_36BIT_NAND_defconfig | 85 --
> .../P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig | 62 --
> configs/P1010RDB-PA_36BIT_NOR_defconfig | 67 --
> configs/P1010RDB-PA_36BIT_SDCARD_defconfig | 79 --
> ...010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig | 64 --
> configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig | 81 --
> configs/P1010RDB-PA_NAND_SECBOOT_defconfig | 62 --
> configs/P1010RDB-PA_NAND_defconfig | 84 --
> configs/P1010RDB-PA_NOR_SECBOOT_defconfig | 60 --
> configs/P1010RDB-PA_NOR_defconfig | 66 --
> configs/P1010RDB-PA_SDCARD_defconfig | 78 --
> .../P1010RDB-PA_SPIFLASH_SECBOOT_defconfig | 63 --
> configs/P1010RDB-PA_SPIFLASH_defconfig | 80 --
> .../P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig | 63 --
> configs/P1010RDB-PB_36BIT_NAND_defconfig | 85 --
> .../P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig | 62 --
> configs/P1010RDB-PB_36BIT_NOR_defconfig | 67 --
> configs/P1010RDB-PB_36BIT_SDCARD_defconfig | 79 --
> ...010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig | 64 --
> configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig | 81 --
> configs/P1010RDB-PB_NAND_SECBOOT_defconfig | 62 --
> configs/P1010RDB-PB_NAND_defconfig | 84 --
> configs/P1010RDB-PB_NOR_SECBOOT_defconfig | 61 --
> configs/P1010RDB-PB_NOR_defconfig | 66 --
> configs/P1010RDB-PB_SDCARD_defconfig | 78 --
> .../P1010RDB-PB_SPIFLASH_SECBOOT_defconfig | 63 --
> configs/P1010RDB-PB_SPIFLASH_defconfig | 80 --
> include/configs/P1010RDB.h | 766 ------------------
> 41 files changed, 4474 deletions(-)
> delete mode 100644 board/freescale/p1010rdb/Kconfig
> delete mode 100644 board/freescale/p1010rdb/MAINTAINERS
> delete mode 100644 board/freescale/p1010rdb/Makefile
> delete mode 100644 board/freescale/p1010rdb/README.P1010RDB-PA
> delete mode 100644 board/freescale/p1010rdb/README.P1010RDB-PB
> delete mode 100644 board/freescale/p1010rdb/ddr.c
> delete mode 100644 board/freescale/p1010rdb/law.c
> delete mode 100644 board/freescale/p1010rdb/p1010rdb.c
> delete mode 100644 board/freescale/p1010rdb/spl.c
> delete mode 100644 board/freescale/p1010rdb/spl_minimal.c
> delete mode 100644 board/freescale/p1010rdb/tlb.c
> delete mode 100644 configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig
> delete mode 100644 configs/P1010RDB-PA_36BIT_NAND_defconfig
> delete mode 100644 configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig
> delete mode 100644 configs/P1010RDB-PA_36BIT_NOR_defconfig
> delete mode 100644 configs/P1010RDB-PA_36BIT_SDCARD_defconfig
> delete mode 100644 configs/P1010RDB-
>PA_36BIT_SPIFLASH_SECBOOT_defconfig
> delete mode 100644 configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
> delete mode 100644 configs/P1010RDB-PA_NAND_SECBOOT_defconfig
> delete mode 100644 configs/P1010RDB-PA_NAND_defconfig
> delete mode 100644 configs/P1010RDB-PA_NOR_SECBOOT_defconfig
> delete mode 100644 configs/P1010RDB-PA_NOR_defconfig
> delete mode 100644 configs/P1010RDB-PA_SDCARD_defconfig
> delete mode 100644 configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig
> delete mode 100644 configs/P1010RDB-PA_SPIFLASH_defconfig
> delete mode 100644 configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig
> delete mode 100644 configs/P1010RDB-PB_36BIT_NAND_defconfig
> delete mode 100644 configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig
> delete mode 100644 configs/P1010RDB-PB_36BIT_NOR_defconfig
> delete mode 100644 configs/P1010RDB-PB_36BIT_SDCARD_defconfig
> delete mode 100644 configs/P1010RDB-
>PB_36BIT_SPIFLASH_SECBOOT_defconfig
> delete mode 100644 configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
> delete mode 100644 configs/P1010RDB-PB_NAND_SECBOOT_defconfig
> delete mode 100644 configs/P1010RDB-PB_NAND_defconfig
> delete mode 100644 configs/P1010RDB-PB_NOR_SECBOOT_defconfig
> delete mode 100644 configs/P1010RDB-PB_NOR_defconfig
> delete mode 100644 configs/P1010RDB-PB_SDCARD_defconfig
> delete mode 100644 configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig
> delete mode 100644 configs/P1010RDB-PB_SPIFLASH_defconfig
> delete mode 100644 include/configs/P1010RDB.h
>
<snip>
NXP plans to keep maintaining P1010RDB board. Please don't merge this patch .
The espi series of patches for DM migration were in review since long, but could not be merged because of dependency.
NXP engineers are working on rebasing the DM espi migration series.
http://patchwork.ozlabs.org/project/uboot/list/?series=127282&state=*
http://patchwork.ozlabs.org/project/uboot/list/?series=138873
Nacked-by: Priyanka Jain <priyanka.jain@nxp.com>
^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH 08/24] arm: Remove configs/P1020MBG-PC_36BIT_SDCARD_defconfig board
2020-05-27 16:46 ` [PATCH 08/24] arm: Remove configs/P1020MBG-PC_36BIT_SDCARD_defconfig board Jagan Teki
@ 2020-05-28 7:07 ` Priyanka Jain
2020-05-28 20:14 ` Tom Rini
0 siblings, 1 reply; 59+ messages in thread
From: Priyanka Jain @ 2020-05-28 7:07 UTC (permalink / raw)
To: u-boot
>-----Original Message-----
>From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Jagan Teki
>Sent: Wednesday, May 27, 2020 10:17 PM
>To: Simon Glass <sjg@chromium.org>; Tom Rini <trini@konsulko.com>
>Cc: u-boot at lists.denx.de; linux-amarula at amarulasolutions.com; Jagan Teki
><jagan@amarulasolutions.com>
>Subject: [PATCH 08/24] arm: Remove configs/P1020MBG-
>PC_36BIT_SDCARD_defconfig board
>
>This board has not been converted to CONFIG_DM_SPI by the deadline.
>
>Remove it.
>
>Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
>---
> arch/powerpc/cpu/mpc85xx/Kconfig | 1 -
> board/freescale/p1_p2_rdb_pc/Kconfig | 19 -
> board/freescale/p1_p2_rdb_pc/MAINTAINERS | 51 --
> board/freescale/p1_p2_rdb_pc/Makefile | 24 -
> board/freescale/p1_p2_rdb_pc/README | 66 --
> board/freescale/p1_p2_rdb_pc/ddr.c | 292 ------
> board/freescale/p1_p2_rdb_pc/law.c | 22 -
> board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 536 -----------
> board/freescale/p1_p2_rdb_pc/spl.c | 123 ---
> board/freescale/p1_p2_rdb_pc/spl_minimal.c | 63 --
> board/freescale/p1_p2_rdb_pc/tlb.c | 110 ---
> configs/P1020MBG-PC_36BIT_SDCARD_defconfig | 67 --
> configs/P1020MBG-PC_36BIT_defconfig | 55 --
> configs/P1020MBG-PC_SDCARD_defconfig | 66 --
> configs/P1020MBG-PC_defconfig | 54 --
> configs/P1020RDB-PC_36BIT_NAND_defconfig | 85 --
> configs/P1020RDB-PC_36BIT_SDCARD_defconfig | 80 --
> configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 82 --
> configs/P1020RDB-PC_36BIT_defconfig | 69 --
> configs/P1020RDB-PC_NAND_defconfig | 84 --
> configs/P1020RDB-PC_SDCARD_defconfig | 79 --
> configs/P1020RDB-PC_SPIFLASH_defconfig | 81 --
> configs/P1020RDB-PC_defconfig | 68 --
> configs/P1020RDB-PD_NAND_defconfig | 88 --
> configs/P1020RDB-PD_SDCARD_defconfig | 83 --
> configs/P1020RDB-PD_SPIFLASH_defconfig | 85 --
> configs/P1020RDB-PD_defconfig | 72 --
> configs/P1020UTM-PC_36BIT_SDCARD_defconfig | 67 --
> configs/P1020UTM-PC_36BIT_defconfig | 55 --
> configs/P1020UTM-PC_SDCARD_defconfig | 66 --
> configs/P1020UTM-PC_defconfig | 54 --
> configs/P1021RDB-PC_36BIT_NAND_defconfig | 84 --
> configs/P1021RDB-PC_36BIT_SDCARD_defconfig | 79 --
> configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig | 81 --
> configs/P1021RDB-PC_36BIT_defconfig | 67 --
> configs/P1021RDB-PC_NAND_defconfig | 83 --
> configs/P1021RDB-PC_SDCARD_defconfig | 78 --
> configs/P1021RDB-PC_SPIFLASH_defconfig | 80 --
> configs/P1021RDB-PC_defconfig | 66 --
> configs/P1024RDB_36BIT_defconfig | 61 --
> configs/P1024RDB_NAND_defconfig | 77 --
> configs/P1024RDB_SDCARD_defconfig | 71 --
> configs/P1024RDB_SPIFLASH_defconfig | 73 --
> configs/P1024RDB_defconfig | 60 --
> configs/P1025RDB_36BIT_defconfig | 63 --
> configs/P1025RDB_NAND_defconfig | 80 --
> configs/P1025RDB_SDCARD_defconfig | 73 --
> configs/P1025RDB_SPIFLASH_defconfig | 76 --
> configs/P1025RDB_defconfig | 62 --
> configs/P2020RDB-PC_36BIT_NAND_defconfig | 90 --
> configs/P2020RDB-PC_36BIT_SDCARD_defconfig | 85 --
> configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 87 --
> configs/P2020RDB-PC_36BIT_defconfig | 74 --
> configs/P2020RDB-PC_NAND_defconfig | 89 --
> configs/P2020RDB-PC_SDCARD_defconfig | 84 --
> configs/P2020RDB-PC_SPIFLASH_defconfig | 86 --
> configs/P2020RDB-PC_defconfig | 73 --
> include/configs/p1_p2_rdb_pc.h | 881 -------------------
> 58 files changed, 5610 deletions(-)
> delete mode 100644 board/freescale/p1_p2_rdb_pc/Kconfig
> delete mode 100644 board/freescale/p1_p2_rdb_pc/MAINTAINERS
> delete mode 100644 board/freescale/p1_p2_rdb_pc/Makefile
> delete mode 100644 board/freescale/p1_p2_rdb_pc/README
> delete mode 100644 board/freescale/p1_p2_rdb_pc/ddr.c
> delete mode 100644 board/freescale/p1_p2_rdb_pc/law.c
> delete mode 100644 board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
> delete mode 100644 board/freescale/p1_p2_rdb_pc/spl.c
> delete mode 100644 board/freescale/p1_p2_rdb_pc/spl_minimal.c
> delete mode 100644 board/freescale/p1_p2_rdb_pc/tlb.c
> delete mode 100644 configs/P1020MBG-PC_36BIT_SDCARD_defconfig
> delete mode 100644 configs/P1020MBG-PC_36BIT_defconfig
> delete mode 100644 configs/P1020MBG-PC_SDCARD_defconfig
> delete mode 100644 configs/P1020MBG-PC_defconfig
> delete mode 100644 configs/P1020RDB-PC_36BIT_NAND_defconfig
> delete mode 100644 configs/P1020RDB-PC_36BIT_SDCARD_defconfig
> delete mode 100644 configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
> delete mode 100644 configs/P1020RDB-PC_36BIT_defconfig
> delete mode 100644 configs/P1020RDB-PC_NAND_defconfig
> delete mode 100644 configs/P1020RDB-PC_SDCARD_defconfig
> delete mode 100644 configs/P1020RDB-PC_SPIFLASH_defconfig
> delete mode 100644 configs/P1020RDB-PC_defconfig
> delete mode 100644 configs/P1020RDB-PD_NAND_defconfig
> delete mode 100644 configs/P1020RDB-PD_SDCARD_defconfig
> delete mode 100644 configs/P1020RDB-PD_SPIFLASH_defconfig
> delete mode 100644 configs/P1020RDB-PD_defconfig
> delete mode 100644 configs/P1020UTM-PC_36BIT_SDCARD_defconfig
> delete mode 100644 configs/P1020UTM-PC_36BIT_defconfig
> delete mode 100644 configs/P1020UTM-PC_SDCARD_defconfig
> delete mode 100644 configs/P1020UTM-PC_defconfig
> delete mode 100644 configs/P1021RDB-PC_36BIT_NAND_defconfig
> delete mode 100644 configs/P1021RDB-PC_36BIT_SDCARD_defconfig
> delete mode 100644 configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig
> delete mode 100644 configs/P1021RDB-PC_36BIT_defconfig
> delete mode 100644 configs/P1021RDB-PC_NAND_defconfig
> delete mode 100644 configs/P1021RDB-PC_SDCARD_defconfig
> delete mode 100644 configs/P1021RDB-PC_SPIFLASH_defconfig
> delete mode 100644 configs/P1021RDB-PC_defconfig
> delete mode 100644 configs/P1024RDB_36BIT_defconfig
> delete mode 100644 configs/P1024RDB_NAND_defconfig
> delete mode 100644 configs/P1024RDB_SDCARD_defconfig
> delete mode 100644 configs/P1024RDB_SPIFLASH_defconfig
> delete mode 100644 configs/P1024RDB_defconfig
> delete mode 100644 configs/P1025RDB_36BIT_defconfig
> delete mode 100644 configs/P1025RDB_NAND_defconfig
> delete mode 100644 configs/P1025RDB_SDCARD_defconfig
> delete mode 100644 configs/P1025RDB_SPIFLASH_defconfig
> delete mode 100644 configs/P1025RDB_defconfig
> delete mode 100644 configs/P2020RDB-PC_36BIT_NAND_defconfig
> delete mode 100644 configs/P2020RDB-PC_36BIT_SDCARD_defconfig
> delete mode 100644 configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
> delete mode 100644 configs/P2020RDB-PC_36BIT_defconfig
> delete mode 100644 configs/P2020RDB-PC_NAND_defconfig
> delete mode 100644 configs/P2020RDB-PC_SDCARD_defconfig
> delete mode 100644 configs/P2020RDB-PC_SPIFLASH_defconfig
> delete mode 100644 configs/P2020RDB-PC_defconfig
> delete mode 100644 include/configs/p1_p2_rdb_pc.h
>
<snip>
NXP plans to keep maintaining these boards. Please don't merge this patch .
The espi series of patches for DM migration were in review since long, but could not be merged because of dependency.
NXP engineers are working on rebasing the DM espi migration series.
http://patchwork.ozlabs.org/project/uboot/list/?series=127282&state=*
http://patchwork.ozlabs.org/project/uboot/list/?series=138873
Nacked-by: Priyanka Jain <priyanka.jain@nxp.com>
^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH 12/24] arm: Remove configs/T1023RDB_NAND_defconfig board
2020-05-27 16:46 ` [PATCH 12/24] arm: Remove configs/T1023RDB_NAND_defconfig board Jagan Teki
@ 2020-05-28 7:08 ` Priyanka Jain
2020-05-28 20:18 ` Tom Rini
0 siblings, 1 reply; 59+ messages in thread
From: Priyanka Jain @ 2020-05-28 7:08 UTC (permalink / raw)
To: u-boot
>-----Original Message-----
>From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Jagan Teki
>Sent: Wednesday, May 27, 2020 10:17 PM
>To: Simon Glass <sjg@chromium.org>; Tom Rini <trini@konsulko.com>
>Cc: u-boot at lists.denx.de; linux-amarula at amarulasolutions.com; Jagan Teki
><jagan@amarulasolutions.com>
>Subject: [PATCH 12/24] arm: Remove configs/T1023RDB_NAND_defconfig
>board
>
>This board has not been converted to CONFIG_DM_SPI by the deadline.
>
>Remove it.
>
>Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
>---
> arch/powerpc/cpu/mpc85xx/Kconfig | 1 -
> board/freescale/t102xrdb/Kconfig | 14 -
> board/freescale/t102xrdb/MAINTAINERS | 15 -
> board/freescale/t102xrdb/Makefile | 17 -
> board/freescale/t102xrdb/README | 340 ---------
> board/freescale/t102xrdb/cpld.c | 102 ---
> board/freescale/t102xrdb/cpld.h | 48 --
> board/freescale/t102xrdb/ddr.c | 257 -------
> board/freescale/t102xrdb/eth_t102xrdb.c | 146 ----
> board/freescale/t102xrdb/law.c | 31 -
> board/freescale/t102xrdb/pci.c | 25 -
> board/freescale/t102xrdb/spl.c | 143 ----
> board/freescale/t102xrdb/t1023_nand_rcw.cfg | 8 -
> board/freescale/t102xrdb/t1023_sd_rcw.cfg | 8 -
> board/freescale/t102xrdb/t1023_spi_rcw.cfg | 8 -
> board/freescale/t102xrdb/t1024_nand_rcw.cfg | 8 -
> board/freescale/t102xrdb/t1024_pbi.cfg | 26 -
> board/freescale/t102xrdb/t1024_sd_rcw.cfg | 8 -
> board/freescale/t102xrdb/t1024_spi_rcw.cfg | 8 -
> board/freescale/t102xrdb/t102xrdb.c | 394 -----------
> board/freescale/t102xrdb/t102xrdb.h | 15 -
> board/freescale/t102xrdb/tlb.c | 116 ----
> configs/T1023RDB_NAND_defconfig | 77 ---
> configs/T1023RDB_SDCARD_defconfig | 74 --
> configs/T1023RDB_SECURE_BOOT_defconfig | 64 --
> configs/T1023RDB_SPIFLASH_defconfig | 77 ---
> configs/T1023RDB_defconfig | 61 --
> configs/T1024RDB_NAND_defconfig | 86 ---
> configs/T1024RDB_SDCARD_defconfig | 83 ---
> configs/T1024RDB_SECURE_BOOT_defconfig | 66 --
> configs/T1024RDB_SPIFLASH_defconfig | 86 ---
> configs/T1024RDB_defconfig | 71 --
> include/configs/T102xRDB.h | 721 --------------------
> 33 files changed, 3204 deletions(-)
> delete mode 100644 board/freescale/t102xrdb/Kconfig
> delete mode 100644 board/freescale/t102xrdb/MAINTAINERS
> delete mode 100644 board/freescale/t102xrdb/Makefile
> delete mode 100644 board/freescale/t102xrdb/README
> delete mode 100644 board/freescale/t102xrdb/cpld.c
> delete mode 100644 board/freescale/t102xrdb/cpld.h
> delete mode 100644 board/freescale/t102xrdb/ddr.c
> delete mode 100644 board/freescale/t102xrdb/eth_t102xrdb.c
> delete mode 100644 board/freescale/t102xrdb/law.c
> delete mode 100644 board/freescale/t102xrdb/pci.c
> delete mode 100644 board/freescale/t102xrdb/spl.c
> delete mode 100644 board/freescale/t102xrdb/t1023_nand_rcw.cfg
> delete mode 100644 board/freescale/t102xrdb/t1023_sd_rcw.cfg
> delete mode 100644 board/freescale/t102xrdb/t1023_spi_rcw.cfg
> delete mode 100644 board/freescale/t102xrdb/t1024_nand_rcw.cfg
> delete mode 100644 board/freescale/t102xrdb/t1024_pbi.cfg
> delete mode 100644 board/freescale/t102xrdb/t1024_sd_rcw.cfg
> delete mode 100644 board/freescale/t102xrdb/t1024_spi_rcw.cfg
> delete mode 100644 board/freescale/t102xrdb/t102xrdb.c
> delete mode 100644 board/freescale/t102xrdb/t102xrdb.h
> delete mode 100644 board/freescale/t102xrdb/tlb.c
> delete mode 100644 configs/T1023RDB_NAND_defconfig
> delete mode 100644 configs/T1023RDB_SDCARD_defconfig
> delete mode 100644 configs/T1023RDB_SECURE_BOOT_defconfig
> delete mode 100644 configs/T1023RDB_SPIFLASH_defconfig
> delete mode 100644 configs/T1023RDB_defconfig
> delete mode 100644 configs/T1024RDB_NAND_defconfig
> delete mode 100644 configs/T1024RDB_SDCARD_defconfig
> delete mode 100644 configs/T1024RDB_SECURE_BOOT_defconfig
> delete mode 100644 configs/T1024RDB_SPIFLASH_defconfig
> delete mode 100644 configs/T1024RDB_defconfig
> delete mode 100644 include/configs/T102xRDB.h
>
<snip>
NXP plans to keep maintaining these boards. Please don't merge this patch .
The espi series of patches for DM migration were in review since long, but could not be merged because of dependency.
NXP engineers are working on rebasing the DM espi migration series.
http://patchwork.ozlabs.org/project/uboot/list/?series=127282&state=*
http://patchwork.ozlabs.org/project/uboot/list/?series=138873
Nacked-by: Priyanka Jain <priyanka.jain@nxp.com>
^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH 11/24] arm: Remove configs/P3041DS_NAND_SECURE_BOOT_defconfig board
2020-05-27 16:46 ` [PATCH 11/24] arm: Remove configs/P3041DS_NAND_SECURE_BOOT_defconfig board Jagan Teki
@ 2020-05-28 7:09 ` Priyanka Jain
2020-05-28 20:37 ` Tom Rini
0 siblings, 1 reply; 59+ messages in thread
From: Priyanka Jain @ 2020-05-28 7:09 UTC (permalink / raw)
To: u-boot
>-----Original Message-----
>From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Jagan Teki
>Sent: Wednesday, May 27, 2020 10:17 PM
>To: Simon Glass <sjg@chromium.org>; Tom Rini <trini@konsulko.com>
>Cc: u-boot at lists.denx.de; linux-amarula at amarulasolutions.com; Jagan Teki
><jagan@amarulasolutions.com>
>Subject: [PATCH 11/24] arm: Remove
>configs/P3041DS_NAND_SECURE_BOOT_defconfig board
>
>This board has not been converted to CONFIG_DM_SPI by the deadline.
>
>Remove it.
>
>Patch-cc: Ruchika Gupta <ruchika.gupta@nxp.com>
>Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
>---
> arch/powerpc/cpu/mpc85xx/Kconfig | 1 -
> board/freescale/corenet_ds/Kconfig | 59 --
> board/freescale/corenet_ds/MAINTAINERS | 37 -
> board/freescale/corenet_ds/Makefile | 16 -
> board/freescale/corenet_ds/corenet_ds.c | 215 ------
> board/freescale/corenet_ds/corenet_ds.h | 12 -
> board/freescale/corenet_ds/ddr.c | 286 --------
> board/freescale/corenet_ds/eth_hydra.c | 520 -------------
> board/freescale/corenet_ds/eth_p4080.c | 483 ------------
> board/freescale/corenet_ds/eth_superhydra.c | 771 --------------------
> board/freescale/corenet_ds/p3041ds_ddr.c | 11 -
> board/freescale/corenet_ds/p4080ds_ddr.c | 347 ---------
> board/freescale/corenet_ds/p5020ds_ddr.c | 15 -
> board/freescale/corenet_ds/p5040ds_ddr.c | 15 -
> board/freescale/corenet_ds/pbi.cfg | 33 -
> board/freescale/corenet_ds/rcw_p2041rdb.cfg | 11 -
> board/freescale/corenet_ds/rcw_p3041ds.cfg | 11 -
> board/freescale/corenet_ds/rcw_p4080ds.cfg | 11 -
> board/freescale/corenet_ds/rcw_p5020ds.cfg | 11 -
> board/freescale/corenet_ds/rcw_p5040ds.cfg | 11 -
> configs/P3041DS_NAND_SECURE_BOOT_defconfig | 59 --
> configs/P3041DS_NAND_defconfig | 64 --
> configs/P3041DS_SDCARD_defconfig | 63 --
> configs/P3041DS_SECURE_BOOT_defconfig | 57 --
> configs/P3041DS_SPIFLASH_defconfig | 64 --
> configs/P3041DS_SRIO_PCIE_BOOT_defconfig | 50 --
> configs/P3041DS_defconfig | 62 --
> configs/P4080DS_SDCARD_defconfig | 62 --
> configs/P4080DS_SECURE_BOOT_defconfig | 56 --
> configs/P4080DS_SPIFLASH_defconfig | 63 --
> configs/P4080DS_SRIO_PCIE_BOOT_defconfig | 48 --
> configs/P4080DS_defconfig | 61 --
> configs/P5020DS_NAND_SECURE_BOOT_defconfig | 60 --
> configs/P5020DS_NAND_defconfig | 57 --
> configs/P5020DS_SDCARD_defconfig | 55 --
> configs/P5020DS_SECURE_BOOT_defconfig | 57 --
> configs/P5020DS_SPIFLASH_defconfig | 56 --
> configs/P5020DS_SRIO_PCIE_BOOT_defconfig | 50 --
> configs/P5020DS_defconfig | 54 --
> configs/P5040DS_NAND_SECURE_BOOT_defconfig | 60 --
> configs/P5040DS_NAND_defconfig | 65 --
> configs/P5040DS_SDCARD_defconfig | 63 --
> configs/P5040DS_SECURE_BOOT_defconfig | 57 --
> configs/P5040DS_SPIFLASH_defconfig | 64 --
> configs/P5040DS_defconfig | 62 --
> include/configs/P3041DS.h | 24 -
> include/configs/P4080DS.h | 23 -
> include/configs/P5020DS.h | 25 -
> include/configs/P5040DS.h | 19 -
> 49 files changed, 4436 deletions(-)
> delete mode 100644 board/freescale/corenet_ds/Kconfig
> delete mode 100644 board/freescale/corenet_ds/MAINTAINERS
> delete mode 100644 board/freescale/corenet_ds/Makefile
> delete mode 100644 board/freescale/corenet_ds/corenet_ds.c
> delete mode 100644 board/freescale/corenet_ds/corenet_ds.h
> delete mode 100644 board/freescale/corenet_ds/ddr.c
> delete mode 100644 board/freescale/corenet_ds/eth_hydra.c
> delete mode 100644 board/freescale/corenet_ds/eth_p4080.c
> delete mode 100644 board/freescale/corenet_ds/eth_superhydra.c
> delete mode 100644 board/freescale/corenet_ds/p3041ds_ddr.c
> delete mode 100644 board/freescale/corenet_ds/p4080ds_ddr.c
> delete mode 100644 board/freescale/corenet_ds/p5020ds_ddr.c
> delete mode 100644 board/freescale/corenet_ds/p5040ds_ddr.c
> delete mode 100644 board/freescale/corenet_ds/pbi.cfg
> delete mode 100644 board/freescale/corenet_ds/rcw_p2041rdb.cfg
> delete mode 100644 board/freescale/corenet_ds/rcw_p3041ds.cfg
> delete mode 100644 board/freescale/corenet_ds/rcw_p4080ds.cfg
> delete mode 100644 board/freescale/corenet_ds/rcw_p5020ds.cfg
> delete mode 100644 board/freescale/corenet_ds/rcw_p5040ds.cfg
> delete mode 100644 configs/P3041DS_NAND_SECURE_BOOT_defconfig
> delete mode 100644 configs/P3041DS_NAND_defconfig
> delete mode 100644 configs/P3041DS_SDCARD_defconfig
> delete mode 100644 configs/P3041DS_SECURE_BOOT_defconfig
> delete mode 100644 configs/P3041DS_SPIFLASH_defconfig
> delete mode 100644 configs/P3041DS_SRIO_PCIE_BOOT_defconfig
> delete mode 100644 configs/P3041DS_defconfig
> delete mode 100644 configs/P4080DS_SDCARD_defconfig
> delete mode 100644 configs/P4080DS_SECURE_BOOT_defconfig
> delete mode 100644 configs/P4080DS_SPIFLASH_defconfig
> delete mode 100644 configs/P4080DS_SRIO_PCIE_BOOT_defconfig
> delete mode 100644 configs/P4080DS_defconfig
> delete mode 100644 configs/P5020DS_NAND_SECURE_BOOT_defconfig
> delete mode 100644 configs/P5020DS_NAND_defconfig
> delete mode 100644 configs/P5020DS_SDCARD_defconfig
> delete mode 100644 configs/P5020DS_SECURE_BOOT_defconfig
> delete mode 100644 configs/P5020DS_SPIFLASH_defconfig
> delete mode 100644 configs/P5020DS_SRIO_PCIE_BOOT_defconfig
> delete mode 100644 configs/P5020DS_defconfig
> delete mode 100644 configs/P5040DS_NAND_SECURE_BOOT_defconfig
> delete mode 100644 configs/P5040DS_NAND_defconfig
> delete mode 100644 configs/P5040DS_SDCARD_defconfig
> delete mode 100644 configs/P5040DS_SECURE_BOOT_defconfig
> delete mode 100644 configs/P5040DS_SPIFLASH_defconfig
> delete mode 100644 configs/P5040DS_defconfig
> delete mode 100644 include/configs/P3041DS.h
> delete mode 100644 include/configs/P4080DS.h
> delete mode 100644 include/configs/P5020DS.h
> delete mode 100644 include/configs/P5040DS.h
>
<snip>
NXP plans to keep maintaining these boards. Please don't merge this patch .
The espi series of patches for DM migration were in review since long, but could not be merged because of dependency.
NXP engineers are working on rebasing the DM espi migration series.
http://patchwork.ozlabs.org/project/uboot/list/?series=127282&state=*
http://patchwork.ozlabs.org/project/uboot/list/?series=138873
Nacked-by: Priyanka Jain <priyanka.jain@nxp.com>
^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH 13/24] arm: Remove configs/T1024QDS_DDR4_SECURE_BOOT_defconfig board
2020-05-27 16:46 ` [PATCH 13/24] arm: Remove configs/T1024QDS_DDR4_SECURE_BOOT_defconfig board Jagan Teki
@ 2020-05-28 7:10 ` Priyanka Jain
0 siblings, 0 replies; 59+ messages in thread
From: Priyanka Jain @ 2020-05-28 7:10 UTC (permalink / raw)
To: u-boot
>-----Original Message-----
>From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Jagan Teki
>Sent: Wednesday, May 27, 2020 10:17 PM
>To: Simon Glass <sjg@chromium.org>; Tom Rini <trini@konsulko.com>
>Cc: u-boot at lists.denx.de; linux-amarula at amarulasolutions.com; Jagan Teki
><jagan@amarulasolutions.com>
>Subject: [PATCH 13/24] arm: Remove
>configs/T1024QDS_DDR4_SECURE_BOOT_defconfig board
>
>This board has not been converted to CONFIG_DM_SPI by the deadline.
>
>Remove it.
>
>Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
>---
> arch/powerpc/cpu/mpc85xx/Kconfig | 1 -
> board/freescale/t102xqds/Kconfig | 14 -
> board/freescale/t102xqds/MAINTAINERS | 12 -
> board/freescale/t102xqds/Makefile | 15 -
> board/freescale/t102xqds/README | 328 ---------
> board/freescale/t102xqds/ddr.c | 195 -----
> board/freescale/t102xqds/eth_t102xqds.c | 445 ------------
> board/freescale/t102xqds/law.c | 31 -
> board/freescale/t102xqds/pci.c | 23 -
> board/freescale/t102xqds/spl.c | 156 ----
> board/freescale/t102xqds/t1024_nand_rcw.cfg | 10 -
> board/freescale/t102xqds/t1024_pbi.cfg | 26 -
> board/freescale/t102xqds/t1024_sd_rcw.cfg | 10 -
> board/freescale/t102xqds/t1024_spi_rcw.cfg | 10 -
> board/freescale/t102xqds/t102xqds.c | 497 -------------
> board/freescale/t102xqds/t102xqds.h | 14 -
> board/freescale/t102xqds/t102xqds_qixis.h | 63 --
> board/freescale/t102xqds/tlb.c | 116 ---
> configs/T1024QDS_DDR4_SECURE_BOOT_defconfig | 69 --
> configs/T1024QDS_DDR4_defconfig | 64 --
> configs/T1024QDS_NAND_defconfig | 83 ---
> configs/T1024QDS_SDCARD_defconfig | 80 ---
> configs/T1024QDS_SECURE_BOOT_defconfig | 70 --
> configs/T1024QDS_SPIFLASH_defconfig | 83 ---
> configs/T1024QDS_defconfig | 67 --
> include/configs/T102xQDS.h | 756 --------------------
> 26 files changed, 3238 deletions(-)
> delete mode 100644 board/freescale/t102xqds/Kconfig
> delete mode 100644 board/freescale/t102xqds/MAINTAINERS
> delete mode 100644 board/freescale/t102xqds/Makefile
> delete mode 100644 board/freescale/t102xqds/README
> delete mode 100644 board/freescale/t102xqds/ddr.c
> delete mode 100644 board/freescale/t102xqds/eth_t102xqds.c
> delete mode 100644 board/freescale/t102xqds/law.c
> delete mode 100644 board/freescale/t102xqds/pci.c
> delete mode 100644 board/freescale/t102xqds/spl.c
> delete mode 100644 board/freescale/t102xqds/t1024_nand_rcw.cfg
> delete mode 100644 board/freescale/t102xqds/t1024_pbi.cfg
> delete mode 100644 board/freescale/t102xqds/t1024_sd_rcw.cfg
> delete mode 100644 board/freescale/t102xqds/t1024_spi_rcw.cfg
> delete mode 100644 board/freescale/t102xqds/t102xqds.c
> delete mode 100644 board/freescale/t102xqds/t102xqds.h
> delete mode 100644 board/freescale/t102xqds/t102xqds_qixis.h
> delete mode 100644 board/freescale/t102xqds/tlb.c
> delete mode 100644 configs/T1024QDS_DDR4_SECURE_BOOT_defconfig
> delete mode 100644 configs/T1024QDS_DDR4_defconfig
> delete mode 100644 configs/T1024QDS_NAND_defconfig
> delete mode 100644 configs/T1024QDS_SDCARD_defconfig
> delete mode 100644 configs/T1024QDS_SECURE_BOOT_defconfig
> delete mode 100644 configs/T1024QDS_SPIFLASH_defconfig
> delete mode 100644 configs/T1024QDS_defconfig
> delete mode 100644 include/configs/T102xQDS.h
>
<snip>
Please replace arm to powerpc in subject. Rest is fine
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH 14/24] arm: Remove configs/T1040D4RDB_NAND_defconfig board
2020-05-27 16:46 ` [PATCH 14/24] arm: Remove configs/T1040D4RDB_NAND_defconfig board Jagan Teki
@ 2020-05-28 7:11 ` Priyanka Jain
2020-05-28 20:40 ` Tom Rini
0 siblings, 1 reply; 59+ messages in thread
From: Priyanka Jain @ 2020-05-28 7:11 UTC (permalink / raw)
To: u-boot
>-----Original Message-----
>From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Jagan Teki
>Sent: Wednesday, May 27, 2020 10:17 PM
>To: Simon Glass <sjg@chromium.org>; Tom Rini <trini@konsulko.com>
>Cc: u-boot at lists.denx.de; linux-amarula at amarulasolutions.com; Jagan Teki
><jagan@amarulasolutions.com>
>Subject: [PATCH 14/24] arm: Remove configs/T1040D4RDB_NAND_defconfig
>board
>
>This board has not been converted to CONFIG_DM_SPI by the deadline.
>
>Remove it.
>
>Patch-cc: Priyanka Jain <priyanka.jain@nxp.com>
>Patch-cc: Priyanka Jain <priyanka.jain@nxp.com>
>Patch-cc: Ruchika Gupta <ruchika.gupta@nxp.com>
>Patch-cc: Sumit Garg <sumit.garg@nxp.com>
>Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
>---
> arch/powerpc/cpu/mpc85xx/Kconfig | 1 -
> board/freescale/t104xrdb/Kconfig | 16 -
> board/freescale/t104xrdb/MAINTAINERS | 38 -
> board/freescale/t104xrdb/Makefile | 16 -
> board/freescale/t104xrdb/README | 386 ---------
> board/freescale/t104xrdb/cpld.c | 115 ---
> board/freescale/t104xrdb/cpld.h | 46 -
> board/freescale/t104xrdb/ddr.c | 145 ----
> board/freescale/t104xrdb/ddr.h | 56 --
> board/freescale/t104xrdb/diu.c | 84 --
> board/freescale/t104xrdb/eth.c | 154 ----
> board/freescale/t104xrdb/law.c | 31 -
> board/freescale/t104xrdb/pci.c | 25 -
> board/freescale/t104xrdb/spl.c | 142 ---
> board/freescale/t104xrdb/t1040_nand_rcw.cfg | 7 -
> board/freescale/t104xrdb/t1040_sd_rcw.cfg | 7 -
> board/freescale/t104xrdb/t1040_spi_rcw.cfg | 7 -
> board/freescale/t104xrdb/t1040d4_nand_rcw.cfg | 7 -
> board/freescale/t104xrdb/t1040d4_sd_rcw.cfg | 7 -
> board/freescale/t104xrdb/t1040d4_spi_rcw.cfg | 7 -
> board/freescale/t104xrdb/t1042_nand_rcw.cfg | 7 -
> .../freescale/t104xrdb/t1042_pi_nand_rcw.cfg | 7 -
> board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg | 7 -
> board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg | 7 -
> board/freescale/t104xrdb/t1042_sd_rcw.cfg | 7 -
> board/freescale/t104xrdb/t1042_spi_rcw.cfg | 7 -
> board/freescale/t104xrdb/t1042d4_nand_rcw.cfg | 7 -
> board/freescale/t104xrdb/t1042d4_sd_rcw.cfg | 7 -
> board/freescale/t104xrdb/t1042d4_spi_rcw.cfg | 7 -
> board/freescale/t104xrdb/t104x_pbi.cfg | 36 -
> board/freescale/t104xrdb/t104x_pbi_sb.cfg | 38 -
> board/freescale/t104xrdb/t104xrdb.c | 161 ----
> board/freescale/t104xrdb/t104xrdb.h | 12 -
> board/freescale/t104xrdb/tlb.c | 131 ---
> configs/T1040D4RDB_NAND_defconfig | 75 --
> configs/T1040D4RDB_SDCARD_defconfig | 72 --
> configs/T1040D4RDB_SECURE_BOOT_defconfig | 61 --
> configs/T1040D4RDB_SPIFLASH_defconfig | 75 --
> configs/T1040D4RDB_defconfig | 59 --
> configs/T1040RDB_NAND_defconfig | 76 --
> configs/T1040RDB_SDCARD_defconfig | 73 --
> configs/T1040RDB_SECURE_BOOT_defconfig | 62 --
> configs/T1040RDB_SPIFLASH_defconfig | 76 --
> configs/T1040RDB_defconfig | 60 --
> configs/T1042D4RDB_NAND_defconfig | 86 --
> configs/T1042D4RDB_SDCARD_defconfig | 83 --
> configs/T1042D4RDB_SECURE_BOOT_defconfig | 64 --
> configs/T1042D4RDB_SPIFLASH_defconfig | 86 --
> configs/T1042D4RDB_defconfig | 71 --
> .../T1042RDB_PI_NAND_SECURE_BOOT_defconfig | 85 --
> configs/T1042RDB_PI_NAND_defconfig | 80 --
> configs/T1042RDB_PI_SDCARD_defconfig | 77 --
> configs/T1042RDB_PI_SPIFLASH_defconfig | 80 --
> configs/T1042RDB_PI_defconfig | 64 --
> configs/T1042RDB_SECURE_BOOT_defconfig | 61 --
> configs/T1042RDB_defconfig | 59 --
> include/configs/T104xRDB.h | 813 ------------------
> 57 files changed, 4136 deletions(-)
> delete mode 100644 board/freescale/t104xrdb/Kconfig
> delete mode 100644 board/freescale/t104xrdb/MAINTAINERS
> delete mode 100644 board/freescale/t104xrdb/Makefile
> delete mode 100644 board/freescale/t104xrdb/README
> delete mode 100644 board/freescale/t104xrdb/cpld.c
> delete mode 100644 board/freescale/t104xrdb/cpld.h
> delete mode 100644 board/freescale/t104xrdb/ddr.c
> delete mode 100644 board/freescale/t104xrdb/ddr.h
> delete mode 100644 board/freescale/t104xrdb/diu.c
> delete mode 100644 board/freescale/t104xrdb/eth.c
> delete mode 100644 board/freescale/t104xrdb/law.c
> delete mode 100644 board/freescale/t104xrdb/pci.c
> delete mode 100644 board/freescale/t104xrdb/spl.c
> delete mode 100644 board/freescale/t104xrdb/t1040_nand_rcw.cfg
> delete mode 100644 board/freescale/t104xrdb/t1040_sd_rcw.cfg
> delete mode 100644 board/freescale/t104xrdb/t1040_spi_rcw.cfg
> delete mode 100644 board/freescale/t104xrdb/t1040d4_nand_rcw.cfg
> delete mode 100644 board/freescale/t104xrdb/t1040d4_sd_rcw.cfg
> delete mode 100644 board/freescale/t104xrdb/t1040d4_spi_rcw.cfg
> delete mode 100644 board/freescale/t104xrdb/t1042_nand_rcw.cfg
> delete mode 100644 board/freescale/t104xrdb/t1042_pi_nand_rcw.cfg
> delete mode 100644 board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg
> delete mode 100644 board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg
> delete mode 100644 board/freescale/t104xrdb/t1042_sd_rcw.cfg
> delete mode 100644 board/freescale/t104xrdb/t1042_spi_rcw.cfg
> delete mode 100644 board/freescale/t104xrdb/t1042d4_nand_rcw.cfg
> delete mode 100644 board/freescale/t104xrdb/t1042d4_sd_rcw.cfg
> delete mode 100644 board/freescale/t104xrdb/t1042d4_spi_rcw.cfg
> delete mode 100644 board/freescale/t104xrdb/t104x_pbi.cfg
> delete mode 100644 board/freescale/t104xrdb/t104x_pbi_sb.cfg
> delete mode 100644 board/freescale/t104xrdb/t104xrdb.c
> delete mode 100644 board/freescale/t104xrdb/t104xrdb.h
> delete mode 100644 board/freescale/t104xrdb/tlb.c
> delete mode 100644 configs/T1040D4RDB_NAND_defconfig
> delete mode 100644 configs/T1040D4RDB_SDCARD_defconfig
> delete mode 100644 configs/T1040D4RDB_SECURE_BOOT_defconfig
> delete mode 100644 configs/T1040D4RDB_SPIFLASH_defconfig
> delete mode 100644 configs/T1040D4RDB_defconfig
> delete mode 100644 configs/T1040RDB_NAND_defconfig
> delete mode 100644 configs/T1040RDB_SDCARD_defconfig
> delete mode 100644 configs/T1040RDB_SECURE_BOOT_defconfig
> delete mode 100644 configs/T1040RDB_SPIFLASH_defconfig
> delete mode 100644 configs/T1040RDB_defconfig
> delete mode 100644 configs/T1042D4RDB_NAND_defconfig
> delete mode 100644 configs/T1042D4RDB_SDCARD_defconfig
> delete mode 100644 configs/T1042D4RDB_SECURE_BOOT_defconfig
> delete mode 100644 configs/T1042D4RDB_SPIFLASH_defconfig
> delete mode 100644 configs/T1042D4RDB_defconfig
> delete mode 100644 configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig
> delete mode 100644 configs/T1042RDB_PI_NAND_defconfig
> delete mode 100644 configs/T1042RDB_PI_SDCARD_defconfig
> delete mode 100644 configs/T1042RDB_PI_SPIFLASH_defconfig
> delete mode 100644 configs/T1042RDB_PI_defconfig
> delete mode 100644 configs/T1042RDB_SECURE_BOOT_defconfig
> delete mode 100644 configs/T1042RDB_defconfig
> delete mode 100644 include/configs/T104xRDB.h
>
<snip>
NXP plans to keep maintaining these boards. Please don't merge this patch .
The espi series of patches for DM migration were in review since long, but could not be merged because of dependency.
NXP engineers are working on rebasing the DM espi migration series.
http://patchwork.ozlabs.org/project/uboot/list/?series=127282&state=*
http://patchwork.ozlabs.org/project/uboot/list/?series=138873
Nacked-by: Priyanka Jain <priyanka.jain@nxp.com>
^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH 20/24] arm: Remove configs/TWR-P1025_defconfig board
2020-05-27 16:46 ` [PATCH 20/24] arm: Remove configs/TWR-P1025_defconfig board Jagan Teki
@ 2020-05-28 7:12 ` Priyanka Jain
0 siblings, 0 replies; 59+ messages in thread
From: Priyanka Jain @ 2020-05-28 7:12 UTC (permalink / raw)
To: u-boot
>-----Original Message-----
>From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Jagan Teki
>Sent: Wednesday, May 27, 2020 10:17 PM
>To: Simon Glass <sjg@chromium.org>; Tom Rini <trini@konsulko.com>
>Cc: u-boot at lists.denx.de; linux-amarula at amarulasolutions.com; Jagan Teki
><jagan@amarulasolutions.com>
>Subject: [PATCH 20/24] arm: Remove configs/TWR-P1025_defconfig board
>
>This board has not been converted to CONFIG_DM_SPI by the deadline.
>
>Remove it.
>
>Patch-cc: Xiaobo Xie <xiaobo.xie@nxp.com>
>Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
>---
> arch/powerpc/cpu/mpc85xx/Kconfig | 1 -
> board/freescale/p1_twr/Kconfig | 12 -
> board/freescale/p1_twr/MAINTAINERS | 6 -
> board/freescale/p1_twr/Makefile | 9 -
> board/freescale/p1_twr/ddr.c | 69 -----
> board/freescale/p1_twr/law.c | 15 -
> board/freescale/p1_twr/p1_twr.c | 292 ------------------
> board/freescale/p1_twr/tlb.c | 75 -----
> configs/TWR-P1025_defconfig | 64 ----
> include/configs/p1_twr.h | 480 -----------------------------
> 10 files changed, 1023 deletions(-)
> delete mode 100644 board/freescale/p1_twr/Kconfig delete mode 100644
>board/freescale/p1_twr/MAINTAINERS
> delete mode 100644 board/freescale/p1_twr/Makefile delete mode 100644
>board/freescale/p1_twr/ddr.c delete mode 100644
>board/freescale/p1_twr/law.c delete mode 100644
>board/freescale/p1_twr/p1_twr.c delete mode 100644
>board/freescale/p1_twr/tlb.c delete mode 100644 configs/TWR-
>P1025_defconfig delete mode 100644 include/configs/p1_twr.h
>
<snip>
Please replace arm to powerpc in subject. Rest is fine
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH 16/24] arm: Remove configs/T2080QDS_NAND_defconfig board
2020-05-27 16:46 ` [PATCH 16/24] arm: Remove configs/T2080QDS_NAND_defconfig board Jagan Teki
@ 2020-05-28 7:14 ` Priyanka Jain
2020-05-28 20:42 ` Tom Rini
0 siblings, 1 reply; 59+ messages in thread
From: Priyanka Jain @ 2020-05-28 7:14 UTC (permalink / raw)
To: u-boot
>-----Original Message-----
>From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Jagan Teki
>Sent: Wednesday, May 27, 2020 10:17 PM
>To: Simon Glass <sjg@chromium.org>; Tom Rini <trini@konsulko.com>
>Cc: u-boot at lists.denx.de; linux-amarula at amarulasolutions.com; Jagan Teki
><jagan@amarulasolutions.com>
>Subject: [PATCH 16/24] arm: Remove configs/T2080QDS_NAND_defconfig
>board
>
>This board has not been converted to CONFIG_DM_SPI by the deadline.
>
>Remove it.
>
>Patch-cc: Shengzhou Liu <Shengzhou.Liu@nxp.com>
>Patch-cc: Ruchika Gupta <ruchika.gupta@nxp.com>
>Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
>---
> arch/powerpc/cpu/mpc85xx/Kconfig | 1 -
> board/freescale/t208xqds/Kconfig | 14 -
> board/freescale/t208xqds/MAINTAINERS | 20 -
> board/freescale/t208xqds/Makefile | 17 -
> board/freescale/t208xqds/README | 293 -------
> board/freescale/t208xqds/ddr.c | 125 ---
> board/freescale/t208xqds/ddr.h | 70 --
> board/freescale/t208xqds/eth_t208xqds.c | 826 --------------------
> board/freescale/t208xqds/law.c | 33 -
> board/freescale/t208xqds/pci.c | 25 -
> board/freescale/t208xqds/spl.c | 142 ----
> board/freescale/t208xqds/t2080_nand_rcw.cfg | 16 -
> board/freescale/t208xqds/t2080_sd_rcw.cfg | 16 -
> board/freescale/t208xqds/t2080_spi_rcw.cfg | 16 -
> board/freescale/t208xqds/t2081_nand_rcw.cfg | 8 -
> board/freescale/t208xqds/t2081_sd_rcw.cfg | 8 -
> board/freescale/t208xqds/t2081_spi_rcw.cfg | 8 -
> board/freescale/t208xqds/t208x_pbi.cfg | 40 -
> board/freescale/t208xqds/t208xqds.c | 489 ------------
> board/freescale/t208xqds/t208xqds.h | 12 -
> board/freescale/t208xqds/t208xqds_qixis.h | 48 --
> board/freescale/t208xqds/tlb.c | 152 ----
> configs/T2080QDS_NAND_defconfig | 83 --
> configs/T2080QDS_SDCARD_defconfig | 80 --
> configs/T2080QDS_SECURE_BOOT_defconfig | 70 --
> configs/T2080QDS_SPIFLASH_defconfig | 83 --
> configs/T2080QDS_SRIO_PCIE_BOOT_defconfig | 60 --
> configs/T2080QDS_defconfig | 68 --
> configs/T2081QDS_NAND_defconfig | 75 --
> configs/T2081QDS_SDCARD_defconfig | 72 --
> configs/T2081QDS_SPIFLASH_defconfig | 75 --
> configs/T2081QDS_SRIO_PCIE_BOOT_defconfig | 51 --
> configs/T2081QDS_defconfig | 59 --
> include/configs/T208xQDS.h | 771 ------------------
> 34 files changed, 3926 deletions(-)
> delete mode 100644 board/freescale/t208xqds/Kconfig
> delete mode 100644 board/freescale/t208xqds/MAINTAINERS
> delete mode 100644 board/freescale/t208xqds/Makefile
> delete mode 100755 board/freescale/t208xqds/README
> delete mode 100644 board/freescale/t208xqds/ddr.c
> delete mode 100644 board/freescale/t208xqds/ddr.h
> delete mode 100644 board/freescale/t208xqds/eth_t208xqds.c
> delete mode 100644 board/freescale/t208xqds/law.c
> delete mode 100644 board/freescale/t208xqds/pci.c
> delete mode 100644 board/freescale/t208xqds/spl.c
> delete mode 100644 board/freescale/t208xqds/t2080_nand_rcw.cfg
> delete mode 100644 board/freescale/t208xqds/t2080_sd_rcw.cfg
> delete mode 100644 board/freescale/t208xqds/t2080_spi_rcw.cfg
> delete mode 100644 board/freescale/t208xqds/t2081_nand_rcw.cfg
> delete mode 100644 board/freescale/t208xqds/t2081_sd_rcw.cfg
> delete mode 100644 board/freescale/t208xqds/t2081_spi_rcw.cfg
> delete mode 100644 board/freescale/t208xqds/t208x_pbi.cfg
> delete mode 100644 board/freescale/t208xqds/t208xqds.c
> delete mode 100644 board/freescale/t208xqds/t208xqds.h
> delete mode 100644 board/freescale/t208xqds/t208xqds_qixis.h
> delete mode 100644 board/freescale/t208xqds/tlb.c
> delete mode 100644 configs/T2080QDS_NAND_defconfig
> delete mode 100644 configs/T2080QDS_SDCARD_defconfig
> delete mode 100644 configs/T2080QDS_SECURE_BOOT_defconfig
> delete mode 100644 configs/T2080QDS_SPIFLASH_defconfig
> delete mode 100644 configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
> delete mode 100644 configs/T2080QDS_defconfig
> delete mode 100644 configs/T2081QDS_NAND_defconfig
> delete mode 100644 configs/T2081QDS_SDCARD_defconfig
> delete mode 100644 configs/T2081QDS_SPIFLASH_defconfig
> delete mode 100644 configs/T2081QDS_SRIO_PCIE_BOOT_defconfig
> delete mode 100644 configs/T2081QDS_defconfig
> delete mode 100644 include/configs/T208xQDS.h
>
<snip>
NXP plans to keep maintaining these boards. Please don't merge this patch .
The espi series of patches for DM migration were in review since long, but could not be merged because of dependency.
NXP engineers are working on rebasing the DM espi migration series.
http://patchwork.ozlabs.org/project/uboot/list/?series=127282&state=*
http://patchwork.ozlabs.org/project/uboot/list/?series=138873
Nacked-by: Priyanka Jain <priyanka.jain@nxp.com>
^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH 18/24] arm: Remove configs/T4160QDS_NAND_defconfig board
2020-05-27 16:46 ` [PATCH 18/24] arm: Remove configs/T4160QDS_NAND_defconfig board Jagan Teki
@ 2020-05-28 7:15 ` Priyanka Jain
0 siblings, 0 replies; 59+ messages in thread
From: Priyanka Jain @ 2020-05-28 7:15 UTC (permalink / raw)
To: u-boot
>-----Original Message-----
>From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Jagan Teki
>Sent: Wednesday, May 27, 2020 10:17 PM
>To: Simon Glass <sjg@chromium.org>; Tom Rini <trini@konsulko.com>
>Cc: u-boot at lists.denx.de; linux-amarula at amarulasolutions.com; Jagan Teki
><jagan@amarulasolutions.com>
>Subject: [PATCH 18/24] arm: Remove configs/T4160QDS_NAND_defconfig
>board
>
>This board has not been converted to CONFIG_DM_SPI by the deadline.
>
>Remove it.
>
>Patch-cc: Ruchika Gupta <ruchika.gupta@nxp.com>
>Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
>---
> arch/powerpc/cpu/mpc85xx/Kconfig | 1 -
> board/freescale/t4qds/Kconfig | 14 -
> board/freescale/t4qds/MAINTAINERS | 18 -
> board/freescale/t4qds/Makefile | 15 -
> board/freescale/t4qds/README | 194 -----
> board/freescale/t4qds/ddr.c | 134 ----
> board/freescale/t4qds/ddr.h | 81 --
> board/freescale/t4qds/eth.c | 869 --------------------
> board/freescale/t4qds/law.c | 33 -
> board/freescale/t4qds/pci.c | 23 -
> board/freescale/t4qds/spl.c | 145 ----
> board/freescale/t4qds/t4240emu.c | 85 --
> board/freescale/t4qds/t4240qds.c | 927 ----------------------
> board/freescale/t4qds/t4240qds_qixis.h | 42 -
> board/freescale/t4qds/t4_nand_rcw.cfg | 7 -
> board/freescale/t4qds/t4_pbi.cfg | 21 -
> board/freescale/t4qds/t4_sd_rcw.cfg | 7 -
> board/freescale/t4qds/t4qds.h | 12 -
> board/freescale/t4qds/tlb.c | 146 ----
> configs/T4160QDS_NAND_defconfig | 69 --
> configs/T4160QDS_SDCARD_defconfig | 66 --
> configs/T4160QDS_SECURE_BOOT_defconfig | 56 --
> configs/T4160QDS_defconfig | 53 --
> configs/T4240QDS_NAND_defconfig | 69 --
> configs/T4240QDS_SDCARD_defconfig | 66 --
> configs/T4240QDS_SECURE_BOOT_defconfig | 56 --
> configs/T4240QDS_SRIO_PCIE_BOOT_defconfig | 49 --
> configs/T4240QDS_defconfig | 53 --
> include/configs/T4240QDS.h | 555 -------------
> 29 files changed, 3866 deletions(-)
> delete mode 100644 board/freescale/t4qds/Kconfig
> delete mode 100644 board/freescale/t4qds/MAINTAINERS
> delete mode 100644 board/freescale/t4qds/Makefile
> delete mode 100644 board/freescale/t4qds/README
> delete mode 100644 board/freescale/t4qds/ddr.c
> delete mode 100644 board/freescale/t4qds/ddr.h
> delete mode 100644 board/freescale/t4qds/eth.c
> delete mode 100644 board/freescale/t4qds/law.c
> delete mode 100644 board/freescale/t4qds/pci.c
> delete mode 100644 board/freescale/t4qds/spl.c
> delete mode 100644 board/freescale/t4qds/t4240emu.c
> delete mode 100644 board/freescale/t4qds/t4240qds.c
> delete mode 100644 board/freescale/t4qds/t4240qds_qixis.h
> delete mode 100644 board/freescale/t4qds/t4_nand_rcw.cfg
> delete mode 100644 board/freescale/t4qds/t4_pbi.cfg
> delete mode 100644 board/freescale/t4qds/t4_sd_rcw.cfg
> delete mode 100644 board/freescale/t4qds/t4qds.h
> delete mode 100644 board/freescale/t4qds/tlb.c
> delete mode 100644 configs/T4160QDS_NAND_defconfig
> delete mode 100644 configs/T4160QDS_SDCARD_defconfig
> delete mode 100644 configs/T4160QDS_SECURE_BOOT_defconfig
> delete mode 100644 configs/T4160QDS_defconfig
> delete mode 100644 configs/T4240QDS_NAND_defconfig
> delete mode 100644 configs/T4240QDS_SDCARD_defconfig
> delete mode 100644 configs/T4240QDS_SECURE_BOOT_defconfig
> delete mode 100644 configs/T4240QDS_SRIO_PCIE_BOOT_defconfig
> delete mode 100644 configs/T4240QDS_defconfig
> delete mode 100644 include/configs/T4240QDS.h
>
<snip>
Please replace arm to powerpc in subject. Rest is fine
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH 00/24] spi: dm-conversion (part2)
2020-05-27 16:46 [PATCH 00/24] spi: dm-conversion (part2) Jagan Teki
` (21 preceding siblings ...)
2020-05-28 0:56 ` Bin Meng
@ 2020-05-28 9:44 ` Priyanka Jain
2020-05-28 9:51 ` Jagan Teki
22 siblings, 1 reply; 59+ messages in thread
From: Priyanka Jain @ 2020-05-28 9:44 UTC (permalink / raw)
To: u-boot
>-----Original Message-----
>From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Jagan Teki
>Sent: Wednesday, May 27, 2020 10:17 PM
>To: Simon Glass <sjg@chromium.org>; Tom Rini <trini@konsulko.com>
>Cc: u-boot at lists.denx.de; linux-amarula at amarulasolutions.com; Jagan Teki
><jagan@amarulasolutions.com>
>Subject: [PATCH 00/24] spi: dm-conversion (part2)
>
>I believe some boards can directly enable DM_SPI if it has
>OF_CONTROL enabled already, so now it's the last call for
>board maintainers to take care of this.
>
>Now all boards which are using fsl_espi are removed due to
>no action on dm conversion from years.
>
>These will merge as soon as possible, based on the response.
>
>Travis-CI:
>https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Ftravis-
>ci.org%2Fgithub%2Fopenedev%2Fu-boot-
>amarula%2Fbuilds%2F691819005&data=02%7C01%7Cpriyanka.jain%40
>nxp.com%7C171852fb35434a5d673408d8025dac41%7C686ea1d3bc2b4c6f
>a92cd99c5c301635%7C0%7C0%7C637261948643488219&sdata=9QAJ
>qHESjU3J%2FEvB38hpxhtjaQwKfeVQppe73jPzXag%3D&reserved=0
>
>Any inputs?
>Jagan.
>
>Jagan Teki (24):
> arm: Remove configs/B4420QDS_NAND_defconfig board
> arm: Remove configs/BSC9131RDB_NAND_SYSCLK100_defconfig board
> arm: Remove configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig
>board
> arm: Remove configs/C29XPCIE_NAND_defconfig board
> arm: Remove configs/Cyrus_P5020_defconfig board
> arm: Remove configs/MPC8536DS_36BIT_defconfig board
> arm: Remove configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig
>board
> arm: Remove configs/P1020MBG-PC_36BIT_SDCARD_defconfig board
> arm: Remove configs/P1022DS_36BIT_NAND_defconfig board
> arm: Remove configs/P2041RDB_NAND_defconfig board
> arm: Remove configs/P3041DS_NAND_SECURE_BOOT_defconfig board
> arm: Remove configs/T1023RDB_NAND_defconfig board
> arm: Remove configs/T1024QDS_DDR4_SECURE_BOOT_defconfig board
> arm: Remove configs/T1040D4RDB_NAND_defconfig board
> arm: Remove configs/T1040QDS_DDR4_defconfig board
> arm: Remove configs/T2080QDS_NAND_defconfig board
> arm: Remove configs/T2080RDB_NAND_defconfig board
> arm: Remove configs/T4160QDS_NAND_defconfig board
> arm: Remove configs/T4160RDB_defconfig board
> arm: Remove configs/TWR-P1025_defconfig board
> arm: Remove configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig
> board
> arm: Remove configs/kmcoge4_defconfig board
> spi: Zap fsl_espi
> mtd: spi: Drop fsl_espi_spl
>
<snip>
Dear Jagan,
NXP do plan to keep maintaining some of the powerpc boards.
We had send espi series of patches for DM migration last year
http://patchwork.ozlabs.org/project/uboot/list/?series=127282&state=*
http://patchwork.ozlabs.org/project/uboot/list/?series=138873
But they could not be merged due to dependency on other patches
https://patchwork.ozlabs.org/project/uboot/cover/20190813134731.25024-1-lukma at denx.de/
Now we have taken agreement from original author of dependent patches (Lukasz Majewski) and will be sending the combined series of espi DM migration next week.
So, please don't remove these boards
Thanks
Priyanka
^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH 00/24] spi: dm-conversion (part2)
2020-05-28 0:56 ` Bin Meng
@ 2020-05-28 9:46 ` Jagan Teki
0 siblings, 0 replies; 59+ messages in thread
From: Jagan Teki @ 2020-05-28 9:46 UTC (permalink / raw)
To: u-boot
Hi Bin,
On Thu, May 28, 2020 at 6:26 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> Hi Jagan,
>
> On Thu, May 28, 2020 at 12:47 AM Jagan Teki <jagan@amarulasolutions.com> wrote:
> >
> > I believe some boards can directly enable DM_SPI if it has
> > OF_CONTROL enabled already, so now it's the last call for
> > board maintainers to take care of this.
> >
> > Now all boards which are using fsl_espi are removed due to
> > no action on dm conversion from years.
> >
> > These will merge as soon as possible, based on the response.
> >
> > Travis-CI:
> > https://travis-ci.org/github/openedev/u-boot-amarula/builds/691819005
> >
> > Any inputs?
> > Jagan.
> >
> > Jagan Teki (24):
> > arm: Remove configs/B4420QDS_NAND_defconfig board
> > arm: Remove configs/BSC9131RDB_NAND_SYSCLK100_defconfig board
> > arm: Remove configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig board
> > arm: Remove configs/C29XPCIE_NAND_defconfig board
> > arm: Remove configs/Cyrus_P5020_defconfig board
> > arm: Remove configs/MPC8536DS_36BIT_defconfig board
> > arm: Remove configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig board
> > arm: Remove configs/P1020MBG-PC_36BIT_SDCARD_defconfig board
> > arm: Remove configs/P1022DS_36BIT_NAND_defconfig board
> > arm: Remove configs/P2041RDB_NAND_defconfig board
> > arm: Remove configs/P3041DS_NAND_SECURE_BOOT_defconfig board
> > arm: Remove configs/T1023RDB_NAND_defconfig board
> > arm: Remove configs/T1024QDS_DDR4_SECURE_BOOT_defconfig board
> > arm: Remove configs/T1040D4RDB_NAND_defconfig board
> > arm: Remove configs/T1040QDS_DDR4_defconfig board
> > arm: Remove configs/T2080QDS_NAND_defconfig board
> > arm: Remove configs/T2080RDB_NAND_defconfig board
> > arm: Remove configs/T4160QDS_NAND_defconfig board
> > arm: Remove configs/T4160RDB_defconfig board
> > arm: Remove configs/TWR-P1025_defconfig board
> > arm: Remove configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig
> > board
> > arm: Remove configs/kmcoge4_defconfig board
> > spi: Zap fsl_espi
> > mtd: spi: Drop fsl_espi_spl
>
> All these boards are powerpc, not arm. So the tag of these patches
> should be fixed to use powerpc.
Thanks for the catch, will update it.
Jagan.
^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH 00/24] spi: dm-conversion (part2)
2020-05-28 9:44 ` Priyanka Jain
@ 2020-05-28 9:51 ` Jagan Teki
0 siblings, 0 replies; 59+ messages in thread
From: Jagan Teki @ 2020-05-28 9:51 UTC (permalink / raw)
To: u-boot
On Thu, May 28, 2020 at 3:14 PM Priyanka Jain <priyanka.jain@nxp.com> wrote:
>
> >-----Original Message-----
> >From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Jagan Teki
> >Sent: Wednesday, May 27, 2020 10:17 PM
> >To: Simon Glass <sjg@chromium.org>; Tom Rini <trini@konsulko.com>
> >Cc: u-boot at lists.denx.de; linux-amarula at amarulasolutions.com; Jagan Teki
> ><jagan@amarulasolutions.com>
> >Subject: [PATCH 00/24] spi: dm-conversion (part2)
> >
> >I believe some boards can directly enable DM_SPI if it has
> >OF_CONTROL enabled already, so now it's the last call for
> >board maintainers to take care of this.
> >
> >Now all boards which are using fsl_espi are removed due to
> >no action on dm conversion from years.
> >
> >These will merge as soon as possible, based on the response.
> >
> >Travis-CI:
> >https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Ftravis-
> >ci.org%2Fgithub%2Fopenedev%2Fu-boot-
> >amarula%2Fbuilds%2F691819005&data=02%7C01%7Cpriyanka.jain%40
> >nxp.com%7C171852fb35434a5d673408d8025dac41%7C686ea1d3bc2b4c6f
> >a92cd99c5c301635%7C0%7C0%7C637261948643488219&sdata=9QAJ
> >qHESjU3J%2FEvB38hpxhtjaQwKfeVQppe73jPzXag%3D&reserved=0
> >
> >Any inputs?
> >Jagan.
> >
> >Jagan Teki (24):
> > arm: Remove configs/B4420QDS_NAND_defconfig board
> > arm: Remove configs/BSC9131RDB_NAND_SYSCLK100_defconfig board
> > arm: Remove configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig
> >board
> > arm: Remove configs/C29XPCIE_NAND_defconfig board
> > arm: Remove configs/Cyrus_P5020_defconfig board
> > arm: Remove configs/MPC8536DS_36BIT_defconfig board
> > arm: Remove configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig
> >board
> > arm: Remove configs/P1020MBG-PC_36BIT_SDCARD_defconfig board
> > arm: Remove configs/P1022DS_36BIT_NAND_defconfig board
> > arm: Remove configs/P2041RDB_NAND_defconfig board
> > arm: Remove configs/P3041DS_NAND_SECURE_BOOT_defconfig board
> > arm: Remove configs/T1023RDB_NAND_defconfig board
> > arm: Remove configs/T1024QDS_DDR4_SECURE_BOOT_defconfig board
> > arm: Remove configs/T1040D4RDB_NAND_defconfig board
> > arm: Remove configs/T1040QDS_DDR4_defconfig board
> > arm: Remove configs/T2080QDS_NAND_defconfig board
> > arm: Remove configs/T2080RDB_NAND_defconfig board
> > arm: Remove configs/T4160QDS_NAND_defconfig board
> > arm: Remove configs/T4160RDB_defconfig board
> > arm: Remove configs/TWR-P1025_defconfig board
> > arm: Remove configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig
> > board
> > arm: Remove configs/kmcoge4_defconfig board
> > spi: Zap fsl_espi
> > mtd: spi: Drop fsl_espi_spl
> >
> <snip>
> Dear Jagan,
>
> NXP do plan to keep maintaining some of the powerpc boards.
> We had send espi series of patches for DM migration last year
> http://patchwork.ozlabs.org/project/uboot/list/?series=127282&state=*
> http://patchwork.ozlabs.org/project/uboot/list/?series=138873
>
> But they could not be merged due to dependency on other patches
> https://patchwork.ozlabs.org/project/uboot/cover/20190813134731.25024-1-lukma at denx.de/
>
> Now we have taken agreement from original author of dependent patches (Lukasz Majewski) and will be sending the combined series of espi DM migration next week.
>
> So, please don't remove these boards
Yes, hopefully this would be last call. Anyway, will pause requested
boards till first week of MW others will go this release itself.
Jagan.
^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH 07/24] arm: Remove configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig board
2020-05-28 7:05 ` Priyanka Jain
@ 2020-05-28 20:02 ` Tom Rini
2020-06-01 5:23 ` Priyanka Jain
0 siblings, 1 reply; 59+ messages in thread
From: Tom Rini @ 2020-05-28 20:02 UTC (permalink / raw)
To: u-boot
On Thu, May 28, 2020 at 07:05:38AM +0000, Priyanka Jain wrote:
> >-----Original Message-----
> >From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Jagan Teki
> >Sent: Wednesday, May 27, 2020 10:17 PM
> >To: Simon Glass <sjg@chromium.org>; Tom Rini <trini@konsulko.com>
> >Cc: u-boot at lists.denx.de; linux-amarula at amarulasolutions.com; Jagan Teki
> ><jagan@amarulasolutions.com>
> >Subject: [PATCH 07/24] arm: Remove configs/P1010RDB-
> >PA_36BIT_NAND_SECBOOT_defconfig board
> >
> >This board has not been converted to CONFIG_DM_SPI by the deadline.
> >
> >Remove it.
> >
> >Patch-cc: Qiang Zhao <qiang.zhao@nxp.com>
> >Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> >---
> > arch/powerpc/cpu/mpc85xx/Kconfig | 1 -
> > board/freescale/p1010rdb/Kconfig | 14 -
> > board/freescale/p1010rdb/MAINTAINERS | 33 -
> > board/freescale/p1010rdb/Makefile | 24 -
> > board/freescale/p1010rdb/README.P1010RDB-PA | 208 -----
> > board/freescale/p1010rdb/README.P1010RDB-PB | 188 -----
> > board/freescale/p1010rdb/ddr.c | 235 ------
> > board/freescale/p1010rdb/law.c | 16 -
> > board/freescale/p1010rdb/p1010rdb.c | 731 -----------------
> > board/freescale/p1010rdb/spl.c | 114 ---
> > board/freescale/p1010rdb/spl_minimal.c | 65 --
> > board/freescale/p1010rdb/tlb.c | 90 --
> > .../P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig | 63 --
> > configs/P1010RDB-PA_36BIT_NAND_defconfig | 85 --
> > .../P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig | 62 --
> > configs/P1010RDB-PA_36BIT_NOR_defconfig | 67 --
> > configs/P1010RDB-PA_36BIT_SDCARD_defconfig | 79 --
> > ...010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig | 64 --
> > configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig | 81 --
> > configs/P1010RDB-PA_NAND_SECBOOT_defconfig | 62 --
> > configs/P1010RDB-PA_NAND_defconfig | 84 --
> > configs/P1010RDB-PA_NOR_SECBOOT_defconfig | 60 --
> > configs/P1010RDB-PA_NOR_defconfig | 66 --
> > configs/P1010RDB-PA_SDCARD_defconfig | 78 --
> > .../P1010RDB-PA_SPIFLASH_SECBOOT_defconfig | 63 --
> > configs/P1010RDB-PA_SPIFLASH_defconfig | 80 --
> > .../P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig | 63 --
> > configs/P1010RDB-PB_36BIT_NAND_defconfig | 85 --
> > .../P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig | 62 --
> > configs/P1010RDB-PB_36BIT_NOR_defconfig | 67 --
> > configs/P1010RDB-PB_36BIT_SDCARD_defconfig | 79 --
> > ...010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig | 64 --
> > configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig | 81 --
> > configs/P1010RDB-PB_NAND_SECBOOT_defconfig | 62 --
> > configs/P1010RDB-PB_NAND_defconfig | 84 --
> > configs/P1010RDB-PB_NOR_SECBOOT_defconfig | 61 --
> > configs/P1010RDB-PB_NOR_defconfig | 66 --
> > configs/P1010RDB-PB_SDCARD_defconfig | 78 --
> > .../P1010RDB-PB_SPIFLASH_SECBOOT_defconfig | 63 --
> > configs/P1010RDB-PB_SPIFLASH_defconfig | 80 --
> > include/configs/P1010RDB.h | 766 ------------------
> > 41 files changed, 4474 deletions(-)
> > delete mode 100644 board/freescale/p1010rdb/Kconfig
> > delete mode 100644 board/freescale/p1010rdb/MAINTAINERS
> > delete mode 100644 board/freescale/p1010rdb/Makefile
> > delete mode 100644 board/freescale/p1010rdb/README.P1010RDB-PA
> > delete mode 100644 board/freescale/p1010rdb/README.P1010RDB-PB
> > delete mode 100644 board/freescale/p1010rdb/ddr.c
> > delete mode 100644 board/freescale/p1010rdb/law.c
> > delete mode 100644 board/freescale/p1010rdb/p1010rdb.c
> > delete mode 100644 board/freescale/p1010rdb/spl.c
> > delete mode 100644 board/freescale/p1010rdb/spl_minimal.c
> > delete mode 100644 board/freescale/p1010rdb/tlb.c
> > delete mode 100644 configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig
> > delete mode 100644 configs/P1010RDB-PA_36BIT_NAND_defconfig
> > delete mode 100644 configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig
> > delete mode 100644 configs/P1010RDB-PA_36BIT_NOR_defconfig
> > delete mode 100644 configs/P1010RDB-PA_36BIT_SDCARD_defconfig
> > delete mode 100644 configs/P1010RDB-
> >PA_36BIT_SPIFLASH_SECBOOT_defconfig
> > delete mode 100644 configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
> > delete mode 100644 configs/P1010RDB-PA_NAND_SECBOOT_defconfig
> > delete mode 100644 configs/P1010RDB-PA_NAND_defconfig
> > delete mode 100644 configs/P1010RDB-PA_NOR_SECBOOT_defconfig
> > delete mode 100644 configs/P1010RDB-PA_NOR_defconfig
> > delete mode 100644 configs/P1010RDB-PA_SDCARD_defconfig
> > delete mode 100644 configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig
> > delete mode 100644 configs/P1010RDB-PA_SPIFLASH_defconfig
> > delete mode 100644 configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig
> > delete mode 100644 configs/P1010RDB-PB_36BIT_NAND_defconfig
> > delete mode 100644 configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig
> > delete mode 100644 configs/P1010RDB-PB_36BIT_NOR_defconfig
> > delete mode 100644 configs/P1010RDB-PB_36BIT_SDCARD_defconfig
> > delete mode 100644 configs/P1010RDB-
> >PB_36BIT_SPIFLASH_SECBOOT_defconfig
> > delete mode 100644 configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
> > delete mode 100644 configs/P1010RDB-PB_NAND_SECBOOT_defconfig
> > delete mode 100644 configs/P1010RDB-PB_NAND_defconfig
> > delete mode 100644 configs/P1010RDB-PB_NOR_SECBOOT_defconfig
> > delete mode 100644 configs/P1010RDB-PB_NOR_defconfig
> > delete mode 100644 configs/P1010RDB-PB_SDCARD_defconfig
> > delete mode 100644 configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig
> > delete mode 100644 configs/P1010RDB-PB_SPIFLASH_defconfig
> > delete mode 100644 include/configs/P1010RDB.h
> >
> <snip>
> NXP plans to keep maintaining P1010RDB board. Please don't merge this patch .
>
> The espi series of patches for DM migration were in review since long, but could not be merged because of dependency.
> NXP engineers are working on rebasing the DM espi migration series.
>
> http://patchwork.ozlabs.org/project/uboot/list/?series=127282&state=*
> http://patchwork.ozlabs.org/project/uboot/list/?series=138873
>
> Nacked-by: Priyanka Jain <priyanka.jain@nxp.com>
So, _this_ platform also runs in to:
+(P1010RDB-PB_SDCARD) ===================== WARNING ======================
+(P1010RDB-PB_SDCARD) This board does not use CONFIG_DM_MMC. Please update
+(P1010RDB-PB_SDCARD) the board to use CONFIG_DM_MMC before the v2019.04 release.
+(P1010RDB-PB_SDCARD) Failure to update by the deadline may result in board removal.
+(P1010RDB-PB_SDCARD) See doc/driver-model/migration.rst for more info.
+(P1010RDB-PB_SDCARD) ====================================================
So how far along is NXP on doing the needed conversions there? Thanks!
--
Tom
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^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH 08/24] arm: Remove configs/P1020MBG-PC_36BIT_SDCARD_defconfig board
2020-05-28 7:07 ` Priyanka Jain
@ 2020-05-28 20:14 ` Tom Rini
2020-05-28 20:32 ` Simon Glass
0 siblings, 1 reply; 59+ messages in thread
From: Tom Rini @ 2020-05-28 20:14 UTC (permalink / raw)
To: u-boot
On Thu, May 28, 2020 at 07:07:14AM +0000, Priyanka Jain wrote:
> >-----Original Message-----
> >From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Jagan Teki
> >Sent: Wednesday, May 27, 2020 10:17 PM
> >To: Simon Glass <sjg@chromium.org>; Tom Rini <trini@konsulko.com>
> >Cc: u-boot at lists.denx.de; linux-amarula at amarulasolutions.com; Jagan Teki
> ><jagan@amarulasolutions.com>
> >Subject: [PATCH 08/24] arm: Remove configs/P1020MBG-
> >PC_36BIT_SDCARD_defconfig board
> >
> >This board has not been converted to CONFIG_DM_SPI by the deadline.
> >
> >Remove it.
> >
> >Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> >---
> > arch/powerpc/cpu/mpc85xx/Kconfig | 1 -
> > board/freescale/p1_p2_rdb_pc/Kconfig | 19 -
> > board/freescale/p1_p2_rdb_pc/MAINTAINERS | 51 --
> > board/freescale/p1_p2_rdb_pc/Makefile | 24 -
> > board/freescale/p1_p2_rdb_pc/README | 66 --
> > board/freescale/p1_p2_rdb_pc/ddr.c | 292 ------
> > board/freescale/p1_p2_rdb_pc/law.c | 22 -
> > board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 536 -----------
> > board/freescale/p1_p2_rdb_pc/spl.c | 123 ---
> > board/freescale/p1_p2_rdb_pc/spl_minimal.c | 63 --
> > board/freescale/p1_p2_rdb_pc/tlb.c | 110 ---
> > configs/P1020MBG-PC_36BIT_SDCARD_defconfig | 67 --
> > configs/P1020MBG-PC_36BIT_defconfig | 55 --
> > configs/P1020MBG-PC_SDCARD_defconfig | 66 --
> > configs/P1020MBG-PC_defconfig | 54 --
> > configs/P1020RDB-PC_36BIT_NAND_defconfig | 85 --
> > configs/P1020RDB-PC_36BIT_SDCARD_defconfig | 80 --
> > configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 82 --
> > configs/P1020RDB-PC_36BIT_defconfig | 69 --
> > configs/P1020RDB-PC_NAND_defconfig | 84 --
> > configs/P1020RDB-PC_SDCARD_defconfig | 79 --
> > configs/P1020RDB-PC_SPIFLASH_defconfig | 81 --
> > configs/P1020RDB-PC_defconfig | 68 --
> > configs/P1020RDB-PD_NAND_defconfig | 88 --
> > configs/P1020RDB-PD_SDCARD_defconfig | 83 --
> > configs/P1020RDB-PD_SPIFLASH_defconfig | 85 --
> > configs/P1020RDB-PD_defconfig | 72 --
> > configs/P1020UTM-PC_36BIT_SDCARD_defconfig | 67 --
> > configs/P1020UTM-PC_36BIT_defconfig | 55 --
> > configs/P1020UTM-PC_SDCARD_defconfig | 66 --
> > configs/P1020UTM-PC_defconfig | 54 --
> > configs/P1021RDB-PC_36BIT_NAND_defconfig | 84 --
> > configs/P1021RDB-PC_36BIT_SDCARD_defconfig | 79 --
> > configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig | 81 --
> > configs/P1021RDB-PC_36BIT_defconfig | 67 --
> > configs/P1021RDB-PC_NAND_defconfig | 83 --
> > configs/P1021RDB-PC_SDCARD_defconfig | 78 --
> > configs/P1021RDB-PC_SPIFLASH_defconfig | 80 --
> > configs/P1021RDB-PC_defconfig | 66 --
> > configs/P1024RDB_36BIT_defconfig | 61 --
> > configs/P1024RDB_NAND_defconfig | 77 --
> > configs/P1024RDB_SDCARD_defconfig | 71 --
> > configs/P1024RDB_SPIFLASH_defconfig | 73 --
> > configs/P1024RDB_defconfig | 60 --
> > configs/P1025RDB_36BIT_defconfig | 63 --
> > configs/P1025RDB_NAND_defconfig | 80 --
> > configs/P1025RDB_SDCARD_defconfig | 73 --
> > configs/P1025RDB_SPIFLASH_defconfig | 76 --
> > configs/P1025RDB_defconfig | 62 --
> > configs/P2020RDB-PC_36BIT_NAND_defconfig | 90 --
> > configs/P2020RDB-PC_36BIT_SDCARD_defconfig | 85 --
> > configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 87 --
> > configs/P2020RDB-PC_36BIT_defconfig | 74 --
> > configs/P2020RDB-PC_NAND_defconfig | 89 --
> > configs/P2020RDB-PC_SDCARD_defconfig | 84 --
> > configs/P2020RDB-PC_SPIFLASH_defconfig | 86 --
> > configs/P2020RDB-PC_defconfig | 73 --
> > include/configs/p1_p2_rdb_pc.h | 881 -------------------
> > 58 files changed, 5610 deletions(-)
> > delete mode 100644 board/freescale/p1_p2_rdb_pc/Kconfig
> > delete mode 100644 board/freescale/p1_p2_rdb_pc/MAINTAINERS
> > delete mode 100644 board/freescale/p1_p2_rdb_pc/Makefile
> > delete mode 100644 board/freescale/p1_p2_rdb_pc/README
> > delete mode 100644 board/freescale/p1_p2_rdb_pc/ddr.c
> > delete mode 100644 board/freescale/p1_p2_rdb_pc/law.c
> > delete mode 100644 board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
> > delete mode 100644 board/freescale/p1_p2_rdb_pc/spl.c
> > delete mode 100644 board/freescale/p1_p2_rdb_pc/spl_minimal.c
> > delete mode 100644 board/freescale/p1_p2_rdb_pc/tlb.c
> > delete mode 100644 configs/P1020MBG-PC_36BIT_SDCARD_defconfig
> > delete mode 100644 configs/P1020MBG-PC_36BIT_defconfig
> > delete mode 100644 configs/P1020MBG-PC_SDCARD_defconfig
> > delete mode 100644 configs/P1020MBG-PC_defconfig
> > delete mode 100644 configs/P1020RDB-PC_36BIT_NAND_defconfig
> > delete mode 100644 configs/P1020RDB-PC_36BIT_SDCARD_defconfig
> > delete mode 100644 configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
> > delete mode 100644 configs/P1020RDB-PC_36BIT_defconfig
> > delete mode 100644 configs/P1020RDB-PC_NAND_defconfig
> > delete mode 100644 configs/P1020RDB-PC_SDCARD_defconfig
> > delete mode 100644 configs/P1020RDB-PC_SPIFLASH_defconfig
> > delete mode 100644 configs/P1020RDB-PC_defconfig
> > delete mode 100644 configs/P1020RDB-PD_NAND_defconfig
> > delete mode 100644 configs/P1020RDB-PD_SDCARD_defconfig
> > delete mode 100644 configs/P1020RDB-PD_SPIFLASH_defconfig
> > delete mode 100644 configs/P1020RDB-PD_defconfig
> > delete mode 100644 configs/P1020UTM-PC_36BIT_SDCARD_defconfig
> > delete mode 100644 configs/P1020UTM-PC_36BIT_defconfig
> > delete mode 100644 configs/P1020UTM-PC_SDCARD_defconfig
> > delete mode 100644 configs/P1020UTM-PC_defconfig
> > delete mode 100644 configs/P1021RDB-PC_36BIT_NAND_defconfig
> > delete mode 100644 configs/P1021RDB-PC_36BIT_SDCARD_defconfig
> > delete mode 100644 configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig
> > delete mode 100644 configs/P1021RDB-PC_36BIT_defconfig
> > delete mode 100644 configs/P1021RDB-PC_NAND_defconfig
> > delete mode 100644 configs/P1021RDB-PC_SDCARD_defconfig
> > delete mode 100644 configs/P1021RDB-PC_SPIFLASH_defconfig
> > delete mode 100644 configs/P1021RDB-PC_defconfig
> > delete mode 100644 configs/P1024RDB_36BIT_defconfig
> > delete mode 100644 configs/P1024RDB_NAND_defconfig
> > delete mode 100644 configs/P1024RDB_SDCARD_defconfig
> > delete mode 100644 configs/P1024RDB_SPIFLASH_defconfig
> > delete mode 100644 configs/P1024RDB_defconfig
> > delete mode 100644 configs/P1025RDB_36BIT_defconfig
> > delete mode 100644 configs/P1025RDB_NAND_defconfig
> > delete mode 100644 configs/P1025RDB_SDCARD_defconfig
> > delete mode 100644 configs/P1025RDB_SPIFLASH_defconfig
> > delete mode 100644 configs/P1025RDB_defconfig
> > delete mode 100644 configs/P2020RDB-PC_36BIT_NAND_defconfig
> > delete mode 100644 configs/P2020RDB-PC_36BIT_SDCARD_defconfig
> > delete mode 100644 configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
> > delete mode 100644 configs/P2020RDB-PC_36BIT_defconfig
> > delete mode 100644 configs/P2020RDB-PC_NAND_defconfig
> > delete mode 100644 configs/P2020RDB-PC_SDCARD_defconfig
> > delete mode 100644 configs/P2020RDB-PC_SPIFLASH_defconfig
> > delete mode 100644 configs/P2020RDB-PC_defconfig
> > delete mode 100644 include/configs/p1_p2_rdb_pc.h
> >
> <snip>
> NXP plans to keep maintaining these boards. Please don't merge this patch .
>
> The espi series of patches for DM migration were in review since long, but could not be merged because of dependency.
> NXP engineers are working on rebasing the DM espi migration series.
>
> http://patchwork.ozlabs.org/project/uboot/list/?series=127282&state=*
> http://patchwork.ozlabs.org/project/uboot/list/?series=138873
Of this series, P1020MBG-PC_SDCARD, P1020UTM-PC_SDCARD,
P1021RDB-PC_36BIT_SDCARD, P1021RDB-PC_SDCARD, P1024RDB_SDCARD,
P1025RDB_SDCARD
and also sometimes:
+(P1021RDB-PC_36BIT_SDCARD) This board does not use CONFIG_DM_USB. Please update
+(P1021RDB-PC_36BIT_SDCARD) the board to use CONFIG_DM_USB before the v2019.07 release.
+(P1021RDB-PC_36BIT_SDCARD) This board does use CONFIG_LIBATA but has CONFIG_AHCI not
+(P1021RDB-PC_36BIT_SDCARD) enabled. Please update the storage controller driver to use
+(P1021RDB-PC_36BIT_SDCARD) CONFIG_AHCI before the v2019.07 release.
or:
+(P1021RDB-PC_SDCARD) This board does not use CONFIG_DM_PCI Please update
+(P1021RDB-PC_SDCARD) the board to use CONFIG_DM_PCI before the v2019.07 release.
And of course those non-MMC issues show up on other configs of the
family. How far along are the plans to address those? Thanks!
--
Tom
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^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH 12/24] arm: Remove configs/T1023RDB_NAND_defconfig board
2020-05-28 7:08 ` Priyanka Jain
@ 2020-05-28 20:18 ` Tom Rini
0 siblings, 0 replies; 59+ messages in thread
From: Tom Rini @ 2020-05-28 20:18 UTC (permalink / raw)
To: u-boot
On Thu, May 28, 2020 at 07:08:14AM +0000, Priyanka Jain wrote:
> >-----Original Message-----
> >From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Jagan Teki
> >Sent: Wednesday, May 27, 2020 10:17 PM
> >To: Simon Glass <sjg@chromium.org>; Tom Rini <trini@konsulko.com>
> >Cc: u-boot at lists.denx.de; linux-amarula at amarulasolutions.com; Jagan Teki
> ><jagan@amarulasolutions.com>
> >Subject: [PATCH 12/24] arm: Remove configs/T1023RDB_NAND_defconfig
> >board
> >
> >This board has not been converted to CONFIG_DM_SPI by the deadline.
> >
> >Remove it.
> >
> >Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> >---
> > arch/powerpc/cpu/mpc85xx/Kconfig | 1 -
> > board/freescale/t102xrdb/Kconfig | 14 -
> > board/freescale/t102xrdb/MAINTAINERS | 15 -
> > board/freescale/t102xrdb/Makefile | 17 -
> > board/freescale/t102xrdb/README | 340 ---------
> > board/freescale/t102xrdb/cpld.c | 102 ---
> > board/freescale/t102xrdb/cpld.h | 48 --
> > board/freescale/t102xrdb/ddr.c | 257 -------
> > board/freescale/t102xrdb/eth_t102xrdb.c | 146 ----
> > board/freescale/t102xrdb/law.c | 31 -
> > board/freescale/t102xrdb/pci.c | 25 -
> > board/freescale/t102xrdb/spl.c | 143 ----
> > board/freescale/t102xrdb/t1023_nand_rcw.cfg | 8 -
> > board/freescale/t102xrdb/t1023_sd_rcw.cfg | 8 -
> > board/freescale/t102xrdb/t1023_spi_rcw.cfg | 8 -
> > board/freescale/t102xrdb/t1024_nand_rcw.cfg | 8 -
> > board/freescale/t102xrdb/t1024_pbi.cfg | 26 -
> > board/freescale/t102xrdb/t1024_sd_rcw.cfg | 8 -
> > board/freescale/t102xrdb/t1024_spi_rcw.cfg | 8 -
> > board/freescale/t102xrdb/t102xrdb.c | 394 -----------
> > board/freescale/t102xrdb/t102xrdb.h | 15 -
> > board/freescale/t102xrdb/tlb.c | 116 ----
> > configs/T1023RDB_NAND_defconfig | 77 ---
> > configs/T1023RDB_SDCARD_defconfig | 74 --
> > configs/T1023RDB_SECURE_BOOT_defconfig | 64 --
> > configs/T1023RDB_SPIFLASH_defconfig | 77 ---
> > configs/T1023RDB_defconfig | 61 --
> > configs/T1024RDB_NAND_defconfig | 86 ---
> > configs/T1024RDB_SDCARD_defconfig | 83 ---
> > configs/T1024RDB_SECURE_BOOT_defconfig | 66 --
> > configs/T1024RDB_SPIFLASH_defconfig | 86 ---
> > configs/T1024RDB_defconfig | 71 --
> > include/configs/T102xRDB.h | 721 --------------------
> > 33 files changed, 3204 deletions(-)
> > delete mode 100644 board/freescale/t102xrdb/Kconfig
> > delete mode 100644 board/freescale/t102xrdb/MAINTAINERS
> > delete mode 100644 board/freescale/t102xrdb/Makefile
> > delete mode 100644 board/freescale/t102xrdb/README
> > delete mode 100644 board/freescale/t102xrdb/cpld.c
> > delete mode 100644 board/freescale/t102xrdb/cpld.h
> > delete mode 100644 board/freescale/t102xrdb/ddr.c
> > delete mode 100644 board/freescale/t102xrdb/eth_t102xrdb.c
> > delete mode 100644 board/freescale/t102xrdb/law.c
> > delete mode 100644 board/freescale/t102xrdb/pci.c
> > delete mode 100644 board/freescale/t102xrdb/spl.c
> > delete mode 100644 board/freescale/t102xrdb/t1023_nand_rcw.cfg
> > delete mode 100644 board/freescale/t102xrdb/t1023_sd_rcw.cfg
> > delete mode 100644 board/freescale/t102xrdb/t1023_spi_rcw.cfg
> > delete mode 100644 board/freescale/t102xrdb/t1024_nand_rcw.cfg
> > delete mode 100644 board/freescale/t102xrdb/t1024_pbi.cfg
> > delete mode 100644 board/freescale/t102xrdb/t1024_sd_rcw.cfg
> > delete mode 100644 board/freescale/t102xrdb/t1024_spi_rcw.cfg
> > delete mode 100644 board/freescale/t102xrdb/t102xrdb.c
> > delete mode 100644 board/freescale/t102xrdb/t102xrdb.h
> > delete mode 100644 board/freescale/t102xrdb/tlb.c
> > delete mode 100644 configs/T1023RDB_NAND_defconfig
> > delete mode 100644 configs/T1023RDB_SDCARD_defconfig
> > delete mode 100644 configs/T1023RDB_SECURE_BOOT_defconfig
> > delete mode 100644 configs/T1023RDB_SPIFLASH_defconfig
> > delete mode 100644 configs/T1023RDB_defconfig
> > delete mode 100644 configs/T1024RDB_NAND_defconfig
> > delete mode 100644 configs/T1024RDB_SDCARD_defconfig
> > delete mode 100644 configs/T1024RDB_SECURE_BOOT_defconfig
> > delete mode 100644 configs/T1024RDB_SPIFLASH_defconfig
> > delete mode 100644 configs/T1024RDB_defconfig
> > delete mode 100644 include/configs/T102xRDB.h
> >
> <snip>
> NXP plans to keep maintaining these boards. Please don't merge this patch .
>
> The espi series of patches for DM migration were in review since long, but could not be merged because of dependency.
> NXP engineers are working on rebasing the DM espi migration series.
>
> http://patchwork.ozlabs.org/project/uboot/list/?series=127282&state=*
> http://patchwork.ozlabs.org/project/uboot/list/?series=138873
Here we also see the MMC/USB/PCI problems on T1023RDB_SDCARD.
--
Tom
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^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH 08/24] arm: Remove configs/P1020MBG-PC_36BIT_SDCARD_defconfig board
2020-05-28 20:14 ` Tom Rini
@ 2020-05-28 20:32 ` Simon Glass
2020-05-28 20:44 ` Tom Rini
0 siblings, 1 reply; 59+ messages in thread
From: Simon Glass @ 2020-05-28 20:32 UTC (permalink / raw)
To: u-boot
Hi,
On Thu, 28 May 2020 at 14:15, Tom Rini <trini@konsulko.com> wrote:
>
> On Thu, May 28, 2020 at 07:07:14AM +0000, Priyanka Jain wrote:
> > >-----Original Message-----
> > >From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Jagan Teki
> > >Sent: Wednesday, May 27, 2020 10:17 PM
> > >To: Simon Glass <sjg@chromium.org>; Tom Rini <trini@konsulko.com>
> > >Cc: u-boot at lists.denx.de; linux-amarula at amarulasolutions.com; Jagan Teki
> > ><jagan@amarulasolutions.com>
> > >Subject: [PATCH 08/24] arm: Remove configs/P1020MBG-
> > >PC_36BIT_SDCARD_defconfig board
> > >
> > >This board has not been converted to CONFIG_DM_SPI by the deadline.
> > >
> > >Remove it.
> > >
> > >Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> > >---
> > > arch/powerpc/cpu/mpc85xx/Kconfig | 1 -
> > > board/freescale/p1_p2_rdb_pc/Kconfig | 19 -
> > > board/freescale/p1_p2_rdb_pc/MAINTAINERS | 51 --
> > > board/freescale/p1_p2_rdb_pc/Makefile | 24 -
> > > board/freescale/p1_p2_rdb_pc/README | 66 --
> > > board/freescale/p1_p2_rdb_pc/ddr.c | 292 ------
> > > board/freescale/p1_p2_rdb_pc/law.c | 22 -
> > > board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 536 -----------
> > > board/freescale/p1_p2_rdb_pc/spl.c | 123 ---
> > > board/freescale/p1_p2_rdb_pc/spl_minimal.c | 63 --
> > > board/freescale/p1_p2_rdb_pc/tlb.c | 110 ---
> > > configs/P1020MBG-PC_36BIT_SDCARD_defconfig | 67 --
> > > configs/P1020MBG-PC_36BIT_defconfig | 55 --
> > > configs/P1020MBG-PC_SDCARD_defconfig | 66 --
> > > configs/P1020MBG-PC_defconfig | 54 --
> > > configs/P1020RDB-PC_36BIT_NAND_defconfig | 85 --
> > > configs/P1020RDB-PC_36BIT_SDCARD_defconfig | 80 --
> > > configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 82 --
> > > configs/P1020RDB-PC_36BIT_defconfig | 69 --
> > > configs/P1020RDB-PC_NAND_defconfig | 84 --
> > > configs/P1020RDB-PC_SDCARD_defconfig | 79 --
> > > configs/P1020RDB-PC_SPIFLASH_defconfig | 81 --
> > > configs/P1020RDB-PC_defconfig | 68 --
> > > configs/P1020RDB-PD_NAND_defconfig | 88 --
> > > configs/P1020RDB-PD_SDCARD_defconfig | 83 --
> > > configs/P1020RDB-PD_SPIFLASH_defconfig | 85 --
> > > configs/P1020RDB-PD_defconfig | 72 --
> > > configs/P1020UTM-PC_36BIT_SDCARD_defconfig | 67 --
> > > configs/P1020UTM-PC_36BIT_defconfig | 55 --
> > > configs/P1020UTM-PC_SDCARD_defconfig | 66 --
> > > configs/P1020UTM-PC_defconfig | 54 --
> > > configs/P1021RDB-PC_36BIT_NAND_defconfig | 84 --
> > > configs/P1021RDB-PC_36BIT_SDCARD_defconfig | 79 --
> > > configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig | 81 --
> > > configs/P1021RDB-PC_36BIT_defconfig | 67 --
> > > configs/P1021RDB-PC_NAND_defconfig | 83 --
> > > configs/P1021RDB-PC_SDCARD_defconfig | 78 --
> > > configs/P1021RDB-PC_SPIFLASH_defconfig | 80 --
> > > configs/P1021RDB-PC_defconfig | 66 --
> > > configs/P1024RDB_36BIT_defconfig | 61 --
> > > configs/P1024RDB_NAND_defconfig | 77 --
> > > configs/P1024RDB_SDCARD_defconfig | 71 --
> > > configs/P1024RDB_SPIFLASH_defconfig | 73 --
> > > configs/P1024RDB_defconfig | 60 --
> > > configs/P1025RDB_36BIT_defconfig | 63 --
> > > configs/P1025RDB_NAND_defconfig | 80 --
> > > configs/P1025RDB_SDCARD_defconfig | 73 --
> > > configs/P1025RDB_SPIFLASH_defconfig | 76 --
> > > configs/P1025RDB_defconfig | 62 --
> > > configs/P2020RDB-PC_36BIT_NAND_defconfig | 90 --
> > > configs/P2020RDB-PC_36BIT_SDCARD_defconfig | 85 --
> > > configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 87 --
> > > configs/P2020RDB-PC_36BIT_defconfig | 74 --
> > > configs/P2020RDB-PC_NAND_defconfig | 89 --
> > > configs/P2020RDB-PC_SDCARD_defconfig | 84 --
> > > configs/P2020RDB-PC_SPIFLASH_defconfig | 86 --
> > > configs/P2020RDB-PC_defconfig | 73 --
> > > include/configs/p1_p2_rdb_pc.h | 881 -------------------
> > > 58 files changed, 5610 deletions(-)
> > > delete mode 100644 board/freescale/p1_p2_rdb_pc/Kconfig
> > > delete mode 100644 board/freescale/p1_p2_rdb_pc/MAINTAINERS
> > > delete mode 100644 board/freescale/p1_p2_rdb_pc/Makefile
> > > delete mode 100644 board/freescale/p1_p2_rdb_pc/README
> > > delete mode 100644 board/freescale/p1_p2_rdb_pc/ddr.c
> > > delete mode 100644 board/freescale/p1_p2_rdb_pc/law.c
> > > delete mode 100644 board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
> > > delete mode 100644 board/freescale/p1_p2_rdb_pc/spl.c
> > > delete mode 100644 board/freescale/p1_p2_rdb_pc/spl_minimal.c
> > > delete mode 100644 board/freescale/p1_p2_rdb_pc/tlb.c
> > > delete mode 100644 configs/P1020MBG-PC_36BIT_SDCARD_defconfig
> > > delete mode 100644 configs/P1020MBG-PC_36BIT_defconfig
> > > delete mode 100644 configs/P1020MBG-PC_SDCARD_defconfig
> > > delete mode 100644 configs/P1020MBG-PC_defconfig
> > > delete mode 100644 configs/P1020RDB-PC_36BIT_NAND_defconfig
> > > delete mode 100644 configs/P1020RDB-PC_36BIT_SDCARD_defconfig
> > > delete mode 100644 configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
> > > delete mode 100644 configs/P1020RDB-PC_36BIT_defconfig
> > > delete mode 100644 configs/P1020RDB-PC_NAND_defconfig
> > > delete mode 100644 configs/P1020RDB-PC_SDCARD_defconfig
> > > delete mode 100644 configs/P1020RDB-PC_SPIFLASH_defconfig
> > > delete mode 100644 configs/P1020RDB-PC_defconfig
> > > delete mode 100644 configs/P1020RDB-PD_NAND_defconfig
> > > delete mode 100644 configs/P1020RDB-PD_SDCARD_defconfig
> > > delete mode 100644 configs/P1020RDB-PD_SPIFLASH_defconfig
> > > delete mode 100644 configs/P1020RDB-PD_defconfig
> > > delete mode 100644 configs/P1020UTM-PC_36BIT_SDCARD_defconfig
> > > delete mode 100644 configs/P1020UTM-PC_36BIT_defconfig
> > > delete mode 100644 configs/P1020UTM-PC_SDCARD_defconfig
> > > delete mode 100644 configs/P1020UTM-PC_defconfig
> > > delete mode 100644 configs/P1021RDB-PC_36BIT_NAND_defconfig
> > > delete mode 100644 configs/P1021RDB-PC_36BIT_SDCARD_defconfig
> > > delete mode 100644 configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig
> > > delete mode 100644 configs/P1021RDB-PC_36BIT_defconfig
> > > delete mode 100644 configs/P1021RDB-PC_NAND_defconfig
> > > delete mode 100644 configs/P1021RDB-PC_SDCARD_defconfig
> > > delete mode 100644 configs/P1021RDB-PC_SPIFLASH_defconfig
> > > delete mode 100644 configs/P1021RDB-PC_defconfig
> > > delete mode 100644 configs/P1024RDB_36BIT_defconfig
> > > delete mode 100644 configs/P1024RDB_NAND_defconfig
> > > delete mode 100644 configs/P1024RDB_SDCARD_defconfig
> > > delete mode 100644 configs/P1024RDB_SPIFLASH_defconfig
> > > delete mode 100644 configs/P1024RDB_defconfig
> > > delete mode 100644 configs/P1025RDB_36BIT_defconfig
> > > delete mode 100644 configs/P1025RDB_NAND_defconfig
> > > delete mode 100644 configs/P1025RDB_SDCARD_defconfig
> > > delete mode 100644 configs/P1025RDB_SPIFLASH_defconfig
> > > delete mode 100644 configs/P1025RDB_defconfig
> > > delete mode 100644 configs/P2020RDB-PC_36BIT_NAND_defconfig
> > > delete mode 100644 configs/P2020RDB-PC_36BIT_SDCARD_defconfig
> > > delete mode 100644 configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
> > > delete mode 100644 configs/P2020RDB-PC_36BIT_defconfig
> > > delete mode 100644 configs/P2020RDB-PC_NAND_defconfig
> > > delete mode 100644 configs/P2020RDB-PC_SDCARD_defconfig
> > > delete mode 100644 configs/P2020RDB-PC_SPIFLASH_defconfig
> > > delete mode 100644 configs/P2020RDB-PC_defconfig
> > > delete mode 100644 include/configs/p1_p2_rdb_pc.h
> > >
> > <snip>
> > NXP plans to keep maintaining these boards. Please don't merge this patch .
> >
> > The espi series of patches for DM migration were in review since long, but could not be merged because of dependency.
> > NXP engineers are working on rebasing the DM espi migration series.
> >
> > http://patchwork.ozlabs.org/project/uboot/list/?series=127282&state=*
> > http://patchwork.ozlabs.org/project/uboot/list/?series=138873
>
> Of this series, P1020MBG-PC_SDCARD, P1020UTM-PC_SDCARD,
> P1021RDB-PC_36BIT_SDCARD, P1021RDB-PC_SDCARD, P1024RDB_SDCARD,
> P1025RDB_SDCARD
> and also sometimes:
> +(P1021RDB-PC_36BIT_SDCARD) This board does not use CONFIG_DM_USB. Please update
> +(P1021RDB-PC_36BIT_SDCARD) the board to use CONFIG_DM_USB before the v2019.07 release.
> +(P1021RDB-PC_36BIT_SDCARD) This board does use CONFIG_LIBATA but has CONFIG_AHCI not
> +(P1021RDB-PC_36BIT_SDCARD) enabled. Please update the storage controller driver to use
> +(P1021RDB-PC_36BIT_SDCARD) CONFIG_AHCI before the v2019.07 release.
> or:
> +(P1021RDB-PC_SDCARD) This board does not use CONFIG_DM_PCI Please update
> +(P1021RDB-PC_SDCARD) the board to use CONFIG_DM_PCI before the v2019.07 release.
>
> And of course those non-MMC issues show up on other configs of the
> family. How far along are the plans to address those? Thanks!
I think it might be best to re-introduce the board later when it is
ready, since we are so far past the migration deadline. That will
unblock the SPI patches, which after all we want to get in to this
release or at least the next merge window.
Or perhaps just disable SPI flash, etc. for the board?
Regards,
Simon
^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH 11/24] arm: Remove configs/P3041DS_NAND_SECURE_BOOT_defconfig board
2020-05-28 7:09 ` Priyanka Jain
@ 2020-05-28 20:37 ` Tom Rini
0 siblings, 0 replies; 59+ messages in thread
From: Tom Rini @ 2020-05-28 20:37 UTC (permalink / raw)
To: u-boot
On Thu, May 28, 2020 at 07:09:35AM +0000, Priyanka Jain wrote:
> >-----Original Message-----
> >From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Jagan Teki
> >Sent: Wednesday, May 27, 2020 10:17 PM
> >To: Simon Glass <sjg@chromium.org>; Tom Rini <trini@konsulko.com>
> >Cc: u-boot at lists.denx.de; linux-amarula at amarulasolutions.com; Jagan Teki
> ><jagan@amarulasolutions.com>
> >Subject: [PATCH 11/24] arm: Remove
> >configs/P3041DS_NAND_SECURE_BOOT_defconfig board
> >
> >This board has not been converted to CONFIG_DM_SPI by the deadline.
> >
> >Remove it.
> >
> >Patch-cc: Ruchika Gupta <ruchika.gupta@nxp.com>
> >Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> >---
> > arch/powerpc/cpu/mpc85xx/Kconfig | 1 -
> > board/freescale/corenet_ds/Kconfig | 59 --
> > board/freescale/corenet_ds/MAINTAINERS | 37 -
> > board/freescale/corenet_ds/Makefile | 16 -
> > board/freescale/corenet_ds/corenet_ds.c | 215 ------
> > board/freescale/corenet_ds/corenet_ds.h | 12 -
> > board/freescale/corenet_ds/ddr.c | 286 --------
> > board/freescale/corenet_ds/eth_hydra.c | 520 -------------
> > board/freescale/corenet_ds/eth_p4080.c | 483 ------------
> > board/freescale/corenet_ds/eth_superhydra.c | 771 --------------------
> > board/freescale/corenet_ds/p3041ds_ddr.c | 11 -
> > board/freescale/corenet_ds/p4080ds_ddr.c | 347 ---------
> > board/freescale/corenet_ds/p5020ds_ddr.c | 15 -
> > board/freescale/corenet_ds/p5040ds_ddr.c | 15 -
> > board/freescale/corenet_ds/pbi.cfg | 33 -
> > board/freescale/corenet_ds/rcw_p2041rdb.cfg | 11 -
> > board/freescale/corenet_ds/rcw_p3041ds.cfg | 11 -
> > board/freescale/corenet_ds/rcw_p4080ds.cfg | 11 -
> > board/freescale/corenet_ds/rcw_p5020ds.cfg | 11 -
> > board/freescale/corenet_ds/rcw_p5040ds.cfg | 11 -
> > configs/P3041DS_NAND_SECURE_BOOT_defconfig | 59 --
> > configs/P3041DS_NAND_defconfig | 64 --
> > configs/P3041DS_SDCARD_defconfig | 63 --
> > configs/P3041DS_SECURE_BOOT_defconfig | 57 --
> > configs/P3041DS_SPIFLASH_defconfig | 64 --
> > configs/P3041DS_SRIO_PCIE_BOOT_defconfig | 50 --
> > configs/P3041DS_defconfig | 62 --
> > configs/P4080DS_SDCARD_defconfig | 62 --
> > configs/P4080DS_SECURE_BOOT_defconfig | 56 --
> > configs/P4080DS_SPIFLASH_defconfig | 63 --
> > configs/P4080DS_SRIO_PCIE_BOOT_defconfig | 48 --
> > configs/P4080DS_defconfig | 61 --
> > configs/P5020DS_NAND_SECURE_BOOT_defconfig | 60 --
> > configs/P5020DS_NAND_defconfig | 57 --
> > configs/P5020DS_SDCARD_defconfig | 55 --
> > configs/P5020DS_SECURE_BOOT_defconfig | 57 --
> > configs/P5020DS_SPIFLASH_defconfig | 56 --
> > configs/P5020DS_SRIO_PCIE_BOOT_defconfig | 50 --
> > configs/P5020DS_defconfig | 54 --
> > configs/P5040DS_NAND_SECURE_BOOT_defconfig | 60 --
> > configs/P5040DS_NAND_defconfig | 65 --
> > configs/P5040DS_SDCARD_defconfig | 63 --
> > configs/P5040DS_SECURE_BOOT_defconfig | 57 --
> > configs/P5040DS_SPIFLASH_defconfig | 64 --
> > configs/P5040DS_defconfig | 62 --
> > include/configs/P3041DS.h | 24 -
> > include/configs/P4080DS.h | 23 -
> > include/configs/P5020DS.h | 25 -
> > include/configs/P5040DS.h | 19 -
> > 49 files changed, 4436 deletions(-)
> > delete mode 100644 board/freescale/corenet_ds/Kconfig
> > delete mode 100644 board/freescale/corenet_ds/MAINTAINERS
> > delete mode 100644 board/freescale/corenet_ds/Makefile
> > delete mode 100644 board/freescale/corenet_ds/corenet_ds.c
> > delete mode 100644 board/freescale/corenet_ds/corenet_ds.h
> > delete mode 100644 board/freescale/corenet_ds/ddr.c
> > delete mode 100644 board/freescale/corenet_ds/eth_hydra.c
> > delete mode 100644 board/freescale/corenet_ds/eth_p4080.c
> > delete mode 100644 board/freescale/corenet_ds/eth_superhydra.c
> > delete mode 100644 board/freescale/corenet_ds/p3041ds_ddr.c
> > delete mode 100644 board/freescale/corenet_ds/p4080ds_ddr.c
> > delete mode 100644 board/freescale/corenet_ds/p5020ds_ddr.c
> > delete mode 100644 board/freescale/corenet_ds/p5040ds_ddr.c
> > delete mode 100644 board/freescale/corenet_ds/pbi.cfg
> > delete mode 100644 board/freescale/corenet_ds/rcw_p2041rdb.cfg
> > delete mode 100644 board/freescale/corenet_ds/rcw_p3041ds.cfg
> > delete mode 100644 board/freescale/corenet_ds/rcw_p4080ds.cfg
> > delete mode 100644 board/freescale/corenet_ds/rcw_p5020ds.cfg
> > delete mode 100644 board/freescale/corenet_ds/rcw_p5040ds.cfg
> > delete mode 100644 configs/P3041DS_NAND_SECURE_BOOT_defconfig
> > delete mode 100644 configs/P3041DS_NAND_defconfig
> > delete mode 100644 configs/P3041DS_SDCARD_defconfig
> > delete mode 100644 configs/P3041DS_SECURE_BOOT_defconfig
> > delete mode 100644 configs/P3041DS_SPIFLASH_defconfig
> > delete mode 100644 configs/P3041DS_SRIO_PCIE_BOOT_defconfig
> > delete mode 100644 configs/P3041DS_defconfig
> > delete mode 100644 configs/P4080DS_SDCARD_defconfig
> > delete mode 100644 configs/P4080DS_SECURE_BOOT_defconfig
> > delete mode 100644 configs/P4080DS_SPIFLASH_defconfig
> > delete mode 100644 configs/P4080DS_SRIO_PCIE_BOOT_defconfig
> > delete mode 100644 configs/P4080DS_defconfig
> > delete mode 100644 configs/P5020DS_NAND_SECURE_BOOT_defconfig
> > delete mode 100644 configs/P5020DS_NAND_defconfig
> > delete mode 100644 configs/P5020DS_SDCARD_defconfig
> > delete mode 100644 configs/P5020DS_SECURE_BOOT_defconfig
> > delete mode 100644 configs/P5020DS_SPIFLASH_defconfig
> > delete mode 100644 configs/P5020DS_SRIO_PCIE_BOOT_defconfig
> > delete mode 100644 configs/P5020DS_defconfig
> > delete mode 100644 configs/P5040DS_NAND_SECURE_BOOT_defconfig
> > delete mode 100644 configs/P5040DS_NAND_defconfig
> > delete mode 100644 configs/P5040DS_SDCARD_defconfig
> > delete mode 100644 configs/P5040DS_SECURE_BOOT_defconfig
> > delete mode 100644 configs/P5040DS_SPIFLASH_defconfig
> > delete mode 100644 configs/P5040DS_defconfig
> > delete mode 100644 include/configs/P3041DS.h
> > delete mode 100644 include/configs/P4080DS.h
> > delete mode 100644 include/configs/P5020DS.h
> > delete mode 100644 include/configs/P5040DS.h
> >
> <snip>
> NXP plans to keep maintaining these boards. Please don't merge this patch .
>
> The espi series of patches for DM migration were in review since long, but could not be merged because of dependency.
> NXP engineers are working on rebasing the DM espi migration series.
>
> http://patchwork.ozlabs.org/project/uboot/list/?series=127282&state=*
> http://patchwork.ozlabs.org/project/uboot/list/?series=138873
Here we see the very late migration problems on the P5020DS family.
--
Tom
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^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH 14/24] arm: Remove configs/T1040D4RDB_NAND_defconfig board
2020-05-28 7:11 ` Priyanka Jain
@ 2020-05-28 20:40 ` Tom Rini
0 siblings, 0 replies; 59+ messages in thread
From: Tom Rini @ 2020-05-28 20:40 UTC (permalink / raw)
To: u-boot
On Thu, May 28, 2020 at 07:11:55AM +0000, Priyanka Jain wrote:
> >-----Original Message-----
> >From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Jagan Teki
> >Sent: Wednesday, May 27, 2020 10:17 PM
> >To: Simon Glass <sjg@chromium.org>; Tom Rini <trini@konsulko.com>
> >Cc: u-boot at lists.denx.de; linux-amarula at amarulasolutions.com; Jagan Teki
> ><jagan@amarulasolutions.com>
> >Subject: [PATCH 14/24] arm: Remove configs/T1040D4RDB_NAND_defconfig
> >board
> >
> >This board has not been converted to CONFIG_DM_SPI by the deadline.
> >
> >Remove it.
> >
> >Patch-cc: Priyanka Jain <priyanka.jain@nxp.com>
> >Patch-cc: Priyanka Jain <priyanka.jain@nxp.com>
> >Patch-cc: Ruchika Gupta <ruchika.gupta@nxp.com>
> >Patch-cc: Sumit Garg <sumit.garg@nxp.com>
> >Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> >---
> > arch/powerpc/cpu/mpc85xx/Kconfig | 1 -
> > board/freescale/t104xrdb/Kconfig | 16 -
> > board/freescale/t104xrdb/MAINTAINERS | 38 -
> > board/freescale/t104xrdb/Makefile | 16 -
> > board/freescale/t104xrdb/README | 386 ---------
> > board/freescale/t104xrdb/cpld.c | 115 ---
> > board/freescale/t104xrdb/cpld.h | 46 -
> > board/freescale/t104xrdb/ddr.c | 145 ----
> > board/freescale/t104xrdb/ddr.h | 56 --
> > board/freescale/t104xrdb/diu.c | 84 --
> > board/freescale/t104xrdb/eth.c | 154 ----
> > board/freescale/t104xrdb/law.c | 31 -
> > board/freescale/t104xrdb/pci.c | 25 -
> > board/freescale/t104xrdb/spl.c | 142 ---
> > board/freescale/t104xrdb/t1040_nand_rcw.cfg | 7 -
> > board/freescale/t104xrdb/t1040_sd_rcw.cfg | 7 -
> > board/freescale/t104xrdb/t1040_spi_rcw.cfg | 7 -
> > board/freescale/t104xrdb/t1040d4_nand_rcw.cfg | 7 -
> > board/freescale/t104xrdb/t1040d4_sd_rcw.cfg | 7 -
> > board/freescale/t104xrdb/t1040d4_spi_rcw.cfg | 7 -
> > board/freescale/t104xrdb/t1042_nand_rcw.cfg | 7 -
> > .../freescale/t104xrdb/t1042_pi_nand_rcw.cfg | 7 -
> > board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg | 7 -
> > board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg | 7 -
> > board/freescale/t104xrdb/t1042_sd_rcw.cfg | 7 -
> > board/freescale/t104xrdb/t1042_spi_rcw.cfg | 7 -
> > board/freescale/t104xrdb/t1042d4_nand_rcw.cfg | 7 -
> > board/freescale/t104xrdb/t1042d4_sd_rcw.cfg | 7 -
> > board/freescale/t104xrdb/t1042d4_spi_rcw.cfg | 7 -
> > board/freescale/t104xrdb/t104x_pbi.cfg | 36 -
> > board/freescale/t104xrdb/t104x_pbi_sb.cfg | 38 -
> > board/freescale/t104xrdb/t104xrdb.c | 161 ----
> > board/freescale/t104xrdb/t104xrdb.h | 12 -
> > board/freescale/t104xrdb/tlb.c | 131 ---
> > configs/T1040D4RDB_NAND_defconfig | 75 --
> > configs/T1040D4RDB_SDCARD_defconfig | 72 --
> > configs/T1040D4RDB_SECURE_BOOT_defconfig | 61 --
> > configs/T1040D4RDB_SPIFLASH_defconfig | 75 --
> > configs/T1040D4RDB_defconfig | 59 --
> > configs/T1040RDB_NAND_defconfig | 76 --
> > configs/T1040RDB_SDCARD_defconfig | 73 --
> > configs/T1040RDB_SECURE_BOOT_defconfig | 62 --
> > configs/T1040RDB_SPIFLASH_defconfig | 76 --
> > configs/T1040RDB_defconfig | 60 --
> > configs/T1042D4RDB_NAND_defconfig | 86 --
> > configs/T1042D4RDB_SDCARD_defconfig | 83 --
> > configs/T1042D4RDB_SECURE_BOOT_defconfig | 64 --
> > configs/T1042D4RDB_SPIFLASH_defconfig | 86 --
> > configs/T1042D4RDB_defconfig | 71 --
> > .../T1042RDB_PI_NAND_SECURE_BOOT_defconfig | 85 --
> > configs/T1042RDB_PI_NAND_defconfig | 80 --
> > configs/T1042RDB_PI_SDCARD_defconfig | 77 --
> > configs/T1042RDB_PI_SPIFLASH_defconfig | 80 --
> > configs/T1042RDB_PI_defconfig | 64 --
> > configs/T1042RDB_SECURE_BOOT_defconfig | 61 --
> > configs/T1042RDB_defconfig | 59 --
> > include/configs/T104xRDB.h | 813 ------------------
> > 57 files changed, 4136 deletions(-)
> > delete mode 100644 board/freescale/t104xrdb/Kconfig
> > delete mode 100644 board/freescale/t104xrdb/MAINTAINERS
> > delete mode 100644 board/freescale/t104xrdb/Makefile
> > delete mode 100644 board/freescale/t104xrdb/README
> > delete mode 100644 board/freescale/t104xrdb/cpld.c
> > delete mode 100644 board/freescale/t104xrdb/cpld.h
> > delete mode 100644 board/freescale/t104xrdb/ddr.c
> > delete mode 100644 board/freescale/t104xrdb/ddr.h
> > delete mode 100644 board/freescale/t104xrdb/diu.c
> > delete mode 100644 board/freescale/t104xrdb/eth.c
> > delete mode 100644 board/freescale/t104xrdb/law.c
> > delete mode 100644 board/freescale/t104xrdb/pci.c
> > delete mode 100644 board/freescale/t104xrdb/spl.c
> > delete mode 100644 board/freescale/t104xrdb/t1040_nand_rcw.cfg
> > delete mode 100644 board/freescale/t104xrdb/t1040_sd_rcw.cfg
> > delete mode 100644 board/freescale/t104xrdb/t1040_spi_rcw.cfg
> > delete mode 100644 board/freescale/t104xrdb/t1040d4_nand_rcw.cfg
> > delete mode 100644 board/freescale/t104xrdb/t1040d4_sd_rcw.cfg
> > delete mode 100644 board/freescale/t104xrdb/t1040d4_spi_rcw.cfg
> > delete mode 100644 board/freescale/t104xrdb/t1042_nand_rcw.cfg
> > delete mode 100644 board/freescale/t104xrdb/t1042_pi_nand_rcw.cfg
> > delete mode 100644 board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg
> > delete mode 100644 board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg
> > delete mode 100644 board/freescale/t104xrdb/t1042_sd_rcw.cfg
> > delete mode 100644 board/freescale/t104xrdb/t1042_spi_rcw.cfg
> > delete mode 100644 board/freescale/t104xrdb/t1042d4_nand_rcw.cfg
> > delete mode 100644 board/freescale/t104xrdb/t1042d4_sd_rcw.cfg
> > delete mode 100644 board/freescale/t104xrdb/t1042d4_spi_rcw.cfg
> > delete mode 100644 board/freescale/t104xrdb/t104x_pbi.cfg
> > delete mode 100644 board/freescale/t104xrdb/t104x_pbi_sb.cfg
> > delete mode 100644 board/freescale/t104xrdb/t104xrdb.c
> > delete mode 100644 board/freescale/t104xrdb/t104xrdb.h
> > delete mode 100644 board/freescale/t104xrdb/tlb.c
> > delete mode 100644 configs/T1040D4RDB_NAND_defconfig
> > delete mode 100644 configs/T1040D4RDB_SDCARD_defconfig
> > delete mode 100644 configs/T1040D4RDB_SECURE_BOOT_defconfig
> > delete mode 100644 configs/T1040D4RDB_SPIFLASH_defconfig
> > delete mode 100644 configs/T1040D4RDB_defconfig
> > delete mode 100644 configs/T1040RDB_NAND_defconfig
> > delete mode 100644 configs/T1040RDB_SDCARD_defconfig
> > delete mode 100644 configs/T1040RDB_SECURE_BOOT_defconfig
> > delete mode 100644 configs/T1040RDB_SPIFLASH_defconfig
> > delete mode 100644 configs/T1040RDB_defconfig
> > delete mode 100644 configs/T1042D4RDB_NAND_defconfig
> > delete mode 100644 configs/T1042D4RDB_SDCARD_defconfig
> > delete mode 100644 configs/T1042D4RDB_SECURE_BOOT_defconfig
> > delete mode 100644 configs/T1042D4RDB_SPIFLASH_defconfig
> > delete mode 100644 configs/T1042D4RDB_defconfig
> > delete mode 100644 configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig
> > delete mode 100644 configs/T1042RDB_PI_NAND_defconfig
> > delete mode 100644 configs/T1042RDB_PI_SDCARD_defconfig
> > delete mode 100644 configs/T1042RDB_PI_SPIFLASH_defconfig
> > delete mode 100644 configs/T1042RDB_PI_defconfig
> > delete mode 100644 configs/T1042RDB_SECURE_BOOT_defconfig
> > delete mode 100644 configs/T1042RDB_defconfig
> > delete mode 100644 include/configs/T104xRDB.h
> >
> <snip>
> NXP plans to keep maintaining these boards. Please don't merge this patch .
>
> The espi series of patches for DM migration were in review since long, but could not be merged because of dependency.
> NXP engineers are working on rebasing the DM espi migration series.
>
> http://patchwork.ozlabs.org/project/uboot/list/?series=127282&state=*
> http://patchwork.ozlabs.org/project/uboot/list/?series=138873
Here the T1042RDB_PI and T1040D4RDB families have the various migration
problems I've mentioned.
--
Tom
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^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH 16/24] arm: Remove configs/T2080QDS_NAND_defconfig board
2020-05-28 7:14 ` Priyanka Jain
@ 2020-05-28 20:42 ` Tom Rini
0 siblings, 0 replies; 59+ messages in thread
From: Tom Rini @ 2020-05-28 20:42 UTC (permalink / raw)
To: u-boot
On Thu, May 28, 2020 at 07:14:02AM +0000, Priyanka Jain wrote:
> >-----Original Message-----
> >From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Jagan Teki
> >Sent: Wednesday, May 27, 2020 10:17 PM
> >To: Simon Glass <sjg@chromium.org>; Tom Rini <trini@konsulko.com>
> >Cc: u-boot at lists.denx.de; linux-amarula at amarulasolutions.com; Jagan Teki
> ><jagan@amarulasolutions.com>
> >Subject: [PATCH 16/24] arm: Remove configs/T2080QDS_NAND_defconfig
> >board
> >
> >This board has not been converted to CONFIG_DM_SPI by the deadline.
> >
> >Remove it.
> >
> >Patch-cc: Shengzhou Liu <Shengzhou.Liu@nxp.com>
> >Patch-cc: Ruchika Gupta <ruchika.gupta@nxp.com>
> >Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> >---
> > arch/powerpc/cpu/mpc85xx/Kconfig | 1 -
> > board/freescale/t208xqds/Kconfig | 14 -
> > board/freescale/t208xqds/MAINTAINERS | 20 -
> > board/freescale/t208xqds/Makefile | 17 -
> > board/freescale/t208xqds/README | 293 -------
> > board/freescale/t208xqds/ddr.c | 125 ---
> > board/freescale/t208xqds/ddr.h | 70 --
> > board/freescale/t208xqds/eth_t208xqds.c | 826 --------------------
> > board/freescale/t208xqds/law.c | 33 -
> > board/freescale/t208xqds/pci.c | 25 -
> > board/freescale/t208xqds/spl.c | 142 ----
> > board/freescale/t208xqds/t2080_nand_rcw.cfg | 16 -
> > board/freescale/t208xqds/t2080_sd_rcw.cfg | 16 -
> > board/freescale/t208xqds/t2080_spi_rcw.cfg | 16 -
> > board/freescale/t208xqds/t2081_nand_rcw.cfg | 8 -
> > board/freescale/t208xqds/t2081_sd_rcw.cfg | 8 -
> > board/freescale/t208xqds/t2081_spi_rcw.cfg | 8 -
> > board/freescale/t208xqds/t208x_pbi.cfg | 40 -
> > board/freescale/t208xqds/t208xqds.c | 489 ------------
> > board/freescale/t208xqds/t208xqds.h | 12 -
> > board/freescale/t208xqds/t208xqds_qixis.h | 48 --
> > board/freescale/t208xqds/tlb.c | 152 ----
> > configs/T2080QDS_NAND_defconfig | 83 --
> > configs/T2080QDS_SDCARD_defconfig | 80 --
> > configs/T2080QDS_SECURE_BOOT_defconfig | 70 --
> > configs/T2080QDS_SPIFLASH_defconfig | 83 --
> > configs/T2080QDS_SRIO_PCIE_BOOT_defconfig | 60 --
> > configs/T2080QDS_defconfig | 68 --
> > configs/T2081QDS_NAND_defconfig | 75 --
> > configs/T2081QDS_SDCARD_defconfig | 72 --
> > configs/T2081QDS_SPIFLASH_defconfig | 75 --
> > configs/T2081QDS_SRIO_PCIE_BOOT_defconfig | 51 --
> > configs/T2081QDS_defconfig | 59 --
> > include/configs/T208xQDS.h | 771 ------------------
> > 34 files changed, 3926 deletions(-)
> > delete mode 100644 board/freescale/t208xqds/Kconfig
> > delete mode 100644 board/freescale/t208xqds/MAINTAINERS
> > delete mode 100644 board/freescale/t208xqds/Makefile
> > delete mode 100755 board/freescale/t208xqds/README
> > delete mode 100644 board/freescale/t208xqds/ddr.c
> > delete mode 100644 board/freescale/t208xqds/ddr.h
> > delete mode 100644 board/freescale/t208xqds/eth_t208xqds.c
> > delete mode 100644 board/freescale/t208xqds/law.c
> > delete mode 100644 board/freescale/t208xqds/pci.c
> > delete mode 100644 board/freescale/t208xqds/spl.c
> > delete mode 100644 board/freescale/t208xqds/t2080_nand_rcw.cfg
> > delete mode 100644 board/freescale/t208xqds/t2080_sd_rcw.cfg
> > delete mode 100644 board/freescale/t208xqds/t2080_spi_rcw.cfg
> > delete mode 100644 board/freescale/t208xqds/t2081_nand_rcw.cfg
> > delete mode 100644 board/freescale/t208xqds/t2081_sd_rcw.cfg
> > delete mode 100644 board/freescale/t208xqds/t2081_spi_rcw.cfg
> > delete mode 100644 board/freescale/t208xqds/t208x_pbi.cfg
> > delete mode 100644 board/freescale/t208xqds/t208xqds.c
> > delete mode 100644 board/freescale/t208xqds/t208xqds.h
> > delete mode 100644 board/freescale/t208xqds/t208xqds_qixis.h
> > delete mode 100644 board/freescale/t208xqds/tlb.c
> > delete mode 100644 configs/T2080QDS_NAND_defconfig
> > delete mode 100644 configs/T2080QDS_SDCARD_defconfig
> > delete mode 100644 configs/T2080QDS_SECURE_BOOT_defconfig
> > delete mode 100644 configs/T2080QDS_SPIFLASH_defconfig
> > delete mode 100644 configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
> > delete mode 100644 configs/T2080QDS_defconfig
> > delete mode 100644 configs/T2081QDS_NAND_defconfig
> > delete mode 100644 configs/T2081QDS_SDCARD_defconfig
> > delete mode 100644 configs/T2081QDS_SPIFLASH_defconfig
> > delete mode 100644 configs/T2081QDS_SRIO_PCIE_BOOT_defconfig
> > delete mode 100644 configs/T2081QDS_defconfig
> > delete mode 100644 include/configs/T208xQDS.h
> >
> <snip>
> NXP plans to keep maintaining these boards. Please don't merge this patch .
>
> The espi series of patches for DM migration were in review since long, but could not be merged because of dependency.
> NXP engineers are working on rebasing the DM espi migration series.
>
> http://patchwork.ozlabs.org/project/uboot/list/?series=127282&state=*
> http://patchwork.ozlabs.org/project/uboot/list/?series=138873
Here the T2081QDS family has all of the other migration issues.
--
Tom
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^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH 08/24] arm: Remove configs/P1020MBG-PC_36BIT_SDCARD_defconfig board
2020-05-28 20:32 ` Simon Glass
@ 2020-05-28 20:44 ` Tom Rini
2020-05-29 12:36 ` Jagan Teki
0 siblings, 1 reply; 59+ messages in thread
From: Tom Rini @ 2020-05-28 20:44 UTC (permalink / raw)
To: u-boot
On Thu, May 28, 2020 at 02:32:39PM -0600, Simon Glass wrote:
> Hi,
>
> On Thu, 28 May 2020 at 14:15, Tom Rini <trini@konsulko.com> wrote:
> >
> > On Thu, May 28, 2020 at 07:07:14AM +0000, Priyanka Jain wrote:
> > > >-----Original Message-----
> > > >From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Jagan Teki
> > > >Sent: Wednesday, May 27, 2020 10:17 PM
> > > >To: Simon Glass <sjg@chromium.org>; Tom Rini <trini@konsulko.com>
> > > >Cc: u-boot at lists.denx.de; linux-amarula at amarulasolutions.com; Jagan Teki
> > > ><jagan@amarulasolutions.com>
> > > >Subject: [PATCH 08/24] arm: Remove configs/P1020MBG-
> > > >PC_36BIT_SDCARD_defconfig board
> > > >
> > > >This board has not been converted to CONFIG_DM_SPI by the deadline.
> > > >
> > > >Remove it.
> > > >
> > > >Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> > > >---
> > > > arch/powerpc/cpu/mpc85xx/Kconfig | 1 -
> > > > board/freescale/p1_p2_rdb_pc/Kconfig | 19 -
> > > > board/freescale/p1_p2_rdb_pc/MAINTAINERS | 51 --
> > > > board/freescale/p1_p2_rdb_pc/Makefile | 24 -
> > > > board/freescale/p1_p2_rdb_pc/README | 66 --
> > > > board/freescale/p1_p2_rdb_pc/ddr.c | 292 ------
> > > > board/freescale/p1_p2_rdb_pc/law.c | 22 -
> > > > board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 536 -----------
> > > > board/freescale/p1_p2_rdb_pc/spl.c | 123 ---
> > > > board/freescale/p1_p2_rdb_pc/spl_minimal.c | 63 --
> > > > board/freescale/p1_p2_rdb_pc/tlb.c | 110 ---
> > > > configs/P1020MBG-PC_36BIT_SDCARD_defconfig | 67 --
> > > > configs/P1020MBG-PC_36BIT_defconfig | 55 --
> > > > configs/P1020MBG-PC_SDCARD_defconfig | 66 --
> > > > configs/P1020MBG-PC_defconfig | 54 --
> > > > configs/P1020RDB-PC_36BIT_NAND_defconfig | 85 --
> > > > configs/P1020RDB-PC_36BIT_SDCARD_defconfig | 80 --
> > > > configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 82 --
> > > > configs/P1020RDB-PC_36BIT_defconfig | 69 --
> > > > configs/P1020RDB-PC_NAND_defconfig | 84 --
> > > > configs/P1020RDB-PC_SDCARD_defconfig | 79 --
> > > > configs/P1020RDB-PC_SPIFLASH_defconfig | 81 --
> > > > configs/P1020RDB-PC_defconfig | 68 --
> > > > configs/P1020RDB-PD_NAND_defconfig | 88 --
> > > > configs/P1020RDB-PD_SDCARD_defconfig | 83 --
> > > > configs/P1020RDB-PD_SPIFLASH_defconfig | 85 --
> > > > configs/P1020RDB-PD_defconfig | 72 --
> > > > configs/P1020UTM-PC_36BIT_SDCARD_defconfig | 67 --
> > > > configs/P1020UTM-PC_36BIT_defconfig | 55 --
> > > > configs/P1020UTM-PC_SDCARD_defconfig | 66 --
> > > > configs/P1020UTM-PC_defconfig | 54 --
> > > > configs/P1021RDB-PC_36BIT_NAND_defconfig | 84 --
> > > > configs/P1021RDB-PC_36BIT_SDCARD_defconfig | 79 --
> > > > configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig | 81 --
> > > > configs/P1021RDB-PC_36BIT_defconfig | 67 --
> > > > configs/P1021RDB-PC_NAND_defconfig | 83 --
> > > > configs/P1021RDB-PC_SDCARD_defconfig | 78 --
> > > > configs/P1021RDB-PC_SPIFLASH_defconfig | 80 --
> > > > configs/P1021RDB-PC_defconfig | 66 --
> > > > configs/P1024RDB_36BIT_defconfig | 61 --
> > > > configs/P1024RDB_NAND_defconfig | 77 --
> > > > configs/P1024RDB_SDCARD_defconfig | 71 --
> > > > configs/P1024RDB_SPIFLASH_defconfig | 73 --
> > > > configs/P1024RDB_defconfig | 60 --
> > > > configs/P1025RDB_36BIT_defconfig | 63 --
> > > > configs/P1025RDB_NAND_defconfig | 80 --
> > > > configs/P1025RDB_SDCARD_defconfig | 73 --
> > > > configs/P1025RDB_SPIFLASH_defconfig | 76 --
> > > > configs/P1025RDB_defconfig | 62 --
> > > > configs/P2020RDB-PC_36BIT_NAND_defconfig | 90 --
> > > > configs/P2020RDB-PC_36BIT_SDCARD_defconfig | 85 --
> > > > configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 87 --
> > > > configs/P2020RDB-PC_36BIT_defconfig | 74 --
> > > > configs/P2020RDB-PC_NAND_defconfig | 89 --
> > > > configs/P2020RDB-PC_SDCARD_defconfig | 84 --
> > > > configs/P2020RDB-PC_SPIFLASH_defconfig | 86 --
> > > > configs/P2020RDB-PC_defconfig | 73 --
> > > > include/configs/p1_p2_rdb_pc.h | 881 -------------------
> > > > 58 files changed, 5610 deletions(-)
> > > > delete mode 100644 board/freescale/p1_p2_rdb_pc/Kconfig
> > > > delete mode 100644 board/freescale/p1_p2_rdb_pc/MAINTAINERS
> > > > delete mode 100644 board/freescale/p1_p2_rdb_pc/Makefile
> > > > delete mode 100644 board/freescale/p1_p2_rdb_pc/README
> > > > delete mode 100644 board/freescale/p1_p2_rdb_pc/ddr.c
> > > > delete mode 100644 board/freescale/p1_p2_rdb_pc/law.c
> > > > delete mode 100644 board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
> > > > delete mode 100644 board/freescale/p1_p2_rdb_pc/spl.c
> > > > delete mode 100644 board/freescale/p1_p2_rdb_pc/spl_minimal.c
> > > > delete mode 100644 board/freescale/p1_p2_rdb_pc/tlb.c
> > > > delete mode 100644 configs/P1020MBG-PC_36BIT_SDCARD_defconfig
> > > > delete mode 100644 configs/P1020MBG-PC_36BIT_defconfig
> > > > delete mode 100644 configs/P1020MBG-PC_SDCARD_defconfig
> > > > delete mode 100644 configs/P1020MBG-PC_defconfig
> > > > delete mode 100644 configs/P1020RDB-PC_36BIT_NAND_defconfig
> > > > delete mode 100644 configs/P1020RDB-PC_36BIT_SDCARD_defconfig
> > > > delete mode 100644 configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
> > > > delete mode 100644 configs/P1020RDB-PC_36BIT_defconfig
> > > > delete mode 100644 configs/P1020RDB-PC_NAND_defconfig
> > > > delete mode 100644 configs/P1020RDB-PC_SDCARD_defconfig
> > > > delete mode 100644 configs/P1020RDB-PC_SPIFLASH_defconfig
> > > > delete mode 100644 configs/P1020RDB-PC_defconfig
> > > > delete mode 100644 configs/P1020RDB-PD_NAND_defconfig
> > > > delete mode 100644 configs/P1020RDB-PD_SDCARD_defconfig
> > > > delete mode 100644 configs/P1020RDB-PD_SPIFLASH_defconfig
> > > > delete mode 100644 configs/P1020RDB-PD_defconfig
> > > > delete mode 100644 configs/P1020UTM-PC_36BIT_SDCARD_defconfig
> > > > delete mode 100644 configs/P1020UTM-PC_36BIT_defconfig
> > > > delete mode 100644 configs/P1020UTM-PC_SDCARD_defconfig
> > > > delete mode 100644 configs/P1020UTM-PC_defconfig
> > > > delete mode 100644 configs/P1021RDB-PC_36BIT_NAND_defconfig
> > > > delete mode 100644 configs/P1021RDB-PC_36BIT_SDCARD_defconfig
> > > > delete mode 100644 configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig
> > > > delete mode 100644 configs/P1021RDB-PC_36BIT_defconfig
> > > > delete mode 100644 configs/P1021RDB-PC_NAND_defconfig
> > > > delete mode 100644 configs/P1021RDB-PC_SDCARD_defconfig
> > > > delete mode 100644 configs/P1021RDB-PC_SPIFLASH_defconfig
> > > > delete mode 100644 configs/P1021RDB-PC_defconfig
> > > > delete mode 100644 configs/P1024RDB_36BIT_defconfig
> > > > delete mode 100644 configs/P1024RDB_NAND_defconfig
> > > > delete mode 100644 configs/P1024RDB_SDCARD_defconfig
> > > > delete mode 100644 configs/P1024RDB_SPIFLASH_defconfig
> > > > delete mode 100644 configs/P1024RDB_defconfig
> > > > delete mode 100644 configs/P1025RDB_36BIT_defconfig
> > > > delete mode 100644 configs/P1025RDB_NAND_defconfig
> > > > delete mode 100644 configs/P1025RDB_SDCARD_defconfig
> > > > delete mode 100644 configs/P1025RDB_SPIFLASH_defconfig
> > > > delete mode 100644 configs/P1025RDB_defconfig
> > > > delete mode 100644 configs/P2020RDB-PC_36BIT_NAND_defconfig
> > > > delete mode 100644 configs/P2020RDB-PC_36BIT_SDCARD_defconfig
> > > > delete mode 100644 configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
> > > > delete mode 100644 configs/P2020RDB-PC_36BIT_defconfig
> > > > delete mode 100644 configs/P2020RDB-PC_NAND_defconfig
> > > > delete mode 100644 configs/P2020RDB-PC_SDCARD_defconfig
> > > > delete mode 100644 configs/P2020RDB-PC_SPIFLASH_defconfig
> > > > delete mode 100644 configs/P2020RDB-PC_defconfig
> > > > delete mode 100644 include/configs/p1_p2_rdb_pc.h
> > > >
> > > <snip>
> > > NXP plans to keep maintaining these boards. Please don't merge this patch .
> > >
> > > The espi series of patches for DM migration were in review since long, but could not be merged because of dependency.
> > > NXP engineers are working on rebasing the DM espi migration series.
> > >
> > > http://patchwork.ozlabs.org/project/uboot/list/?series=127282&state=*
> > > http://patchwork.ozlabs.org/project/uboot/list/?series=138873
> >
> > Of this series, P1020MBG-PC_SDCARD, P1020UTM-PC_SDCARD,
> > P1021RDB-PC_36BIT_SDCARD, P1021RDB-PC_SDCARD, P1024RDB_SDCARD,
> > P1025RDB_SDCARD
> > and also sometimes:
> > +(P1021RDB-PC_36BIT_SDCARD) This board does not use CONFIG_DM_USB. Please update
> > +(P1021RDB-PC_36BIT_SDCARD) the board to use CONFIG_DM_USB before the v2019.07 release.
> > +(P1021RDB-PC_36BIT_SDCARD) This board does use CONFIG_LIBATA but has CONFIG_AHCI not
> > +(P1021RDB-PC_36BIT_SDCARD) enabled. Please update the storage controller driver to use
> > +(P1021RDB-PC_36BIT_SDCARD) CONFIG_AHCI before the v2019.07 release.
> > or:
> > +(P1021RDB-PC_SDCARD) This board does not use CONFIG_DM_PCI Please update
> > +(P1021RDB-PC_SDCARD) the board to use CONFIG_DM_PCI before the v2019.07 release.
> >
> > And of course those non-MMC issues show up on other configs of the
> > family. How far along are the plans to address those? Thanks!
>
> I think it might be best to re-introduce the board later when it is
> ready, since we are so far past the migration deadline. That will
> unblock the SPI patches, which after all we want to get in to this
> release or at least the next merge window.
>
> Or perhaps just disable SPI flash, etc. for the board?
If we disable all of the far-past-migration features and fix the
resulting build issues (usually errata that don't have a proper guard)
there's little to nothing functional left in many cases, so removal and
reintroduction would be better.
To be clear, I'm not suggesting any of these get dropped for v2020.07
but I do want to see stuff removed or fixed for v2020.10 and I will be
doing more removal patches myself. Jagan beat me to it, and this is a
good place to raise all of the other problems these platforms show :)
--
Tom
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^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH 08/24] arm: Remove configs/P1020MBG-PC_36BIT_SDCARD_defconfig board
2020-05-28 20:44 ` Tom Rini
@ 2020-05-29 12:36 ` Jagan Teki
2020-05-29 13:27 ` Tom Rini
0 siblings, 1 reply; 59+ messages in thread
From: Jagan Teki @ 2020-05-29 12:36 UTC (permalink / raw)
To: u-boot
On Fri, May 29, 2020 at 2:14 AM Tom Rini <trini@konsulko.com> wrote:
>
> On Thu, May 28, 2020 at 02:32:39PM -0600, Simon Glass wrote:
> > Hi,
> >
> > On Thu, 28 May 2020 at 14:15, Tom Rini <trini@konsulko.com> wrote:
> > >
> > > On Thu, May 28, 2020 at 07:07:14AM +0000, Priyanka Jain wrote:
> > > > >-----Original Message-----
> > > > >From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Jagan Teki
> > > > >Sent: Wednesday, May 27, 2020 10:17 PM
> > > > >To: Simon Glass <sjg@chromium.org>; Tom Rini <trini@konsulko.com>
> > > > >Cc: u-boot at lists.denx.de; linux-amarula at amarulasolutions.com; Jagan Teki
> > > > ><jagan@amarulasolutions.com>
> > > > >Subject: [PATCH 08/24] arm: Remove configs/P1020MBG-
> > > > >PC_36BIT_SDCARD_defconfig board
> > > > >
> > > > >This board has not been converted to CONFIG_DM_SPI by the deadline.
> > > > >
> > > > >Remove it.
> > > > >
> > > > >Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> > > > >---
> > > > > arch/powerpc/cpu/mpc85xx/Kconfig | 1 -
> > > > > board/freescale/p1_p2_rdb_pc/Kconfig | 19 -
> > > > > board/freescale/p1_p2_rdb_pc/MAINTAINERS | 51 --
> > > > > board/freescale/p1_p2_rdb_pc/Makefile | 24 -
> > > > > board/freescale/p1_p2_rdb_pc/README | 66 --
> > > > > board/freescale/p1_p2_rdb_pc/ddr.c | 292 ------
> > > > > board/freescale/p1_p2_rdb_pc/law.c | 22 -
> > > > > board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 536 -----------
> > > > > board/freescale/p1_p2_rdb_pc/spl.c | 123 ---
> > > > > board/freescale/p1_p2_rdb_pc/spl_minimal.c | 63 --
> > > > > board/freescale/p1_p2_rdb_pc/tlb.c | 110 ---
> > > > > configs/P1020MBG-PC_36BIT_SDCARD_defconfig | 67 --
> > > > > configs/P1020MBG-PC_36BIT_defconfig | 55 --
> > > > > configs/P1020MBG-PC_SDCARD_defconfig | 66 --
> > > > > configs/P1020MBG-PC_defconfig | 54 --
> > > > > configs/P1020RDB-PC_36BIT_NAND_defconfig | 85 --
> > > > > configs/P1020RDB-PC_36BIT_SDCARD_defconfig | 80 --
> > > > > configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 82 --
> > > > > configs/P1020RDB-PC_36BIT_defconfig | 69 --
> > > > > configs/P1020RDB-PC_NAND_defconfig | 84 --
> > > > > configs/P1020RDB-PC_SDCARD_defconfig | 79 --
> > > > > configs/P1020RDB-PC_SPIFLASH_defconfig | 81 --
> > > > > configs/P1020RDB-PC_defconfig | 68 --
> > > > > configs/P1020RDB-PD_NAND_defconfig | 88 --
> > > > > configs/P1020RDB-PD_SDCARD_defconfig | 83 --
> > > > > configs/P1020RDB-PD_SPIFLASH_defconfig | 85 --
> > > > > configs/P1020RDB-PD_defconfig | 72 --
> > > > > configs/P1020UTM-PC_36BIT_SDCARD_defconfig | 67 --
> > > > > configs/P1020UTM-PC_36BIT_defconfig | 55 --
> > > > > configs/P1020UTM-PC_SDCARD_defconfig | 66 --
> > > > > configs/P1020UTM-PC_defconfig | 54 --
> > > > > configs/P1021RDB-PC_36BIT_NAND_defconfig | 84 --
> > > > > configs/P1021RDB-PC_36BIT_SDCARD_defconfig | 79 --
> > > > > configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig | 81 --
> > > > > configs/P1021RDB-PC_36BIT_defconfig | 67 --
> > > > > configs/P1021RDB-PC_NAND_defconfig | 83 --
> > > > > configs/P1021RDB-PC_SDCARD_defconfig | 78 --
> > > > > configs/P1021RDB-PC_SPIFLASH_defconfig | 80 --
> > > > > configs/P1021RDB-PC_defconfig | 66 --
> > > > > configs/P1024RDB_36BIT_defconfig | 61 --
> > > > > configs/P1024RDB_NAND_defconfig | 77 --
> > > > > configs/P1024RDB_SDCARD_defconfig | 71 --
> > > > > configs/P1024RDB_SPIFLASH_defconfig | 73 --
> > > > > configs/P1024RDB_defconfig | 60 --
> > > > > configs/P1025RDB_36BIT_defconfig | 63 --
> > > > > configs/P1025RDB_NAND_defconfig | 80 --
> > > > > configs/P1025RDB_SDCARD_defconfig | 73 --
> > > > > configs/P1025RDB_SPIFLASH_defconfig | 76 --
> > > > > configs/P1025RDB_defconfig | 62 --
> > > > > configs/P2020RDB-PC_36BIT_NAND_defconfig | 90 --
> > > > > configs/P2020RDB-PC_36BIT_SDCARD_defconfig | 85 --
> > > > > configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 87 --
> > > > > configs/P2020RDB-PC_36BIT_defconfig | 74 --
> > > > > configs/P2020RDB-PC_NAND_defconfig | 89 --
> > > > > configs/P2020RDB-PC_SDCARD_defconfig | 84 --
> > > > > configs/P2020RDB-PC_SPIFLASH_defconfig | 86 --
> > > > > configs/P2020RDB-PC_defconfig | 73 --
> > > > > include/configs/p1_p2_rdb_pc.h | 881 -------------------
> > > > > 58 files changed, 5610 deletions(-)
> > > > > delete mode 100644 board/freescale/p1_p2_rdb_pc/Kconfig
> > > > > delete mode 100644 board/freescale/p1_p2_rdb_pc/MAINTAINERS
> > > > > delete mode 100644 board/freescale/p1_p2_rdb_pc/Makefile
> > > > > delete mode 100644 board/freescale/p1_p2_rdb_pc/README
> > > > > delete mode 100644 board/freescale/p1_p2_rdb_pc/ddr.c
> > > > > delete mode 100644 board/freescale/p1_p2_rdb_pc/law.c
> > > > > delete mode 100644 board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
> > > > > delete mode 100644 board/freescale/p1_p2_rdb_pc/spl.c
> > > > > delete mode 100644 board/freescale/p1_p2_rdb_pc/spl_minimal.c
> > > > > delete mode 100644 board/freescale/p1_p2_rdb_pc/tlb.c
> > > > > delete mode 100644 configs/P1020MBG-PC_36BIT_SDCARD_defconfig
> > > > > delete mode 100644 configs/P1020MBG-PC_36BIT_defconfig
> > > > > delete mode 100644 configs/P1020MBG-PC_SDCARD_defconfig
> > > > > delete mode 100644 configs/P1020MBG-PC_defconfig
> > > > > delete mode 100644 configs/P1020RDB-PC_36BIT_NAND_defconfig
> > > > > delete mode 100644 configs/P1020RDB-PC_36BIT_SDCARD_defconfig
> > > > > delete mode 100644 configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
> > > > > delete mode 100644 configs/P1020RDB-PC_36BIT_defconfig
> > > > > delete mode 100644 configs/P1020RDB-PC_NAND_defconfig
> > > > > delete mode 100644 configs/P1020RDB-PC_SDCARD_defconfig
> > > > > delete mode 100644 configs/P1020RDB-PC_SPIFLASH_defconfig
> > > > > delete mode 100644 configs/P1020RDB-PC_defconfig
> > > > > delete mode 100644 configs/P1020RDB-PD_NAND_defconfig
> > > > > delete mode 100644 configs/P1020RDB-PD_SDCARD_defconfig
> > > > > delete mode 100644 configs/P1020RDB-PD_SPIFLASH_defconfig
> > > > > delete mode 100644 configs/P1020RDB-PD_defconfig
> > > > > delete mode 100644 configs/P1020UTM-PC_36BIT_SDCARD_defconfig
> > > > > delete mode 100644 configs/P1020UTM-PC_36BIT_defconfig
> > > > > delete mode 100644 configs/P1020UTM-PC_SDCARD_defconfig
> > > > > delete mode 100644 configs/P1020UTM-PC_defconfig
> > > > > delete mode 100644 configs/P1021RDB-PC_36BIT_NAND_defconfig
> > > > > delete mode 100644 configs/P1021RDB-PC_36BIT_SDCARD_defconfig
> > > > > delete mode 100644 configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig
> > > > > delete mode 100644 configs/P1021RDB-PC_36BIT_defconfig
> > > > > delete mode 100644 configs/P1021RDB-PC_NAND_defconfig
> > > > > delete mode 100644 configs/P1021RDB-PC_SDCARD_defconfig
> > > > > delete mode 100644 configs/P1021RDB-PC_SPIFLASH_defconfig
> > > > > delete mode 100644 configs/P1021RDB-PC_defconfig
> > > > > delete mode 100644 configs/P1024RDB_36BIT_defconfig
> > > > > delete mode 100644 configs/P1024RDB_NAND_defconfig
> > > > > delete mode 100644 configs/P1024RDB_SDCARD_defconfig
> > > > > delete mode 100644 configs/P1024RDB_SPIFLASH_defconfig
> > > > > delete mode 100644 configs/P1024RDB_defconfig
> > > > > delete mode 100644 configs/P1025RDB_36BIT_defconfig
> > > > > delete mode 100644 configs/P1025RDB_NAND_defconfig
> > > > > delete mode 100644 configs/P1025RDB_SDCARD_defconfig
> > > > > delete mode 100644 configs/P1025RDB_SPIFLASH_defconfig
> > > > > delete mode 100644 configs/P1025RDB_defconfig
> > > > > delete mode 100644 configs/P2020RDB-PC_36BIT_NAND_defconfig
> > > > > delete mode 100644 configs/P2020RDB-PC_36BIT_SDCARD_defconfig
> > > > > delete mode 100644 configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
> > > > > delete mode 100644 configs/P2020RDB-PC_36BIT_defconfig
> > > > > delete mode 100644 configs/P2020RDB-PC_NAND_defconfig
> > > > > delete mode 100644 configs/P2020RDB-PC_SDCARD_defconfig
> > > > > delete mode 100644 configs/P2020RDB-PC_SPIFLASH_defconfig
> > > > > delete mode 100644 configs/P2020RDB-PC_defconfig
> > > > > delete mode 100644 include/configs/p1_p2_rdb_pc.h
> > > > >
> > > > <snip>
> > > > NXP plans to keep maintaining these boards. Please don't merge this patch .
> > > >
> > > > The espi series of patches for DM migration were in review since long, but could not be merged because of dependency.
> > > > NXP engineers are working on rebasing the DM espi migration series.
> > > >
> > > > http://patchwork.ozlabs.org/project/uboot/list/?series=127282&state=*
> > > > http://patchwork.ozlabs.org/project/uboot/list/?series=138873
> > >
> > > Of this series, P1020MBG-PC_SDCARD, P1020UTM-PC_SDCARD,
> > > P1021RDB-PC_36BIT_SDCARD, P1021RDB-PC_SDCARD, P1024RDB_SDCARD,
> > > P1025RDB_SDCARD
> > > and also sometimes:
> > > +(P1021RDB-PC_36BIT_SDCARD) This board does not use CONFIG_DM_USB. Please update
> > > +(P1021RDB-PC_36BIT_SDCARD) the board to use CONFIG_DM_USB before the v2019.07 release.
> > > +(P1021RDB-PC_36BIT_SDCARD) This board does use CONFIG_LIBATA but has CONFIG_AHCI not
> > > +(P1021RDB-PC_36BIT_SDCARD) enabled. Please update the storage controller driver to use
> > > +(P1021RDB-PC_36BIT_SDCARD) CONFIG_AHCI before the v2019.07 release.
> > > or:
> > > +(P1021RDB-PC_SDCARD) This board does not use CONFIG_DM_PCI Please update
> > > +(P1021RDB-PC_SDCARD) the board to use CONFIG_DM_PCI before the v2019.07 release.
> > >
> > > And of course those non-MMC issues show up on other configs of the
> > > family. How far along are the plans to address those? Thanks!
> >
> > I think it might be best to re-introduce the board later when it is
> > ready, since we are so far past the migration deadline. That will
> > unblock the SPI patches, which after all we want to get in to this
> > release or at least the next merge window.
> >
> > Or perhaps just disable SPI flash, etc. for the board?
>
> If we disable all of the far-past-migration features and fix the
> resulting build issues (usually errata that don't have a proper guard)
> there's little to nothing functional left in many cases, so removal and
> reintroduction would be better.
>
> To be clear, I'm not suggesting any of these get dropped for v2020.07
> but I do want to see stuff removed or fixed for v2020.10 and I will be
Yes, I have mentioned a similar point to Priyanka on the other thread,
but I will pull whatever Priyanka acked on this series for this
release.
Jagan.
^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH 08/24] arm: Remove configs/P1020MBG-PC_36BIT_SDCARD_defconfig board
2020-05-29 12:36 ` Jagan Teki
@ 2020-05-29 13:27 ` Tom Rini
0 siblings, 0 replies; 59+ messages in thread
From: Tom Rini @ 2020-05-29 13:27 UTC (permalink / raw)
To: u-boot
On Fri, May 29, 2020 at 06:06:16PM +0530, Jagan Teki wrote:
> On Fri, May 29, 2020 at 2:14 AM Tom Rini <trini@konsulko.com> wrote:
> >
> > On Thu, May 28, 2020 at 02:32:39PM -0600, Simon Glass wrote:
> > > Hi,
> > >
> > > On Thu, 28 May 2020 at 14:15, Tom Rini <trini@konsulko.com> wrote:
> > > >
> > > > On Thu, May 28, 2020 at 07:07:14AM +0000, Priyanka Jain wrote:
> > > > > >-----Original Message-----
> > > > > >From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Jagan Teki
> > > > > >Sent: Wednesday, May 27, 2020 10:17 PM
> > > > > >To: Simon Glass <sjg@chromium.org>; Tom Rini <trini@konsulko.com>
> > > > > >Cc: u-boot at lists.denx.de; linux-amarula at amarulasolutions.com; Jagan Teki
> > > > > ><jagan@amarulasolutions.com>
> > > > > >Subject: [PATCH 08/24] arm: Remove configs/P1020MBG-
> > > > > >PC_36BIT_SDCARD_defconfig board
> > > > > >
> > > > > >This board has not been converted to CONFIG_DM_SPI by the deadline.
> > > > > >
> > > > > >Remove it.
> > > > > >
> > > > > >Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> > > > > >---
> > > > > > arch/powerpc/cpu/mpc85xx/Kconfig | 1 -
> > > > > > board/freescale/p1_p2_rdb_pc/Kconfig | 19 -
> > > > > > board/freescale/p1_p2_rdb_pc/MAINTAINERS | 51 --
> > > > > > board/freescale/p1_p2_rdb_pc/Makefile | 24 -
> > > > > > board/freescale/p1_p2_rdb_pc/README | 66 --
> > > > > > board/freescale/p1_p2_rdb_pc/ddr.c | 292 ------
> > > > > > board/freescale/p1_p2_rdb_pc/law.c | 22 -
> > > > > > board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 536 -----------
> > > > > > board/freescale/p1_p2_rdb_pc/spl.c | 123 ---
> > > > > > board/freescale/p1_p2_rdb_pc/spl_minimal.c | 63 --
> > > > > > board/freescale/p1_p2_rdb_pc/tlb.c | 110 ---
> > > > > > configs/P1020MBG-PC_36BIT_SDCARD_defconfig | 67 --
> > > > > > configs/P1020MBG-PC_36BIT_defconfig | 55 --
> > > > > > configs/P1020MBG-PC_SDCARD_defconfig | 66 --
> > > > > > configs/P1020MBG-PC_defconfig | 54 --
> > > > > > configs/P1020RDB-PC_36BIT_NAND_defconfig | 85 --
> > > > > > configs/P1020RDB-PC_36BIT_SDCARD_defconfig | 80 --
> > > > > > configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 82 --
> > > > > > configs/P1020RDB-PC_36BIT_defconfig | 69 --
> > > > > > configs/P1020RDB-PC_NAND_defconfig | 84 --
> > > > > > configs/P1020RDB-PC_SDCARD_defconfig | 79 --
> > > > > > configs/P1020RDB-PC_SPIFLASH_defconfig | 81 --
> > > > > > configs/P1020RDB-PC_defconfig | 68 --
> > > > > > configs/P1020RDB-PD_NAND_defconfig | 88 --
> > > > > > configs/P1020RDB-PD_SDCARD_defconfig | 83 --
> > > > > > configs/P1020RDB-PD_SPIFLASH_defconfig | 85 --
> > > > > > configs/P1020RDB-PD_defconfig | 72 --
> > > > > > configs/P1020UTM-PC_36BIT_SDCARD_defconfig | 67 --
> > > > > > configs/P1020UTM-PC_36BIT_defconfig | 55 --
> > > > > > configs/P1020UTM-PC_SDCARD_defconfig | 66 --
> > > > > > configs/P1020UTM-PC_defconfig | 54 --
> > > > > > configs/P1021RDB-PC_36BIT_NAND_defconfig | 84 --
> > > > > > configs/P1021RDB-PC_36BIT_SDCARD_defconfig | 79 --
> > > > > > configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig | 81 --
> > > > > > configs/P1021RDB-PC_36BIT_defconfig | 67 --
> > > > > > configs/P1021RDB-PC_NAND_defconfig | 83 --
> > > > > > configs/P1021RDB-PC_SDCARD_defconfig | 78 --
> > > > > > configs/P1021RDB-PC_SPIFLASH_defconfig | 80 --
> > > > > > configs/P1021RDB-PC_defconfig | 66 --
> > > > > > configs/P1024RDB_36BIT_defconfig | 61 --
> > > > > > configs/P1024RDB_NAND_defconfig | 77 --
> > > > > > configs/P1024RDB_SDCARD_defconfig | 71 --
> > > > > > configs/P1024RDB_SPIFLASH_defconfig | 73 --
> > > > > > configs/P1024RDB_defconfig | 60 --
> > > > > > configs/P1025RDB_36BIT_defconfig | 63 --
> > > > > > configs/P1025RDB_NAND_defconfig | 80 --
> > > > > > configs/P1025RDB_SDCARD_defconfig | 73 --
> > > > > > configs/P1025RDB_SPIFLASH_defconfig | 76 --
> > > > > > configs/P1025RDB_defconfig | 62 --
> > > > > > configs/P2020RDB-PC_36BIT_NAND_defconfig | 90 --
> > > > > > configs/P2020RDB-PC_36BIT_SDCARD_defconfig | 85 --
> > > > > > configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 87 --
> > > > > > configs/P2020RDB-PC_36BIT_defconfig | 74 --
> > > > > > configs/P2020RDB-PC_NAND_defconfig | 89 --
> > > > > > configs/P2020RDB-PC_SDCARD_defconfig | 84 --
> > > > > > configs/P2020RDB-PC_SPIFLASH_defconfig | 86 --
> > > > > > configs/P2020RDB-PC_defconfig | 73 --
> > > > > > include/configs/p1_p2_rdb_pc.h | 881 -------------------
> > > > > > 58 files changed, 5610 deletions(-)
> > > > > > delete mode 100644 board/freescale/p1_p2_rdb_pc/Kconfig
> > > > > > delete mode 100644 board/freescale/p1_p2_rdb_pc/MAINTAINERS
> > > > > > delete mode 100644 board/freescale/p1_p2_rdb_pc/Makefile
> > > > > > delete mode 100644 board/freescale/p1_p2_rdb_pc/README
> > > > > > delete mode 100644 board/freescale/p1_p2_rdb_pc/ddr.c
> > > > > > delete mode 100644 board/freescale/p1_p2_rdb_pc/law.c
> > > > > > delete mode 100644 board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
> > > > > > delete mode 100644 board/freescale/p1_p2_rdb_pc/spl.c
> > > > > > delete mode 100644 board/freescale/p1_p2_rdb_pc/spl_minimal.c
> > > > > > delete mode 100644 board/freescale/p1_p2_rdb_pc/tlb.c
> > > > > > delete mode 100644 configs/P1020MBG-PC_36BIT_SDCARD_defconfig
> > > > > > delete mode 100644 configs/P1020MBG-PC_36BIT_defconfig
> > > > > > delete mode 100644 configs/P1020MBG-PC_SDCARD_defconfig
> > > > > > delete mode 100644 configs/P1020MBG-PC_defconfig
> > > > > > delete mode 100644 configs/P1020RDB-PC_36BIT_NAND_defconfig
> > > > > > delete mode 100644 configs/P1020RDB-PC_36BIT_SDCARD_defconfig
> > > > > > delete mode 100644 configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
> > > > > > delete mode 100644 configs/P1020RDB-PC_36BIT_defconfig
> > > > > > delete mode 100644 configs/P1020RDB-PC_NAND_defconfig
> > > > > > delete mode 100644 configs/P1020RDB-PC_SDCARD_defconfig
> > > > > > delete mode 100644 configs/P1020RDB-PC_SPIFLASH_defconfig
> > > > > > delete mode 100644 configs/P1020RDB-PC_defconfig
> > > > > > delete mode 100644 configs/P1020RDB-PD_NAND_defconfig
> > > > > > delete mode 100644 configs/P1020RDB-PD_SDCARD_defconfig
> > > > > > delete mode 100644 configs/P1020RDB-PD_SPIFLASH_defconfig
> > > > > > delete mode 100644 configs/P1020RDB-PD_defconfig
> > > > > > delete mode 100644 configs/P1020UTM-PC_36BIT_SDCARD_defconfig
> > > > > > delete mode 100644 configs/P1020UTM-PC_36BIT_defconfig
> > > > > > delete mode 100644 configs/P1020UTM-PC_SDCARD_defconfig
> > > > > > delete mode 100644 configs/P1020UTM-PC_defconfig
> > > > > > delete mode 100644 configs/P1021RDB-PC_36BIT_NAND_defconfig
> > > > > > delete mode 100644 configs/P1021RDB-PC_36BIT_SDCARD_defconfig
> > > > > > delete mode 100644 configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig
> > > > > > delete mode 100644 configs/P1021RDB-PC_36BIT_defconfig
> > > > > > delete mode 100644 configs/P1021RDB-PC_NAND_defconfig
> > > > > > delete mode 100644 configs/P1021RDB-PC_SDCARD_defconfig
> > > > > > delete mode 100644 configs/P1021RDB-PC_SPIFLASH_defconfig
> > > > > > delete mode 100644 configs/P1021RDB-PC_defconfig
> > > > > > delete mode 100644 configs/P1024RDB_36BIT_defconfig
> > > > > > delete mode 100644 configs/P1024RDB_NAND_defconfig
> > > > > > delete mode 100644 configs/P1024RDB_SDCARD_defconfig
> > > > > > delete mode 100644 configs/P1024RDB_SPIFLASH_defconfig
> > > > > > delete mode 100644 configs/P1024RDB_defconfig
> > > > > > delete mode 100644 configs/P1025RDB_36BIT_defconfig
> > > > > > delete mode 100644 configs/P1025RDB_NAND_defconfig
> > > > > > delete mode 100644 configs/P1025RDB_SDCARD_defconfig
> > > > > > delete mode 100644 configs/P1025RDB_SPIFLASH_defconfig
> > > > > > delete mode 100644 configs/P1025RDB_defconfig
> > > > > > delete mode 100644 configs/P2020RDB-PC_36BIT_NAND_defconfig
> > > > > > delete mode 100644 configs/P2020RDB-PC_36BIT_SDCARD_defconfig
> > > > > > delete mode 100644 configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
> > > > > > delete mode 100644 configs/P2020RDB-PC_36BIT_defconfig
> > > > > > delete mode 100644 configs/P2020RDB-PC_NAND_defconfig
> > > > > > delete mode 100644 configs/P2020RDB-PC_SDCARD_defconfig
> > > > > > delete mode 100644 configs/P2020RDB-PC_SPIFLASH_defconfig
> > > > > > delete mode 100644 configs/P2020RDB-PC_defconfig
> > > > > > delete mode 100644 include/configs/p1_p2_rdb_pc.h
> > > > > >
> > > > > <snip>
> > > > > NXP plans to keep maintaining these boards. Please don't merge this patch .
> > > > >
> > > > > The espi series of patches for DM migration were in review since long, but could not be merged because of dependency.
> > > > > NXP engineers are working on rebasing the DM espi migration series.
> > > > >
> > > > > http://patchwork.ozlabs.org/project/uboot/list/?series=127282&state=*
> > > > > http://patchwork.ozlabs.org/project/uboot/list/?series=138873
> > > >
> > > > Of this series, P1020MBG-PC_SDCARD, P1020UTM-PC_SDCARD,
> > > > P1021RDB-PC_36BIT_SDCARD, P1021RDB-PC_SDCARD, P1024RDB_SDCARD,
> > > > P1025RDB_SDCARD
> > > > and also sometimes:
> > > > +(P1021RDB-PC_36BIT_SDCARD) This board does not use CONFIG_DM_USB. Please update
> > > > +(P1021RDB-PC_36BIT_SDCARD) the board to use CONFIG_DM_USB before the v2019.07 release.
> > > > +(P1021RDB-PC_36BIT_SDCARD) This board does use CONFIG_LIBATA but has CONFIG_AHCI not
> > > > +(P1021RDB-PC_36BIT_SDCARD) enabled. Please update the storage controller driver to use
> > > > +(P1021RDB-PC_36BIT_SDCARD) CONFIG_AHCI before the v2019.07 release.
> > > > or:
> > > > +(P1021RDB-PC_SDCARD) This board does not use CONFIG_DM_PCI Please update
> > > > +(P1021RDB-PC_SDCARD) the board to use CONFIG_DM_PCI before the v2019.07 release.
> > > >
> > > > And of course those non-MMC issues show up on other configs of the
> > > > family. How far along are the plans to address those? Thanks!
> > >
> > > I think it might be best to re-introduce the board later when it is
> > > ready, since we are so far past the migration deadline. That will
> > > unblock the SPI patches, which after all we want to get in to this
> > > release or at least the next merge window.
> > >
> > > Or perhaps just disable SPI flash, etc. for the board?
> >
> > If we disable all of the far-past-migration features and fix the
> > resulting build issues (usually errata that don't have a proper guard)
> > there's little to nothing functional left in many cases, so removal and
> > reintroduction would be better.
> >
> > To be clear, I'm not suggesting any of these get dropped for v2020.07
> > but I do want to see stuff removed or fixed for v2020.10 and I will be
>
> Yes, I have mentioned a similar point to Priyanka on the other thread,
> but I will pull whatever Priyanka acked on this series for this
> release.
To be clear, where we are in the release cycle, I want these changes
(and other migrations) for -next and not v2020.07, thanks!
--
Tom
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^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH 07/24] arm: Remove configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig board
2020-05-28 20:02 ` Tom Rini
@ 2020-06-01 5:23 ` Priyanka Jain
2020-06-01 11:43 ` Tom Rini
0 siblings, 1 reply; 59+ messages in thread
From: Priyanka Jain @ 2020-06-01 5:23 UTC (permalink / raw)
To: u-boot
>-----Original Message-----
>From: Tom Rini <trini@konsulko.com>
>Sent: Friday, May 29, 2020 1:32 AM
>To: Priyanka Jain <priyanka.jain@nxp.com>
>Cc: Jagan Teki <jagan@amarulasolutions.com>; Simon Glass
><sjg@chromium.org>; u-boot at lists.denx.de; linux-
>amarula at amarulasolutions.com
>Subject: Re: [PATCH 07/24] arm: Remove configs/P1010RDB-
>PA_36BIT_NAND_SECBOOT_defconfig board
>
>On Thu, May 28, 2020 at 07:05:38AM +0000, Priyanka Jain wrote:
>> >-----Original Message-----
>> >From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Jagan Teki
>> >Sent: Wednesday, May 27, 2020 10:17 PM
>> >To: Simon Glass <sjg@chromium.org>; Tom Rini <trini@konsulko.com>
>> >Cc: u-boot at lists.denx.de; linux-amarula at amarulasolutions.com; Jagan
>> >Teki <jagan@amarulasolutions.com>
>> >Subject: [PATCH 07/24] arm: Remove configs/P1010RDB-
>> >PA_36BIT_NAND_SECBOOT_defconfig board
>> >
>> >This board has not been converted to CONFIG_DM_SPI by the deadline.
>> >
>> >Remove it.
>> >
>> >Patch-cc: Qiang Zhao <qiang.zhao@nxp.com>
>> >Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
>> >---
>> > arch/powerpc/cpu/mpc85xx/Kconfig | 1 -
>> > board/freescale/p1010rdb/Kconfig | 14 -
>> > board/freescale/p1010rdb/MAINTAINERS | 33 -
>> > board/freescale/p1010rdb/Makefile | 24 -
>> > board/freescale/p1010rdb/README.P1010RDB-PA | 208 -----
>> > board/freescale/p1010rdb/README.P1010RDB-PB | 188 -----
>> > board/freescale/p1010rdb/ddr.c | 235 ------
>> > board/freescale/p1010rdb/law.c | 16 -
>> > board/freescale/p1010rdb/p1010rdb.c | 731 -----------------
>> > board/freescale/p1010rdb/spl.c | 114 ---
>> > board/freescale/p1010rdb/spl_minimal.c | 65 --
>> > board/freescale/p1010rdb/tlb.c | 90 --
>> > .../P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig | 63 --
>> > configs/P1010RDB-PA_36BIT_NAND_defconfig | 85 --
>> > .../P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig | 62 --
>> > configs/P1010RDB-PA_36BIT_NOR_defconfig | 67 --
>> > configs/P1010RDB-PA_36BIT_SDCARD_defconfig | 79 --
>> > ...010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig | 64 --
>> >configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig | 81 --
>> > configs/P1010RDB-PA_NAND_SECBOOT_defconfig | 62 --
>> > configs/P1010RDB-PA_NAND_defconfig | 84 --
>> > configs/P1010RDB-PA_NOR_SECBOOT_defconfig | 60 --
>> > configs/P1010RDB-PA_NOR_defconfig | 66 --
>> > configs/P1010RDB-PA_SDCARD_defconfig | 78 --
>> > .../P1010RDB-PA_SPIFLASH_SECBOOT_defconfig | 63 --
>> > configs/P1010RDB-PA_SPIFLASH_defconfig | 80 --
>> > .../P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig | 63 --
>> > configs/P1010RDB-PB_36BIT_NAND_defconfig | 85 --
>> > .../P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig | 62 --
>> > configs/P1010RDB-PB_36BIT_NOR_defconfig | 67 --
>> > configs/P1010RDB-PB_36BIT_SDCARD_defconfig | 79 --
>> > ...010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig | 64 --
>> >configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig | 81 --
>> > configs/P1010RDB-PB_NAND_SECBOOT_defconfig | 62 --
>> > configs/P1010RDB-PB_NAND_defconfig | 84 --
>> > configs/P1010RDB-PB_NOR_SECBOOT_defconfig | 61 --
>> > configs/P1010RDB-PB_NOR_defconfig | 66 --
>> > configs/P1010RDB-PB_SDCARD_defconfig | 78 --
>> > .../P1010RDB-PB_SPIFLASH_SECBOOT_defconfig | 63 --
>> > configs/P1010RDB-PB_SPIFLASH_defconfig | 80 --
>> > include/configs/P1010RDB.h | 766 ------------------
>> > 41 files changed, 4474 deletions(-)
>> > delete mode 100644 board/freescale/p1010rdb/Kconfig delete mode
>> >100644 board/freescale/p1010rdb/MAINTAINERS
>> > delete mode 100644 board/freescale/p1010rdb/Makefile delete mode
>> >100644 board/freescale/p1010rdb/README.P1010RDB-PA
>> > delete mode 100644 board/freescale/p1010rdb/README.P1010RDB-PB
>> > delete mode 100644 board/freescale/p1010rdb/ddr.c delete mode
>> >100644 board/freescale/p1010rdb/law.c delete mode 100644
>> >board/freescale/p1010rdb/p1010rdb.c
>> > delete mode 100644 board/freescale/p1010rdb/spl.c delete mode
>> >100644 board/freescale/p1010rdb/spl_minimal.c
>> > delete mode 100644 board/freescale/p1010rdb/tlb.c delete mode
>> >100644 configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig
>> > delete mode 100644 configs/P1010RDB-PA_36BIT_NAND_defconfig
>> > delete mode 100644 configs/P1010RDB-
>PA_36BIT_NOR_SECBOOT_defconfig
>> > delete mode 100644 configs/P1010RDB-PA_36BIT_NOR_defconfig
>> > delete mode 100644 configs/P1010RDB-PA_36BIT_SDCARD_defconfig
>> > delete mode 100644 configs/P1010RDB-
>> >PA_36BIT_SPIFLASH_SECBOOT_defconfig
>> > delete mode 100644 configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
>> > delete mode 100644 configs/P1010RDB-PA_NAND_SECBOOT_defconfig
>> > delete mode 100644 configs/P1010RDB-PA_NAND_defconfig
>> > delete mode 100644 configs/P1010RDB-PA_NOR_SECBOOT_defconfig
>> > delete mode 100644 configs/P1010RDB-PA_NOR_defconfig delete mode
>> >100644 configs/P1010RDB-PA_SDCARD_defconfig
>> > delete mode 100644 configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig
>> > delete mode 100644 configs/P1010RDB-PA_SPIFLASH_defconfig
>> > delete mode 100644 configs/P1010RDB-
>PB_36BIT_NAND_SECBOOT_defconfig
>> > delete mode 100644 configs/P1010RDB-PB_36BIT_NAND_defconfig
>> > delete mode 100644 configs/P1010RDB-
>PB_36BIT_NOR_SECBOOT_defconfig
>> > delete mode 100644 configs/P1010RDB-PB_36BIT_NOR_defconfig
>> > delete mode 100644 configs/P1010RDB-PB_36BIT_SDCARD_defconfig
>> > delete mode 100644 configs/P1010RDB-
>> >PB_36BIT_SPIFLASH_SECBOOT_defconfig
>> > delete mode 100644 configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
>> > delete mode 100644 configs/P1010RDB-PB_NAND_SECBOOT_defconfig
>> > delete mode 100644 configs/P1010RDB-PB_NAND_defconfig
>> > delete mode 100644 configs/P1010RDB-PB_NOR_SECBOOT_defconfig
>> > delete mode 100644 configs/P1010RDB-PB_NOR_defconfig delete mode
>> >100644 configs/P1010RDB-PB_SDCARD_defconfig
>> > delete mode 100644 configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig
>> > delete mode 100644 configs/P1010RDB-PB_SPIFLASH_defconfig
>> > delete mode 100644 include/configs/P1010RDB.h
>> >
>> <snip>
>> NXP plans to keep maintaining P1010RDB board. Please don't merge this
>patch .
>>
>> The espi series of patches for DM migration were in review since long, but
>could not be merged because of dependency.
>> NXP engineers are working on rebasing the DM espi migration series.
>>
>> http://patchwork.ozlabs.org/project/uboot/list/?series=127282&state=*
>> http://patchwork.ozlabs.org/project/uboot/list/?series=138873
>>
>> Nacked-by: Priyanka Jain <priyanka.jain@nxp.com>
>
>So, _this_ platform also runs in to:
>+(P1010RDB-PB_SDCARD) ===================== WARNING
>+======================
>+(P1010RDB-PB_SDCARD) This board does not use CONFIG_DM_MMC. Please
>+update
>+(P1010RDB-PB_SDCARD) the board to use CONFIG_DM_MMC before the
>v2019.04 release.
>+(P1010RDB-PB_SDCARD) Failure to update by the deadline may result in
>board removal.
>+(P1010RDB-PB_SDCARD) See doc/driver-model/migration.rst for more info.
>+(P1010RDB-PB_SDCARD)
>+====================================================
>
>So how far along is NXP on doing the needed conversions there? Thanks!
>
>--
>Tom
Some of the boards from above list can be removed but not all.
I will send patch to remove those boards.
Thanks
Priyanka
^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH 07/24] arm: Remove configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig board
2020-06-01 5:23 ` Priyanka Jain
@ 2020-06-01 11:43 ` Tom Rini
2020-06-02 7:18 ` Priyanka Jain
0 siblings, 1 reply; 59+ messages in thread
From: Tom Rini @ 2020-06-01 11:43 UTC (permalink / raw)
To: u-boot
On Mon, Jun 01, 2020 at 05:23:09AM +0000, Priyanka Jain wrote:
> >-----Original Message-----
> >From: Tom Rini <trini@konsulko.com>
> >Sent: Friday, May 29, 2020 1:32 AM
> >To: Priyanka Jain <priyanka.jain@nxp.com>
> >Cc: Jagan Teki <jagan@amarulasolutions.com>; Simon Glass
> ><sjg@chromium.org>; u-boot at lists.denx.de; linux-
> >amarula at amarulasolutions.com
> >Subject: Re: [PATCH 07/24] arm: Remove configs/P1010RDB-
> >PA_36BIT_NAND_SECBOOT_defconfig board
> >
> >On Thu, May 28, 2020 at 07:05:38AM +0000, Priyanka Jain wrote:
> >> >-----Original Message-----
> >> >From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Jagan Teki
> >> >Sent: Wednesday, May 27, 2020 10:17 PM
> >> >To: Simon Glass <sjg@chromium.org>; Tom Rini <trini@konsulko.com>
> >> >Cc: u-boot at lists.denx.de; linux-amarula at amarulasolutions.com; Jagan
> >> >Teki <jagan@amarulasolutions.com>
> >> >Subject: [PATCH 07/24] arm: Remove configs/P1010RDB-
> >> >PA_36BIT_NAND_SECBOOT_defconfig board
> >> >
> >> >This board has not been converted to CONFIG_DM_SPI by the deadline.
> >> >
> >> >Remove it.
> >> >
> >> >Patch-cc: Qiang Zhao <qiang.zhao@nxp.com>
> >> >Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> >> >---
> >> > arch/powerpc/cpu/mpc85xx/Kconfig | 1 -
> >> > board/freescale/p1010rdb/Kconfig | 14 -
> >> > board/freescale/p1010rdb/MAINTAINERS | 33 -
> >> > board/freescale/p1010rdb/Makefile | 24 -
> >> > board/freescale/p1010rdb/README.P1010RDB-PA | 208 -----
> >> > board/freescale/p1010rdb/README.P1010RDB-PB | 188 -----
> >> > board/freescale/p1010rdb/ddr.c | 235 ------
> >> > board/freescale/p1010rdb/law.c | 16 -
> >> > board/freescale/p1010rdb/p1010rdb.c | 731 -----------------
> >> > board/freescale/p1010rdb/spl.c | 114 ---
> >> > board/freescale/p1010rdb/spl_minimal.c | 65 --
> >> > board/freescale/p1010rdb/tlb.c | 90 --
> >> > .../P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig | 63 --
> >> > configs/P1010RDB-PA_36BIT_NAND_defconfig | 85 --
> >> > .../P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig | 62 --
> >> > configs/P1010RDB-PA_36BIT_NOR_defconfig | 67 --
> >> > configs/P1010RDB-PA_36BIT_SDCARD_defconfig | 79 --
> >> > ...010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig | 64 --
> >> >configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig | 81 --
> >> > configs/P1010RDB-PA_NAND_SECBOOT_defconfig | 62 --
> >> > configs/P1010RDB-PA_NAND_defconfig | 84 --
> >> > configs/P1010RDB-PA_NOR_SECBOOT_defconfig | 60 --
> >> > configs/P1010RDB-PA_NOR_defconfig | 66 --
> >> > configs/P1010RDB-PA_SDCARD_defconfig | 78 --
> >> > .../P1010RDB-PA_SPIFLASH_SECBOOT_defconfig | 63 --
> >> > configs/P1010RDB-PA_SPIFLASH_defconfig | 80 --
> >> > .../P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig | 63 --
> >> > configs/P1010RDB-PB_36BIT_NAND_defconfig | 85 --
> >> > .../P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig | 62 --
> >> > configs/P1010RDB-PB_36BIT_NOR_defconfig | 67 --
> >> > configs/P1010RDB-PB_36BIT_SDCARD_defconfig | 79 --
> >> > ...010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig | 64 --
> >> >configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig | 81 --
> >> > configs/P1010RDB-PB_NAND_SECBOOT_defconfig | 62 --
> >> > configs/P1010RDB-PB_NAND_defconfig | 84 --
> >> > configs/P1010RDB-PB_NOR_SECBOOT_defconfig | 61 --
> >> > configs/P1010RDB-PB_NOR_defconfig | 66 --
> >> > configs/P1010RDB-PB_SDCARD_defconfig | 78 --
> >> > .../P1010RDB-PB_SPIFLASH_SECBOOT_defconfig | 63 --
> >> > configs/P1010RDB-PB_SPIFLASH_defconfig | 80 --
> >> > include/configs/P1010RDB.h | 766 ------------------
> >> > 41 files changed, 4474 deletions(-)
> >> > delete mode 100644 board/freescale/p1010rdb/Kconfig delete mode
> >> >100644 board/freescale/p1010rdb/MAINTAINERS
> >> > delete mode 100644 board/freescale/p1010rdb/Makefile delete mode
> >> >100644 board/freescale/p1010rdb/README.P1010RDB-PA
> >> > delete mode 100644 board/freescale/p1010rdb/README.P1010RDB-PB
> >> > delete mode 100644 board/freescale/p1010rdb/ddr.c delete mode
> >> >100644 board/freescale/p1010rdb/law.c delete mode 100644
> >> >board/freescale/p1010rdb/p1010rdb.c
> >> > delete mode 100644 board/freescale/p1010rdb/spl.c delete mode
> >> >100644 board/freescale/p1010rdb/spl_minimal.c
> >> > delete mode 100644 board/freescale/p1010rdb/tlb.c delete mode
> >> >100644 configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig
> >> > delete mode 100644 configs/P1010RDB-PA_36BIT_NAND_defconfig
> >> > delete mode 100644 configs/P1010RDB-
> >PA_36BIT_NOR_SECBOOT_defconfig
> >> > delete mode 100644 configs/P1010RDB-PA_36BIT_NOR_defconfig
> >> > delete mode 100644 configs/P1010RDB-PA_36BIT_SDCARD_defconfig
> >> > delete mode 100644 configs/P1010RDB-
> >> >PA_36BIT_SPIFLASH_SECBOOT_defconfig
> >> > delete mode 100644 configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
> >> > delete mode 100644 configs/P1010RDB-PA_NAND_SECBOOT_defconfig
> >> > delete mode 100644 configs/P1010RDB-PA_NAND_defconfig
> >> > delete mode 100644 configs/P1010RDB-PA_NOR_SECBOOT_defconfig
> >> > delete mode 100644 configs/P1010RDB-PA_NOR_defconfig delete mode
> >> >100644 configs/P1010RDB-PA_SDCARD_defconfig
> >> > delete mode 100644 configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig
> >> > delete mode 100644 configs/P1010RDB-PA_SPIFLASH_defconfig
> >> > delete mode 100644 configs/P1010RDB-
> >PB_36BIT_NAND_SECBOOT_defconfig
> >> > delete mode 100644 configs/P1010RDB-PB_36BIT_NAND_defconfig
> >> > delete mode 100644 configs/P1010RDB-
> >PB_36BIT_NOR_SECBOOT_defconfig
> >> > delete mode 100644 configs/P1010RDB-PB_36BIT_NOR_defconfig
> >> > delete mode 100644 configs/P1010RDB-PB_36BIT_SDCARD_defconfig
> >> > delete mode 100644 configs/P1010RDB-
> >> >PB_36BIT_SPIFLASH_SECBOOT_defconfig
> >> > delete mode 100644 configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
> >> > delete mode 100644 configs/P1010RDB-PB_NAND_SECBOOT_defconfig
> >> > delete mode 100644 configs/P1010RDB-PB_NAND_defconfig
> >> > delete mode 100644 configs/P1010RDB-PB_NOR_SECBOOT_defconfig
> >> > delete mode 100644 configs/P1010RDB-PB_NOR_defconfig delete mode
> >> >100644 configs/P1010RDB-PB_SDCARD_defconfig
> >> > delete mode 100644 configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig
> >> > delete mode 100644 configs/P1010RDB-PB_SPIFLASH_defconfig
> >> > delete mode 100644 include/configs/P1010RDB.h
> >> >
> >> <snip>
> >> NXP plans to keep maintaining P1010RDB board. Please don't merge this
> >patch .
> >>
> >> The espi series of patches for DM migration were in review since long, but
> >could not be merged because of dependency.
> >> NXP engineers are working on rebasing the DM espi migration series.
> >>
> >> http://patchwork.ozlabs.org/project/uboot/list/?series=127282&state=*
> >> http://patchwork.ozlabs.org/project/uboot/list/?series=138873
> >>
> >> Nacked-by: Priyanka Jain <priyanka.jain@nxp.com>
> >
> >So, _this_ platform also runs in to:
> >+(P1010RDB-PB_SDCARD) ===================== WARNING
> >+======================
> >+(P1010RDB-PB_SDCARD) This board does not use CONFIG_DM_MMC. Please
> >+update
> >+(P1010RDB-PB_SDCARD) the board to use CONFIG_DM_MMC before the
> >v2019.04 release.
> >+(P1010RDB-PB_SDCARD) Failure to update by the deadline may result in
> >board removal.
> >+(P1010RDB-PB_SDCARD) See doc/driver-model/migration.rst for more info.
> >+(P1010RDB-PB_SDCARD)
> >+====================================================
> >
> >So how far along is NXP on doing the needed conversions there? Thanks!
> >
> >--
> >Tom
> Some of the boards from above list can be removed but not all.
> I will send patch to remove those boards.
Trimming the number of boards is good. But I started that list based on
what you said in this thread are boards NXP cares about. So unless
you're removing all of the ones I noted, my initial question stands.
Thanks!
--
Tom
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^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH 07/24] arm: Remove configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig board
2020-06-01 11:43 ` Tom Rini
@ 2020-06-02 7:18 ` Priyanka Jain
0 siblings, 0 replies; 59+ messages in thread
From: Priyanka Jain @ 2020-06-02 7:18 UTC (permalink / raw)
To: u-boot
>-----Original Message-----
>From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Tom Rini
>Sent: Monday, June 1, 2020 5:13 PM
>To: Priyanka Jain <priyanka.jain@nxp.com>
>Cc: Jagan Teki <jagan@amarulasolutions.com>; Simon Glass
><sjg@chromium.org>; u-boot at lists.denx.de; linux-
>amarula at amarulasolutions.com
>Subject: Re: [PATCH 07/24] arm: Remove configs/P1010RDB-
>PA_36BIT_NAND_SECBOOT_defconfig board
>
>On Mon, Jun 01, 2020 at 05:23:09AM +0000, Priyanka Jain wrote:
>> >-----Original Message-----
>> >From: Tom Rini <trini@konsulko.com>
>> >Sent: Friday, May 29, 2020 1:32 AM
>> >To: Priyanka Jain <priyanka.jain@nxp.com>
>> >Cc: Jagan Teki <jagan@amarulasolutions.com>; Simon Glass
>> ><sjg@chromium.org>; u-boot at lists.denx.de; linux-
>> >amarula at amarulasolutions.com
>> >Subject: Re: [PATCH 07/24] arm: Remove configs/P1010RDB-
>> >PA_36BIT_NAND_SECBOOT_defconfig board
>> >
>> >On Thu, May 28, 2020 at 07:05:38AM +0000, Priyanka Jain wrote:
>> >> >-----Original Message-----
>> >> >From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Jagan
>> >> >Teki
>> >> >Sent: Wednesday, May 27, 2020 10:17 PM
>> >> >To: Simon Glass <sjg@chromium.org>; Tom Rini <trini@konsulko.com>
>> >> >Cc: u-boot at lists.denx.de; linux-amarula at amarulasolutions.com;
>> >> >Jagan Teki <jagan@amarulasolutions.com>
>> >> >Subject: [PATCH 07/24] arm: Remove configs/P1010RDB-
>> >> >PA_36BIT_NAND_SECBOOT_defconfig board
>> >> >
>> >> >This board has not been converted to CONFIG_DM_SPI by the deadline.
>> >> >
>> >> >Remove it.
>> >> >
>> >> >Patch-cc: Qiang Zhao <qiang.zhao@nxp.com>
>> >> >Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
>> >> >---
>> >> > arch/powerpc/cpu/mpc85xx/Kconfig | 1 -
>> >> > board/freescale/p1010rdb/Kconfig | 14 -
>> >> > board/freescale/p1010rdb/MAINTAINERS | 33 -
>> >> > board/freescale/p1010rdb/Makefile | 24 -
>> >> > board/freescale/p1010rdb/README.P1010RDB-PA | 208 -----
>> >> > board/freescale/p1010rdb/README.P1010RDB-PB | 188 -----
>> >> > board/freescale/p1010rdb/ddr.c | 235 ------
>> >> > board/freescale/p1010rdb/law.c | 16 -
>> >> > board/freescale/p1010rdb/p1010rdb.c | 731 -----------------
>> >> > board/freescale/p1010rdb/spl.c | 114 ---
>> >> > board/freescale/p1010rdb/spl_minimal.c | 65 --
>> >> > board/freescale/p1010rdb/tlb.c | 90 --
>> >> > .../P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig | 63 --
>> >> > configs/P1010RDB-PA_36BIT_NAND_defconfig | 85 --
>> >> > .../P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig | 62 --
>> >> > configs/P1010RDB-PA_36BIT_NOR_defconfig | 67 --
>> >> > configs/P1010RDB-PA_36BIT_SDCARD_defconfig | 79 --
>> >> > ...010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig | 64 --
>> >> >configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig | 81 --
>> >> > configs/P1010RDB-PA_NAND_SECBOOT_defconfig | 62 --
>> >> > configs/P1010RDB-PA_NAND_defconfig | 84 --
>> >> > configs/P1010RDB-PA_NOR_SECBOOT_defconfig | 60 --
>> >> > configs/P1010RDB-PA_NOR_defconfig | 66 --
>> >> > configs/P1010RDB-PA_SDCARD_defconfig | 78 --
>> >> > .../P1010RDB-PA_SPIFLASH_SECBOOT_defconfig | 63 --
>> >> > configs/P1010RDB-PA_SPIFLASH_defconfig | 80 --
>> >> > .../P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig | 63 --
>> >> > configs/P1010RDB-PB_36BIT_NAND_defconfig | 85 --
>> >> > .../P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig | 62 --
>> >> > configs/P1010RDB-PB_36BIT_NOR_defconfig | 67 --
>> >> > configs/P1010RDB-PB_36BIT_SDCARD_defconfig | 79 --
>> >> > ...010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig | 64 --
>> >> >configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig | 81 --
>> >> > configs/P1010RDB-PB_NAND_SECBOOT_defconfig | 62 --
>> >> > configs/P1010RDB-PB_NAND_defconfig | 84 --
>> >> > configs/P1010RDB-PB_NOR_SECBOOT_defconfig | 61 --
>> >> > configs/P1010RDB-PB_NOR_defconfig | 66 --
>> >> > configs/P1010RDB-PB_SDCARD_defconfig | 78 --
>> >> > .../P1010RDB-PB_SPIFLASH_SECBOOT_defconfig | 63 --
>> >> > configs/P1010RDB-PB_SPIFLASH_defconfig | 80 --
>> >> > include/configs/P1010RDB.h | 766 ------------------
>> >> > 41 files changed, 4474 deletions(-) delete mode 100644
>> >> >board/freescale/p1010rdb/Kconfig delete mode
>> >> >100644 board/freescale/p1010rdb/MAINTAINERS
>> >> > delete mode 100644 board/freescale/p1010rdb/Makefile delete mode
>> >> >100644 board/freescale/p1010rdb/README.P1010RDB-PA
>> >> > delete mode 100644 board/freescale/p1010rdb/README.P1010RDB-PB
>> >> > delete mode 100644 board/freescale/p1010rdb/ddr.c delete mode
>> >> >100644 board/freescale/p1010rdb/law.c delete mode 100644
>> >> >board/freescale/p1010rdb/p1010rdb.c
>> >> > delete mode 100644 board/freescale/p1010rdb/spl.c delete mode
>> >> >100644 board/freescale/p1010rdb/spl_minimal.c
>> >> > delete mode 100644 board/freescale/p1010rdb/tlb.c delete mode
>> >> >100644 configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig
>> >> > delete mode 100644 configs/P1010RDB-PA_36BIT_NAND_defconfig
>> >> > delete mode 100644 configs/P1010RDB-
>> >PA_36BIT_NOR_SECBOOT_defconfig
>> >> > delete mode 100644 configs/P1010RDB-PA_36BIT_NOR_defconfig
>> >> > delete mode 100644 configs/P1010RDB-PA_36BIT_SDCARD_defconfig
>> >> > delete mode 100644 configs/P1010RDB-
>> >> >PA_36BIT_SPIFLASH_SECBOOT_defconfig
>> >> > delete mode 100644 configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
>> >> > delete mode 100644 configs/P1010RDB-PA_NAND_SECBOOT_defconfig
>> >> > delete mode 100644 configs/P1010RDB-PA_NAND_defconfig
>> >> > delete mode 100644 configs/P1010RDB-PA_NOR_SECBOOT_defconfig
>> >> > delete mode 100644 configs/P1010RDB-PA_NOR_defconfig delete mode
>> >> >100644 configs/P1010RDB-PA_SDCARD_defconfig
>> >> > delete mode 100644 configs/P1010RDB-
>PA_SPIFLASH_SECBOOT_defconfig
>> >> > delete mode 100644 configs/P1010RDB-PA_SPIFLASH_defconfig
>> >> > delete mode 100644 configs/P1010RDB-
>> >PB_36BIT_NAND_SECBOOT_defconfig
>> >> > delete mode 100644 configs/P1010RDB-PB_36BIT_NAND_defconfig
>> >> > delete mode 100644 configs/P1010RDB-
>> >PB_36BIT_NOR_SECBOOT_defconfig
>> >> > delete mode 100644 configs/P1010RDB-PB_36BIT_NOR_defconfig
>> >> > delete mode 100644 configs/P1010RDB-PB_36BIT_SDCARD_defconfig
>> >> > delete mode 100644 configs/P1010RDB-
>> >> >PB_36BIT_SPIFLASH_SECBOOT_defconfig
>> >> > delete mode 100644 configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
>> >> > delete mode 100644 configs/P1010RDB-PB_NAND_SECBOOT_defconfig
>> >> > delete mode 100644 configs/P1010RDB-PB_NAND_defconfig
>> >> > delete mode 100644 configs/P1010RDB-PB_NOR_SECBOOT_defconfig
>> >> > delete mode 100644 configs/P1010RDB-PB_NOR_defconfig delete mode
>> >> >100644 configs/P1010RDB-PB_SDCARD_defconfig
>> >> > delete mode 100644 configs/P1010RDB-
>PB_SPIFLASH_SECBOOT_defconfig
>> >> > delete mode 100644 configs/P1010RDB-PB_SPIFLASH_defconfig
>> >> > delete mode 100644 include/configs/P1010RDB.h
>> >> >
>> >> <snip>
>> >> NXP plans to keep maintaining P1010RDB board. Please don't merge
>> >> this
>> >patch .
>> >>
>> >> The espi series of patches for DM migration were in review since
>> >> long, but
>> >could not be merged because of dependency.
>> >> NXP engineers are working on rebasing the DM espi migration series.
>> >>
>> >> http://patchwork.ozlabs.org/project/uboot/list/?series=127282&state
>> >> =*
>> >> http://patchwork.ozlabs.org/project/uboot/list/?series=138873
>> >>
>> >> Nacked-by: Priyanka Jain <priyanka.jain@nxp.com>
>> >
>> >So, _this_ platform also runs in to:
>> >+(P1010RDB-PB_SDCARD) ===================== WARNING
>> >+======================
>> >+(P1010RDB-PB_SDCARD) This board does not use CONFIG_DM_MMC. Please
>> >+update
>> >+(P1010RDB-PB_SDCARD) the board to use CONFIG_DM_MMC before the
>> >v2019.04 release.
>> >+(P1010RDB-PB_SDCARD) Failure to update by the deadline may result in
>> >board removal.
>> >+(P1010RDB-PB_SDCARD) See doc/driver-model/migration.rst for more info.
>> >+(P1010RDB-PB_SDCARD)
>> >+====================================================
>> >
>> >So how far along is NXP on doing the needed conversions there? Thanks!
>> >
>> >--
>> >Tom
>> Some of the boards from above list can be removed but not all.
>> I will send patch to remove those boards.
>
>Trimming the number of boards is good. But I started that list based on what you
>said in this thread are boards NXP cares about. So unless you're removing all of
>the ones I noted, my initial question stands.
>Thanks!
>
>--
>Tom
Yes Tom,
We will either fix DM related issues or will remove the boards which NXP no longer wants to maintain.
I will take care of all Warnings pointed by you in different patches.
Regards
Priyanka
^ permalink raw reply [flat|nested] 59+ messages in thread
end of thread, other threads:[~2020-06-02 7:18 UTC | newest]
Thread overview: 59+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-05-27 16:46 [PATCH 00/24] spi: dm-conversion (part2) Jagan Teki
2020-05-27 16:46 ` [PATCH 01/24] arm: Remove configs/B4420QDS_NAND_defconfig board Jagan Teki
2020-05-28 7:00 ` Priyanka Jain
2020-05-27 16:46 ` [PATCH 02/24] arm: Remove configs/BSC9131RDB_NAND_SYSCLK100_defconfig board Jagan Teki
2020-05-28 4:17 ` Priyanka Jain
2020-05-27 16:46 ` [PATCH 03/24] arm: Remove configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig board Jagan Teki
2020-05-28 5:26 ` Priyanka Jain
2020-05-27 16:46 ` [PATCH 04/24] arm: Remove configs/C29XPCIE_NAND_defconfig board Jagan Teki
2020-05-28 5:28 ` Priyanka Jain
2020-05-27 16:46 ` [PATCH 05/24] arm: Remove configs/Cyrus_P5020_defconfig board Jagan Teki
2020-05-27 16:46 ` [PATCH 06/24] arm: Remove configs/MPC8536DS_36BIT_defconfig board Jagan Teki
2020-05-28 5:32 ` Priyanka Jain
2020-05-27 16:46 ` [PATCH 07/24] arm: Remove configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig board Jagan Teki
2020-05-28 7:05 ` Priyanka Jain
2020-05-28 20:02 ` Tom Rini
2020-06-01 5:23 ` Priyanka Jain
2020-06-01 11:43 ` Tom Rini
2020-06-02 7:18 ` Priyanka Jain
2020-05-27 16:46 ` [PATCH 08/24] arm: Remove configs/P1020MBG-PC_36BIT_SDCARD_defconfig board Jagan Teki
2020-05-28 7:07 ` Priyanka Jain
2020-05-28 20:14 ` Tom Rini
2020-05-28 20:32 ` Simon Glass
2020-05-28 20:44 ` Tom Rini
2020-05-29 12:36 ` Jagan Teki
2020-05-29 13:27 ` Tom Rini
2020-05-27 16:46 ` [PATCH 09/24] arm: Remove configs/P1022DS_36BIT_NAND_defconfig board Jagan Teki
2020-05-28 5:37 ` Priyanka Jain
2020-05-27 16:46 ` [PATCH 10/24] arm: Remove configs/P2041RDB_NAND_defconfig board Jagan Teki
2020-05-28 5:43 ` Priyanka Jain
2020-05-27 16:46 ` [PATCH 11/24] arm: Remove configs/P3041DS_NAND_SECURE_BOOT_defconfig board Jagan Teki
2020-05-28 7:09 ` Priyanka Jain
2020-05-28 20:37 ` Tom Rini
2020-05-27 16:46 ` [PATCH 12/24] arm: Remove configs/T1023RDB_NAND_defconfig board Jagan Teki
2020-05-28 7:08 ` Priyanka Jain
2020-05-28 20:18 ` Tom Rini
2020-05-27 16:46 ` [PATCH 13/24] arm: Remove configs/T1024QDS_DDR4_SECURE_BOOT_defconfig board Jagan Teki
2020-05-28 7:10 ` Priyanka Jain
2020-05-27 16:46 ` [PATCH 14/24] arm: Remove configs/T1040D4RDB_NAND_defconfig board Jagan Teki
2020-05-28 7:11 ` Priyanka Jain
2020-05-28 20:40 ` Tom Rini
2020-05-27 16:46 ` [PATCH 15/24] arm: Remove configs/T1040QDS_DDR4_defconfig board Jagan Teki
2020-05-28 7:01 ` Priyanka Jain
2020-05-27 16:46 ` [PATCH 16/24] arm: Remove configs/T2080QDS_NAND_defconfig board Jagan Teki
2020-05-28 7:14 ` Priyanka Jain
2020-05-28 20:42 ` Tom Rini
2020-05-27 16:46 ` [PATCH 17/24] arm: Remove configs/T2080RDB_NAND_defconfig board Jagan Teki
2020-05-28 7:02 ` Priyanka Jain
2020-05-27 16:46 ` [PATCH 18/24] arm: Remove configs/T4160QDS_NAND_defconfig board Jagan Teki
2020-05-28 7:15 ` Priyanka Jain
2020-05-27 16:46 ` [PATCH 19/24] arm: Remove configs/T4160RDB_defconfig board Jagan Teki
2020-05-28 7:04 ` Priyanka Jain
2020-05-27 16:46 ` [PATCH 20/24] arm: Remove configs/TWR-P1025_defconfig board Jagan Teki
2020-05-28 7:12 ` Priyanka Jain
2020-05-27 18:38 ` [PATCH 00/24] spi: dm-conversion (part2) Joakim Tjernlund
2020-05-27 18:49 ` Jagan Teki
2020-05-28 0:56 ` Bin Meng
2020-05-28 9:46 ` Jagan Teki
2020-05-28 9:44 ` Priyanka Jain
2020-05-28 9:51 ` Jagan Teki
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