From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.1 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 830D3C433DF for ; Thu, 28 May 2020 02:18:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5CFAB208DB for ; Thu, 28 May 2020 02:18:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1590632312; bh=jvukpDLIP9hjWGOlL+1CqDEZNqUL7PyqfBDQP6F0TRo=; h=Date:From:To:List-Id:Cc:Subject:References:In-Reply-To:List-ID: From; b=jme5A0ZYUkqxJcZg+OF/8urxwYCSWejlNBP5nUuQM2EDSiY4DCg29yAMVN5gzuqWI V+vl5mBEgdtXyxxCkYUicbk9kguD12g04eSAtOLxN+A3NcTmb/01FqlIrINbQ8oosn Ep32D3mrjyzfGTsxX3wHx36NE1tKWz9Zr9fnHRLU= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726701AbgE1CS3 (ORCPT ); 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Wed, 27 May 2020 19:18:27 -0700 (PDT) Received: from xps15 ([64.188.179.252]) by smtp.gmail.com with ESMTPSA id s71sm2536741ilc.32.2020.05.27.19.18.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 May 2020 19:18:27 -0700 (PDT) Received: (nullmailer pid 3229541 invoked by uid 1000); Thu, 28 May 2020 02:18:26 -0000 Date: Wed, 27 May 2020 20:18:26 -0600 From: Rob Herring To: Lars Povlsen List-Id: Cc: SoC Team , Arnd Bergmann , Stephen Boyd , Linus Walleij , Steen Hegelund , Microchip Linux Driver Support , Olof Johansson , Michael Turquette , devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Alexandre Belloni Subject: Re: [PATCH 10/14] dt-bindings: clock: sparx5: Add Sparx5 SoC DPLL clock Message-ID: <20200528021826.GA3221035@bogus> References: <20200513125532.24585-1-lars.povlsen@microchip.com> <20200513125532.24585-11-lars.povlsen@microchip.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200513125532.24585-11-lars.povlsen@microchip.com> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org On Wed, May 13, 2020 at 02:55:28PM +0200, Lars Povlsen wrote: > This add the DT bindings documentation for the Sparx5 SoC DPLL clock > > Reviewed-by: Alexandre Belloni > Signed-off-by: Lars Povlsen > --- > .../bindings/clock/microchip,sparx5-dpll.yaml | 46 +++++++++++++++++++ > 1 file changed, 46 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/microchip,sparx5-dpll.yaml > > diff --git a/Documentation/devicetree/bindings/clock/microchip,sparx5-dpll.yaml b/Documentation/devicetree/bindings/clock/microchip,sparx5-dpll.yaml > new file mode 100644 > index 0000000000000..594007d8fc59a > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/microchip,sparx5-dpll.yaml > @@ -0,0 +1,46 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/microchip,sparx5-dpll.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Microchip Sparx5 DPLL Clock > + > +maintainers: > + - Lars Povlsen > + > +description: | > + The Sparx5 DPLL clock controller generates and supplies clock to > + various peripherals within the SoC. > + > + This binding uses common clock bindings > + [1] Documentation/devicetree/bindings/clock/clock-bindings.txt > + > +properties: > + compatible: > + const: microchip,sparx5-dpll > + > + reg: > + items: > + - description: dpll registers For a single entry, just: maxItems: 1 > + > + '#clock-cells': > + const: 1 > + > +required: > + - compatible > + - reg > + - '#clock-cells' > + > +additionalProperties: false > + > +examples: > + # Clock provider for eMMC: > + - | > + clks: clks@61110000c { clock-controller@1110000c { > + compatible = "microchip,sparx5-dpll"; > + #clock-cells = <1>; > + reg = <0x1110000c 0x24>; Looks like this is a sub-block in some other h/w block. What's the parent device? That should be described and this should be part of it either as a single node or a child node. Without a complete view of what this block has I can't provide any guidance. Rob From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7490AC433DF for ; Thu, 28 May 2020 02:18:34 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3E83B2100A for ; Thu, 28 May 2020 02:18:34 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="ojCLC7kN" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3E83B2100A Authentication-Results: mail.kernel.org; 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Wed, 27 May 2020 19:18:27 -0700 (PDT) Received: from xps15 ([64.188.179.252]) by smtp.gmail.com with ESMTPSA id s71sm2536741ilc.32.2020.05.27.19.18.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 May 2020 19:18:27 -0700 (PDT) Received: (nullmailer pid 3229541 invoked by uid 1000); Thu, 28 May 2020 02:18:26 -0000 Date: Wed, 27 May 2020 20:18:26 -0600 From: Rob Herring To: Lars Povlsen Subject: Re: [PATCH 10/14] dt-bindings: clock: sparx5: Add Sparx5 SoC DPLL clock Message-ID: <20200528021826.GA3221035@bogus> References: <20200513125532.24585-1-lars.povlsen@microchip.com> <20200513125532.24585-11-lars.povlsen@microchip.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200513125532.24585-11-lars.povlsen@microchip.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200527_191829_494153_C0497952 X-CRM114-Status: GOOD ( 15.63 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , List-Id: Cc: devicetree@vger.kernel.org, Alexandre Belloni , Arnd Bergmann , linux-gpio@vger.kernel.org, Stephen Boyd , Steen Hegelund , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Microchip Linux Driver Support , Michael Turquette , SoC Team , Olof Johansson , Linus Walleij , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, May 13, 2020 at 02:55:28PM +0200, Lars Povlsen wrote: > This add the DT bindings documentation for the Sparx5 SoC DPLL clock > > Reviewed-by: Alexandre Belloni > Signed-off-by: Lars Povlsen > --- > .../bindings/clock/microchip,sparx5-dpll.yaml | 46 +++++++++++++++++++ > 1 file changed, 46 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/microchip,sparx5-dpll.yaml > > diff --git a/Documentation/devicetree/bindings/clock/microchip,sparx5-dpll.yaml b/Documentation/devicetree/bindings/clock/microchip,sparx5-dpll.yaml > new file mode 100644 > index 0000000000000..594007d8fc59a > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/microchip,sparx5-dpll.yaml > @@ -0,0 +1,46 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/microchip,sparx5-dpll.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Microchip Sparx5 DPLL Clock > + > +maintainers: > + - Lars Povlsen > + > +description: | > + The Sparx5 DPLL clock controller generates and supplies clock to > + various peripherals within the SoC. > + > + This binding uses common clock bindings > + [1] Documentation/devicetree/bindings/clock/clock-bindings.txt > + > +properties: > + compatible: > + const: microchip,sparx5-dpll > + > + reg: > + items: > + - description: dpll registers For a single entry, just: maxItems: 1 > + > + '#clock-cells': > + const: 1 > + > +required: > + - compatible > + - reg > + - '#clock-cells' > + > +additionalProperties: false > + > +examples: > + # Clock provider for eMMC: > + - | > + clks: clks@61110000c { clock-controller@1110000c { > + compatible = "microchip,sparx5-dpll"; > + #clock-cells = <1>; > + reg = <0x1110000c 0x24>; Looks like this is a sub-block in some other h/w block. What's the parent device? That should be described and this should be part of it either as a single node or a child node. Without a complete view of what this block has I can't provide any guidance. Rob _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel