On Mon, Jun 01, 2020 at 05:01:08PM +0300, Dan Carpenter wrote: > Hi Stanislav, > > url: https://github.com/0day-ci/linux/commits/Stanislav-Lisovskiy/drm-i915-Fix-wrong-CDCLK-adjustment-changes/20200526-180642 > base: git://anongit.freedesktop.org/drm/drm-tip drm-tip > config: i386-randconfig-m021-20200531 (attached as .config) > compiler: gcc-9 (Debian 9.3.0-13) 9.3.0 > > If you fix the issue, kindly add following tag as appropriate > Reported-by: kbuild test robot > Reported-by: Dan Carpenter > > smatch warnings: > drivers/gpu/drm/i915/display/intel_bw.c:453 skl_bw_calc_min_cdclk() error: uninitialized symbol 'pipe'. > > # https://github.com/0day-ci/linux/commit/21b0324886122a396687d977d67eb6ce3caf2b17 > git remote add linux-review https://github.com/0day-ci/linux > git remote update linux-review > git checkout 21b0324886122a396687d977d67eb6ce3caf2b17 > vim +/pipe +453 drivers/gpu/drm/i915/display/intel_bw.c > > 366b6200f76e0f Jani Nikula 2019-08-06 430 > cd19154608610a Stanislav Lisovskiy 2020-05-20 431 int skl_bw_calc_min_cdclk(struct intel_atomic_state *state) > cd19154608610a Stanislav Lisovskiy 2020-05-20 432 { > cd19154608610a Stanislav Lisovskiy 2020-05-20 433 struct drm_i915_private *dev_priv = to_i915(state->base.dev); > cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 434 struct intel_bw_state *new_bw_state = NULL; > cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 435 struct intel_bw_state *old_bw_state = NULL; > cd19154608610a Stanislav Lisovskiy 2020-05-20 436 const struct intel_crtc_state *crtc_state; > cd19154608610a Stanislav Lisovskiy 2020-05-20 437 struct intel_crtc *crtc; > cd19154608610a Stanislav Lisovskiy 2020-05-20 438 int max_bw = 0; > cd19154608610a Stanislav Lisovskiy 2020-05-20 439 int slice_id; > 21b0324886122a Stanislav Lisovskiy 2020-05-26 440 enum pipe pipe; > cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 441 int i; > cd19154608610a Stanislav Lisovskiy 2020-05-20 442 > cd19154608610a Stanislav Lisovskiy 2020-05-20 443 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { > cd19154608610a Stanislav Lisovskiy 2020-05-20 444 enum plane_id plane_id; > cd19154608610a Stanislav Lisovskiy 2020-05-20 445 struct intel_dbuf_bw *crtc_bw; > cd19154608610a Stanislav Lisovskiy 2020-05-20 446 > cd19154608610a Stanislav Lisovskiy 2020-05-20 447 new_bw_state = intel_atomic_get_bw_state(state); > cd19154608610a Stanislav Lisovskiy 2020-05-20 448 if (IS_ERR(new_bw_state)) > cd19154608610a Stanislav Lisovskiy 2020-05-20 449 return PTR_ERR(new_bw_state); > cd19154608610a Stanislav Lisovskiy 2020-05-20 450 > 21b0324886122a Stanislav Lisovskiy 2020-05-26 451 old_bw_state = intel_atomic_get_old_bw_state(state); > 21b0324886122a Stanislav Lisovskiy 2020-05-26 452 > 21b0324886122a Stanislav Lisovskiy 2020-05-26 @453 crtc_bw = &new_bw_state->dbuf_bw[pipe]; > ^^^^ > Not initialized. Probably "i" was intended? Ahh.. Rather silly typo - it should be crtc->pipe. Thanks for spotting. Stan > > cd19154608610a Stanislav Lisovskiy 2020-05-20 454 > cd19154608610a Stanislav Lisovskiy 2020-05-20 455 memset(&crtc_bw->used_bw, 0, sizeof(crtc_bw->used_bw)); > cd19154608610a Stanislav Lisovskiy 2020-05-20 456 > cd19154608610a Stanislav Lisovskiy 2020-05-20 457 for_each_plane_id_on_crtc(crtc, plane_id) { > cd19154608610a Stanislav Lisovskiy 2020-05-20 458 const struct skl_ddb_entry *plane_alloc = > cd19154608610a Stanislav Lisovskiy 2020-05-20 459 &crtc_state->wm.skl.plane_ddb_y[plane_id]; > cd19154608610a Stanislav Lisovskiy 2020-05-20 460 const struct skl_ddb_entry *uv_plane_alloc = > cd19154608610a Stanislav Lisovskiy 2020-05-20 461 &crtc_state->wm.skl.plane_ddb_uv[plane_id]; > cd19154608610a Stanislav Lisovskiy 2020-05-20 462 unsigned int data_rate = crtc_state->data_rate[plane_id]; > cd19154608610a Stanislav Lisovskiy 2020-05-20 463 unsigned int dbuf_mask = 0; > cd19154608610a Stanislav Lisovskiy 2020-05-20 464 > cd19154608610a Stanislav Lisovskiy 2020-05-20 465 dbuf_mask |= skl_ddb_dbuf_slice_mask(dev_priv, plane_alloc); > cd19154608610a Stanislav Lisovskiy 2020-05-20 466 dbuf_mask |= skl_ddb_dbuf_slice_mask(dev_priv, uv_plane_alloc); > cd19154608610a Stanislav Lisovskiy 2020-05-20 467 > cd19154608610a Stanislav Lisovskiy 2020-05-20 468 /* > cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 469 * FIXME: To calculate that more properly we probably > cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 470 * need to to split per plane data_rate into data_rate_y > cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 471 * and data_rate_uv for multiplanar formats in order not > cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 472 * to get accounted those twice if they happen to reside > cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 473 * on different slices. > cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 474 * However for pre-icl this would work anyway because > cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 475 * we have only single slice and for icl+ uv plane has > cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 476 * non-zero data rate. > cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 477 * So in worst case those calculation are a bit > cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 478 * pessimistic, which shouldn't pose any significant > cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 479 * problem anyway. > cd19154608610a Stanislav Lisovskiy 2020-05-20 480 */ > cd19154608610a Stanislav Lisovskiy 2020-05-20 481 for_each_dbuf_slice_in_mask(slice_id, dbuf_mask) > cd19154608610a Stanislav Lisovskiy 2020-05-20 482 crtc_bw->used_bw[slice_id] += data_rate; > cd19154608610a Stanislav Lisovskiy 2020-05-20 483 } > 21b0324886122a Stanislav Lisovskiy 2020-05-26 484 } > 21b0324886122a Stanislav Lisovskiy 2020-05-26 485 > 21b0324886122a Stanislav Lisovskiy 2020-05-26 486 if (!old_bw_state) > 21b0324886122a Stanislav Lisovskiy 2020-05-26 487 return 0; > 21b0324886122a Stanislav Lisovskiy 2020-05-26 488 > 21b0324886122a Stanislav Lisovskiy 2020-05-26 489 for_each_pipe(dev_priv, pipe) { > 21b0324886122a Stanislav Lisovskiy 2020-05-26 490 struct intel_dbuf_bw *crtc_bw; > 21b0324886122a Stanislav Lisovskiy 2020-05-26 491 > 21b0324886122a Stanislav Lisovskiy 2020-05-26 492 crtc_bw = &new_bw_state->dbuf_bw[pipe]; > cd19154608610a Stanislav Lisovskiy 2020-05-20 493 > cd19154608610a Stanislav Lisovskiy 2020-05-20 494 for_each_dbuf_slice(slice_id) { > cd19154608610a Stanislav Lisovskiy 2020-05-20 495 /* > cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 496 * Current experimental observations show that contrary > cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 497 * to BSpec we get underruns once we exceed 64 * CDCLK > cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 498 * for slices in total. > cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 499 * As a temporary measure in order not to keep CDCLK > cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 500 * bumped up all the time we calculate CDCLK according > cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 501 * to this formula for overall bw consumed by slices. > cd19154608610a Stanislav Lisovskiy 2020-05-20 502 */ > cd19154608610a Stanislav Lisovskiy 2020-05-20 503 max_bw += crtc_bw->used_bw[slice_id]; > cd19154608610a Stanislav Lisovskiy 2020-05-20 504 } > cd19154608610a Stanislav Lisovskiy 2020-05-20 505 } > cd19154608610a Stanislav Lisovskiy 2020-05-20 506 > 21b0324886122a Stanislav Lisovskiy 2020-05-26 507 new_bw_state->min_cdclk = max_bw / 64; > cd19154608610a Stanislav Lisovskiy 2020-05-20 508 > cd19154608610a Stanislav Lisovskiy 2020-05-20 509 if (new_bw_state->min_cdclk != old_bw_state->min_cdclk) { > cd19154608610a Stanislav Lisovskiy 2020-05-20 510 int ret = intel_atomic_lock_global_state(&new_bw_state->base); > cd19154608610a Stanislav Lisovskiy 2020-05-20 511 > cd19154608610a Stanislav Lisovskiy 2020-05-20 512 if (ret) > cd19154608610a Stanislav Lisovskiy 2020-05-20 513 return ret; > cd19154608610a Stanislav Lisovskiy 2020-05-20 514 } > cd19154608610a Stanislav Lisovskiy 2020-05-20 515 > cd19154608610a Stanislav Lisovskiy 2020-05-20 516 return 0; > cd19154608610a Stanislav Lisovskiy 2020-05-20 517 } > > --- > 0-DAY CI Kernel Test Service, Intel Corporation > https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx