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[165.204.84.11]) by smtp.gmail.com with ESMTPSA id w10sm106849qtc.15.2020.06.01.11.21.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Jun 2020 11:21:49 -0700 (PDT) From: Alex Deucher X-Google-Original-From: Alex Deucher To: amd-gfx@lists.freedesktop.org Subject: [PATCH 124/207] drm/amd/powerplay: enable MM DPM PG for sienna_cichlid (v2) Date: Mon, 1 Jun 2020 14:19:31 -0400 Message-Id: <20200601182054.1267858-35-alexander.deucher@amd.com> X-Mailer: git-send-email 2.25.4 In-Reply-To: <20200601182054.1267858-1-alexander.deucher@amd.com> References: <20200601182054.1267858-1-alexander.deucher@amd.com> MIME-Version: 1.0 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alex Deucher , Likun Gao , Kenneth Feng Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" From: Likun Gao Enable VCN dpm set for sienna_cichlid. Enable JPEG dpm set for sienna_cichlid. v2: squash in BACO fix (Kenneth) Signed-off-by: Likun Gao Reviewed-by: Kenneth Feng Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/inc/smu_types.h | 1 + .../drm/amd/powerplay/sienna_cichlid_ppt.c | 51 +++++++++++++++++-- 2 files changed, 48 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_types.h b/drivers/gpu/drm/amd/powerplay/inc/smu_types.h index 1ef791f36888..3efadf2cff9c 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/smu_types.h +++ b/drivers/gpu/drm/amd/powerplay/inc/smu_types.h @@ -247,6 +247,7 @@ enum smu_clk_type { __SMU_DUMMY_MAP(FW_DSTATE), \ __SMU_DUMMY_MAP(BACO), \ __SMU_DUMMY_MAP(VCN_PG), \ + __SMU_DUMMY_MAP(MM_DPM_PG), \ __SMU_DUMMY_MAP(JPEG_PG), \ __SMU_DUMMY_MAP(USB_PG), \ __SMU_DUMMY_MAP(RSMU_SMN_CG), \ diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c index 2d844569ed8d..80a099877a68 100644 --- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c @@ -141,6 +141,7 @@ static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_feature_mask_map[SMU_FEAT FEA_MAP(FW_DSTATE), FEA_MAP(GFXOFF), FEA_MAP(BACO), + FEA_MAP(MM_DPM_PG), FEA_MAP(RSMU_SMN_CG), FEA_MAP(PPT), FEA_MAP(TDC), @@ -327,6 +328,10 @@ sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu, if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK) *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT); + if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN || + smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG) + *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_PG_BIT); + return 0; } @@ -485,15 +490,21 @@ static int sienna_cichlid_dpm_set_uvd_enable(struct smu_context *smu, bool enabl if (enable) { /* vcn dpm on is a prerequisite for vcn power gate messages */ - if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) { - ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1, NULL); + if (smu_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) { + ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL); + if (ret) + return ret; + ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0x10000, NULL); if (ret) return ret; } power_gate->vcn_gated = false; } else { - if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) { - ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownVcn, NULL); + if (smu_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) { + ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn, 0, NULL); + if (ret) + return ret; + ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn, 0x10000, NULL); if (ret) return ret; } @@ -503,6 +514,37 @@ static int sienna_cichlid_dpm_set_uvd_enable(struct smu_context *smu, bool enabl return ret; } +static int sienna_cichlid_dpm_set_jpeg_enable(struct smu_context *smu, bool enable) +{ + struct smu_power_context *smu_power = &smu->smu_power; + struct smu_power_gate *power_gate = &smu_power->power_gate; + int ret = 0; + + if (enable) { + if (smu_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) { + ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL); + if (ret) + return ret; + ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0x10000, NULL); + if (ret) + return ret; + } + power_gate->jpeg_gated = false; + } else { + if (smu_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) { + ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL); + if (ret) + return ret; + ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0x10000, NULL); + if (ret) + return ret; + } + power_gate->jpeg_gated = true; + } + + return ret; +} + static int sienna_cichlid_get_current_clk_freq_by_table(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *value) @@ -2214,6 +2256,7 @@ static const struct pptable_funcs sienna_cichlid_ppt_funcs = { .get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask, .set_default_dpm_table = sienna_cichlid_set_default_dpm_table, .dpm_set_uvd_enable = sienna_cichlid_dpm_set_uvd_enable, + .dpm_set_jpeg_enable = sienna_cichlid_dpm_set_jpeg_enable, .get_current_clk_freq_by_table = sienna_cichlid_get_current_clk_freq_by_table, .print_clk_levels = sienna_cichlid_print_clk_levels, .force_clk_levels = sienna_cichlid_force_clk_levels, -- 2.25.4 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx