All of lore.kernel.org
 help / color / mirror / Atom feed
From: Alex Deucher <alexdeucher@gmail.com>
To: amd-gfx@lists.freedesktop.org
Cc: Alex Deucher <alexander.deucher@amd.com>, Le Ma <le.ma@amd.com>,
	Hawking Zhang <Hawking.Zhang@amd.com>
Subject: [PATCH 129/207] drm/amdgpu/mes: update mes fw api
Date: Mon,  1 Jun 2020 14:19:36 -0400	[thread overview]
Message-ID: <20200601182054.1267858-40-alexander.deucher@amd.com> (raw)
In-Reply-To: <20200601182054.1267858-1-alexander.deucher@amd.com>

From: Le Ma <le.ma@amd.com>

Update mes_api_def.h to match the latest mes fw.

v2: clean up coding style based on kernel standards:
  - fix indentation and alignment
  - break long lines
  - put the opening brace last on the line
  - remove unnecessary blank line and space
  - replace uint(32|64) with standard uint(32|64)_t

Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/mes_api_def.h | 644 ++++++++++++-----------
 1 file changed, 341 insertions(+), 303 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/mes_api_def.h b/drivers/gpu/drm/amd/amdgpu/mes_api_def.h
index da040845de00..3f4fca5fd1da 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_api_def.h
+++ b/drivers/gpu/drm/amd/amdgpu/mes_api_def.h
@@ -26,95 +26,88 @@
 
 #pragma pack(push, 4)
 
-typedef uint32_t uint32;
-typedef uint64_t uint64;
-
 #define MES_API_VERSION 1
 
-//Driver submits one API(cmd) as a single Frame and this command size is same for all API
-//to ease the debugging and parsing of ring buffer.
-enum {API_FRAME_SIZE_IN_DWORDS = 64};
+/* Driver submits one API(cmd) as a single Frame and this command size is same
+ * for all API to ease the debugging and parsing of ring buffer.
+ */
+enum { API_FRAME_SIZE_IN_DWORDS = 64 };
 
-//To avoid command in scheduler context to be overwritten whenenver mutilple interrupts come in, 
-//this creates another queue
-enum {API_NUMBER_OF_COMMAND_MAX   = 32};
+/* To avoid command in scheduler context to be overwritten whenenver mutilple
+ * interrupts come in, this creates another queue.
+ */
+enum { API_NUMBER_OF_COMMAND_MAX = 32 };
 
-enum MES_API_TYPE
-{
-    MES_API_TYPE_SCHEDULER = 1,
-    MES_API_TYPE_MAX
+enum MES_API_TYPE {
+	MES_API_TYPE_SCHEDULER = 1,
+	MES_API_TYPE_MAX
 };
 
-enum MES_SCH_API_OPCODE
-{
-    MES_SCH_API_SET_HW_RSRC                  = 0,
-    MES_SCH_API_SET_SCHEDULING_CONFIG        = 1, //agreegated db, quantums, etc
-    MES_SCH_API_ADD_QUEUE                    = 2,
-    MES_SCH_API_REMOVE_QUEUE                 = 3,
-    MES_SCH_API_PERFORM_YIELD                = 4,
-    MES_SCH_API_SET_GANG_PRIORITY_LEVEL      = 5, //For windows GANG = Context
-    MES_SCH_API_SUSPEND                      = 6,
-    MES_SCH_API_RESUME                       = 7,
-    MES_SCH_API_RESET                        = 8,
-    MES_SCH_API_SET_LOG_BUFFER               = 9,
-    MES_SCH_API_CHANGE_GANG_PRORITY          = 10,
-    MES_SCH_API_QUERY_SCHEDULER_STATUS       = 11,
-    MES_SCH_API_PROGRAM_GDS                  = 12,
-    MES_SCH_API_MAX                          = 0xFF
+enum MES_SCH_API_OPCODE {
+	MES_SCH_API_SET_HW_RSRC			= 0,
+	MES_SCH_API_SET_SCHEDULING_CONFIG	= 1, /* agreegated db, quantums, etc */
+	MES_SCH_API_ADD_QUEUE			= 2,
+	MES_SCH_API_REMOVE_QUEUE		= 3,
+	MES_SCH_API_PERFORM_YIELD		= 4,
+	MES_SCH_API_SET_GANG_PRIORITY_LEVEL	= 5,
+	MES_SCH_API_SUSPEND			= 6,
+	MES_SCH_API_RESUME			= 7,
+	MES_SCH_API_RESET			= 8,
+	MES_SCH_API_SET_LOG_BUFFER		= 9,
+	MES_SCH_API_CHANGE_GANG_PRORITY		= 10,
+	MES_SCH_API_QUERY_SCHEDULER_STATUS	= 11,
+	MES_SCH_API_PROGRAM_GDS			= 12,
+	MES_SCH_API_SET_DEBUG_VMID		= 13,
+	MES_SCH_API_MISC			= 14,
+	MES_SCH_API_MAX				= 0xFF
 };
 
-union MES_API_HEADER
-{
-    struct
-    {
-        uint32 type	: 4; // 0 - Invalid; 1 - Scheduling; 2 - TBD
-        uint32 opcode   : 8;
-        uint32 dwsize   : 8; //including header
-        uint32 reserved : 12;
-    };
-
-    uint32 u32All;
+union MES_API_HEADER {
+	struct {
+		uint32_t type		: 4; /* 0 - Invalid; 1 - Scheduling; 2 - TBD */
+		uint32_t opcode		: 8;
+		uint32_t dwsize		: 8; /* including header */
+		uint32_t reserved	: 12;
+	};
+
+	uint32_t	u32All;
 };
 
-enum MES_AMD_PRIORITY_LEVEL
-{
-    AMD_PRIORITY_LEVEL_LOW       = 0,
-    AMD_PRIORITY_LEVEL_NORMAL    = 1,
-    AMD_PRIORITY_LEVEL_MEDIUM    = 2,
-    AMD_PRIORITY_LEVEL_HIGH      = 3,
-    AMD_PRIORITY_LEVEL_REALTIME  = 4,
-    AMD_PRIORITY_NUM_LEVELS
+enum MES_AMD_PRIORITY_LEVEL {
+	AMD_PRIORITY_LEVEL_LOW		= 0,
+	AMD_PRIORITY_LEVEL_NORMAL	= 1,
+	AMD_PRIORITY_LEVEL_MEDIUM	= 2,
+	AMD_PRIORITY_LEVEL_HIGH		= 3,
+	AMD_PRIORITY_LEVEL_REALTIME	= 4,
+	AMD_PRIORITY_NUM_LEVELS
 };
 
-enum MES_QUEUE_TYPE
-{
-    MES_QUEUE_TYPE_GFX,
-    MES_QUEUE_TYPE_COMPUTE,
-    MES_QUEUE_TYPE_SDMA,
-    MES_QUEUE_TYPE_MAX,
+enum MES_QUEUE_TYPE {
+	MES_QUEUE_TYPE_GFX,
+	MES_QUEUE_TYPE_COMPUTE,
+	MES_QUEUE_TYPE_SDMA,
+	MES_QUEUE_TYPE_MAX,
 };
 
-struct MES_API_STATUS
-{
-    uint64 api_completion_fence_addr;
-    uint64 api_completion_fence_value;
+struct MES_API_STATUS {
+	uint64_t	api_completion_fence_addr;
+	uint64_t	api_completion_fence_value;
 };
 
 enum { MAX_COMPUTE_PIPES = 8 };
-enum { MAX_GFX_PIPES	 = 2 };
-enum { MAX_SDMA_PIPES    = 2 };
+enum { MAX_GFX_PIPES = 2 };
+enum { MAX_SDMA_PIPES = 2 };
 
-enum { MAX_COMPUTE_HQD_PER_PIPE     = 8 };
-enum { MAX_GFX_HQD_PER_PIPE         = 8 };
-enum { MAX_SDMA_HQD_PER_PIPE        = 10 };
+enum { MAX_COMPUTE_HQD_PER_PIPE = 8 };
+enum { MAX_GFX_HQD_PER_PIPE = 8 };
+enum { MAX_SDMA_HQD_PER_PIPE = 10 };
 
 enum { MAX_QUEUES_IN_A_GANG = 8 };
 
-enum VM_HUB_TYPE
-{
-    VM_HUB_TYPE_GC = 0,
-    VM_HUB_TYPE_MM = 1,
-    VM_HUB_TYPE_MAX,
+enum VM_HUB_TYPE {
+	VM_HUB_TYPE_GC = 0,
+	VM_HUB_TYPE_MM = 1,
+	VM_HUB_TYPE_MAX,
 };
 
 enum { VMID_INVALID = 0xffff };
@@ -122,283 +115,328 @@ enum { VMID_INVALID = 0xffff };
 enum { MAX_VMID_GCHUB = 16 };
 enum { MAX_VMID_MMHUB = 16 };
 
-enum MES_LOG_OPERATION
-{
-    MES_LOG_OPERATION_CONTEXT_STATE_CHANGE = 0
+enum MES_LOG_OPERATION {
+	MES_LOG_OPERATION_CONTEXT_STATE_CHANGE = 0
 };
 
-enum MES_LOG_CONTEXT_STATE
-{
-    MES_LOG_CONTEXT_STATE_IDLE = 0,
-    MES_LOG_CONTEXT_STATE_RUNNING = 1,
-    MES_LOG_CONTEXT_STATE_READY = 2,
-    MES_LOG_CONTEXT_STATE_READY_STANDBY = 3,
+enum MES_LOG_CONTEXT_STATE {
+	MES_LOG_CONTEXT_STATE_IDLE		= 0,
+	MES_LOG_CONTEXT_STATE_RUNNING		= 1,
+	MES_LOG_CONTEXT_STATE_READY		= 2,
+	MES_LOG_CONTEXT_STATE_READY_STANDBY	= 3,
 };
 
-struct MES_LOG_CONTEXT_STATE_CHANGE
-{
-    void*                   h_context;
-    enum MES_LOG_CONTEXT_STATE   new_context_state;
+struct MES_LOG_CONTEXT_STATE_CHANGE {
+	void				*h_context;
+	enum MES_LOG_CONTEXT_STATE	new_context_state;
 };
 
-struct MES_LOG_ENTRY_HEADER
-{
-    uint32 first_free_entry_index;
-    uint32 wraparound_count;
-    uint64 number_of_entries;
-    uint64 reserved[2];
+struct MES_LOG_ENTRY_HEADER {
+	uint32_t	first_free_entry_index;
+	uint32_t	wraparound_count;
+	uint64_t	number_of_entries;
+	uint64_t	reserved[2];
 };
 
-struct MES_LOG_ENTRY_DATA
-{
-    uint64 gpu_time_stamp;
-    uint32 operation_type; //operation_type is of MES_LOG_OPERATION type
-    uint32 reserved_operation_type_bits;
-    union
-    {
-        struct MES_LOG_CONTEXT_STATE_CHANGE  context_state_change;
-        uint64                        reserved_operation_data[2];
-    };
+struct MES_LOG_ENTRY_DATA {
+	uint64_t	gpu_time_stamp;
+	uint32_t	operation_type; /* operation_type is of MES_LOG_OPERATION type */
+	uint32_t	reserved_operation_type_bits;
+	union {
+		struct MES_LOG_CONTEXT_STATE_CHANGE	context_state_change;
+		uint64_t				reserved_operation_data[2];
+	};
 };
 
-struct MES_LOG_BUFFER
-{
-    struct MES_LOG_ENTRY_HEADER header;
-    struct MES_LOG_ENTRY_DATA   entries[1];
+struct MES_LOG_BUFFER {
+	struct MES_LOG_ENTRY_HEADER	header;
+	struct MES_LOG_ENTRY_DATA	entries[1];
 };
 
-union MESAPI_SET_HW_RESOURCES
-{
-    struct
-    {
-        union MES_API_HEADER                header;
-        uint32                              vmid_mask_mmhub;
-        uint32                              vmid_mask_gfxhub;
-        uint32                              gds_size;
-        uint32                              paging_vmid;
-        uint32                              compute_hqd_mask[MAX_COMPUTE_PIPES];
-        uint32                              gfx_hqd_mask[MAX_GFX_PIPES];
-        uint32                              sdma_hqd_mask[MAX_SDMA_PIPES];
-        uint32                              agreegated_doorbells[AMD_PRIORITY_NUM_LEVELS];
-        uint64                              g_sch_ctx_gpu_mc_ptr;
-        struct MES_API_STATUS               api_status;
-    };
-
-    uint32 max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
+union MESAPI_SET_HW_RESOURCES {
+	struct {
+		union MES_API_HEADER	header;
+		uint32_t		vmid_mask_mmhub;
+		uint32_t		vmid_mask_gfxhub;
+		uint32_t		gds_size;
+		uint32_t		paging_vmid;
+		uint32_t		compute_hqd_mask[MAX_COMPUTE_PIPES];
+		uint32_t		gfx_hqd_mask[MAX_GFX_PIPES];
+		uint32_t		sdma_hqd_mask[MAX_SDMA_PIPES];
+		uint32_t		agreegated_doorbells[AMD_PRIORITY_NUM_LEVELS];
+		uint64_t		g_sch_ctx_gpu_mc_ptr;
+		uint64_t		query_status_fence_gpu_mc_ptr;
+		struct MES_API_STATUS	api_status;
+		union {
+			struct {
+				uint32_t disable_reset	: 1;
+				uint32_t reserved	: 31;
+			};
+			uint32_t	uint32_t_all;
+		};
+	};
+
+	uint32_t	max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
 };
 
-union MESAPI__ADD_QUEUE
-{
-    struct
-    {
-        union MES_API_HEADER        header;
-        uint32                      process_id;
-        uint64                      page_table_base_addr;
-        uint64                      process_va_start;
-        uint64                      process_va_end;
-        uint64                      process_quantum;
-        uint64                      process_context_addr;
-        uint64                      gang_quantum;
-        uint64                      gang_context_addr;
-        uint32                      inprocess_gang_priority;
-        enum MES_AMD_PRIORITY_LEVEL gang_global_priority_level;
-        uint32                      doorbell_offset;
-        uint64                      mqd_addr;
-        uint64                      wptr_addr;
-        enum MES_QUEUE_TYPE         queue_type;
-        uint32                      gds_base;
-        uint32                      gds_size;
-        uint32                      gws_base;
-        uint32                      gws_size;
-        uint32                      oa_mask;
-
-        struct
-        {
-            uint32 paging      : 1;
-            uint32 program_gds : 1;
-            uint32 reserved    : 30;
-        };
-        struct MES_API_STATUS       api_status;
-    };
-
-    uint32 max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
+union MESAPI__ADD_QUEUE {
+	struct {
+		union MES_API_HEADER		header;
+		uint32_t			process_id;
+		uint64_t			page_table_base_addr;
+		uint64_t			process_va_start;
+		uint64_t			process_va_end;
+		uint64_t			process_quantum;
+		uint64_t			process_context_addr;
+		uint64_t			gang_quantum;
+		uint64_t			gang_context_addr;
+		uint32_t			inprocess_gang_priority;
+		enum MES_AMD_PRIORITY_LEVEL	gang_global_priority_level;
+		uint32_t			doorbell_offset;
+		uint64_t			mqd_addr;
+		uint64_t			wptr_addr;
+		enum MES_QUEUE_TYPE		queue_type;
+		uint32_t			gds_base;
+		uint32_t			gds_size;
+		uint32_t			gws_base;
+		uint32_t			gws_size;
+		uint32_t			oa_mask;
+
+		struct {
+			uint32_t paging			: 1;
+			uint32_t debug_vmid		: 4;
+			uint32_t program_gds		: 1;
+			uint32_t is_gang_suspended	: 1;
+			uint32_t is_tmz_queue		: 1;
+			uint32_t reserved		: 24;
+		};
+		struct MES_API_STATUS		api_status;
+	};
+
+	uint32_t	max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
 };
 
-union MESAPI__REMOVE_QUEUE
-{
-    struct
-    {
-        union MES_API_HEADER        header;
-        uint32                      doorbell_offset;
-        uint64                      gang_context_addr;
-        struct MES_API_STATUS       api_status;
-    };
-
-    uint32 max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
-};
+union MESAPI__REMOVE_QUEUE {
+	struct {
+		union MES_API_HEADER	header;
+		uint32_t		doorbell_offset;
+		uint64_t		gang_context_addr;
 
-union MESAPI__SET_SCHEDULING_CONFIG
-{
-    struct
-    {
-        union MES_API_HEADER        header;
-        // Grace period when preempting another priority band for this priority band.
-        // The value for idle priority band is ignored, as it never preempts other bands.
-        uint64                      grace_period_other_levels[AMD_PRIORITY_NUM_LEVELS];
+		struct {
+			uint32_t unmap_legacy_gfx_queue	: 1;
+			uint32_t reserved		: 31;
+		};
+		struct MES_API_STATUS	api_status;
+	};
 
-        // Default quantum for scheduling across processes within a priority band.
-        uint64                      process_quantum_for_level[AMD_PRIORITY_NUM_LEVELS];
+	uint32_t	max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
+};
 
-        // Default grace period for processes that preempt each other within a priority band.
-        uint64                      process_grace_period_same_level[AMD_PRIORITY_NUM_LEVELS];
+union MESAPI__SET_SCHEDULING_CONFIG {
+	struct {
+		union MES_API_HEADER	header;
+		/* Grace period when preempting another priority band for this
+		 * priority band. The value for idle priority band is ignored,
+		 * as it never preempts other bands.
+		 */
+		uint64_t		grace_period_other_levels[AMD_PRIORITY_NUM_LEVELS];
+		/* Default quantum for scheduling across processes within
+		 * a priority band.
+		 */
+		uint64_t		process_quantum_for_level[AMD_PRIORITY_NUM_LEVELS];
+		/* Default grace period for processes that preempt each other
+		 * within a priority band.
+		 */
+		uint64_t		process_grace_period_same_level[AMD_PRIORITY_NUM_LEVELS];
+		/* For normal level this field specifies the target GPU
+		 * percentage in situations when it's starved by the high level.
+		 * Valid values are between 0 and 50, with the default being 10.
+		 */
+		uint32_t		normal_yield_percent;
+		struct MES_API_STATUS	api_status;
+	};
+
+	uint32_t	max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
+};
 
-        // For normal level this field specifies the target GPU percentage in situations when it's starved by the high level.
-        // Valid values are between 0 and 50, with the default being 10.
-        uint32                      normal_yield_percent;
+union MESAPI__PERFORM_YIELD {
+	struct {
+		union MES_API_HEADER	header;
+		uint32_t		dummy;
+		struct MES_API_STATUS	api_status;
+	};
 
-        struct MES_API_STATUS       api_status;
-    };
+	uint32_t	max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
+};
 
-    uint32 max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
+union MESAPI__CHANGE_GANG_PRIORITY_LEVEL {
+	struct {
+		union MES_API_HEADER		header;
+		uint32_t			inprocess_gang_priority;
+		enum MES_AMD_PRIORITY_LEVEL	gang_global_priority_level;
+		uint64_t			gang_quantum;
+		uint64_t			gang_context_addr;
+		struct MES_API_STATUS		api_status;
+	};
+
+	uint32_t	max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
 };
 
-union MESAPI__PERFORM_YIELD
-{
-    struct
-    {
-        union MES_API_HEADER    header;
-        uint32                  dummy;
-        struct MES_API_STATUS   api_status;
-    };
+union MESAPI__SUSPEND {
+	struct {
+		union MES_API_HEADER	header;
+		/* false - suspend all gangs; true - specific gang */
+		struct {
+			uint32_t suspend_all_gangs	: 1;
+			uint32_t reserved		: 31;
+		};
+		/* gang_context_addr is valid only if suspend_all = false */
+		uint64_t		gang_context_addr;
 
-    uint32 max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
-};
+		uint64_t		suspend_fence_addr;
+		uint32_t		suspend_fence_value;
+
+		struct MES_API_STATUS	api_status;
+	};
 
-union MESAPI__CHANGE_GANG_PRIORITY_LEVEL
-{
-    struct
-    {
-        union MES_API_HEADER        header;
-        uint32                      inprocess_gang_priority;
-        enum MES_AMD_PRIORITY_LEVEL gang_global_priority_level;
-        uint64                      gang_quantum;
-        uint64                      gang_context_addr;
-        struct MES_API_STATUS       api_status;
-    };
-
-    uint32 max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
+	uint32_t	max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
 };
 
-union MESAPI__SUSPEND
-{
-    struct
-    {
-        union MES_API_HEADER        header;
-        //false - suspend all gangs; true - specific gang
-        struct
-        {
-            uint32                  suspend_all_gangs : 1;
-            uint32                  reserved : 31;
-        };
-        //gang_context_addr is valid only if suspend_all = false
-        uint64                      gang_context_addr;
-
-        uint64                      suspend_fence_addr;
-        uint32                      suspend_fence_value;
-
-        struct MES_API_STATUS       api_status;
-    };
-
-    uint32 max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
+union MESAPI__RESUME {
+	struct {
+		union MES_API_HEADER	header;
+		/* false - resume all gangs; true - specified gang */
+		struct {
+			uint32_t resume_all_gangs	: 1;
+			uint32_t reserved		: 31;
+		};
+		/* valid only if resume_all_gangs = false */
+		uint64_t		gang_context_addr;
+
+		struct MES_API_STATUS	api_status;
+	};
+
+	uint32_t	max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
 };
 
-union MESAPI__RESUME
-{
-    struct
-    {
-        union MES_API_HEADER        header;
-        //false - resume all gangs; true - specified gang
-        struct
-        {
-            uint32                  resume_all_gangs : 1;
-            uint32                  reserved : 31;
-        };
-        //valid only if resume_all_gangs = false
-        uint64                      gang_context_addr;
-
-        struct MES_API_STATUS       api_status;
-    };
-
-    uint32 max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
+union MESAPI__RESET {
+	struct {
+		union MES_API_HEADER	header;
+
+		struct {
+			uint32_t reset_queue	: 1;
+			uint32_t reserved	: 31;
+		};
+
+		uint64_t		gang_context_addr;
+		uint32_t		doorbell_offset; /* valid only if reset_queue = true */
+		struct MES_API_STATUS	api_status;
+	};
+
+	uint32_t	max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
 };
 
-union MESAPI__RESET
-{
-    struct
-    {
-        union MES_API_HEADER        header;
+union MESAPI__SET_LOGGING_BUFFER {
+	struct {
+		union MES_API_HEADER	header;
+		/* There are separate log buffers for each queue type */
+		enum MES_QUEUE_TYPE	log_type;
+		/* Log buffer GPU Address */
+		uint64_t		logging_buffer_addr;
+		/* number of entries in the log buffer */
+		uint32_t		number_of_entries;
+		/* Entry index at which CPU interrupt needs to be signalled */
+		uint32_t		interrupt_entry;
+
+		struct MES_API_STATUS	api_status;
+	};
+
+	uint32_t	max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
+};
 
-        struct
-        {
-            uint32                  reset_queue : 1;
-            uint32                  reserved : 31;
-        };
+union MESAPI__QUERY_MES_STATUS {
+	struct {
+		union MES_API_HEADER	header;
+		bool			mes_healthy; /* 0 - not healthy, 1 - healthy */
+		struct MES_API_STATUS	api_status;
+	};
 
-        uint64                      gang_context_addr;
-        uint32                      doorbell_offset; //valid only if reset_queue = true
-        struct MES_API_STATUS       api_status;
-    };
+	uint32_t	max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
+};
 
-    uint32 max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
+union MESAPI__PROGRAM_GDS {
+	struct {
+		union MES_API_HEADER	header;
+		uint64_t		process_context_addr;
+		uint32_t		gds_base;
+		uint32_t		gds_size;
+		uint32_t		gws_base;
+		uint32_t		gws_size;
+		uint32_t		oa_mask;
+		struct MES_API_STATUS	api_status;
+	};
+
+	uint32_t	max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
 };
 
-union MESAPI__SET_LOGGING_BUFFER
-{
-    struct
-    {
-        union MES_API_HEADER        header;
-        //There are separate log buffers for each queue type
-        enum MES_QUEUE_TYPE         log_type;
-        //Log buffer GPU Address
-        uint64                      logging_buffer_addr;
-        //number of entries in the log buffer
-        uint32                      number_of_entries;
-        //Entry index at which CPU interrupt needs to be signalled
-        uint32                      interrupt_entry;
-
-        struct MES_API_STATUS       api_status;
-    };
-
-    uint32 max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
+union MESAPI__SET_DEBUG_VMID {
+	struct {
+		union MES_API_HEADER	header;
+		struct MES_API_STATUS	api_status;
+		union {
+			struct {
+				uint32_t use_gds	: 1;
+				uint32_t reserved	: 31;
+			} flags;
+			uint32_t	u32All;
+		};
+		uint32_t		reserved;
+		uint32_t		debug_vmid;
+		uint64_t		process_context_addr;
+		uint64_t		page_table_base_addr;
+		uint64_t		process_va_start;
+		uint64_t		process_va_end;
+		uint32_t		gds_base;
+		uint32_t		gds_size;
+		uint32_t		gws_base;
+		uint32_t		gws_size;
+		uint32_t		oa_mask;
+	};
+
+	uint32_t	max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
 };
 
-union MESAPI__QUERY_MES_STATUS
-{
-    struct
-    {
-        union MES_API_HEADER        header;
-        bool                        mes_healthy; //0 - not healthy, 1 - healthy
-        struct MES_API_STATUS       api_status;
-    };
+enum MESAPI_MISC_OPCODE {
+	MESAPI_MISC__MODIFY_REG,
+	MESAPI_MISC__MAX,
+};
 
-    uint32 max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
+enum MODIFY_REG_SUBCODE {
+	MODIFY_REG__OVERWRITE,
+	MODIFY_REG__RMW_OR,
+	MODIFY_REG__RMW_AND,
+	MODIFY_REG__MAX,
 };
 
-union MESAPI__PROGRAM_GDS
-{
-    struct
-    {
-        union MES_API_HEADER        header;
-        uint64                      process_context_addr;
-        uint32                      gds_base;
-        uint32                      gds_size;
-        uint32                      gws_base;
-        uint32                      gws_size;
-        uint32                      oa_mask;
-        struct MES_API_STATUS       api_status;
-    };
-
-    uint32 max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
+enum { MISC_DATA_MAX_SIZE_IN_DWORDS = 20 };
+
+union MESAPI__MISC {
+	struct {
+		union MES_API_HEADER	header;
+		enum MESAPI_MISC_OPCODE	opcode;
+		struct MES_API_STATUS	api_status;
+
+		union {
+			struct {
+				enum MODIFY_REG_SUBCODE	subcode;
+				uint32_t		reg_offset;
+				uint32_t		reg_value;
+			} modify_reg;
+			uint32_t	data[MISC_DATA_MAX_SIZE_IN_DWORDS];
+		};
+	};
+
+	uint32_t	max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
 };
 
 #pragma pack(pop)
-- 
2.25.4

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

  parent reply	other threads:[~2020-06-01 18:21 UTC|newest]

Thread overview: 90+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-01 18:18 [PATCH 090/207] drm/amdgpu: enable JPEG3.0 for Sienna_Cichlid Alex Deucher
2020-06-01 18:18 ` [PATCH 091/207] drm/amdgpu/gfx10: add gc golden setting for sienna_cichlid Alex Deucher
2020-06-01 18:18 ` [PATCH 092/207] drm/amdgpu: force pa_sc_tile_steering_override to 0 for gfx10.3 Alex Deucher
2020-06-01 18:19 ` [PATCH 093/207] drm/amdgpu: add cp firmware backdoor loading triger Alex Deucher
2020-06-01 18:19 ` [PATCH 094/207] drm/amdgpu: disable gfxoff for sienna_cichlid Alex Deucher
2020-06-01 18:19 ` [PATCH 095/207] drm/amdgpu: add vram_info v2_5 in atomfirmware header Alex Deucher
2020-06-01 18:19 ` [PATCH 096/207] drm/amdgpu: support query vram info for sienna_cichlid Alex Deucher
2020-06-01 18:19 ` [PATCH 097/207] drm/amdgpu: drop gfx_v10_0_tiling_mode_table_init Alex Deucher
2020-06-01 18:19 ` [PATCH 098/207] drm/amdgpu: only send one sdma firmware for sienna_cichlid Alex Deucher
2020-06-01 18:19 ` [PATCH 099/207] drm/amdgpu: add firmware_info v3_4 structure for Sienna_Cichlid Alex Deucher
2020-06-01 18:19 ` [PATCH 100/207] drm/amdgpu: add atomfirmware helper funciton to query reserved fb size Alex Deucher
2020-06-01 18:19 ` [PATCH 101/207] drm/amdgpu: switch to query reserved fb size from vbios (v3) Alex Deucher
2020-06-01 18:19 ` [PATCH 102/207] drm/amdgpu: open GFX clock gating for sienna_cichlid Alex Deucher
2020-06-01 18:19 ` [PATCH 103/207] drm/amdgpu: change the offset for VCN FW cache window Alex Deucher
2020-06-01 18:19 ` [PATCH 104/207] drm/amdgpu: fix the PSP front door loading VCN firmware Alex Deucher
2020-06-01 18:19 ` [PATCH 105/207] drm/amdgpu: set the LMI ctrl and reset earlier Alex Deucher
2020-06-01 18:19 ` [PATCH 106/207] drm/amdgpu: update golden setting for gfx10.3 Alex Deucher
2020-06-01 18:19 ` [PATCH 107/207] drm/amd/amdgpu: fix the HDP LS/DS/SD programming Alex Deucher
2020-06-01 18:19 ` [PATCH 108/207] drm/amd/amdgpu: add HDP mgcg and ls support Alex Deucher
2020-06-01 18:19 ` [PATCH 109/207] drm/amd/amdgpu: add IH cg support Alex Deucher
2020-06-01 18:19 ` [PATCH 110/207] drm/amd/amdgpu: add athub ls support Alex Deucher
2020-06-01 18:19 ` [PATCH 111/207] drm/amdgpu: Enable Multi Media Hub (MMHUB) Clock Gating for sienna_cichlid Alex Deucher
2020-06-01 18:19 ` [PATCH 112/207] drm/amdgpu: fix SDMA hdp flush engine conflict Alex Deucher
2020-06-02 12:17   ` Christian König
2020-06-01 18:19 ` [PATCH 113/207] drm/amdgpu: enable 3D pipe 1 on Sienna_Cichlid Alex Deucher
2020-06-01 18:19 ` [PATCH 114/207] sound/pci/hda: add sienna_cichlid audio asic id for sienna_cichlid up Alex Deucher
2020-06-01 18:19 ` [PATCH 115/207] drm/amdgpu/dc: Add missing Sienna_Cichlid chip id Alex Deucher
2020-06-01 18:19 ` [PATCH 116/207] drm/amdkfd: Support Sienna_Cichlid KFD v4 Alex Deucher
2020-06-01 18:19 ` [PATCH 117/207] drm/amdkfd: Add Sienna_Cichlid trap handler support Alex Deucher
2020-06-01 18:19 ` [PATCH 118/207] drm/amdkfd: Support newer assemblers in gfx10 trap handler Alex Deucher
2020-06-01 18:19 ` [PATCH 119/207] drm/amdkfd: Support debugger in Navi1x " Alex Deucher
2020-06-01 18:19 ` [PATCH 120/207] drm/amdkfd: sienna_cichlid virtual function support Alex Deucher
2020-06-01 18:19 ` [PATCH 121/207] drm/amd/powerplay: enable VR0HOT for sienna_cichlid Alex Deucher
2020-06-01 18:19 ` [PATCH 122/207] drm/amd/powerplay: enable FCLK DS " Alex Deucher
2020-06-01 18:19 ` [PATCH 123/207] drm/amdgpu: fix typo for vcn3/jpeg3 idle check Alex Deucher
2020-06-01 18:19 ` [PATCH 124/207] drm/amd/powerplay: enable MM DPM PG for sienna_cichlid (v2) Alex Deucher
2020-06-01 18:19 ` [PATCH 125/207] drm/amdgpu: Sienna_Cichlid don't enable SMU for SRIOV Alex Deucher
2020-06-01 18:19 ` [PATCH 126/207] drm/amd/powerplay: enable BACO for sienna_cichlid Alex Deucher
2020-06-01 18:19 ` [PATCH 127/207] drm/amd/powerplay: enable APCC DFLL " Alex Deucher
2020-06-01 18:19 ` [PATCH 128/207] drm/amd/powerplay: add function to get power limit " Alex Deucher
2020-06-01 18:19 ` Alex Deucher [this message]
2020-06-01 18:19 ` [PATCH 130/207] drm/amdgpu/mes: add status fence memory definitions Alex Deucher
2020-06-01 18:19 ` [PATCH 131/207] drm/amdgpu/mes: allocate memory slots for hw resource setting Alex Deucher
2020-06-01 18:19 ` [PATCH 132/207] drm/amdgpu: skip VM inv eng assignment for mes ring Alex Deucher
2020-06-01 18:19 ` [PATCH 133/207] drm/amd/powerplay: enable athub pg Alex Deucher
2020-06-01 18:19 ` [PATCH 134/207] drm/amd/powerplay: enable mmhub pg Alex Deucher
2020-06-01 18:19 ` [PATCH 135/207] drm/amd/powerplay: enable GPO Alex Deucher
2020-06-01 18:19 ` [PATCH 136/207] drm/amd/powerplay: bundle GPO with gfx DPM Alex Deucher
2020-06-01 18:19 ` [PATCH 137/207] drm/amdgpu: update golden setting for sienna_cichlid Alex Deucher
2020-06-01 18:19 ` [PATCH 138/207] drm/amd/powerplay: enable RSMU SMN PG " Alex Deucher
2020-06-01 18:19 ` [PATCH 139/207] drm/am/powerplay: enable OUT OF BAND MONITER " Alex Deucher
2020-06-01 18:19 ` [PATCH 140/207] drm/amdgpu: add clock gating DPG mode for VCN3.0 Alex Deucher
2020-06-01 18:19 ` [PATCH 141/207] drm/amdgpu: add mc resume " Alex Deucher
2020-06-01 18:19 ` [PATCH 142/207] drm/amdgpu: add start " Alex Deucher
2020-06-01 18:19 ` [PATCH 143/207] drm/amdgpu: add stop " Alex Deucher
2020-06-01 18:19 ` [PATCH 144/207] drm/amdgpu: add pause " Alex Deucher
2020-06-01 18:19 ` [PATCH 145/207] drm/amdgpu: set indirect sram " Alex Deucher
2020-06-01 18:19 ` [PATCH 146/207] drm/amdgpu: add internal reg offset translation for VCN inst 1 Alex Deucher
2020-06-01 18:19 ` [PATCH 147/207] drm/amdgpu: rename macro for VCN1.0 Alex Deucher
2020-06-01 18:19 ` [PATCH 148/207] drm/amdgpu: rename macro for VCN2.0 2.5 and 3.0 Alex Deucher
2020-06-01 18:19 ` [PATCH 149/207] drm/amdgpu: add workaround for issue in DPG for VCN3.0 Alex Deucher
2020-06-01 18:19 ` [PATCH 150/207] drm/amdgpu: enable DPG mode " Alex Deucher
2020-06-01 18:19 ` [PATCH 151/207] drm/amdgpu/mes10.1: add no scheduler flag for mes Alex Deucher
2020-06-01 18:19 ` [PATCH 152/207] drm/amdgpu/vcn3.0: schedule instance 0 for decode and 1 for encode Alex Deucher
2020-06-01 18:20 ` [PATCH 153/207] drm/amd/powerplay: enable ULCK DS for sienna_cichlid Alex Deucher
2020-06-01 18:20 ` [PATCH 154/207] drm/amdgpu/sriov : Use kiq to do tlb invalidation for gfx10 on sriov Alex Deucher
2020-06-01 18:20 ` [PATCH 155/207] drm/amd/powerplay: and smc dpm info struct for sienna_cichlid Alex Deucher
2020-06-01 18:20 ` [PATCH 156/207] drm/amd/powerplay: append pptable for sienna_cichlid (v2) Alex Deucher
2020-06-01 18:20 ` [PATCH 157/207] drm/amd/powerplay: enable VDDCI and MVDD for sienna_cichlid Alex Deucher
2020-06-01 18:20 ` [PATCH 158/207] drm/amdgpu: skip GPU scheduler setup for KIQ and MES ring Alex Deucher
2020-06-01 18:20 ` [PATCH 159/207] drm/amd/powerplay: enable fw ctf Alex Deucher
2020-06-01 18:20 ` [PATCH 160/207] drm/amdgpu: disable runtime pm for sienna_cichlid temporarily Alex Deucher
2020-06-01 18:20 ` [PATCH 161/207] drm/amd/powerplay: drop jpeg instance1 dpm setup Alex Deucher
2020-06-01 18:20 ` [PATCH 162/207] drm/amdgpu: only use one gfx pipe for Sienna_Cichlid Alex Deucher
2020-06-01 18:20 ` [PATCH 163/207] drm/amdgpu/sriov : Add sriov detection for sienna_cichlid Alex Deucher
2020-06-01 18:20 ` [PATCH 164/207] drm/amd/powerplay: support mclk socclk limit value set " Alex Deucher
2020-06-01 18:20 ` [PATCH 165/207] drm/amd/amdgpu: disable gfxoff to retrieve gfxclk Alex Deucher
2020-06-01 18:20 ` [PATCH 166/207] drm/amdgpu: enable gfxoff for sienna_cichlid Alex Deucher
2020-06-01 18:20 ` [PATCH 167/207] drm/amd/powerplay: show gfxclk=0 in gfxoff state Alex Deucher
2020-06-01 18:20 ` [PATCH 168/207] drm/amdgpu/psp: add structure to support PSP SPL Alex Deucher
2020-06-01 18:20 ` [PATCH 169/207] drm/amdgpu/psp: initialization PSP SPL fw Alex Deucher
2020-06-01 18:20 ` [PATCH 170/207] drm/amdgpu/psp: support for loading " Alex Deucher
2020-06-01 18:20 ` [PATCH 171/207] drm/amdgpu: update golden setting for sienna_cichlid Alex Deucher
2020-06-01 18:20 ` [PATCH 172/207] drm/amd/powerplay: update smu function " Alex Deucher
2020-06-01 18:20 ` [PATCH 173/207] drm/amd/powerplay: drop sienna_cichlid hardcode of using pptable Alex Deucher
2020-06-01 18:20 ` [PATCH 174/207] drm/amd/powerplay: let PMFW to handle the features disablement on BACO in V2 Alex Deucher
2020-06-01 18:20 ` [PATCH 175/207] drm/amdgpu: reserve fb according to return value from vbios Alex Deucher
2020-06-01 18:20 ` [PATCH 176/207] drm/amdgpu: support memory training for sienna_cichlid Alex Deucher
2020-06-01 18:20 ` [PATCH 177/207] drm/amdgpu: remove unnecessary check for mem train Alex Deucher
2020-06-01 18:20 ` [PATCH 178/207] drm/amdgpu: bypass tmr when reserve c2p memory Alex Deucher

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20200601182054.1267858-40-alexander.deucher@amd.com \
    --to=alexdeucher@gmail.com \
    --cc=Hawking.Zhang@amd.com \
    --cc=alexander.deucher@amd.com \
    --cc=amd-gfx@lists.freedesktop.org \
    --cc=le.ma@amd.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.