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From: kbuild test robot <lkp@intel.com>
To: kbuild-all@lists.01.org
Subject: Re: [PATCH v1] PCI: controller: convert to devm_platform_ioremap_resource_byname()
Date: Tue, 02 Jun 2020 02:13:23 +0800	[thread overview]
Message-ID: <202006020223.1gKcICcv%lkp@intel.com> (raw)
In-Reply-To: <20200601143345.24965-1-zhengdejin5@gmail.com>

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Hi Dejin,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on pci/next]
[also build test WARNING on tegra/for-next rockchip/for-next v5.7 next-20200529]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]

url:    https://github.com/0day-ci/linux/commits/Dejin-Zheng/PCI-controller-convert-to-devm_platform_ioremap_resource_byname/20200601-223757
base:   https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git next
config: x86_64-allyesconfig (attached as .config)
compiler: clang version 11.0.0 (https://github.com/llvm/llvm-project 2388a096e7865c043e83ece4e26654bd3d1a20d5)
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # install x86_64 cross compiling tool for clang build
        # apt-get install binutils-x86-64-linux-gnu
        # save the attached .config to linux build tree
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=x86_64 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kbuild test robot <lkp@intel.com>

All warnings (new ones prefixed by >>, old ones prefixed by <<):

>> drivers/pci/controller/pcie-xilinx-nwl.c:783:25: warning: variable 'res' is uninitialized when used here [-Wuninitialized]
pcie->phys_breg_base = res->start;
^~~
drivers/pci/controller/pcie-xilinx-nwl.c:778:22: note: initialize the variable 'res' to silence this warning
struct resource *res;
^
= NULL
1 warning generated.

vim +/res +783 drivers/pci/controller/pcie-xilinx-nwl.c

ab597d35ef11d2 drivers/pci/host/pcie-xilinx-nwl.c       Bharat Kumar Gogada 2016-03-06  773  
ab597d35ef11d2 drivers/pci/host/pcie-xilinx-nwl.c       Bharat Kumar Gogada 2016-03-06  774  static int nwl_pcie_parse_dt(struct nwl_pcie *pcie,
ab597d35ef11d2 drivers/pci/host/pcie-xilinx-nwl.c       Bharat Kumar Gogada 2016-03-06  775  			     struct platform_device *pdev)
ab597d35ef11d2 drivers/pci/host/pcie-xilinx-nwl.c       Bharat Kumar Gogada 2016-03-06  776  {
adf9e284b4f76d drivers/pci/host/pcie-xilinx-nwl.c       Bjorn Helgaas       2016-10-06  777  	struct device *dev = pcie->dev;
ab597d35ef11d2 drivers/pci/host/pcie-xilinx-nwl.c       Bharat Kumar Gogada 2016-03-06  778  	struct resource *res;
ab597d35ef11d2 drivers/pci/host/pcie-xilinx-nwl.c       Bharat Kumar Gogada 2016-03-06  779  
213cf573e1a8b2 drivers/pci/controller/pcie-xilinx-nwl.c Dejin Zheng         2020-06-01  780  	pcie->breg_base = devm_platform_ioremap_resource_byname(pdev, "breg");
ab597d35ef11d2 drivers/pci/host/pcie-xilinx-nwl.c       Bharat Kumar Gogada 2016-03-06  781  	if (IS_ERR(pcie->breg_base))
ab597d35ef11d2 drivers/pci/host/pcie-xilinx-nwl.c       Bharat Kumar Gogada 2016-03-06  782  		return PTR_ERR(pcie->breg_base);
ab597d35ef11d2 drivers/pci/host/pcie-xilinx-nwl.c       Bharat Kumar Gogada 2016-03-06 @783  	pcie->phys_breg_base = res->start;
ab597d35ef11d2 drivers/pci/host/pcie-xilinx-nwl.c       Bharat Kumar Gogada 2016-03-06  784  
213cf573e1a8b2 drivers/pci/controller/pcie-xilinx-nwl.c Dejin Zheng         2020-06-01  785  	pcie->pcireg_base =
213cf573e1a8b2 drivers/pci/controller/pcie-xilinx-nwl.c Dejin Zheng         2020-06-01  786  		devm_platform_ioremap_resource_byname(pdev, "pcireg");
ab597d35ef11d2 drivers/pci/host/pcie-xilinx-nwl.c       Bharat Kumar Gogada 2016-03-06  787  	if (IS_ERR(pcie->pcireg_base))
ab597d35ef11d2 drivers/pci/host/pcie-xilinx-nwl.c       Bharat Kumar Gogada 2016-03-06  788  		return PTR_ERR(pcie->pcireg_base);
ab597d35ef11d2 drivers/pci/host/pcie-xilinx-nwl.c       Bharat Kumar Gogada 2016-03-06  789  	pcie->phys_pcie_reg_base = res->start;
ab597d35ef11d2 drivers/pci/host/pcie-xilinx-nwl.c       Bharat Kumar Gogada 2016-03-06  790  
ab597d35ef11d2 drivers/pci/host/pcie-xilinx-nwl.c       Bharat Kumar Gogada 2016-03-06  791  	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
cd00f084ed1d50 drivers/pci/host/pcie-xilinx-nwl.c       Lorenzo Pieralisi   2017-04-19  792  	pcie->ecam_base = devm_pci_remap_cfg_resource(dev, res);
ab597d35ef11d2 drivers/pci/host/pcie-xilinx-nwl.c       Bharat Kumar Gogada 2016-03-06  793  	if (IS_ERR(pcie->ecam_base))
ab597d35ef11d2 drivers/pci/host/pcie-xilinx-nwl.c       Bharat Kumar Gogada 2016-03-06  794  		return PTR_ERR(pcie->ecam_base);
ab597d35ef11d2 drivers/pci/host/pcie-xilinx-nwl.c       Bharat Kumar Gogada 2016-03-06  795  	pcie->phys_ecam_base = res->start;
ab597d35ef11d2 drivers/pci/host/pcie-xilinx-nwl.c       Bharat Kumar Gogada 2016-03-06  796  
ab597d35ef11d2 drivers/pci/host/pcie-xilinx-nwl.c       Bharat Kumar Gogada 2016-03-06  797  	/* Get intx IRQ number */
ab597d35ef11d2 drivers/pci/host/pcie-xilinx-nwl.c       Bharat Kumar Gogada 2016-03-06  798  	pcie->irq_intx = platform_get_irq_byname(pdev, "intx");
ab597d35ef11d2 drivers/pci/host/pcie-xilinx-nwl.c       Bharat Kumar Gogada 2016-03-06  799  	if (pcie->irq_intx < 0) {
adf9e284b4f76d drivers/pci/host/pcie-xilinx-nwl.c       Bjorn Helgaas       2016-10-06  800  		dev_err(dev, "failed to get intx IRQ %d\n", pcie->irq_intx);
5fd4bf6a659e45 drivers/pci/host/pcie-xilinx-nwl.c       Fabio Estevam       2017-08-31  801  		return pcie->irq_intx;
ab597d35ef11d2 drivers/pci/host/pcie-xilinx-nwl.c       Bharat Kumar Gogada 2016-03-06  802  	}
ab597d35ef11d2 drivers/pci/host/pcie-xilinx-nwl.c       Bharat Kumar Gogada 2016-03-06  803  
ab597d35ef11d2 drivers/pci/host/pcie-xilinx-nwl.c       Bharat Kumar Gogada 2016-03-06  804  	irq_set_chained_handler_and_data(pcie->irq_intx,
ab597d35ef11d2 drivers/pci/host/pcie-xilinx-nwl.c       Bharat Kumar Gogada 2016-03-06  805  					 nwl_pcie_leg_handler, pcie);
ab597d35ef11d2 drivers/pci/host/pcie-xilinx-nwl.c       Bharat Kumar Gogada 2016-03-06  806  
ab597d35ef11d2 drivers/pci/host/pcie-xilinx-nwl.c       Bharat Kumar Gogada 2016-03-06  807  	return 0;
ab597d35ef11d2 drivers/pci/host/pcie-xilinx-nwl.c       Bharat Kumar Gogada 2016-03-06  808  }
ab597d35ef11d2 drivers/pci/host/pcie-xilinx-nwl.c       Bharat Kumar Gogada 2016-03-06  809  

:::::: The code at line 783 was first introduced by commit
:::::: ab597d35ef11d2a921e0ec507a9b7861bcb44cbd PCI: xilinx-nwl: Add support for Xilinx NWL PCIe Host Controller

:::::: TO: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
:::::: CC: Bjorn Helgaas <bhelgaas@google.com>

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org

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  reply	other threads:[~2020-06-01 18:13 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-01 14:33 [PATCH v1] PCI: controller: convert to devm_platform_ioremap_resource_byname() Dejin Zheng
2020-06-01 18:13 ` kbuild test robot [this message]
2020-06-02 16:41   ` Dejin Zheng
2020-06-01 22:22 ` Rob Herring
2020-06-02 16:58   ` Dejin Zheng

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