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From: Ansuel Smith <ansuelsmth@gmail.com>
To: Rob Herring <robh+dt@kernel.org>
Cc: Ansuel Smith <ansuelsmth@gmail.com>,
	Sham Muthayyan <smuthayy@codeaurora.org>,
	Rob Herring <robh@kernel.org>, Andy Gross <agross@kernel.org>,
	Bjorn Andersson <bjorn.andersson@linaro.org>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Mark Rutland <mark.rutland@arm.com>,
	Stanimir Varbanov <svarbanov@mm-sol.com>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Andrew Murray <amurray@thegoodpenguin.co.uk>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH v5 01/11] PCI: qcom: Add missing ipq806x clocks in PCIe driver
Date: Tue,  2 Jun 2020 13:53:42 +0200	[thread overview]
Message-ID: <20200602115353.20143-2-ansuelsmth@gmail.com> (raw)
In-Reply-To: <20200602115353.20143-1-ansuelsmth@gmail.com>

Aux and Ref clk are missing in PCIe qcom driver. Add support for this
optional clks for ipq8064/apq8064 SoC.

Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver")
Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
 drivers/pci/controller/dwc/pcie-qcom.c | 38 ++++++++++++++++++++++----
 1 file changed, 33 insertions(+), 5 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 5ea527a6bd9f..4bf93ab8c7a7 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -88,6 +88,8 @@ struct qcom_pcie_resources_2_1_0 {
 	struct clk *iface_clk;
 	struct clk *core_clk;
 	struct clk *phy_clk;
+	struct clk *aux_clk;
+	struct clk *ref_clk;
 	struct reset_control *pci_reset;
 	struct reset_control *axi_reset;
 	struct reset_control *ahb_reset;
@@ -246,6 +248,14 @@ static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie)
 	if (IS_ERR(res->phy_clk))
 		return PTR_ERR(res->phy_clk);
 
+	res->aux_clk = devm_clk_get_optional(dev, "aux");
+	if (IS_ERR(res->aux_clk))
+		return PTR_ERR(res->aux_clk);
+
+	res->ref_clk = devm_clk_get_optional(dev, "ref");
+	if (IS_ERR(res->ref_clk))
+		return PTR_ERR(res->ref_clk);
+
 	res->pci_reset = devm_reset_control_get_exclusive(dev, "pci");
 	if (IS_ERR(res->pci_reset))
 		return PTR_ERR(res->pci_reset);
@@ -278,6 +288,8 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie)
 	clk_disable_unprepare(res->iface_clk);
 	clk_disable_unprepare(res->core_clk);
 	clk_disable_unprepare(res->phy_clk);
+	clk_disable_unprepare(res->aux_clk);
+	clk_disable_unprepare(res->ref_clk);
 	regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
 }
 
@@ -307,16 +319,28 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
 		goto err_assert_ahb;
 	}
 
+	ret = clk_prepare_enable(res->core_clk);
+	if (ret) {
+		dev_err(dev, "cannot prepare/enable core clock\n");
+		goto err_clk_core;
+	}
+
 	ret = clk_prepare_enable(res->phy_clk);
 	if (ret) {
 		dev_err(dev, "cannot prepare/enable phy clock\n");
 		goto err_clk_phy;
 	}
 
-	ret = clk_prepare_enable(res->core_clk);
+	ret = clk_prepare_enable(res->aux_clk);
 	if (ret) {
-		dev_err(dev, "cannot prepare/enable core clock\n");
-		goto err_clk_core;
+		dev_err(dev, "cannot prepare/enable aux clock\n");
+		goto err_clk_aux;
+	}
+
+	ret = clk_prepare_enable(res->ref_clk);
+	if (ret) {
+		dev_err(dev, "cannot prepare/enable ref clock\n");
+		goto err_clk_ref;
 	}
 
 	ret = reset_control_deassert(res->ahb_reset);
@@ -372,10 +396,14 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
 	return 0;
 
 err_deassert_ahb:
-	clk_disable_unprepare(res->core_clk);
-err_clk_core:
+	clk_disable_unprepare(res->ref_clk);
+err_clk_ref:
+	clk_disable_unprepare(res->aux_clk);
+err_clk_aux:
 	clk_disable_unprepare(res->phy_clk);
 err_clk_phy:
+	clk_disable_unprepare(res->core_clk);
+err_clk_core:
 	clk_disable_unprepare(res->iface_clk);
 err_assert_ahb:
 	regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
-- 
2.25.1


  reply	other threads:[~2020-06-02 11:55 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-02 11:53 [PATCH v5 00/11] Multiple fixes in PCIe qcom driver Ansuel Smith
2020-06-02 11:53 ` Ansuel Smith [this message]
2020-06-02 11:53 ` [PATCH v5 02/11] dt-bindings: PCI: qcom: Add missing clks Ansuel Smith
2020-06-02 11:53 ` [PATCH v5 03/11] PCI: qcom: Change duplicate PCI reset to phy reset Ansuel Smith
2020-06-02 11:53 ` [PATCH v5 04/11] PCI: qcom: Add missing reset for ipq806x Ansuel Smith
2020-06-02 11:53 ` [PATCH v5 05/11] dt-bindings: PCI: qcom: Add ext reset Ansuel Smith
2020-06-02 11:53 ` [PATCH v5 06/11] PCI: qcom: Use bulk clk api and assert on error Ansuel Smith
2020-06-02 11:53 ` [PATCH v5 07/11] PCI: qcom: Define some PARF params needed for ipq8064 SoC Ansuel Smith
2020-06-05 14:10   ` Sasha Levin
2020-06-06 16:30   ` Stanimir Varbanov
2020-06-02 11:53 ` [PATCH v5 08/11] PCI: qcom: Add support for tx term offset for rev 2.1.0 Ansuel Smith
2020-06-02 11:53 ` [PATCH v5 09/11] PCI: qcom: Add ipq8064 rev2 variant Ansuel Smith
2020-06-02 11:53 ` [PATCH v5 10/11] dt-bindings: PCI: qcom: Add ipq8064 rev 2 variant Ansuel Smith
2020-06-02 11:53 ` [PATCH v5 11/11] PCI: qcom: Add Force GEN1 support Ansuel Smith
2020-06-02 16:32   ` Bjorn Helgaas
2020-06-02 17:07     ` R: " ansuelsmth
2020-06-02 17:28       ` Bjorn Helgaas
2020-06-09 14:48         ` R: " ansuelsmth
2020-06-09 16:41           ` Bjorn Helgaas

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