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Wed, 3 Jun 2020 09:14:35 -0400 (EDT) Date: Wed, 3 Jun 2020 15:14:34 +0200 From: Maxime Ripard To: Stefan Wahren Cc: Eric Anholt , Dave Stevenson , Tim Gover , LKML , DRI Development , Nicolas Saenz Julienne , bcm-kernel-feedback-list@broadcom.com, Phil Elwell , linux-arm-kernel@lists.infradead.org, linux-rpi-kernel@lists.infradead.org Subject: Re: [PATCH v3 032/105] drm/vc4: crtc: Enable and disable the PV in atomic_enable / disable Message-ID: <20200603131434.2gmofg7sf7luakje@gilmour> References: <20200602141228.7zbkob7bw3owajsq@gilmour> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="skfrnwv7a5sl4g3l" Content-Disposition: inline In-Reply-To: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --skfrnwv7a5sl4g3l Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Hi Stefan, On Tue, Jun 02, 2020 at 10:03:13PM +0200, Stefan Wahren wrote: > Am 02.06.20 um 21:31 schrieb Eric Anholt: > > On Tue, Jun 2, 2020 at 8:02 AM Dave Stevenson > > wrote: > >> Hi Maxime and Eric > >> > >> On Tue, 2 Jun 2020 at 15:12, Maxime Ripard wrote: > >>> Hi Eric > >>> > >>> On Wed, May 27, 2020 at 09:54:44AM -0700, Eric Anholt wrote: > >>>> On Wed, May 27, 2020 at 8:50 AM Maxime Ripard wr= ote: > >>>>> The VIDEN bit in the pixelvalve currently being used to enable or d= isable > >>>>> the pixelvalve seems to not be enough in some situations, which whi= ll end > >>>>> up with the pixelvalve stalling. > >>>>> > >>>>> In such a case, even re-enabling VIDEN doesn't bring it back and we= need to > >>>>> clear the FIFO. This can only be done if the pixelvalve is disabled= though. > >>>>> > >>>>> In order to overcome this, we can configure the pixelvalve during > >>>>> mode_set_no_fb, but only enable it in atomic_enable and flush the F= IFO > >>>>> there, and in atomic_disable disable the pixelvalve again. > >>>> What displays has this been tested with? Getting this sequencing > >>>> right is so painful, and things like DSI are tricky to get to light > >>>> up. > >>> That FIFO is between the HVS and the HDMI PVs, so this was obviously > >>> tested against that. Dave also tested the DSI output IIRC, so we shou= ld > >>> be covered here. > >> DSI wasn't working on the first patch set that Maxime sent - I haven't > >> tested this one as yet but will do so. > >> DPI was working early on to both an Adafruit 800x480 DPI panel, and > >> via a VGA666 as VGA. > >> HDMI is obviously working. > >> VEC is being ignored now. The clock structure is more restricted than > >> earlier chips, so to get the required clocks for the VEC without using > >> fractional divides it compromises the clock that other parts of the > >> system can run at (IIRC including the ARM). That's why the VEC has to > >> be explicitly enabled for the firmware to enable it as the only > >> output. It's annoying, but that's just a restriction of the chip. > > I'm more concerned with "make sure we don't regress pre-pi4 with this > > series" than "pi4 displays all work from the beginning" >=20 > unfortuntely i can confirm this. With this patch series (using Maxime's > git repo with multi_v7_defconfig) my Raspberry Pi 3 B hangs up while > starting X (screen stays black, heartbeat stops, no more output at the > debug UART). AFAIR v2 didn't had this issue. Did it happen with a DSI display or something else? I've been trying to setup the DSI display on an RPi3 today, but noticed that it looks like there's a regression in next that prevents the HDMI driver to load entirely (without my patches). Maxime --skfrnwv7a5sl4g3l Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRcEzekXsqa64kGDp7j7w1vZxhRxQUCXteiOgAKCRDj7w1vZxhR xbKWAQDYW0bIeRglf4HXhCDqUGdBhZA9ZXckJcF7Q9T+gYysFQEAyPKFFwR9N3NC f2tspYRw6I0x7UydBz+c6ib42l557wQ= =eXfr -----END PGP SIGNATURE----- --skfrnwv7a5sl4g3l-- From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.8 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 92225C433E0 for ; Wed, 3 Jun 2020 13:14:59 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 626B820679 for ; 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Wed, 3 Jun 2020 09:14:35 -0400 (EDT) Date: Wed, 3 Jun 2020 15:14:34 +0200 From: Maxime Ripard To: Stefan Wahren Subject: Re: [PATCH v3 032/105] drm/vc4: crtc: Enable and disable the PV in atomic_enable / disable Message-ID: <20200603131434.2gmofg7sf7luakje@gilmour> References: <20200602141228.7zbkob7bw3owajsq@gilmour> MIME-Version: 1.0 In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200603_061454_488121_291DB6FB X-CRM114-Status: GOOD ( 22.18 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Tim Gover , Dave Stevenson , LKML , DRI Development , Eric Anholt , bcm-kernel-feedback-list@broadcom.com, linux-arm-kernel@lists.infradead.org, Phil Elwell , Nicolas Saenz Julienne , linux-rpi-kernel@lists.infradead.org Content-Type: multipart/mixed; boundary="===============6352018347147623582==" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org --===============6352018347147623582== Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="skfrnwv7a5sl4g3l" Content-Disposition: inline --skfrnwv7a5sl4g3l Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Hi Stefan, On Tue, Jun 02, 2020 at 10:03:13PM +0200, Stefan Wahren wrote: > Am 02.06.20 um 21:31 schrieb Eric Anholt: > > On Tue, Jun 2, 2020 at 8:02 AM Dave Stevenson > > wrote: > >> Hi Maxime and Eric > >> > >> On Tue, 2 Jun 2020 at 15:12, Maxime Ripard wrote: > >>> Hi Eric > >>> > >>> On Wed, May 27, 2020 at 09:54:44AM -0700, Eric Anholt wrote: > >>>> On Wed, May 27, 2020 at 8:50 AM Maxime Ripard wr= ote: > >>>>> The VIDEN bit in the pixelvalve currently being used to enable or d= isable > >>>>> the pixelvalve seems to not be enough in some situations, which whi= ll end > >>>>> up with the pixelvalve stalling. > >>>>> > >>>>> In such a case, even re-enabling VIDEN doesn't bring it back and we= need to > >>>>> clear the FIFO. This can only be done if the pixelvalve is disabled= though. > >>>>> > >>>>> In order to overcome this, we can configure the pixelvalve during > >>>>> mode_set_no_fb, but only enable it in atomic_enable and flush the F= IFO > >>>>> there, and in atomic_disable disable the pixelvalve again. > >>>> What displays has this been tested with? Getting this sequencing > >>>> right is so painful, and things like DSI are tricky to get to light > >>>> up. > >>> That FIFO is between the HVS and the HDMI PVs, so this was obviously > >>> tested against that. Dave also tested the DSI output IIRC, so we shou= ld > >>> be covered here. > >> DSI wasn't working on the first patch set that Maxime sent - I haven't > >> tested this one as yet but will do so. > >> DPI was working early on to both an Adafruit 800x480 DPI panel, and > >> via a VGA666 as VGA. > >> HDMI is obviously working. > >> VEC is being ignored now. The clock structure is more restricted than > >> earlier chips, so to get the required clocks for the VEC without using > >> fractional divides it compromises the clock that other parts of the > >> system can run at (IIRC including the ARM). That's why the VEC has to > >> be explicitly enabled for the firmware to enable it as the only > >> output. It's annoying, but that's just a restriction of the chip. > > I'm more concerned with "make sure we don't regress pre-pi4 with this > > series" than "pi4 displays all work from the beginning" >=20 > unfortuntely i can confirm this. With this patch series (using Maxime's > git repo with multi_v7_defconfig) my Raspberry Pi 3 B hangs up while > starting X (screen stays black, heartbeat stops, no more output at the > debug UART). AFAIR v2 didn't had this issue. Did it happen with a DSI display or something else? I've been trying to setup the DSI display on an RPi3 today, but noticed that it looks like there's a regression in next that prevents the HDMI driver to load entirely (without my patches). Maxime --skfrnwv7a5sl4g3l Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRcEzekXsqa64kGDp7j7w1vZxhRxQUCXteiOgAKCRDj7w1vZxhR xbKWAQDYW0bIeRglf4HXhCDqUGdBhZA9ZXckJcF7Q9T+gYysFQEAyPKFFwR9N3NC f2tspYRw6I0x7UydBz+c6ib42l557wQ= =eXfr -----END PGP SIGNATURE----- --skfrnwv7a5sl4g3l-- --===============6352018347147623582== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel --===============6352018347147623582==-- From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.6 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6DC85C433E0 for ; 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Wed, 3 Jun 2020 09:14:35 -0400 (EDT) Date: Wed, 3 Jun 2020 15:14:34 +0200 From: Maxime Ripard To: Stefan Wahren Subject: Re: [PATCH v3 032/105] drm/vc4: crtc: Enable and disable the PV in atomic_enable / disable Message-ID: <20200603131434.2gmofg7sf7luakje@gilmour> References: <20200602141228.7zbkob7bw3owajsq@gilmour> MIME-Version: 1.0 In-Reply-To: X-Mailman-Approved-At: Thu, 04 Jun 2020 07:11:42 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Tim Gover , Dave Stevenson , LKML , DRI Development , bcm-kernel-feedback-list@broadcom.com, linux-arm-kernel@lists.infradead.org, Phil Elwell , Nicolas Saenz Julienne , linux-rpi-kernel@lists.infradead.org Content-Type: multipart/mixed; boundary="===============0481146660==" Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" --===============0481146660== Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="skfrnwv7a5sl4g3l" Content-Disposition: inline --skfrnwv7a5sl4g3l Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Hi Stefan, On Tue, Jun 02, 2020 at 10:03:13PM +0200, Stefan Wahren wrote: > Am 02.06.20 um 21:31 schrieb Eric Anholt: > > On Tue, Jun 2, 2020 at 8:02 AM Dave Stevenson > > wrote: > >> Hi Maxime and Eric > >> > >> On Tue, 2 Jun 2020 at 15:12, Maxime Ripard wrote: > >>> Hi Eric > >>> > >>> On Wed, May 27, 2020 at 09:54:44AM -0700, Eric Anholt wrote: > >>>> On Wed, May 27, 2020 at 8:50 AM Maxime Ripard wr= ote: > >>>>> The VIDEN bit in the pixelvalve currently being used to enable or d= isable > >>>>> the pixelvalve seems to not be enough in some situations, which whi= ll end > >>>>> up with the pixelvalve stalling. > >>>>> > >>>>> In such a case, even re-enabling VIDEN doesn't bring it back and we= need to > >>>>> clear the FIFO. This can only be done if the pixelvalve is disabled= though. > >>>>> > >>>>> In order to overcome this, we can configure the pixelvalve during > >>>>> mode_set_no_fb, but only enable it in atomic_enable and flush the F= IFO > >>>>> there, and in atomic_disable disable the pixelvalve again. > >>>> What displays has this been tested with? Getting this sequencing > >>>> right is so painful, and things like DSI are tricky to get to light > >>>> up. > >>> That FIFO is between the HVS and the HDMI PVs, so this was obviously > >>> tested against that. Dave also tested the DSI output IIRC, so we shou= ld > >>> be covered here. > >> DSI wasn't working on the first patch set that Maxime sent - I haven't > >> tested this one as yet but will do so. > >> DPI was working early on to both an Adafruit 800x480 DPI panel, and > >> via a VGA666 as VGA. > >> HDMI is obviously working. > >> VEC is being ignored now. The clock structure is more restricted than > >> earlier chips, so to get the required clocks for the VEC without using > >> fractional divides it compromises the clock that other parts of the > >> system can run at (IIRC including the ARM). That's why the VEC has to > >> be explicitly enabled for the firmware to enable it as the only > >> output. It's annoying, but that's just a restriction of the chip. > > I'm more concerned with "make sure we don't regress pre-pi4 with this > > series" than "pi4 displays all work from the beginning" >=20 > unfortuntely i can confirm this. With this patch series (using Maxime's > git repo with multi_v7_defconfig) my Raspberry Pi 3 B hangs up while > starting X (screen stays black, heartbeat stops, no more output at the > debug UART). AFAIR v2 didn't had this issue. Did it happen with a DSI display or something else? I've been trying to setup the DSI display on an RPi3 today, but noticed that it looks like there's a regression in next that prevents the HDMI driver to load entirely (without my patches). Maxime --skfrnwv7a5sl4g3l Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRcEzekXsqa64kGDp7j7w1vZxhRxQUCXteiOgAKCRDj7w1vZxhR xbKWAQDYW0bIeRglf4HXhCDqUGdBhZA9ZXckJcF7Q9T+gYysFQEAyPKFFwR9N3NC f2tspYRw6I0x7UydBz+c6ib42l557wQ= =eXfr -----END PGP SIGNATURE----- --skfrnwv7a5sl4g3l-- --===============0481146660== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel --===============0481146660==--