tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master head: 6929f71e46bdddbf1c4d67c2728648176c67c555 commit: e44ab4e14d6f4c448ae555132090c1a116b19e5c regmap: Simplify implementation of the regmap_read_poll_timeout() macro date: 6 weeks ago config: arm-randconfig-r035-20200604 (attached as .config) compiler: arm-linux-gnueabi-gcc (GCC) 9.3.0 reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross git checkout e44ab4e14d6f4c448ae555132090c1a116b19e5c # save the attached .config to linux build tree COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=arm If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot All warnings (new ones prefixed by >>, old ones prefixed by <<): >> drivers/reset/reset-intel-gw.c:18: warning: "REG_OFFSET" redefined 18 | #define REG_OFFSET GENMASK(31, 16) | In file included from arch/arm/mach-ixp4xx/include/mach/hardware.h:30, from arch/arm/mach-ixp4xx/include/mach/io.h:15, from arch/arm/include/asm/io.h:198, from include/linux/io.h:13, from include/linux/iopoll.h:14, from include/linux/regmap.h:20, from drivers/reset/reset-intel-gw.c:12: arch/arm/mach-ixp4xx/include/mach/platform.h:25: note: this is the location of the previous definition 25 | #define REG_OFFSET 3 | vim +/REG_OFFSET +18 drivers/reset/reset-intel-gw.c c9aef213e38cde Dilip Kota 2020-01-03 17 c9aef213e38cde Dilip Kota 2020-01-03 @18 #define REG_OFFSET GENMASK(31, 16) c9aef213e38cde Dilip Kota 2020-01-03 19 #define BIT_OFFSET GENMASK(15, 8) c9aef213e38cde Dilip Kota 2020-01-03 20 #define STAT_BIT_OFFSET GENMASK(7, 0) c9aef213e38cde Dilip Kota 2020-01-03 21 :::::: The code at line 18 was first introduced by commit :::::: c9aef213e38cde27d4689a5cbe25a7c1b1db9fad reset: intel: Add system reset controller driver :::::: TO: Dilip Kota :::::: CC: Philipp Zabel --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org