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[68.147.8.254]) by smtp.gmail.com with ESMTPSA id e143sm5288315pfh.42.2020.06.04.14.18.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Jun 2020 14:18:57 -0700 (PDT) Date: Thu, 4 Jun 2020 15:18:55 -0600 From: Mathieu Poirier To: Mike Leach Subject: Re: [PATCH v4 4/5] coresight: etm: perf: Add default sink selection to etm perf Message-ID: <20200604211855.GD18961@xps15> References: <20200526104642.9526-1-mike.leach@linaro.org> <20200526104642.9526-5-mike.leach@linaro.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200526104642.9526-5-mike.leach@linaro.org> User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200604_141901_325532_66A07807 X-CRM114-Status: GOOD ( 20.84 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: coresight@lists.linaro.org, acme@kernel.org, linux-arm-kernel@lists.infradead.org, suzuki.poulose@arm.com Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, May 26, 2020 at 11:46:41AM +0100, Mike Leach wrote: > Add default sink selection to the perf trace handling in the etm driver. > Uses the select default sink infrastructure to select a sink for the perf > session, if no other sink is specified. > > Signed-off-by: Mike Leach > --- > .../hwtracing/coresight/coresight-etm-perf.c | 17 ++++++++++++++--- > 1 file changed, 14 insertions(+), 3 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c > index 84f1dcb69827..1a3169e69bb1 100644 > --- a/drivers/hwtracing/coresight/coresight-etm-perf.c > +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c > @@ -226,9 +226,6 @@ static void *etm_setup_aux(struct perf_event *event, void **pages, > sink = coresight_get_enabled_sink(true); > } > > - if (!sink) > - goto err; > - > mask = &event_data->mask; > > /* > @@ -253,6 +250,16 @@ static void *etm_setup_aux(struct perf_event *event, void **pages, > continue; > } > > + /* > + * No sink provided - look for a default sink for one of the > + * devices. At present we only support topology where all CPUs > + * use the same sink [N:1], so only need to find one sink. The > + * coresight_build_path later will remove any CPU that does not > + * attach to the sink, or if we have not found a sink. > + */ > + if (!sink) > + sink = coresight_find_default_sink(csdev); > + > /* > * Building a path doesn't enable it, it simply builds a > * list of devices from source to sink that can be > @@ -267,6 +274,10 @@ static void *etm_setup_aux(struct perf_event *event, void **pages, > *etm_event_cpu_path_ptr(event_data, cpu) = path; > } > > + /* no sink found for any CPU - cannot trace */ > + if (!sink) > + goto err; > + Reviewed-by: Mathieu Poirier > /* If we don't have any CPUs ready for tracing, abort */ > cpu = cpumask_first(mask); > if (cpu >= nr_cpu_ids) > -- > 2.17.1 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel