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[79.181.55.232]) by smtp.gmail.com with ESMTPSA id a3sm3623724wrp.91.2020.06.09.08.30.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jun 2020 08:30:38 -0700 (PDT) Date: Tue, 9 Jun 2020 11:30:35 -0400 From: "Michael S. Tsirkin" To: "Dr. David Alan Gilbert" Subject: Re: [PATCH] pci: assert configuration access is within bounds Message-ID: <20200609113019-mutt-send-email-mst@kernel.org> References: <20200604113525.58898-1-ppandit@redhat.com> <20200604163631.GB2890@work-vm> MIME-Version: 1.0 In-Reply-To: <20200604163631.GB2890@work-vm> X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit Content-Disposition: inline Received-SPF: pass client-ip=207.211.31.81; envelope-from=mst@redhat.com; helo=us-smtp-delivery-1.mimecast.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/06/08 23:42:34 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] [fuzzy] X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Daniel P =?iso-8859-1?Q?=2E_Berrang=E9?= , Prasad J Pandit , QEMU Developers , P J P , Gerd Hoffmann , Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Thu, Jun 04, 2020 at 05:36:31PM +0100, Dr. David Alan Gilbert wrote: > * P J P (ppandit@redhat.com) wrote: > > From: Prasad J Pandit > > > > While accessing PCI configuration bytes, assert that > > 'address + len' is within PCI configuration space. > > > > Generally it is within bounds. This is more of a defensive > > assert, in case a buggy device was to send 'address' which > > may go out of bounds. > > Can a guest trigger this assert? > > Dave Shouldn't be able to, no. > > Suggested-by: Philippe Mathieu-Daudé > > Signed-off-by: Prasad J Pandit > > --- > > hw/pci/pci.c | 4 ++++ > > 1 file changed, 4 insertions(+) > > > > Update v1: defensive assert as separate patch > > -> https://lists.gnu.org/archive/html/qemu-devel/2020-06/msg00957.html > > -> https://lists.gnu.org/archive/html/qemu-devel/2020-06/msg00960.html > > > > diff --git a/hw/pci/pci.c b/hw/pci/pci.c > > index 70c66965f5..7bf2ae6d92 100644 > > --- a/hw/pci/pci.c > > +++ b/hw/pci/pci.c > > @@ -1381,6 +1381,8 @@ uint32_t pci_default_read_config(PCIDevice *d, > > { > > uint32_t val = 0; > > > > + assert(address + len <= pci_config_size(d)); > > + > > if (pci_is_express_downstream_port(d) && > > ranges_overlap(address, len, d->exp.exp_cap + PCI_EXP_LNKSTA, 2)) { > > pcie_sync_bridge_lnk(d); > > @@ -1394,6 +1396,8 @@ void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val_in, int > > int i, was_irq_disabled = pci_irq_disabled(d); > > uint32_t val = val_in; > > > > + assert(addr + l <= pci_config_size(d)); > > + > > for (i = 0; i < l; val >>= 8, ++i) { > > uint8_t wmask = d->wmask[addr + i]; > > uint8_t w1cmask = d->w1cmask[addr + i]; > > -- > > 2.26.2 > > > > > -- > Dr. David Alan Gilbert / dgilbert@redhat.com / Manchester, UK