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[115.65.196.228]) by smtp.gmail.com with ESMTPSA id l23sm9096977pgc.55.2020.06.09.13.49.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jun 2020 13:49:19 -0700 (PDT) Date: Wed, 10 Jun 2020 05:49:17 +0900 From: Stafford Horne To: Eric Blake Subject: Re: [PATCH] hw/openrisc/openrisc_sim: Add assertion to silent GCC warning Message-ID: <20200609204917.GJ75760@lianli.shorne-pla.net> References: <20200608071409.17024-1-philmd@redhat.com> <95f1d638-3921-ffdf-8f07-2f077d1d0cc9@redhat.com> <20200609204227.GI75760@lianli.shorne-pla.net> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20200609204227.GI75760@lianli.shorne-pla.net> Received-SPF: pass client-ip=2607:f8b0:4864:20::542; envelope-from=shorne@gmail.com; helo=mail-pg1-x542.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Thomas Huth , Jia Liu , qemu-trivial@nongnu.org, Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= , qemu-devel@nongnu.org, Markus Armbruster , 1874073@bugs.launchpad.net, Christophe de Dinechin , Martin =?utf-8?B?TGnFoWth?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Wed, Jun 10, 2020 at 05:42:27AM +0900, Stafford Horne wrote: > On Mon, Jun 08, 2020 at 10:33:24AM -0500, Eric Blake wrote: > > On 6/8/20 2:14 AM, Philippe Mathieu-Daudé wrote: > > > When compiling with GCC 10 (Fedora 32) using CFLAGS=-O2 we get: > > > > In the subject: s/silent/silence/ > > > > > > > > CC or1k-softmmu/hw/openrisc/openrisc_sim.o > > > hw/openrisc/openrisc_sim.c: In function ‘openrisc_sim_init’: > > > hw/openrisc/openrisc_sim.c:87:42: error: ‘cpu_irqs[0]’ may be used uninitialized in this function [-Werror=maybe-uninitialized] > > > 87 | sysbus_connect_irq(s, i, cpu_irqs[i][irq_pin]); > > > | ~~~~~~~~^~~ > > > > > > While humans can tell smp_cpus will always be in the [1, 2] range, > > > (openrisc_sim_machine_init sets mc->max_cpus = 2), the compiler > > > can't. > > > > > > Add an assertion to give the compiler a hint there's no use of > > > uninitialized data. > > > > > > Buglink: https://bugs.launchpad.net/qemu/+bug/1874073 > > > Reported-by: Martin Liška > > > Suggested-by: Peter Maydell > > > Signed-off-by: Philippe Mathieu-Daudé > > > --- > > > hw/openrisc/openrisc_sim.c | 1 + > > > 1 file changed, 1 insertion(+) > > > > Tested-by: Eric Blake > > > > With the typo fixed, > > Reviewed-by: Eric Blake > > Acked-by: Stafford Horne > > I see there are now two patches for this, I kind of like this assert fix. > > Shall I queue it for OpenRISC pulling? Or can someone else pick this up? Hello, Sorry, I see v2 of this patch has already been picked up. -Stafford