[PATCH v2 4/6] ARM: mm: Aligned pte allocation to one page

[Gregory CLEMENT <gregory.clement@bootlin.com>]

In pte_offset_kernel() the pte_index macro is used. This macro makes
the assumption that the address is aligned to a page size.

In arm_pte_allocation, the size allocated is the size needed for 512
entries. Actually this size was calculated to fit in a 4K page. When
using larger page, the size of the table allocated is no more
aligned which end to give a wrong physical address.

The solution is to round up the allocation to a page size instead of
the exact size of the tables (which is 4KB). It allows to comply with
the assumption of pte_index() but the drawback is a waste of memory
for the early allocation if page size is bigger than 4KB.

This is inspired from fa0ca2726ea9 ("DSMP 64K support") and
4ef803e12baf ("mmu: large-page: Added support for multiple kernel page
sizes") from
https://github.com/MarvellEmbeddedProcessors/linux-marvell.git

Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
 arch/arm/mm/mmu.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index ec8d0008bfa1..b7fdea7e0cbe 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -715,7 +715,9 @@ static pte_t * __init arm_pte_alloc(pmd_t *pmd, unsigned long addr,
 				void *(*alloc)(unsigned long sz))
 {
 	if (pmd_none(*pmd)) {
-		pte_t *pte = alloc(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE);
+		/* The PTE needs to be page to be page aligned	 */
+		pte_t *pte = alloc(round_up(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE,
+					    PAGE_SIZE));
 		__pmd_populate(pmd, __pa(pte), prot);
 	}
 	BUG_ON(pmd_bad(*pmd));
-- 
2.26.2


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