From mboxrd@z Thu Jan  1 00:00:00 1970
From: Simon Glass <sjg@chromium.org>
Date: Sun, 14 Jun 2020 21:57:25 -0600
Subject: [PATCH v1 30/43] x86: apl: Support set_hide() in p2sb driver
In-Reply-To: <20200615035738.248710-1-sjg@chromium.org>
References: <20200615035738.248710-1-sjg@chromium.org>
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Add support for this new method in the driver and in the fsp-s setup.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 arch/x86/cpu/apollolake/fsp_s.c  | 26 +++++++++++---------------
 arch/x86/cpu/intel_common/p2sb.c | 30 ++++++++++++++++++++++++++++++
 2 files changed, 41 insertions(+), 15 deletions(-)

diff --git a/arch/x86/cpu/apollolake/fsp_s.c b/arch/x86/cpu/apollolake/fsp_s.c
index 0f5520fc7d..3a54297a28 100644
--- a/arch/x86/cpu/apollolake/fsp_s.c
+++ b/arch/x86/cpu/apollolake/fsp_s.c
@@ -12,6 +12,7 @@
 #include <irq.h>
 #include <log.h>
 #include <malloc.h>
+#include <p2sb.h>
 #include <acpi/acpi_s3.h>
 #include <asm/intel_pinctrl.h>
 #include <asm/io.h>
@@ -21,10 +22,11 @@
 #include <asm/pci.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/systemagent.h>
+#include <asm/arch/fsp_bindings.h>
 #include <asm/arch/fsp/fsp_configs.h>
 #include <asm/arch/fsp/fsp_s_upd.h>
+#include <dm/uclass-internal.h>
 #include <linux/bitops.h>
-#include <asm/arch/fsp_bindings.h>
 
 #define PCH_P2SB_E0		0xe0
 #define HIDE_BIT		BIT(0)
@@ -59,12 +61,6 @@ int fsps_update_config(struct udevice *dev, ulong rom_offset,
 	return fsp_s_update_config_from_dtb(node, cfg);
 }
 
-static void p2sb_set_hide_bit(pci_dev_t dev, int hide)
-{
-	pci_x86_clrset_config(dev, PCH_P2SB_E0 + 1, HIDE_BIT,
-			      hide ? HIDE_BIT : 0, PCI_SIZE_8);
-}
-
 /* Configure package power limits */
 static int set_power_limits(struct udevice *dev)
 {
@@ -137,15 +133,15 @@ static int set_power_limits(struct udevice *dev)
 
 int p2sb_unhide(void)
 {
-	pci_dev_t dev = PCI_BDF(0, 0xd, 0);
-	ulong val;
-
-	p2sb_set_hide_bit(dev, 0);
-
-	pci_x86_read_config(dev, PCI_VENDOR_ID, &val, PCI_SIZE_16);
+	struct udevice *dev;
+	int ret;
 
-	if (val != PCI_VENDOR_ID_INTEL)
-		return log_msg_ret("p2sb unhide", -EIO);
+	ret = uclass_find_first_device(UCLASS_P2SB, &dev);
+	if (ret)
+		return log_msg_ret("p2sb", ret);
+	ret = p2sb_set_hide(dev, false);
+	if (ret)
+		return log_msg_ret("hide", ret);
 
 	return 0;
 }
diff --git a/arch/x86/cpu/intel_common/p2sb.c b/arch/x86/cpu/intel_common/p2sb.c
index ec35d04ae5..ebf8f62aea 100644
--- a/arch/x86/cpu/intel_common/p2sb.c
+++ b/arch/x86/cpu/intel_common/p2sb.c
@@ -16,6 +16,9 @@
 #include <asm/pci.h>
 #include <linux/bitops.h>
 
+#define PCH_P2SB_E0		0xe0
+#define HIDE_BIT		BIT(0)
+
 struct p2sb_platdata {
 #if CONFIG_IS_ENABLED(OF_PLATDATA)
 	struct dtd_intel_p2sb dtplat;
@@ -127,6 +130,29 @@ static int p2sb_probe(struct udevice *dev)
 	return 0;
 }
 
+static void p2sb_set_hide_bit(struct udevice *dev, bool hide)
+{
+	dm_pci_clrset_config8(dev, PCH_P2SB_E0 + 1, HIDE_BIT,
+			      hide ? HIDE_BIT : 0);
+}
+
+static int intel_p2sb_set_hide(struct udevice *dev, bool hide)
+{
+	u16 vendor;
+
+	if (!CONFIG_IS_ENABLED(PCI))
+		return -EPERM;
+	p2sb_set_hide_bit(dev, hide);
+
+	dm_pci_read_config16(dev, PCI_VENDOR_ID, &vendor);
+	if (hide && vendor != 0xffff)
+		return log_msg_ret("hide", -EEXIST);
+	else if (!hide && vendor != PCI_VENDOR_ID_INTEL)
+		return log_msg_ret("unhide", -ENOMEDIUM);
+
+	return 0;
+}
+
 static int p2sb_child_post_bind(struct udevice *dev)
 {
 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
@@ -143,6 +169,10 @@ static int p2sb_child_post_bind(struct udevice *dev)
 	return 0;
 }
 
+struct p2sb_ops p2sb_ops = {
+	.set_hide	= intel_p2sb_set_hide,
+};
+
 static const struct udevice_id p2sb_ids[] = {
 	{ .compatible = "intel,p2sb" },
 	{ }
-- 
2.27.0.290.gba653c62da-goog