From: Sonny Jiang <sonny.jiang@amd.com>
To: amd-gfx@lists.freedesktop.org
Cc: Sonny Jiang <sonny.jiang@amd.com>
Subject: [PATCH 4/7] drm amdgpu: SI UVD context rreg/wreg
Date: Wed, 17 Jun 2020 18:00:13 -0400 [thread overview]
Message-ID: <20200617220016.4844-4-sonny.jiang@amd.com> (raw)
In-Reply-To: <20200617220016.4844-1-sonny.jiang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/si.c | 26 ++++++++++++++++++++++++--
1 file changed, 24 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index 153db3f763bc..f1c33395e3fe 100644
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -973,6 +973,28 @@ static void si_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
}
+static u32 si_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
+{
+ unsigned long flags;
+ u32 r;
+
+ spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
+ WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));
+ r = RREG32(mmUVD_CTX_DATA);
+ spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
+ return r;
+}
+
+static void si_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
+ WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));
+ WREG32(mmUVD_CTX_DATA, (v));
+ spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
+}
+
static struct amdgpu_allowed_register_entry si_allowed_read_registers[] = {
{GRBM_STATUS},
{mmGRBM_STATUS2},
@@ -1443,8 +1465,8 @@ static int si_common_early_init(void *handle)
adev->pcie_wreg = &si_pcie_wreg;
adev->pciep_rreg = &si_pciep_rreg;
adev->pciep_wreg = &si_pciep_wreg;
- adev->uvd_ctx_rreg = NULL;
- adev->uvd_ctx_wreg = NULL;
+ adev->uvd_ctx_rreg = si_uvd_ctx_rreg;
+ adev->uvd_ctx_wreg = si_uvd_ctx_wreg;
adev->didt_rreg = NULL;
adev->didt_wreg = NULL;
--
2.25.1
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next prev parent reply other threads:[~2020-06-17 22:00 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-17 22:00 [PATCH 1/7] drm amdgpu: SI UVD PACKET_TYPE0 Sonny Jiang
2020-06-17 22:00 ` [PATCH 2/7] drm amdgpu: SI UVD registers Sonny Jiang
2020-06-17 22:00 ` [PATCH 3/7] drm amdgpu: SI UVD v3_1 Sonny Jiang
2020-06-17 22:00 ` Sonny Jiang [this message]
2020-06-17 22:00 ` [PATCH 5/7] drm amdgpu: SI UVD add uvd_v3_1 to makefile Sonny Jiang
2020-06-17 22:00 ` [PATCH 6/7] drm amdgpu: SI UVD enable for Oland Sonny Jiang
2020-06-17 22:00 ` [PATCH 7/7] drm amdgpu: SI UVD enabled on Verde, Tahiti, Pitcairn Sonny Jiang
2020-06-18 4:31 ` [PATCH 1/7] drm amdgpu: SI UVD PACKET_TYPE0 Alex Deucher
2020-06-22 18:14 ` Christian König
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