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19 Jun 2020 09:55:58 -0700 IronPort-SDR: T6GGQ2U2sA+ZAKGSh3Dynnzy1N78sGu0jSHtkZWP/EqF5CE5OXgwscwW7AWGy0erN+ieDxZ025 bwvZuZmtCz0Q== WDCIronportException: Internal Received: from unknown (HELO risc6-mainframe.hgst.com) ([10.86.58.142]) by uls-op-cesaip02.wdc.com with ESMTP; 19 Jun 2020 10:07:22 -0700 From: Alistair Francis To: peter.maydell@linaro.org, qemu-devel@nongnu.org Subject: [PULL v2 02/32] sifive_e: Support the revB machine Date: Fri, 19 Jun 2020 09:57:47 -0700 Message-Id: <20200619165817.4144200-3-alistair.francis@wdc.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200619165817.4144200-1-alistair.francis@wdc.com> References: <20200619165817.4144200-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=216.71.153.141; envelope-from=prvs=4324eb4de=alistair.francis@wdc.com; helo=esa3.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/06/19 13:07:21 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, Alistair Francis Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alistair Francis --- include/hw/riscv/sifive_e.h | 1 + hw/riscv/sifive_e.c | 34 ++++++++++++++++++++++++++++++---- 2 files changed, 31 insertions(+), 4 deletions(-) diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h index d386ea9223..637414130b 100644 --- a/include/hw/riscv/sifive_e.h +++ b/include/hw/riscv/sifive_e.h @@ -45,6 +45,7 @@ typedef struct SiFiveEState { /*< public >*/ SiFiveESoCState soc; + bool revb; } SiFiveEState; #define TYPE_RISCV_E_MACHINE MACHINE_TYPE_NAME("sifive_e") diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 1c17d02cf0..36486b72d2 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -95,10 +95,14 @@ static void riscv_sifive_e_init(MachineState *machine) memmap[SIFIVE_E_DTIM].base, main_mem); /* Mask ROM reset vector */ - uint32_t reset_vec[2] = { - 0x204002b7, /* 0x1000: lui t0,0x20400 */ - 0x00028067, /* 0x1004: jr t0 */ - }; + uint32_t reset_vec[2]; + + if (s->revb) { + reset_vec[0] = 0x200102b7; /* 0x1000: lui t0,0x20010 */ + } else { + reset_vec[0] = 0x204002b7; /* 0x1000: lui t0,0x20400 */ + } + reset_vec[1] = 0x00028067; /* 0x1004: jr t0 */ /* copy in the reset vector in little_endian byte order */ for (i = 0; i < sizeof(reset_vec) >> 2; i++) { @@ -112,8 +116,30 @@ static void riscv_sifive_e_init(MachineState *machine) } } +static bool sifive_e_machine_get_revb(Object *obj, Error **errp) +{ + SiFiveEState *s = RISCV_E_MACHINE(obj); + + return s->revb; +} + +static void sifive_e_machine_set_revb(Object *obj, bool value, Error **errp) +{ + SiFiveEState *s = RISCV_E_MACHINE(obj); + + s->revb = value; +} + static void sifive_e_machine_instance_init(Object *obj) { + SiFiveEState *s = RISCV_E_MACHINE(obj); + + s->revb = false; + object_property_add_bool(obj, "revb", sifive_e_machine_get_revb, + sifive_e_machine_set_revb); + object_property_set_description(obj, "revb", + "Set on to tell QEMU that it should model " + "the revB HiFive1 board"); } static void sifive_e_machine_class_init(ObjectClass *oc, void *data) -- 2.27.0