From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2467CC433DF for ; Mon, 22 Jun 2020 19:29:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 088562073E for ; Mon, 22 Jun 2020 19:29:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728615AbgFVT3e (ORCPT ); Mon, 22 Jun 2020 15:29:34 -0400 Received: from vps0.lunn.ch ([185.16.172.187]:54096 "EHLO vps0.lunn.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728578AbgFVT3b (ORCPT ); Mon, 22 Jun 2020 15:29:31 -0400 Received: from andrew by vps0.lunn.ch with local (Exim 4.94) (envelope-from ) id 1jnS8F-001iLy-ND; Mon, 22 Jun 2020 21:29:27 +0200 Date: Mon, 22 Jun 2020 21:29:27 +0200 From: Andrew Lunn To: Daniel Mack Cc: Russell King - ARM Linux admin , netdev@vger.kernel.org, vivien.didelot@gmail.com, f.fainelli@gmail.com Subject: Re: [PATCH] net: dsa: mv88e6xxx: Allow MAC configuration for ports with internal PHY Message-ID: <20200622192927.GH405672@lunn.ch> References: <20200622183443.3355240-1-daniel@zonque.org> <20200622184115.GE405672@lunn.ch> <20200622185837.GN1551@shell.armlinux.org.uk> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org > To recap, my setup features a Cadence GEM that is connected to a 88E1510 > PHY which is then connected to port 4 of the switch (which has an > internal PHY) through a transformer-less link. I know this is not > optimal as the speed is limited to 100M by that, but that was the only > way as all other ports where used up. This is the important bit you failed to mention. Given the number of patches on netdev, you should assume anything older than three days has been forgotten. Back to Back PHYs for the CPU port has never really been supported. It does however work if the PHYs are 1G and there are a few boards out there like this, with their owns having crossed fingers this never breaks. Because it is not really supported. I guess you need to work out why PPU is not working for you. I would not be too surprised if it is because it is the CPU port, it is not supposed to have a PHY, so it is not enabled. Andrew