From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.6 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4018BC433E0 for ; Tue, 23 Jun 2020 11:53:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1BD3320771 for ; Tue, 23 Jun 2020 11:53:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1592913224; bh=LuOYdy9hM+E6UpW0wiB3dYuE7jDUweZJNS5ZAL1MAg0=; h=Date:From:To:Cc:Subject:References:In-Reply-To:List-ID:From; b=pa4tZ7H3+Q6vCNiMmrAH9Mcz3cul3O30f55MfdyPqDQZ4WXIwb6VKy+QZf5OXBiuP 7RufIWDOPLMVGjgZ7Tih3jDGr5ydQ45q4HbDjwMQXpNok2BxXQOay8wbwGXqK1Sv42 V1i6I1GKKrOdCHKRGUEi4pafIF4ausDVVKn5sGjU= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732471AbgFWLxm (ORCPT ); Tue, 23 Jun 2020 07:53:42 -0400 Received: from mail.kernel.org ([198.145.29.99]:34278 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732333AbgFWLxm (ORCPT ); Tue, 23 Jun 2020 07:53:42 -0400 Received: from dragon (80.251.214.228.16clouds.com [80.251.214.228]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 0D5C720738; Tue, 23 Jun 2020 11:53:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1592913221; bh=LuOYdy9hM+E6UpW0wiB3dYuE7jDUweZJNS5ZAL1MAg0=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=fMOOHNZtRJjXYvYkiawh185QMxi4FJyC9A+cQw7a/2YwNm4OscQj1wzIUDtDv6cOg 7ZlvXFKdiaJRkK5/syKubxz/yTWpCx9/876J6sDcc+CQapuC2QHUL9MtrQ58ydQJ8g +wGKKKUlCBoP8SQ6BsNsguo0gVDaO6t21c6GGaSU= Date: Tue, 23 Jun 2020 19:53:36 +0800 From: Shawn Guo To: Sven Van Asbroeck , Fugang Duan Cc: Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v1] ARM: imx6plus: enable internal routing of clk_enet_ref where possible Message-ID: <20200623115335.GC30139@dragon> References: <20200613201703.16788-1-TheSven73@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200613201703.16788-1-TheSven73@gmail.com> User-Agent: Mutt/1.9.4 (2018-02-28) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Fugang, Can you take a look at this patch? Thanks! Shawn On Sat, Jun 13, 2020 at 04:17:03PM -0400, Sven Van Asbroeck wrote: > On imx6, the ethernet reference clock (clk_enet_ref) can be generated > by either the imx6, or an external source (e.g. an oscillator or the > PHY). When generated by the imx6, the clock source (from ANATOP) > must be routed to the input of clk_enet_ref via two pads on the SoC, > typically via a dedicated track on the PCB. > > On an imx6 plus however, there is a new setting which enables this > clock to be routed internally on the SoC, from its ANATOP clock > source, straight to clk_enet_ref, without having to go through > the SoC pads. > > Board designs where the clock is generated by the imx6 should not > be affected by routing the clock internally. Therefore on a plus, > we can enable internal routing by default. > > To: Shawn Guo > Cc: Sascha Hauer > Cc: Pengutronix Kernel Team > Cc: Fabio Estevam > Cc: NXP Linux Team > Cc: linux-arm-kernel@lists.infradead.org > Cc: linux-kernel@vger.kernel.org > Signed-off-by: Sven Van Asbroeck > --- > arch/arm/mach-imx/mach-imx6q.c | 18 ++++++++++++++++++ > include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 1 + > 2 files changed, 19 insertions(+) > > Tree: next-20200613 > > diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c > index 85c084a716ab..4d22567bb650 100644 > --- a/arch/arm/mach-imx/mach-imx6q.c > +++ b/arch/arm/mach-imx/mach-imx6q.c > @@ -203,6 +203,24 @@ static void __init imx6q_1588_init(void) > else > pr_err("failed to find fsl,imx6q-iomuxc-gpr regmap\n"); > > + /* > + * On imx6 plus, enet_ref from ANATOP/CCM can be internally routed to > + * be the PTP clock source, instead of having to be routed through > + * pads. > + * Board designs which route the ANATOP/CCM clock through pads are > + * unaffected when routing happens internally. So on these designs, > + * route internally by default. > + */ > + if (clksel == IMX6Q_GPR1_ENET_CLK_SEL_ANATOP && cpu_is_imx6q() && > + imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0) { > + if (!IS_ERR(gpr)) > + regmap_update_bits(gpr, IOMUXC_GPR5, > + IMX6Q_GPR5_ENET_TXCLK_SEL, > + IMX6Q_GPR5_ENET_TXCLK_SEL); > + else > + pr_err("failed to find fsl,imx6q-iomuxc-gpr regmap\n"); > + } > + > clk_put(enet_ref); > put_ptp_clk: > clk_put(ptp_clk); > diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h > index d4b5e527a7a3..eb65d48da0df 100644 > --- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h > +++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h > @@ -240,6 +240,7 @@ > #define IMX6Q_GPR4_IPU_RD_CACHE_CTL BIT(0) > > #define IMX6Q_GPR5_L2_CLK_STOP BIT(8) > +#define IMX6Q_GPR5_ENET_TXCLK_SEL BIT(9) > #define IMX6Q_GPR5_SATA_SW_PD BIT(10) > #define IMX6Q_GPR5_SATA_SW_RST BIT(11) > > -- > 2.17.1 >