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Thu, 25 Jun 2020 18:02:24 +0300 Date: Thu, 25 Jun 2020 18:02:23 +0300 From: Roman Bolshakov To: Paolo Bonzini Subject: Re: [PATCH 6/8] i386: hvf: Drop hvf_reset_vcpu() Message-ID: <20200625150223.GH25104@SPB-NB-133.local> References: <20200624225850.16982-1-r.bolshakov@yadro.com> <20200624225850.16982-7-r.bolshakov@yadro.com> <20200625123637.GG25104@SPB-NB-133.local> <34821aae-e8f5-adc6-eab5-0a6f6b2835e8@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <34821aae-e8f5-adc6-eab5-0a6f6b2835e8@redhat.com> X-Originating-IP: [172.17.204.212] X-ClientProxiedBy: T-EXCH-01.corp.yadro.com (172.17.10.101) To T-EXCH-02.corp.yadro.com (172.17.10.102) Received-SPF: pass client-ip=89.207.88.252; envelope-from=r.bolshakov@yadro.com; helo=mta-01.yadro.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/06/25 11:02:26 X-ACL-Warn: Detected OS = Linux 3.11 and newer X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , Richard Henderson , qemu-devel@nongnu.org, Cameron Esfahani , Claudio Fontana Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Thu, Jun 25, 2020 at 03:30:38PM +0200, Paolo Bonzini wrote: > On 25/06/20 14:36, Roman Bolshakov wrote: > > > > Yes, there's such a place. post-init and post-reset invoke > > hvf_put_registers() and the latter one calls hvf_put_segments(). > > hvf_put_segments() sets CR4 and CR0 via macvm_set_cr0/macvm_set_cr4 > > using the CR0/CR4 from env. So, the reset is relying on generic QEMU > > CPUX86State now. LMA in EFER is reset there as well. > > Ok, do you want to send a follow-up or a v2 of this? > I'm still trying to understand what I should do :) > > I don't know any alternative for PDPTE and VMCS Entry Controls in > > CPUX86State, that's why I left explicit reset of the VMCS fields in > > post-reset. > > VMCS entry controls should be handled by macvm_set_cr0 as well, because > QEMU does not use any except for the LMA bit. They are initialized zero > > wvmcs(cpu->hvf_fd, VMCS_ENTRY_CTLS, > cap2ctrl(hvf_state->hvf_caps->vmx_cap_entry, 0)); > > but in practice the last argument ends up being zero all the time. > macvm_set_cr0() sets/clears LMA in entry controls only in case of transitions into/out of long mode in enter_long_mode() in exit_long_mode(), respectively. But macvm_set_cr0() doesn't load EFER.LMA from CPUX86State into VMCS entry controls during reset and that's where hvf_put_registers() might not behave properly. As far as I understand you propose to drop explicit LMA reset in post-reset and rather impove synchronization between efer and entry controls in macvm_set_cr0(), right? In that case I don't see a regression in the series, and if possible I'd prefer a follow up patch for the issue. > PDPTEs are not a problem, because they are not used after reset (only if > CR4.PAE=CR4.PG=1 and EFER.LME=0). > Ok, good, then we're leaving PDPTE initialization as is in post-reset. Thanks, Roman