[PATCH net-next 0/2] ethtool: Add support for 100Gbps per lane link modes

[PATCH net-next 0/2] ethtool: Add support for 100Gbps per lane link modes

[Saeed Mahameed]

Hi,

This small series adds new ethtool link modes bits to 
Define 100G, 200G and 400G link modes using 100Gbps per lane.

Thanks,
Saeed.

Meir Lichtinger (2):
  ethtool: Add support for 100Gbps per lane link modes
  net/mlx5: Added support for 100Gbps per lane link modes

 .../net/ethernet/mellanox/mlx5/core/en/port.c |  3 +++
 .../ethernet/mellanox/mlx5/core/en_ethtool.c  | 21 ++++++++++++++++++-
 drivers/net/phy/phy-core.c                    | 17 ++++++++++++++-
 include/linux/mlx5/port.h                     |  3 +++
 include/uapi/linux/ethtool.h                  | 15 +++++++++++++
 net/ethtool/common.c                          | 15 +++++++++++++
 net/ethtool/linkmodes.c                       | 16 ++++++++++++++
 7 files changed, 88 insertions(+), 2 deletions(-)

-- 
2.25.4

[PATCH net-next 1/2] ethtool: Add support for 100Gbps per lane link modes

[Saeed Mahameed]

From: Meir Lichtinger <meirl@mellanox.com>

Define 100G, 200G and 400G link modes using 100Gbps per lane

Signed-off-by: Meir Lichtinger <meirl@mellanox.com>
CC: Andrew Lunn <andrew@lunn.ch>
Reviewed-by: Aya Levin <ayal@mellanox.com>
Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
---
 drivers/net/phy/phy-core.c   | 17 ++++++++++++++++-
 include/uapi/linux/ethtool.h | 15 +++++++++++++++
 net/ethtool/common.c         | 15 +++++++++++++++
 net/ethtool/linkmodes.c      | 16 ++++++++++++++++
 4 files changed, 62 insertions(+), 1 deletion(-)

diff --git a/drivers/net/phy/phy-core.c b/drivers/net/phy/phy-core.c
index 66b8c61ca74c..a71fc8b18973 100644
--- a/drivers/net/phy/phy-core.c
+++ b/drivers/net/phy/phy-core.c
@@ -8,7 +8,7 @@
 
 const char *phy_speed_to_str(int speed)
 {
-	BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 75,
+	BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 90,
 		"Enum ethtool_link_mode_bit_indices and phylib are out of sync. "
 		"If a speed or mode has been added please update phy_speed_to_str "
 		"and the PHY settings array.\n");
@@ -78,12 +78,22 @@ static const struct phy_setting settings[] = {
 	PHY_SETTING( 400000, FULL, 400000baseLR8_ER8_FR8_Full	),
 	PHY_SETTING( 400000, FULL, 400000baseDR8_Full		),
 	PHY_SETTING( 400000, FULL, 400000baseSR8_Full		),
+	PHY_SETTING( 400000, FULL, 400000baseCR4_Full		),
+	PHY_SETTING( 400000, FULL, 400000baseKR4_Full		),
+	PHY_SETTING( 400000, FULL, 400000baseLR4_ER4_FR4_Full	),
+	PHY_SETTING( 400000, FULL, 400000baseDR4_Full		),
+	PHY_SETTING( 400000, FULL, 400000baseSR4_Full		),
 	/* 200G */
 	PHY_SETTING( 200000, FULL, 200000baseCR4_Full		),
 	PHY_SETTING( 200000, FULL, 200000baseKR4_Full		),
 	PHY_SETTING( 200000, FULL, 200000baseLR4_ER4_FR4_Full	),
 	PHY_SETTING( 200000, FULL, 200000baseDR4_Full		),
 	PHY_SETTING( 200000, FULL, 200000baseSR4_Full		),
+	PHY_SETTING( 200000, FULL, 200000baseCR2_Full		),
+	PHY_SETTING( 200000, FULL, 200000baseKR2_Full		),
+	PHY_SETTING( 200000, FULL, 200000baseLR2_ER2_FR2_Full	),
+	PHY_SETTING( 200000, FULL, 200000baseDR2_Full		),
+	PHY_SETTING( 200000, FULL, 200000baseSR2_Full		),
 	/* 100G */
 	PHY_SETTING( 100000, FULL, 100000baseCR4_Full		),
 	PHY_SETTING( 100000, FULL, 100000baseKR4_Full		),
@@ -94,6 +104,11 @@ static const struct phy_setting settings[] = {
 	PHY_SETTING( 100000, FULL, 100000baseLR2_ER2_FR2_Full	),
 	PHY_SETTING( 100000, FULL, 100000baseDR2_Full		),
 	PHY_SETTING( 100000, FULL, 100000baseSR2_Full		),
+	PHY_SETTING( 100000, FULL, 100000baseCR_Full		),
+	PHY_SETTING( 100000, FULL, 100000baseKR_Full		),
+	PHY_SETTING( 100000, FULL, 100000baseLR_ER_FR_Full	),
+	PHY_SETTING( 100000, FULL, 100000baseDR_Full		),
+	PHY_SETTING( 100000, FULL, 100000baseSR_Full		),
 	/* 56G */
 	PHY_SETTING(  56000, FULL,  56000baseCR4_Full	  	),
 	PHY_SETTING(  56000, FULL,  56000baseKR4_Full	  	),
diff --git a/include/uapi/linux/ethtool.h b/include/uapi/linux/ethtool.h
index 92f737f10117..a3829074a336 100644
--- a/include/uapi/linux/ethtool.h
+++ b/include/uapi/linux/ethtool.h
@@ -1530,6 +1530,21 @@ enum ethtool_link_mode_bit_indices {
 	ETHTOOL_LINK_MODE_400000baseDR8_Full_BIT	 = 72,
 	ETHTOOL_LINK_MODE_400000baseCR8_Full_BIT	 = 73,
 	ETHTOOL_LINK_MODE_FEC_LLRS_BIT			 = 74,
+	ETHTOOL_LINK_MODE_100000baseKR_Full_BIT		 = 75,
+	ETHTOOL_LINK_MODE_100000baseSR_Full_BIT		 = 76,
+	ETHTOOL_LINK_MODE_100000baseLR_ER_FR_Full_BIT	 = 77,
+	ETHTOOL_LINK_MODE_100000baseCR_Full_BIT		 = 78,
+	ETHTOOL_LINK_MODE_100000baseDR_Full_BIT		 = 79,
+	ETHTOOL_LINK_MODE_200000baseKR2_Full_BIT	 = 80,
+	ETHTOOL_LINK_MODE_200000baseSR2_Full_BIT	 = 81,
+	ETHTOOL_LINK_MODE_200000baseLR2_ER2_FR2_Full_BIT = 82,
+	ETHTOOL_LINK_MODE_200000baseDR2_Full_BIT	 = 83,
+	ETHTOOL_LINK_MODE_200000baseCR2_Full_BIT	 = 84,
+	ETHTOOL_LINK_MODE_400000baseKR4_Full_BIT	 = 85,
+	ETHTOOL_LINK_MODE_400000baseSR4_Full_BIT	 = 86,
+	ETHTOOL_LINK_MODE_400000baseLR4_ER4_FR4_Full_BIT = 87,
+	ETHTOOL_LINK_MODE_400000baseDR4_Full_BIT	 = 88,
+	ETHTOOL_LINK_MODE_400000baseCR4_Full_BIT	 = 89,
 	/* must be last entry */
 	__ETHTOOL_LINK_MODE_MASK_NBITS
 };
diff --git a/net/ethtool/common.c b/net/ethtool/common.c
index 423e640e3876..ffb50ac66aad 100644
--- a/net/ethtool/common.c
+++ b/net/ethtool/common.c
@@ -173,6 +173,21 @@ const char link_mode_names[][ETH_GSTRING_LEN] = {
 	__DEFINE_LINK_MODE_NAME(400000, DR8, Full),
 	__DEFINE_LINK_MODE_NAME(400000, CR8, Full),
 	__DEFINE_SPECIAL_MODE_NAME(FEC_LLRS, "LLRS"),
+	__DEFINE_LINK_MODE_NAME(100000, KR, Full),
+	__DEFINE_LINK_MODE_NAME(100000, SR, Full),
+	__DEFINE_LINK_MODE_NAME(100000, LR_ER_FR, Full),
+	__DEFINE_LINK_MODE_NAME(100000, DR, Full),
+	__DEFINE_LINK_MODE_NAME(100000, CR, Full),
+	__DEFINE_LINK_MODE_NAME(200000, KR2, Full),
+	__DEFINE_LINK_MODE_NAME(200000, SR2, Full),
+	__DEFINE_LINK_MODE_NAME(200000, LR2_ER2_FR2, Full),
+	__DEFINE_LINK_MODE_NAME(200000, DR2, Full),
+	__DEFINE_LINK_MODE_NAME(200000, CR2, Full),
+	__DEFINE_LINK_MODE_NAME(400000, KR4, Full),
+	__DEFINE_LINK_MODE_NAME(400000, SR4, Full),
+	__DEFINE_LINK_MODE_NAME(400000, LR4_ER4_FR4, Full),
+	__DEFINE_LINK_MODE_NAME(400000, DR4, Full),
+	__DEFINE_LINK_MODE_NAME(400000, CR4, Full),
 };
 static_assert(ARRAY_SIZE(link_mode_names) == __ETHTOOL_LINK_MODE_MASK_NBITS);
 
diff --git a/net/ethtool/linkmodes.c b/net/ethtool/linkmodes.c
index 452608c6d856..ffa02b7c86d5 100644
--- a/net/ethtool/linkmodes.c
+++ b/net/ethtool/linkmodes.c
@@ -238,6 +238,22 @@ static const struct link_mode_info link_mode_params[] = {
 	__DEFINE_LINK_MODE_PARAMS(400000, DR8, Full),
 	__DEFINE_LINK_MODE_PARAMS(400000, CR8, Full),
 	__DEFINE_SPECIAL_MODE_PARAMS(FEC_LLRS),
+	__DEFINE_LINK_MODE_PARAMS(400000, CR8, Full),
+	__DEFINE_LINK_MODE_PARAMS(100000, KR, Full),
+	__DEFINE_LINK_MODE_PARAMS(100000, SR, Full),
+	__DEFINE_LINK_MODE_PARAMS(100000, LR_ER_FR, Full),
+	__DEFINE_LINK_MODE_PARAMS(100000, DR, Full),
+	__DEFINE_LINK_MODE_PARAMS(100000, CR, Full),
+	__DEFINE_LINK_MODE_PARAMS(200000, KR2, Full),
+	__DEFINE_LINK_MODE_PARAMS(200000, SR2, Full),
+	__DEFINE_LINK_MODE_PARAMS(200000, LR2_ER2_FR2, Full),
+	__DEFINE_LINK_MODE_PARAMS(200000, DR2, Full),
+	__DEFINE_LINK_MODE_PARAMS(200000, CR2, Full),
+	__DEFINE_LINK_MODE_PARAMS(400000, KR4, Full),
+	__DEFINE_LINK_MODE_PARAMS(400000, SR4, Full),
+	__DEFINE_LINK_MODE_PARAMS(400000, LR4_ER4_FR4, Full),
+	__DEFINE_LINK_MODE_PARAMS(400000, DR4, Full),
+	__DEFINE_LINK_MODE_PARAMS(400000, CR4, Full),
 };
 
 static const struct nla_policy
-- 
2.25.4

[PATCH net-next 2/2] net/mlx5: Added support for 100Gbps per lane link modes

[Saeed Mahameed]

From: Meir Lichtinger <meirl@mellanox.com>

This patch exposes new link modes using 100Gbps per lane, including 100G,
200G and 400G modes.

Signed-off-by: Meir Lichtinger <meirl@mellanox.com>
Reviewed-by: Aya Levin <ayal@mellanox.com>
Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
---
 .../net/ethernet/mellanox/mlx5/core/en/port.c |  3 +++
 .../ethernet/mellanox/mlx5/core/en_ethtool.c  | 21 ++++++++++++++++++-
 include/linux/mlx5/port.h                     |  3 +++
 3 files changed, 26 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/port.c b/drivers/net/ethernet/mellanox/mlx5/core/en/port.c
index 2c4a670c8ffd..7747b32c1565 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/en/port.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en/port.c
@@ -76,6 +76,9 @@ static const u32 mlx5e_ext_link_speed[MLX5E_EXT_LINK_MODES_NUMBER] = {
 	[MLX5E_100GAUI_2_100GBASE_CR2_KR2]	= 100000,
 	[MLX5E_200GAUI_4_200GBASE_CR4_KR4]	= 200000,
 	[MLX5E_400GAUI_8]			= 400000,
+	[MLX5E_100GAUI_1_100GBASE_CR_KR]	= 100000,
+	[MLX5E_200GAUI_2_200GBASE_CR2_KR2]	= 200000,
+	[MLX5E_400GAUI_4_400GBASE_CR4_KR4]	= 400000,
 };
 
 static void mlx5e_port_get_speed_arr(struct mlx5_core_dev *mdev,
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c b/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c
index 0279bb7246e1..a03bb4145ddb 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c
@@ -194,6 +194,24 @@ void mlx5e_build_ptys2ethtool_map(void)
 				       ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT,
 				       ETHTOOL_LINK_MODE_200000baseDR4_Full_BIT,
 				       ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT);
+	MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GAUI_1_100GBASE_CR_KR, ext,
+				       ETHTOOL_LINK_MODE_100000baseKR_Full_BIT,
+				       ETHTOOL_LINK_MODE_100000baseSR_Full_BIT,
+				       ETHTOOL_LINK_MODE_100000baseLR_ER_FR_Full_BIT,
+				       ETHTOOL_LINK_MODE_100000baseDR_Full_BIT,
+				       ETHTOOL_LINK_MODE_100000baseCR_Full_BIT);
+	MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_200GAUI_2_200GBASE_CR2_KR2, ext,
+				       ETHTOOL_LINK_MODE_200000baseKR2_Full_BIT,
+				       ETHTOOL_LINK_MODE_200000baseSR2_Full_BIT,
+				       ETHTOOL_LINK_MODE_200000baseLR2_ER2_FR2_Full_BIT,
+				       ETHTOOL_LINK_MODE_200000baseDR2_Full_BIT,
+				       ETHTOOL_LINK_MODE_200000baseCR2_Full_BIT);
+	MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_400GAUI_4_400GBASE_CR4_KR4, ext,
+				       ETHTOOL_LINK_MODE_400000baseKR4_Full_BIT,
+				       ETHTOOL_LINK_MODE_400000baseSR4_Full_BIT,
+				       ETHTOOL_LINK_MODE_400000baseLR4_ER4_FR4_Full_BIT,
+				       ETHTOOL_LINK_MODE_400000baseDR4_Full_BIT,
+				       ETHTOOL_LINK_MODE_400000baseCR4_Full_BIT);
 }
 
 static void mlx5e_ethtool_get_speed_arr(struct mlx5_core_dev *mdev,
@@ -997,7 +1015,8 @@ static u32 mlx5e_ethtool2ptys_ext_adver_link(const unsigned long *link_modes)
 	unsigned long modes[2];
 
 	for (i = 0; i < MLX5E_EXT_LINK_MODES_NUMBER; ++i) {
-		if (*ptys2ext_ethtool_table[i].advertised == 0)
+		if (ptys2ext_ethtool_table[i].advertised[0] == 0 &&
+		    ptys2ext_ethtool_table[i].advertised[1] == 0)
 			continue;
 		memset(modes, 0, sizeof(modes));
 		bitmap_and(modes, ptys2ext_ethtool_table[i].advertised,
diff --git a/include/linux/mlx5/port.h b/include/linux/mlx5/port.h
index de9a272c9f3d..2d45a6af52a4 100644
--- a/include/linux/mlx5/port.h
+++ b/include/linux/mlx5/port.h
@@ -104,8 +104,11 @@ enum mlx5e_ext_link_mode {
 	MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR	= 8,
 	MLX5E_CAUI_4_100GBASE_CR4_KR4		= 9,
 	MLX5E_100GAUI_2_100GBASE_CR2_KR2	= 10,
+	MLX5E_100GAUI_1_100GBASE_CR_KR		= 11,
 	MLX5E_200GAUI_4_200GBASE_CR4_KR4	= 12,
+	MLX5E_200GAUI_2_200GBASE_CR2_KR2	= 13,
 	MLX5E_400GAUI_8				= 15,
+	MLX5E_400GAUI_4_400GBASE_CR4_KR4	= 16,
 	MLX5E_EXT_LINK_MODES_NUMBER,
 };
 
-- 
2.25.4

Re: [PATCH net-next 0/2] ethtool: Add support for 100Gbps per lane link modes

[David Miller]

From: Saeed Mahameed <saeedm@mellanox.com>
Date: Thu, 30 Apr 2020 16:41:04 -0700

> This small series adds new ethtool link modes bits to 
> Define 100G, 200G and 400G link modes using 100Gbps per lane.

Andrew, could you please give this series a quick review?

Thank you.

Re: [PATCH net-next 1/2] ethtool: Add support for 100Gbps per lane link modes

[Andrew Lunn]

On Thu, Apr 30, 2020 at 04:41:05PM -0700, Saeed Mahameed wrote:
> From: Meir Lichtinger <meirl@mellanox.com>
> 
> Define 100G, 200G and 400G link modes using 100Gbps per lane
> 
> Signed-off-by: Meir Lichtinger <meirl@mellanox.com>
> CC: Andrew Lunn <andrew@lunn.ch>
> Reviewed-by: Aya Levin <ayal@mellanox.com>
> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
> ---
>  drivers/net/phy/phy-core.c   | 17 ++++++++++++++++-
>  include/uapi/linux/ethtool.h | 15 +++++++++++++++
>  net/ethtool/common.c         | 15 +++++++++++++++
>  net/ethtool/linkmodes.c      | 16 ++++++++++++++++
>  4 files changed, 62 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/net/phy/phy-core.c b/drivers/net/phy/phy-core.c
> index 66b8c61ca74c..a71fc8b18973 100644
> --- a/drivers/net/phy/phy-core.c
> +++ b/drivers/net/phy/phy-core.c
> @@ -8,7 +8,7 @@
>  
>  const char *phy_speed_to_str(int speed)
>  {
> -	BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 75,
> +	BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 90,
>  		"Enum ethtool_link_mode_bit_indices and phylib are out of sync. "
>  		"If a speed or mode has been added please update phy_speed_to_str "
>  		"and the PHY settings array.\n");
> @@ -78,12 +78,22 @@ static const struct phy_setting settings[] = {
>  	PHY_SETTING( 400000, FULL, 400000baseLR8_ER8_FR8_Full	),
>  	PHY_SETTING( 400000, FULL, 400000baseDR8_Full		),
>  	PHY_SETTING( 400000, FULL, 400000baseSR8_Full		),
> +	PHY_SETTING( 400000, FULL, 400000baseCR4_Full		),
> +	PHY_SETTING( 400000, FULL, 400000baseKR4_Full		),
> +	PHY_SETTING( 400000, FULL, 400000baseLR4_ER4_FR4_Full	),

Hi Mier, Saeed.

Could you explain this last one? Seems unlikely this is a 12 pair link
mode. So i assume it is four pair which can do LR4, ER4 or FR4? Can
you connect a 400000baseLR4 to a 400000baseER4 with a 10Km cable and
it work? How do you know you have connected a 400000baseLR4 to a
400000baseER4 with a 40Km and it is not expected to work, when looking
at ethtool? I assume the EEPROM contents tell you if the module is
LR4, ER4, or FR4?

     Andrew

Re: [PATCH net-next 1/2] ethtool: Add support for 100Gbps per lane link modes

[Meir Lichtinger]

On 02-May-20 18:08, Andrew Lunn wrote:
> On Thu, Apr 30, 2020 at 04:41:05PM -0700, Saeed Mahameed wrote:
>> From: Meir Lichtinger <meirl@mellanox.com>
>>
>> Define 100G, 200G and 400G link modes using 100Gbps per lane
>>
>> Signed-off-by: Meir Lichtinger <meirl@mellanox.com>
>> CC: Andrew Lunn <andrew@lunn.ch>
>> Reviewed-by: Aya Levin <ayal@mellanox.com>
>> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
>> ---
>>   drivers/net/phy/phy-core.c   | 17 ++++++++++++++++-
>>   include/uapi/linux/ethtool.h | 15 +++++++++++++++
>>   net/ethtool/common.c         | 15 +++++++++++++++
>>   net/ethtool/linkmodes.c      | 16 ++++++++++++++++
>>   4 files changed, 62 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/net/phy/phy-core.c b/drivers/net/phy/phy-core.c
>> index 66b8c61ca74c..a71fc8b18973 100644
>> --- a/drivers/net/phy/phy-core.c
>> +++ b/drivers/net/phy/phy-core.c
>> @@ -8,7 +8,7 @@
>>   
>>   const char *phy_speed_to_str(int speed)
>>   {
>> -	BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 75,
>> +	BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 90,
>>   		"Enum ethtool_link_mode_bit_indices and phylib are out of sync. "
>>   		"If a speed or mode has been added please update phy_speed_to_str "
>>   		"and the PHY settings array.\n");
>> @@ -78,12 +78,22 @@ static const struct phy_setting settings[] = {
>>   	PHY_SETTING( 400000, FULL, 400000baseLR8_ER8_FR8_Full	),
>>   	PHY_SETTING( 400000, FULL, 400000baseDR8_Full		),
>>   	PHY_SETTING( 400000, FULL, 400000baseSR8_Full		),
>> +	PHY_SETTING( 400000, FULL, 400000baseCR4_Full		),
>> +	PHY_SETTING( 400000, FULL, 400000baseKR4_Full		),
>> +	PHY_SETTING( 400000, FULL, 400000baseLR4_ER4_FR4_Full	),
> Hi Mier, Saeed.
>
> Could you explain this last one? Seems unlikely this is a 12 pair link
> mode. So i assume it is four pair which can do LR4, ER4 or FR4?
Correct
> Can
> you connect a 400000baseLR4 to a 400000baseER4 with a 10Km cable and
> it work?

LR, ER & FR are using same technology – single mode fiber, w/WDM –

and by design are fully interoperable but haven’t tested all combinations.

> How do you know you have connected a 400000baseLR4 to a
> 400000baseER4 with a 40Km and it is not expected to work, when looking
> at ethtool? I assume the EEPROM contents tell you if the module is
> LR4, ER4, or FR4?
>
>       Andrew
Correct.

In addition, this is the terminology exposed in 50 Gbps and we followed it.


Meir

Re: [PATCH net-next 1/2] ethtool: Add support for 100Gbps per lane link modes

[Andrew Lunn]

> > How do you know you have connected a 400000baseLR4 to a
> > 400000baseER4 with a 40Km and it is not expected to work, when looking
> > at ethtool? I assume the EEPROM contents tell you if the module is
> > LR4, ER4, or FR4?
> > 
> >       Andrew
> Correct.

Hi Meir

Do you also have patches to Ethtool to decode these bits in the SFP EEPROM?

> In addition, this is the terminology exposed in 50 Gbps and we
> followed it.

Yes, i missed the patch which added those. I would probably of
objected. But we have them now, so lets keep going. But we might want
a clear definition of when modes can be combined like this.

  Andrew

Re: [PATCH net-next 1/2] ethtool: Add support for 100Gbps per lane link modes

[Meir Lichtinger]

On 11-Jun-20 16:54, Andrew Lunn wrote:
>>> How do you know you have connected a 400000baseLR4 to a
>>> 400000baseER4 with a 40Km and it is not expected to work, when looking
>>> at ethtool? I assume the EEPROM contents tell you if the module is
>>> LR4, ER4, or FR4?
>>>
>>>        Andrew
>> Correct.
> Hi Meir
>
> Do you also have patches to Ethtool to decode these bits in the SFP EEPROM?

Hi Andrew

We are planning on updating the user space ethtool decoder in the future.

If needed, user can use the raw dump now.

Meir

>> In addition, this is the terminology exposed in 50 Gbps and we
>> followed it.
> Yes, i missed the patch which added those. I would probably of
> objected. But we have them now, so lets keep going. But we might want
> a clear definition of when modes can be combined like this.
>
>    Andrew

Re: [PATCH net-next 1/2] ethtool: Add support for 100Gbps per lane link modes

[Saeed Mahameed]

On Thu, 2020-06-11 at 16:19 +0300, Meir Lichtinger wrote:
> On 02-May-20 18:08, Andrew Lunn wrote:
> > On Thu, Apr 30, 2020 at 04:41:05PM -0700, Saeed Mahameed wrote:
> > > From: Meir Lichtinger <meirl@mellanox.com>
> > > 
> > > Define 100G, 200G and 400G link modes using 100Gbps per lane
> > > 
> > > Signed-off-by: Meir Lichtinger <meirl@mellanox.com>
> > > CC: Andrew Lunn <andrew@lunn.ch>
> > > Reviewed-by: Aya Levin <ayal@mellanox.com>
> > > Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
> > > ---
> > >   drivers/net/phy/phy-core.c   | 17 ++++++++++++++++-
> > >   include/uapi/linux/ethtool.h | 15 +++++++++++++++
> > >   net/ethtool/common.c         | 15 +++++++++++++++
> > >   net/ethtool/linkmodes.c      | 16 ++++++++++++++++
> > >   4 files changed, 62 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/drivers/net/phy/phy-core.c b/drivers/net/phy/phy-
> > > core.c
> > > index 66b8c61ca74c..a71fc8b18973 100644
> > > --- a/drivers/net/phy/phy-core.c
> > > +++ b/drivers/net/phy/phy-core.c
> > > @@ -8,7 +8,7 @@
> > >   
> > >   const char *phy_speed_to_str(int speed)
> > >   {
> > > -	BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 75,
> > > +	BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 90,
> > >   		"Enum ethtool_link_mode_bit_indices and phylib
> > > are out of sync. "
> > >   		"If a speed or mode has been added please
> > > update phy_speed_to_str "
> > >   		"and the PHY settings array.\n");
> > > @@ -78,12 +78,22 @@ static const struct phy_setting settings[] =
> > > {
> > >   	PHY_SETTING( 400000, FULL, 400000baseLR8_ER8_FR8_Full	)
> > > ,
> > >   	PHY_SETTING( 400000, FULL, 400000baseDR8_Full		)
> > > ,
> > >   	PHY_SETTING( 400000, FULL, 400000baseSR8_Full		)
> > > ,
> > > +	PHY_SETTING( 400000, FULL, 400000baseCR4_Full		),
> > > +	PHY_SETTING( 400000, FULL, 400000baseKR4_Full		),
> > > +	PHY_SETTING( 400000, FULL, 400000baseLR4_ER4_FR4_Full	),
> > Hi Mier, Saeed.
> > 
> > Could you explain this last one? Seems unlikely this is a 12 pair
> > link
> > mode. So i assume it is four pair which can do LR4, ER4 or FR4?
> Correct
> > Can
> > you connect a 400000baseLR4 to a 400000baseER4 with a 10Km cable
> > and
> > it work?
> 
> LR, ER & FR are using same technology – single mode fiber, w/WDM –
> 
> and by design are fully interoperable but haven’t tested all
> combinations.
> 
> > How do you know you have connected a 400000baseLR4 to a
> > 400000baseER4 with a 40Km and it is not expected to work, when
> > looking
> > at ethtool? I assume the EEPROM contents tell you if the module is
> > LR4, ER4, or FR4?
> > 
> >       Andrew
> Correct.
> 
> In addition, this is the terminology exposed in 50 Gbps and we
> followed it.
> 

Hi Andrew,

we are going to update the commit message with:

    LR, ER and FR are defined as a single link mode because they are
    using same technology and by design are fully interoperable.
    EEPROM content indicates if the module is LR, ER, or FR, and the
    user space ethtool decoder is planned to support decoding these    
    modes in the EEPROM.

Please let me know it this answer your questions, so we can re-spin
this patch.

Thanks,
Saeed.

Re: [PATCH net-next 1/2] ethtool: Add support for 100Gbps per lane link modes

[Andrew Lunn]

> Hi Andrew,
> 
> we are going to update the commit message with:
> 
>     LR, ER and FR are defined as a single link mode because they are
>     using same technology and by design are fully interoperable.
>     EEPROM content indicates if the module is LR, ER, or FR, and the
>     user space ethtool decoder is planned to support decoding these    
>     modes in the EEPROM.
> 
> Please let me know it this answer your questions, so we can re-spin
> this patch.

Hi Saeed.

This looks good to me.

Thanks
	Andrew