From mboxrd@z Thu Jan 1 00:00:00 1970 From: Vignesh Raghavendra Date: Mon, 6 Jul 2020 13:36:53 +0530 Subject: [PATCH 2/5] net: ti: am65-cpsw-nuss: Set ALE default thread enable In-Reply-To: <20200706080656.19460-1-vigneshr@ti.com> References: <20200706080656.19460-1-vigneshr@ti.com> Message-ID: <20200706080656.19460-3-vigneshr@ti.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Force default thread to be used for RX as ALE is anyways set to Bypass mode. Signed-off-by: Vignesh Raghavendra --- drivers/net/ti/am65-cpsw-nuss.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/net/ti/am65-cpsw-nuss.c b/drivers/net/ti/am65-cpsw-nuss.c index e8fe875e70..753a117300 100644 --- a/drivers/net/ti/am65-cpsw-nuss.c +++ b/drivers/net/ti/am65-cpsw-nuss.c @@ -61,6 +61,9 @@ #define AM65_CPSW_ALE_PN_CTL_REG_MODE_FORWARD 0x3 #define AM65_CPSW_ALE_PN_CTL_REG_MAC_ONLY BIT(11) +#define AM65_CPSW_ALE_THREADMAPDEF_REG 0x134 +#define AM65_CPSW_ALE_DEFTHREAD_EN BIT(15) + #define AM65_CPSW_MACSL_CTL_REG 0x0 #define AM65_CPSW_MACSL_CTL_REG_IFCTL_A BIT(15) #define AM65_CPSW_MACSL_CTL_EXT_EN BIT(18) @@ -364,6 +367,9 @@ static int am65_cpsw_start(struct udevice *dev) writel(AM65_CPSW_ALE_PN_CTL_REG_MODE_FORWARD, common->ale_base + AM65_CPSW_ALE_PN_CTL_REG(0)); + writel(AM65_CPSW_ALE_DEFTHREAD_EN, + common->ale_base + AM65_CPSW_ALE_THREADMAPDEF_REG); + /* PORT x configuration */ /* Port x Max length register */ -- 2.27.0