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From: Vignesh Raghavendra <vigneshr@ti.com>
To: u-boot@lists.denx.de
Subject: [PATCH 5/5] arm: dts: k3-am65: Sync CPSW DT node from kernel
Date: Mon, 6 Jul 2020 13:36:56 +0530	[thread overview]
Message-ID: <20200706080656.19460-6-vigneshr@ti.com> (raw)
In-Reply-To: <20200706080656.19460-1-vigneshr@ti.com>

Sync CPSW DT node from kernel and move it out of -u-boot.dtsi file.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
---
 arch/arm/dts/k3-am65-mcu.dtsi                | 84 ++++++++++++++++++++
 arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 54 +------------
 2 files changed, 85 insertions(+), 53 deletions(-)

diff --git a/arch/arm/dts/k3-am65-mcu.dtsi b/arch/arm/dts/k3-am65-mcu.dtsi
index d1a9fb5de6..1355685839 100644
--- a/arch/arm/dts/k3-am65-mcu.dtsi
+++ b/arch/arm/dts/k3-am65-mcu.dtsi
@@ -6,6 +6,20 @@
  */
 
 &cbass_mcu {
+	mcu_conf: scm_conf at 40f00000 {
+		compatible = "syscon", "simple-mfd";
+		reg = <0x0 0x40f00000 0x0 0x20000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x0 0x0 0x40f00000 0x20000>;
+
+		phy_gmii_sel: phy at 4040 {
+			compatible = "ti,am654-phy-gmii-sel";
+			reg = <0x4040 0x4>;
+			#phy-cells = <1>;
+		};
+	};
+
 	mcu_uart0: serial at 40a00000 {
 		compatible = "ti,am654-uart";
 			reg = <0x00 0x40a00000 0x00 0x100>;
@@ -146,4 +160,74 @@
 			ti,sci-rm-range-rflow = <0x5>; /* GP RFLOW */
 		};
 	};
+
+	mcu_cpsw: ethernet at 46000000 {
+		compatible = "ti,am654-cpsw-nuss";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		reg = <0x0 0x46000000 0x0 0x200000>;
+		reg-names = "cpsw_nuss";
+		ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
+		dma-coherent;
+		clocks = <&k3_clks 5 10>;
+		clock-names = "fck";
+		power-domains = <&k3_pds 5 TI_SCI_PD_EXCLUSIVE>;
+
+		dmas = <&mcu_udmap 0xf000>,
+		       <&mcu_udmap 0xf001>,
+		       <&mcu_udmap 0xf002>,
+		       <&mcu_udmap 0xf003>,
+		       <&mcu_udmap 0xf004>,
+		       <&mcu_udmap 0xf005>,
+		       <&mcu_udmap 0xf006>,
+		       <&mcu_udmap 0xf007>,
+		       <&mcu_udmap 0x7000>;
+		dma-names = "tx0", "tx1", "tx2", "tx3",
+			    "tx4", "tx5", "tx6", "tx7",
+			    "rx";
+
+		ethernet-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			cpsw_port1: port at 1 {
+				reg = <1>;
+				ti,mac-only;
+				label = "port1";
+				ti,syscon-efuse = <&mcu_conf 0x200>;
+				phys = <&phy_gmii_sel 1>;
+			};
+		};
+
+		davinci_mdio: mdio at f00 {
+			compatible = "ti,cpsw-mdio","ti,davinci_mdio";
+			reg = <0x0 0xf00 0x0 0x100>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&k3_clks 5 10>;
+			clock-names = "fck";
+			bus_freq = <1000000>;
+		};
+
+		cpts at 3d000 {
+			compatible = "ti,am65-cpts";
+			reg = <0x0 0x3d000 0x0 0x400>;
+			clocks = <&mcu_cpsw_cpts_mux>;
+			clock-names = "cpts";
+			interrupts-extended = <&gic500 GIC_SPI 570 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "cpts";
+			ti,cpts-ext-ts-inputs = <4>;
+			ti,cpts-periodic-outputs = <2>;
+
+			mcu_cpsw_cpts_mux: refclk-mux {
+				#clock-cells = <0>;
+				clocks = <&k3_clks 118 5>, <&k3_clks 118 11>,
+					<&k3_clks 118 6>, <&k3_clks 118 3>,
+					<&k3_clks 118 8>, <&k3_clks 118 14>,
+					<&k3_clks 120 3>, <&k3_clks 121 3>;
+				assigned-clocks = <&mcu_cpsw_cpts_mux>;
+				assigned-clock-parents = <&k3_clks 118 5>;
+			};
+		};
+	};
 };
diff --git a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
index 1a40fa12b7..d9ff3ed47b 100644
--- a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
@@ -57,59 +57,6 @@
 			u-boot,dm-spl;
 		};
 	};
-
-	mcu_conf: scm_conf at 40f00000 {
-		compatible = "syscon";
-		reg = <0x0 0x40f00000 0x0 0x20000>;
-	};
-
-	mcu_cpsw: cpsw_nuss at 046000000 {
-		compatible = "ti,am654-cpsw-nuss";
-		#address-cells = <2>;
-		#size-cells = <2>;
-		reg = <0x0 0x46000000 0x0 0x200000>;
-		reg-names = "cpsw_nuss";
-		ranges;
-		dma-coherent;
-		clocks = <&k3_clks 5 10>;
-		clock-names = "fck";
-		power-domains = <&k3_pds 5 TI_SCI_PD_EXCLUSIVE>;
-
-		dmas = <&mcu_udmap 0xf000>,
-		       <&mcu_udmap 0xf001>,
-		       <&mcu_udmap 0xf002>,
-		       <&mcu_udmap 0xf003>,
-		       <&mcu_udmap 0xf004>,
-		       <&mcu_udmap 0xf005>,
-		       <&mcu_udmap 0xf006>,
-		       <&mcu_udmap 0xf007>,
-		       <&mcu_udmap 0x7000>;
-		dma-names = "tx0", "tx1", "tx2", "tx3",
-			    "tx4", "tx5", "tx6", "tx7",
-			    "rx";
-
-		ports {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			host: host at 0 {
-				reg = <0>;
-				ti,label = "host";
-			};
-
-			cpsw_port1: port at 1 {
-				reg = <1>;
-				ti,mac-only;
-				ti,label = "port1";
-				ti,syscon-efuse = <&mcu_conf 0x200>;
-			};
-		};
-
-		davinci_mdio: mdio {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			bus_freq = <1000000>;
-		};
-	};
 };
 
 &cbass_wakeup {
@@ -271,6 +218,7 @@
 	reg = <0x0 0x46000000 0x0 0x200000>,
 	      <0x0 0x40f00200 0x0 0x2>;
 	reg-names = "cpsw_nuss", "mac_efuse";
+	/delete-property/ ranges;
 
 	cpsw-phy-sel at 40f04040 {
 		compatible = "ti,am654-cpsw-phy-sel";
-- 
2.27.0

  parent reply	other threads:[~2020-07-06  8:06 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-07-06  8:06 [PATCH 0/5] TI: AM654/J721e: Sync CPSW DT node from kernel Vignesh Raghavendra
2020-07-06  8:06 ` [PATCH 1/5] net: ti: am65-cpsw-nuss: Remove dead code Vignesh Raghavendra
2020-07-06  8:06 ` [PATCH 2/5] net: ti: am65-cpsw-nuss: Set ALE default thread enable Vignesh Raghavendra
2020-07-06  8:06 ` [PATCH 3/5] net: ti: am65-cpsw-nuss: Update driver to use kernel DT Vignesh Raghavendra
2020-07-06  8:06 ` [PATCH 4/5] arm: dts: k3-j721e: Sync CPSW DT node from kernel Vignesh Raghavendra
2020-07-07 13:49   ` Grygorii Strashko
2020-07-07 14:15     ` Vignesh Raghavendra
2020-07-08  7:55       ` Lokesh Vutla
2020-07-06  8:06 ` Vignesh Raghavendra [this message]
2020-07-07 13:50 ` [PATCH 0/5] TI: AM654/J721e: " Grygorii Strashko
2020-07-14  5:41 ` Lokesh Vutla

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