From: "Luck, Tony" <tony.luck@intel.com>
To: Tony W Wang-oc <TonyWWang-oc@zhaoxin.com>
Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de,
x86@kernel.org, hpa@zytor.com, pawan.kumar.gupta@linux.intel.com,
jpoimboe@redhat.com, peterz@infradead.org, thellstrom@vmware.com,
mgross@linux.intel.com, kim.phillips@amd.com,
linux-kernel@vger.kernel.org, DavidWang@zhaoxin.com,
CooperYan@zhaoxin.com, QiyuanWang@zhaoxin.com,
HerryYang@zhaoxin.com, CobeChen@zhaoxin.com
Subject: Re: [PATCH] x86/cpufeatures: Add new Zhaoxin CPU features
Date: Mon, 6 Jul 2020 09:02:28 -0700 [thread overview]
Message-ID: <20200706160228.GA4663@agluck-desk2.amr.corp.intel.com> (raw)
In-Reply-To: <1593429689-25131-1-git-send-email-TonyWWang-oc@zhaoxin.com>
On Mon, Jun 29, 2020 at 07:21:29PM +0800, Tony W Wang-oc wrote:
> Add new Zhaoxin CPU features for enumeration in /proc/cpuinfo:
> SM2, SM2_EN, SM3, SM4, SM3_EN, SM4_EN, PARALLAX, PARALLAX_EN,
> TM3, TM3_EN, RNG2, RNG2_EN, PHE2, PHE2_EN, RSA, RSA_EN.
>
> CPUID.(EAX=0xc0000001,ECX=0):EDX[bit 0] SM2
> CPUID.(EAX=0xc0000001,ECX=0):EDX[bit 1] SM2_EN
> CPUID.(EAX=0xc0000001,ECX=0):EDX[bit 4] SM3 SM4
> CPUID.(EAX=0xc0000001,ECX=0):EDX[bit 5] SM3_EN SM4_EN
> CPUID.(EAX=0xc0000001,ECX=0):EDX[bit 16] PARALLAX
> CPUID.(EAX=0xc0000001,ECX=0):EDX[bit 17] PARALLAX_EN
> CPUID.(EAX=0xc0000001,ECX=0):EDX[bit 20] TM3
> CPUID.(EAX=0xc0000001,ECX=0):EDX[bit 21] TM3_EN
> CPUID.(EAX=0xc0000001,ECX=0):EDX[bit 22] RNG2
> CPUID.(EAX=0xc0000001,ECX=0):EDX[bit 23] RNG2_EN
> CPUID.(EAX=0xc0000001,ECX=0):EDX[bit 25] PHE2
> CPUID.(EAX=0xc0000001,ECX=0):EDX[bit 26] PHE2_EN
> CPUID.(EAX=0xc0000001,ECX=0):EDX[bit 27] RSA
> CPUID.(EAX=0xc0000001,ECX=0):EDX[bit 28] RSA_EN
>
> SM2, SM3, SM4 are Chinese Cipher Security algorithm.
> PARALLAX is a feature that automatically adjusts processors's voltage
> as a function of temperature.
> TM3 is Zhaoxin CPU Thermal Monitor v3.
> RNG2 is Zhaoxin Random Number Generation v2.
> PHE2 is Zhaoxin Padlock Hash Engine v2.
> RSA is Zhaoxin hardware support for RSA algorithm.
Boris is on vacation, so I'll ask the question that he would ask
if he were here ... "Are there some follow-up patches that use all
of these feature bits?"
Just adding bits to /proc/cpuinfo is of limited use.
-Tony
next prev parent reply other threads:[~2020-07-06 16:02 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-29 11:21 [PATCH] x86/cpufeatures: Add new Zhaoxin CPU features Tony W Wang-oc
2020-07-06 16:02 ` Luck, Tony [this message]
2020-07-07 2:43 ` Tony W Wang-oc
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