[PATCH v2 1/4] dt-bindings: clk: versaclock5: fix 'idt' prefix typos

[PATCH v2 1/4] dt-bindings: clk: versaclock5: fix 'idt' prefix typos

[Luca Ceresoli]

'idt' is misspelled 'itd' in a few places, fix it.

Fixes: 34662f6e3084 ("dt: Add additional option bindings for IDT VersaClock")
Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net>
---
 Documentation/devicetree/bindings/clock/idt,versaclock5.txt | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/idt,versaclock5.txt b/Documentation/devicetree/bindings/clock/idt,versaclock5.txt
index 6165b6ddb1a9..9656d4cf221c 100644
--- a/Documentation/devicetree/bindings/clock/idt,versaclock5.txt
+++ b/Documentation/devicetree/bindings/clock/idt,versaclock5.txt
@@ -35,7 +35,7 @@ For all output ports, a corresponding, optional child node named OUT1,
 OUT2, etc. can represent a each output, and the node can be used to
 specify the following:
 
-- itd,mode: can be one of the following:
+- idt,mode: can be one of the following:
                  - VC5_LVPECL
                  - VC5_CMOS
                  - VC5_HCSL33
@@ -106,7 +106,7 @@ i2c-master-node {
 		clock-names = "xin";
 
 		OUT1 {
-			itd,mode = <VC5_CMOS>;
+			idt,mode = <VC5_CMOS>;
 			idt,voltage-microvolts = <1800000>;
 			idt,slew-percent = <80>;
 		};
-- 
2.27.0

[PATCH v2 2/4] MAINTAINERS: take over IDT VersaClock 5 clock driver

[Luca Ceresoli]

Marek has been the primary developer of this driver (thanks!). Now as
he is not working on it anymore he suggested I take over maintainership.

Cc: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net>
---
 MAINTAINERS | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 68f21d46614c..5aa16c245c63 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -8324,7 +8324,7 @@ W:	https://github.com/o2genum/ideapad-slidebar
 F:	drivers/input/misc/ideapad_slidebar.c
 
 IDT VersaClock 5 CLOCK DRIVER
-M:	Marek Vasut <marek.vasut@gmail.com>
+M:	Luca Ceresoli <luca@lucaceresoli.net>
 S:	Maintained
 F:	drivers/clk/clk-versaclock5.c
 
-- 
2.27.0

[PATCH v2 3/4] clk: vc5: use a dedicated struct to describe the output drivers

[Luca Ceresoli]

Reusing the generic struct vc5_hw_data for all blocks is handy. However it
implies we allocate space the div_int and div_frc fields even for the
output drivers where they are unused, and the clk_output_cfg0 and
clk_output_cfg0_mask fields that are used only for the output
drivers.

Use a dedicated struct for the output drivers so that each block uses
exactly the fields it needs, not more.

Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net>
---
 drivers/clk/clk-versaclock5.c | 24 +++++++++++++++---------
 1 file changed, 15 insertions(+), 9 deletions(-)

diff --git a/drivers/clk/clk-versaclock5.c b/drivers/clk/clk-versaclock5.c
index 9a5fb3834b9a..944c7c7c843f 100644
--- a/drivers/clk/clk-versaclock5.c
+++ b/drivers/clk/clk-versaclock5.c
@@ -167,6 +167,12 @@ struct vc5_hw_data {
 	u32			div_int;
 	u32			div_frc;
 	unsigned int		num;
+};
+
+struct vc5_out_data {
+	struct clk_hw		hw;
+	struct vc5_driver_data	*vc5;
+	unsigned int		num;
 	unsigned int		clk_output_cfg0;
 	unsigned int		clk_output_cfg0_mask;
 };
@@ -184,7 +190,7 @@ struct vc5_driver_data {
 	struct clk_hw		clk_pfd;
 	struct vc5_hw_data	clk_pll;
 	struct vc5_hw_data	clk_fod[VC5_MAX_FOD_NUM];
-	struct vc5_hw_data	clk_out[VC5_MAX_CLK_OUT_NUM];
+	struct vc5_out_data	clk_out[VC5_MAX_CLK_OUT_NUM];
 };
 
 /*
@@ -567,7 +573,7 @@ static const struct clk_ops vc5_fod_ops = {
 
 static int vc5_clk_out_prepare(struct clk_hw *hw)
 {
-	struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
+	struct vc5_out_data *hwdata = container_of(hw, struct vc5_out_data, hw);
 	struct vc5_driver_data *vc5 = hwdata->vc5;
 	const u8 mask = VC5_OUT_DIV_CONTROL_SELB_NORM |
 			VC5_OUT_DIV_CONTROL_SEL_EXT |
@@ -609,7 +615,7 @@ static int vc5_clk_out_prepare(struct clk_hw *hw)
 
 static void vc5_clk_out_unprepare(struct clk_hw *hw)
 {
-	struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
+	struct vc5_out_data *hwdata = container_of(hw, struct vc5_out_data, hw);
 	struct vc5_driver_data *vc5 = hwdata->vc5;
 
 	/* Disable the clock buffer */
@@ -619,7 +625,7 @@ static void vc5_clk_out_unprepare(struct clk_hw *hw)
 
 static unsigned char vc5_clk_out_get_parent(struct clk_hw *hw)
 {
-	struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
+	struct vc5_out_data *hwdata = container_of(hw, struct vc5_out_data, hw);
 	struct vc5_driver_data *vc5 = hwdata->vc5;
 	const u8 mask = VC5_OUT_DIV_CONTROL_SELB_NORM |
 			VC5_OUT_DIV_CONTROL_SEL_EXT |
@@ -649,7 +655,7 @@ static unsigned char vc5_clk_out_get_parent(struct clk_hw *hw)
 
 static int vc5_clk_out_set_parent(struct clk_hw *hw, u8 index)
 {
-	struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
+	struct vc5_out_data *hwdata = container_of(hw, struct vc5_out_data, hw);
 	struct vc5_driver_data *vc5 = hwdata->vc5;
 	const u8 mask = VC5_OUT_DIV_CONTROL_RESET |
 			VC5_OUT_DIV_CONTROL_SELB_NORM |
@@ -704,7 +710,7 @@ static int vc5_map_index_to_output(const enum vc5_model model,
 }
 
 static int vc5_update_mode(struct device_node *np_output,
-			   struct vc5_hw_data *clk_out)
+			   struct vc5_out_data *clk_out)
 {
 	u32 value;
 
@@ -729,7 +735,7 @@ static int vc5_update_mode(struct device_node *np_output,
 }
 
 static int vc5_update_power(struct device_node *np_output,
-			    struct vc5_hw_data *clk_out)
+			    struct vc5_out_data *clk_out)
 {
 	u32 value;
 
@@ -754,7 +760,7 @@ static int vc5_update_power(struct device_node *np_output,
 }
 
 static int vc5_update_slew(struct device_node *np_output,
-			   struct vc5_hw_data *clk_out)
+			   struct vc5_out_data *clk_out)
 {
 	u32 value;
 
@@ -782,7 +788,7 @@ static int vc5_update_slew(struct device_node *np_output,
 }
 
 static int vc5_get_output_config(struct i2c_client *client,
-				 struct vc5_hw_data *clk_out)
+				 struct vc5_out_data *clk_out)
 {
 	struct device_node *np_output;
 	char *child_name;
-- 
2.27.0

[PATCH v2 4/4] dt-bindings: clk: versaclock5: convert to yaml

[Luca Ceresoli]

Convert to yaml the VersaClock bindings document. The mapping between
clock specifier and physical pins cannot be described formally in yaml
schema, then keep it verbatim in the description field.

Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net>
---
 .../bindings/clock/idt,versaclock5.txt        | 125 --------------
 .../bindings/clock/idt,versaclock5.yaml       | 160 ++++++++++++++++++
 MAINTAINERS                                   |   1 +
 3 files changed, 161 insertions(+), 125 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/clock/idt,versaclock5.txt
 create mode 100644 Documentation/devicetree/bindings/clock/idt,versaclock5.yaml

diff --git a/Documentation/devicetree/bindings/clock/idt,versaclock5.txt b/Documentation/devicetree/bindings/clock/idt,versaclock5.txt
deleted file mode 100644
index 9656d4cf221c..000000000000
--- a/Documentation/devicetree/bindings/clock/idt,versaclock5.txt
+++ /dev/null
@@ -1,125 +0,0 @@
-Binding for IDT VersaClock 5,6 programmable i2c clock generators.
-
-The IDT VersaClock 5 and VersaClock 6 are programmable i2c clock
-generators providing from 3 to 12 output clocks.
-
-==I2C device node==
-
-Required properties:
-- compatible:	shall be one of
-		"idt,5p49v5923"
-		"idt,5p49v5925"
-		"idt,5p49v5933"
-		"idt,5p49v5935"
-		"idt,5p49v6901"
-		"idt,5p49v6965"
-- reg:		i2c device address, shall be 0x68 or 0x6a.
-- #clock-cells:	from common clock binding; shall be set to 1.
-- clocks:	from common clock binding; list of parent clock handles,
-		- 5p49v5923 and
-		  5p49v5925 and
-		  5p49v6901: (required) either or both of XTAL or CLKIN
-					reference clock.
-		- 5p49v5933 and
-		- 5p49v5935: (optional) property not present (internal
-					Xtal used) or CLKIN reference
-					clock.
-- clock-names:	from common clock binding; clock input names, can be
-		- 5p49v5923 and
-		  5p49v5925 and
-		  5p49v6901: (required) either or both of "xin", "clkin".
-		- 5p49v5933 and
-		- 5p49v5935: (optional) property not present or "clkin".
-
-For all output ports, a corresponding, optional child node named OUT1,
-OUT2, etc. can represent a each output, and the node can be used to
-specify the following:
-
-- idt,mode: can be one of the following:
-                 - VC5_LVPECL
-                 - VC5_CMOS
-                 - VC5_HCSL33
-                 - VC5_LVDS
-                 - VC5_CMOS2
-                 - VC5_CMOSD
-                 - VC5_HCSL25
-
-- idt,voltage-microvolts:  can be one of the following
-                 - 1800000
-                 - 2500000
-                 - 3300000
--  idt,slew-percent: Percent of normal, can be one of
-                 - 80
-                 - 85
-                 - 90
-                 - 100
-
-==Mapping between clock specifier and physical pins==
-
-When referencing the provided clock in the DT using phandle and
-clock specifier, the following mapping applies:
-
-5P49V5923:
-	0 -- OUT0_SEL_I2CB
-	1 -- OUT1
-	2 -- OUT2
-
-5P49V5933:
-	0 -- OUT0_SEL_I2CB
-	1 -- OUT1
-	2 -- OUT4
-
-5P49V5925 and
-5P49V5935:
-	0 -- OUT0_SEL_I2CB
-	1 -- OUT1
-	2 -- OUT2
-	3 -- OUT3
-	4 -- OUT4
-
-5P49V6901:
-	0 -- OUT0_SEL_I2CB
-	1 -- OUT1
-	2 -- OUT2
-	3 -- OUT3
-	4 -- OUT4
-
-==Example==
-
-/* 25MHz reference crystal */
-ref25: ref25m {
-	compatible = "fixed-clock";
-	#clock-cells = <0>;
-	clock-frequency = <25000000>;
-};
-
-i2c-master-node {
-
-	/* IDT 5P49V5923 i2c clock generator */
-	vc5: clock-generator@6a {
-		compatible = "idt,5p49v5923";
-		reg = <0x6a>;
-		#clock-cells = <1>;
-
-		/* Connect XIN input to 25MHz reference */
-		clocks = <&ref25m>;
-		clock-names = "xin";
-
-		OUT1 {
-			idt,mode = <VC5_CMOS>;
-			idt,voltage-microvolts = <1800000>;
-			idt,slew-percent = <80>;
-		};
-		OUT2 {
-			...
-		};
-		...
-	};
-};
-
-/* Consumer referencing the 5P49V5923 pin OUT1 */
-consumer {
-	...
-	clocks = <&vc5 1>;
-	...
-}
diff --git a/Documentation/devicetree/bindings/clock/idt,versaclock5.yaml b/Documentation/devicetree/bindings/clock/idt,versaclock5.yaml
new file mode 100644
index 000000000000..4bdfd6187b48
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/idt,versaclock5.yaml
@@ -0,0 +1,160 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/idt,versaclock5.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Binding for IDT VersaClock 5 and 6 programmable I2C clock generators
+
+description: |
+  The IDT VersaClock 5 and VersaClock 6 are programmable I2C
+  clock generators providing from 3 to 12 output clocks.
+
+  When referencing the provided clock in the DT using phandle and clock
+  specifier, the following mapping applies:
+
+  - 5P49V5923:
+    0 -- OUT0_SEL_I2CB
+    1 -- OUT1
+    2 -- OUT2
+
+  - 5P49V5933:
+    0 -- OUT0_SEL_I2CB
+    1 -- OUT1
+    2 -- OUT4
+
+  - other parts:
+    0 -- OUT0_SEL_I2CB
+    1 -- OUT1
+    2 -- OUT2
+    3 -- OUT3
+    4 -- OUT4
+
+maintainers:
+  - Luca Ceresoli <luca@lucaceresoli.net>
+
+properties:
+  compatible:
+    enum:
+      - idt,5p49v5923
+      - idt,5p49v5925
+      - idt,5p49v5933
+      - idt,5p49v5935
+      - idt,5p49v6901
+      - idt,5p49v6965
+
+  reg:
+    maxItems: 1
+    description: I2C device address, shall be 0x68 or 0x6a.
+
+  '#clock-cells':
+    const: 1
+
+patternProperties:
+  "^OUT[1-4]$":
+    type: object
+    description:
+      Description of one of the outputs (OUT1..OUT4). See "Clock1 Output
+      Configuration" in the Versaclock 5/6/6E Family Register Description
+      and Programming Guide.
+    properties:
+      idt,mode:
+        description:
+          The output drive mode. Values defined in dt-bindings/clk/versaclock.h
+        enum:
+          - VC5_LVPECL
+          - VC5_CMOS
+          - VC5_HCSL33
+          - VC5_LVDS
+          - VC5_CMOS2
+          - VC5_CMOSD
+          - VC5_HCSL25
+      idt,voltage-microvolts:
+        description: The output drive voltage.
+        $ref: /schemas/types.yaml#/definitions/uint32
+        enum: [ 1800000, 2500000, 3300000 ]
+      idt,slew-percent:
+        description: The Slew rate control for CMOS single-ended.
+        $ref: /schemas/types.yaml#/definitions/uint32
+        enum: [ 80, 85, 90, 100 ]
+
+required:
+  - compatible
+  - reg
+  - '#clock-cells'
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - idt,5p49v5933
+              - idt,5p49v5935
+    then:
+      # Devices with builtin crystal, optional external input
+      properties:
+        clock-names:
+          const: clkin
+        clocks:
+          maxItems: 1
+    else:
+      # Devices without builtin crystal
+      properties:
+        clock-names:
+          anyOf:
+            - required: [ xin ]
+            - required: [ clkin ]
+        clocks:
+          minItems: 1
+          maxItems: 2
+      required:
+        - clock-names
+        - clocks
+
+examples:
+  - |
+    #include <dt-bindings/clk/versaclock.h>
+
+    /* 25MHz reference crystal */
+    ref25: ref25m {
+        compatible = "fixed-clock";
+        #clock-cells = <0>;
+        clock-frequency = <25000000>;
+    };
+
+    i2c@0 {
+        reg = <0x0 0x100>;
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        /* IDT 5P49V5923 I2C clock generator */
+        vc5: clock-generator@6a {
+            compatible = "idt,5p49v5923";
+            reg = <0x6a>;
+            #clock-cells = <1>;
+
+            /* Connect XIN input to 25MHz reference */
+            clocks = <&ref25m>;
+            clock-names = "xin";
+
+            OUT1 {
+                idt,drive-mode = <VC5_CMOSD>;
+                idt,voltage-microvolts = <1800000>;
+                idt,slew-percent = <80>;
+            };
+
+            OUT4 {
+                idt,drive-mode = <VC5_LVDS>;
+            };
+        };
+    };
+
+    /* Consumer referencing the 5P49V5923 pin OUT1 */
+    consumer {
+        /* ... */
+        clocks = <&vc5 1>;
+        /* ... */
+    };
+
+...
diff --git a/MAINTAINERS b/MAINTAINERS
index 5aa16c245c63..09d6efd1d0d0 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -8326,6 +8326,7 @@ F:	drivers/input/misc/ideapad_slidebar.c
 IDT VersaClock 5 CLOCK DRIVER
 M:	Luca Ceresoli <luca@lucaceresoli.net>
 S:	Maintained
+F:	Documentation/devicetree/bindings/clock/idt,versaclock5.yaml
 F:	drivers/clk/clk-versaclock5.c
 
 IEEE 802.15.4 SUBSYSTEM
-- 
2.27.0

Re: [PATCH v2 1/4] dt-bindings: clk: versaclock5: fix 'idt' prefix typos

[Luca Ceresoli]

Hi,

On 08/07/20 09:40, Luca Ceresoli wrote:
> 'idt' is misspelled 'itd' in a few places, fix it.
> 
> Fixes: 34662f6e3084 ("dt: Add additional option bindings for IDT VersaClock")

This line triggers a warning in patchwork:

WARNING: Unknown commit id '34662f6e3084', maybe rebased or not pulled?

The commit is in the clk-next branch of
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git, and thus
supposed to be merged into mainline.

-- 
Luca

Re: [PATCH v2 1/4] dt-bindings: clk: versaclock5: fix 'idt' prefix typos

[Rob Herring]

On Wed, 08 Jul 2020 09:40:32 +0200, Luca Ceresoli wrote:
> 'idt' is misspelled 'itd' in a few places, fix it.
> 
> Fixes: 34662f6e3084 ("dt: Add additional option bindings for IDT VersaClock")
> Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net>
> ---
>  Documentation/devicetree/bindings/clock/idt,versaclock5.txt | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 

Reviewed-by: Rob Herring <robh@kernel.org>

Re: [PATCH v2 4/4] dt-bindings: clk: versaclock5: convert to yaml

[Rob Herring]

On Wed, Jul 08, 2020 at 09:40:35AM +0200, Luca Ceresoli wrote:
> Convert to yaml the VersaClock bindings document. The mapping between
> clock specifier and physical pins cannot be described formally in yaml
> schema, then keep it verbatim in the description field.
> 
> Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net>
> ---
>  .../bindings/clock/idt,versaclock5.txt        | 125 --------------
>  .../bindings/clock/idt,versaclock5.yaml       | 160 ++++++++++++++++++
>  MAINTAINERS                                   |   1 +
>  3 files changed, 161 insertions(+), 125 deletions(-)
>  delete mode 100644 Documentation/devicetree/bindings/clock/idt,versaclock5.txt
>  create mode 100644 Documentation/devicetree/bindings/clock/idt,versaclock5.yaml
> 
> diff --git a/Documentation/devicetree/bindings/clock/idt,versaclock5.txt b/Documentation/devicetree/bindings/clock/idt,versaclock5.txt
> deleted file mode 100644
> index 9656d4cf221c..000000000000
> --- a/Documentation/devicetree/bindings/clock/idt,versaclock5.txt
> +++ /dev/null
> @@ -1,125 +0,0 @@
> -Binding for IDT VersaClock 5,6 programmable i2c clock generators.
> -
> -The IDT VersaClock 5 and VersaClock 6 are programmable i2c clock
> -generators providing from 3 to 12 output clocks.
> -
> -==I2C device node==
> -
> -Required properties:
> -- compatible:	shall be one of
> -		"idt,5p49v5923"
> -		"idt,5p49v5925"
> -		"idt,5p49v5933"
> -		"idt,5p49v5935"
> -		"idt,5p49v6901"
> -		"idt,5p49v6965"
> -- reg:		i2c device address, shall be 0x68 or 0x6a.
> -- #clock-cells:	from common clock binding; shall be set to 1.
> -- clocks:	from common clock binding; list of parent clock handles,
> -		- 5p49v5923 and
> -		  5p49v5925 and
> -		  5p49v6901: (required) either or both of XTAL or CLKIN
> -					reference clock.
> -		- 5p49v5933 and
> -		- 5p49v5935: (optional) property not present (internal
> -					Xtal used) or CLKIN reference
> -					clock.
> -- clock-names:	from common clock binding; clock input names, can be
> -		- 5p49v5923 and
> -		  5p49v5925 and
> -		  5p49v6901: (required) either or both of "xin", "clkin".
> -		- 5p49v5933 and
> -		- 5p49v5935: (optional) property not present or "clkin".
> -
> -For all output ports, a corresponding, optional child node named OUT1,
> -OUT2, etc. can represent a each output, and the node can be used to
> -specify the following:
> -
> -- idt,mode: can be one of the following:
> -                 - VC5_LVPECL
> -                 - VC5_CMOS
> -                 - VC5_HCSL33
> -                 - VC5_LVDS
> -                 - VC5_CMOS2
> -                 - VC5_CMOSD
> -                 - VC5_HCSL25
> -
> -- idt,voltage-microvolts:  can be one of the following
> -                 - 1800000
> -                 - 2500000
> -                 - 3300000
> --  idt,slew-percent: Percent of normal, can be one of
> -                 - 80
> -                 - 85
> -                 - 90
> -                 - 100
> -
> -==Mapping between clock specifier and physical pins==
> -
> -When referencing the provided clock in the DT using phandle and
> -clock specifier, the following mapping applies:
> -
> -5P49V5923:
> -	0 -- OUT0_SEL_I2CB
> -	1 -- OUT1
> -	2 -- OUT2
> -
> -5P49V5933:
> -	0 -- OUT0_SEL_I2CB
> -	1 -- OUT1
> -	2 -- OUT4
> -
> -5P49V5925 and
> -5P49V5935:
> -	0 -- OUT0_SEL_I2CB
> -	1 -- OUT1
> -	2 -- OUT2
> -	3 -- OUT3
> -	4 -- OUT4
> -
> -5P49V6901:
> -	0 -- OUT0_SEL_I2CB
> -	1 -- OUT1
> -	2 -- OUT2
> -	3 -- OUT3
> -	4 -- OUT4
> -
> -==Example==
> -
> -/* 25MHz reference crystal */
> -ref25: ref25m {
> -	compatible = "fixed-clock";
> -	#clock-cells = <0>;
> -	clock-frequency = <25000000>;
> -};
> -
> -i2c-master-node {
> -
> -	/* IDT 5P49V5923 i2c clock generator */
> -	vc5: clock-generator@6a {
> -		compatible = "idt,5p49v5923";
> -		reg = <0x6a>;
> -		#clock-cells = <1>;
> -
> -		/* Connect XIN input to 25MHz reference */
> -		clocks = <&ref25m>;
> -		clock-names = "xin";
> -
> -		OUT1 {
> -			idt,mode = <VC5_CMOS>;
> -			idt,voltage-microvolts = <1800000>;
> -			idt,slew-percent = <80>;
> -		};
> -		OUT2 {
> -			...
> -		};
> -		...
> -	};
> -};
> -
> -/* Consumer referencing the 5P49V5923 pin OUT1 */
> -consumer {
> -	...
> -	clocks = <&vc5 1>;
> -	...
> -}
> diff --git a/Documentation/devicetree/bindings/clock/idt,versaclock5.yaml b/Documentation/devicetree/bindings/clock/idt,versaclock5.yaml
> new file mode 100644
> index 000000000000..4bdfd6187b48
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/idt,versaclock5.yaml
> @@ -0,0 +1,160 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/idt,versaclock5.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Binding for IDT VersaClock 5 and 6 programmable I2C clock generators
> +
> +description: |
> +  The IDT VersaClock 5 and VersaClock 6 are programmable I2C
> +  clock generators providing from 3 to 12 output clocks.
> +
> +  When referencing the provided clock in the DT using phandle and clock
> +  specifier, the following mapping applies:
> +
> +  - 5P49V5923:
> +    0 -- OUT0_SEL_I2CB
> +    1 -- OUT1
> +    2 -- OUT2
> +
> +  - 5P49V5933:
> +    0 -- OUT0_SEL_I2CB
> +    1 -- OUT1
> +    2 -- OUT4
> +
> +  - other parts:
> +    0 -- OUT0_SEL_I2CB
> +    1 -- OUT1
> +    2 -- OUT2
> +    3 -- OUT3
> +    4 -- OUT4
> +
> +maintainers:
> +  - Luca Ceresoli <luca@lucaceresoli.net>
> +
> +properties:
> +  compatible:
> +    enum:
> +      - idt,5p49v5923
> +      - idt,5p49v5925
> +      - idt,5p49v5933
> +      - idt,5p49v5935
> +      - idt,5p49v6901
> +      - idt,5p49v6965
> +
> +  reg:
> +    maxItems: 1
> +    description: I2C device address, shall be 0x68 or 0x6a.

Can be a schema:

enum: [ 0x68, 0x6a ]

> +
> +  '#clock-cells':
> +    const: 1
> +
> +patternProperties:
> +  "^OUT[1-4]$":
> +    type: object
> +    description:
> +      Description of one of the outputs (OUT1..OUT4). See "Clock1 Output
> +      Configuration" in the Versaclock 5/6/6E Family Register Description
> +      and Programming Guide.
> +    properties:
> +      idt,mode:
> +        description:
> +          The output drive mode. Values defined in dt-bindings/clk/versaclock.h
> +        enum:
> +          - VC5_LVPECL

This is defining a string. Can't use defines here.

> +          - VC5_CMOS
> +          - VC5_HCSL33
> +          - VC5_LVDS
> +          - VC5_CMOS2
> +          - VC5_CMOSD
> +          - VC5_HCSL25
> +      idt,voltage-microvolts:
> +        description: The output drive voltage.
> +        $ref: /schemas/types.yaml#/definitions/uint32

Standard unit suffixes have a type already, so drop.

> +        enum: [ 1800000, 2500000, 3300000 ]
> +      idt,slew-percent:
> +        description: The Slew rate control for CMOS single-ended.
> +        $ref: /schemas/types.yaml#/definitions/uint32

Here too.

> +        enum: [ 80, 85, 90, 100 ]
> +
> +required:
> +  - compatible
> +  - reg
> +  - '#clock-cells'
> +
> +allOf:
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            enum:
> +              - idt,5p49v5933
> +              - idt,5p49v5935
> +    then:
> +      # Devices with builtin crystal, optional external input
> +      properties:
> +        clock-names:
> +          const: clkin
> +        clocks:
> +          maxItems: 1
> +    else:
> +      # Devices without builtin crystal
> +      properties:
> +        clock-names:
> +          anyOf:
> +            - required: [ xin ]
> +            - required: [ clkin ]

This isn't valid. I think you want:

clock-names:
  minItems: 1
  items:
    - const: xin
    - const: clkin

This would mean 'xin' is always required, clkin is optional.

> +        clocks:
> +          minItems: 1
> +          maxItems: 2
> +      required:
> +        - clock-names
> +        - clocks
> +
> +examples:
> +  - |
> +    #include <dt-bindings/clk/versaclock.h>
> +
> +    /* 25MHz reference crystal */
> +    ref25: ref25m {
> +        compatible = "fixed-clock";
> +        #clock-cells = <0>;
> +        clock-frequency = <25000000>;
> +    };
> +
> +    i2c@0 {
> +        reg = <0x0 0x100>;
> +        #address-cells = <1>;
> +        #size-cells = <0>;
> +
> +        /* IDT 5P49V5923 I2C clock generator */
> +        vc5: clock-generator@6a {
> +            compatible = "idt,5p49v5923";
> +            reg = <0x6a>;
> +            #clock-cells = <1>;
> +
> +            /* Connect XIN input to 25MHz reference */
> +            clocks = <&ref25m>;
> +            clock-names = "xin";
> +
> +            OUT1 {
> +                idt,drive-mode = <VC5_CMOSD>;
> +                idt,voltage-microvolts = <1800000>;
> +                idt,slew-percent = <80>;
> +            };
> +
> +            OUT4 {
> +                idt,drive-mode = <VC5_LVDS>;
> +            };
> +        };
> +    };
> +
> +    /* Consumer referencing the 5P49V5923 pin OUT1 */
> +    consumer {
> +        /* ... */
> +        clocks = <&vc5 1>;
> +        /* ... */
> +    };
> +
> +...
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 5aa16c245c63..09d6efd1d0d0 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -8326,6 +8326,7 @@ F:	drivers/input/misc/ideapad_slidebar.c
>  IDT VersaClock 5 CLOCK DRIVER
>  M:	Luca Ceresoli <luca@lucaceresoli.net>
>  S:	Maintained
> +F:	Documentation/devicetree/bindings/clock/idt,versaclock5.yaml
>  F:	drivers/clk/clk-versaclock5.c
>  
>  IEEE 802.15.4 SUBSYSTEM
> -- 
> 2.27.0
> 

Re: [PATCH v2 4/4] dt-bindings: clk: versaclock5: convert to yaml

[Luca Ceresoli]

Hi Rob,

thanks for you review!

On 14/07/20 05:11, Rob Herring wrote:
> On Wed, Jul 08, 2020 at 09:40:35AM +0200, Luca Ceresoli wrote:
>> Convert to yaml the VersaClock bindings document. The mapping between
>> clock specifier and physical pins cannot be described formally in yaml
>> schema, then keep it verbatim in the description field.
>>
>> Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net>

[...]

>> +  reg:
>> +    maxItems: 1
>> +    description: I2C device address, shall be 0x68 or 0x6a.
> 
> Can be a schema:
> 
> enum: [ 0x68, 0x6a ]

Nice, will fix.

>> +
>> +  '#clock-cells':
>> +    const: 1
>> +
>> +patternProperties:
>> +  "^OUT[1-4]$":
>> +    type: object
>> +    description:
>> +      Description of one of the outputs (OUT1..OUT4). See "Clock1 Output
>> +      Configuration" in the Versaclock 5/6/6E Family Register Description
>> +      and Programming Guide.
>> +    properties:
>> +      idt,mode:
>> +        description:
>> +          The output drive mode. Values defined in dt-bindings/clk/versaclock.h
>> +        enum:
>> +          - VC5_LVPECL
> 
> This is defining a string. Can't use defines here.

How do I use the defines from include/dt-bindings then? Or should I just
use the numeric values then, like:

  idt,mode:
    description:
      The output drive mode. Values defined in
      dt-bindings/clk/versaclock.h
    minimum: 0
    maximum: 6

?

>> +      idt,voltage-microvolts:
>> +        description: The output drive voltage.
>> +        $ref: /schemas/types.yaml#/definitions/uint32
> 
> Standard unit suffixes have a type already, so drop.

Ok.

>> +allOf:
>> +  - if:
>> +      properties:
>> +        compatible:
>> +          contains:
>> +            enum:
>> +              - idt,5p49v5933
>> +              - idt,5p49v5935
>> +    then:
>> +      # Devices with builtin crystal, optional external input
>> +      properties:
>> +        clock-names:
>> +          const: clkin
>> +        clocks:
>> +          maxItems: 1
>> +    else:
>> +      # Devices without builtin crystal
>> +      properties:
>> +        clock-names:
>> +          anyOf:
>> +            - required: [ xin ]
>> +            - required: [ clkin ]
> 
> This isn't valid. I think you want:
> 
> clock-names:
>   minItems: 1
>   items:
>     - const: xin
>     - const: clkin
> 
> This would mean 'xin' is always required, clkin is optional.

No, what I wanted to mean is that allowed cases are:
 * for idt,5p49v5933 and idt,5p49v5935:
   - only 'xin' (required)
 * for the other parts one of these:
   - only 'xin'
   - only 'clkin'
   - both 'xin' and 'clkin'

How do I express that?


A general note: as a newcomer to yaml bindings I found a steep learning
curve. Finding a correct construct (not to mention the best one) for
each situation is time consuming and frustrating. I've been looking at
existing files for suitable examples but it doesn't work very well.

Is there any guide to yaml bindings for beginners with examples of
typical cases? It would greatly help in producing better patches and
saving time for everybody.

Thanks,
-- 
Luca

Re: [PATCH v2 4/4] dt-bindings: clk: versaclock5: convert to yaml

[Rob Herring]

On Tue, Jul 14, 2020 at 3:15 AM Luca Ceresoli <luca@lucaceresoli.net> wrote:
>
> Hi Rob,
>
> thanks for you review!
>
> On 14/07/20 05:11, Rob Herring wrote:
> > On Wed, Jul 08, 2020 at 09:40:35AM +0200, Luca Ceresoli wrote:
> >> Convert to yaml the VersaClock bindings document. The mapping between
> >> clock specifier and physical pins cannot be described formally in yaml
> >> schema, then keep it verbatim in the description field.
> >>
> >> Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net>
>
> [...]
>
> >> +  reg:
> >> +    maxItems: 1
> >> +    description: I2C device address, shall be 0x68 or 0x6a.
> >
> > Can be a schema:
> >
> > enum: [ 0x68, 0x6a ]
>
> Nice, will fix.
>
> >> +
> >> +  '#clock-cells':
> >> +    const: 1
> >> +
> >> +patternProperties:
> >> +  "^OUT[1-4]$":
> >> +    type: object
> >> +    description:
> >> +      Description of one of the outputs (OUT1..OUT4). See "Clock1 Output
> >> +      Configuration" in the Versaclock 5/6/6E Family Register Description
> >> +      and Programming Guide.
> >> +    properties:
> >> +      idt,mode:
> >> +        description:
> >> +          The output drive mode. Values defined in dt-bindings/clk/versaclock.h
> >> +        enum:
> >> +          - VC5_LVPECL
> >
> > This is defining a string. Can't use defines here.
>
> How do I use the defines from include/dt-bindings then? Or should I just
> use the numeric values then, like:
>
>   idt,mode:
>     description:
>       The output drive mode. Values defined in
>       dt-bindings/clk/versaclock.h
>     minimum: 0
>     maximum: 6
>
> ?

Yes.

>
> >> +      idt,voltage-microvolts:
> >> +        description: The output drive voltage.
> >> +        $ref: /schemas/types.yaml#/definitions/uint32
> >
> > Standard unit suffixes have a type already, so drop.
>
> Ok.
>
> >> +allOf:
> >> +  - if:
> >> +      properties:
> >> +        compatible:
> >> +          contains:
> >> +            enum:
> >> +              - idt,5p49v5933
> >> +              - idt,5p49v5935
> >> +    then:
> >> +      # Devices with builtin crystal, optional external input
> >> +      properties:
> >> +        clock-names:
> >> +          const: clkin
> >> +        clocks:
> >> +          maxItems: 1
> >> +    else:
> >> +      # Devices without builtin crystal
> >> +      properties:
> >> +        clock-names:
> >> +          anyOf:
> >> +            - required: [ xin ]
> >> +            - required: [ clkin ]
> >
> > This isn't valid. I think you want:
> >
> > clock-names:
> >   minItems: 1
> >   items:
> >     - const: xin
> >     - const: clkin
> >
> > This would mean 'xin' is always required, clkin is optional.
>
> No, what I wanted to mean is that allowed cases are:
>  * for idt,5p49v5933 and idt,5p49v5935:
>    - only 'xin' (required)

For this you need an if/then schema. There are plenty of examples in
the tree, but this is what you need:

if:
  properties:
    compatible:
      enum:
        - idt,5p49v5933
        - idt,5p49v5935
then:
  properties:
    clocks:
      maxItems: 1
    clock-names:
      const: xin

>  * for the other parts one of these:
>    - only 'xin'
>    - only 'clkin'
>    - both 'xin' and 'clkin'
>
> How do I express that?

For the 2nd part:

clock-names:
  minItems: 1
  maxItems: 2
  items:
    enum: [ xin, clkin ]

> A general note: as a newcomer to yaml bindings I found a steep learning
> curve. Finding a correct construct (not to mention the best one) for
> each situation is time consuming and frustrating. I've been looking at
> existing files for suitable examples but it doesn't work very well.
>
> Is there any guide to yaml bindings for beginners with examples of
> typical cases? It would greatly help in producing better patches and
> saving time for everybody.

bindings/example-schema.yaml is intended to do that. No doubt it could
use more examples. Though from my perspective people already don't
read and follow things it says there.

The problem I think is not the typical cases, but the atypical ones. I
don't think we can enumerate all the atypical cases. At that point you
really need some understanding of json-schema which I agree has a bit
of a learning curve if you've never used anything like it (I hadn't).

Rob

Re: [PATCH v2 4/4] dt-bindings: clk: versaclock5: convert to yaml

[Luca Ceresoli]

Hi Rob,

On 14/07/20 05:11, Rob Herring wrote:
> On Wed, Jul 08, 2020 at 09:40:35AM +0200, Luca Ceresoli wrote:
>> Convert to yaml the VersaClock bindings document. The mapping between
>> clock specifier and physical pins cannot be described formally in yaml
>> schema, then keep it verbatim in the description field.
>>
>> Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net>
>> ---
>>  .../bindings/clock/idt,versaclock5.txt        | 125 --------------
>>  .../bindings/clock/idt,versaclock5.yaml       | 160 ++++++++++++++++++
>>  MAINTAINERS                                   |   1 +
>>  3 files changed, 161 insertions(+), 125 deletions(-)
>>  delete mode 100644 Documentation/devicetree/bindings/clock/idt,versaclock5.txt
>>  create mode 100644 Documentation/devicetree/bindings/clock/idt,versaclock5.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/clock/idt,versaclock5.txt b/Documentation/devicetree/bindings/clock/idt,versaclock5.txt
>> deleted file mode 100644
>> index 9656d4cf221c..000000000000
>> --- a/Documentation/devicetree/bindings/clock/idt,versaclock5.txt
>> +++ /dev/null
>> @@ -1,125 +0,0 @@
>> -Binding for IDT VersaClock 5,6 programmable i2c clock generators.
>> -
>> -The IDT VersaClock 5 and VersaClock 6 are programmable i2c clock
>> -generators providing from 3 to 12 output clocks.
>> -
>> -==I2C device node==
>> -
>> -Required properties:
>> -- compatible:	shall be one of
>> -		"idt,5p49v5923"
>> -		"idt,5p49v5925"
>> -		"idt,5p49v5933"
>> -		"idt,5p49v5935"
>> -		"idt,5p49v6901"
>> -		"idt,5p49v6965"
>> -- reg:		i2c device address, shall be 0x68 or 0x6a.
>> -- #clock-cells:	from common clock binding; shall be set to 1.
>> -- clocks:	from common clock binding; list of parent clock handles,
>> -		- 5p49v5923 and
>> -		  5p49v5925 and
>> -		  5p49v6901: (required) either or both of XTAL or CLKIN
>> -					reference clock.
>> -		- 5p49v5933 and
>> -		- 5p49v5935: (optional) property not present (internal
>> -					Xtal used) or CLKIN reference
>> -					clock.
>> -- clock-names:	from common clock binding; clock input names, can be
>> -		- 5p49v5923 and
>> -		  5p49v5925 and
>> -		  5p49v6901: (required) either or both of "xin", "clkin".
>> -		- 5p49v5933 and
>> -		- 5p49v5935: (optional) property not present or "clkin".
>> -
>> -For all output ports, a corresponding, optional child node named OUT1,
>> -OUT2, etc. can represent a each output, and the node can be used to
>> -specify the following:
>> -
>> -- idt,mode: can be one of the following:
>> -                 - VC5_LVPECL
>> -                 - VC5_CMOS
>> -                 - VC5_HCSL33
>> -                 - VC5_LVDS
>> -                 - VC5_CMOS2
>> -                 - VC5_CMOSD
>> -                 - VC5_HCSL25
>> -
>> -- idt,voltage-microvolts:  can be one of the following
>> -                 - 1800000
>> -                 - 2500000
>> -                 - 3300000
>> --  idt,slew-percent: Percent of normal, can be one of
>> -                 - 80
>> -                 - 85
>> -                 - 90
>> -                 - 100
>> -
>> -==Mapping between clock specifier and physical pins==
>> -
>> -When referencing the provided clock in the DT using phandle and
>> -clock specifier, the following mapping applies:
>> -
>> -5P49V5923:
>> -	0 -- OUT0_SEL_I2CB
>> -	1 -- OUT1
>> -	2 -- OUT2
>> -
>> -5P49V5933:
>> -	0 -- OUT0_SEL_I2CB
>> -	1 -- OUT1
>> -	2 -- OUT4
>> -
>> -5P49V5925 and
>> -5P49V5935:
>> -	0 -- OUT0_SEL_I2CB
>> -	1 -- OUT1
>> -	2 -- OUT2
>> -	3 -- OUT3
>> -	4 -- OUT4
>> -
>> -5P49V6901:
>> -	0 -- OUT0_SEL_I2CB
>> -	1 -- OUT1
>> -	2 -- OUT2
>> -	3 -- OUT3
>> -	4 -- OUT4
>> -
>> -==Example==
>> -
>> -/* 25MHz reference crystal */
>> -ref25: ref25m {
>> -	compatible = "fixed-clock";
>> -	#clock-cells = <0>;
>> -	clock-frequency = <25000000>;
>> -};
>> -
>> -i2c-master-node {
>> -
>> -	/* IDT 5P49V5923 i2c clock generator */
>> -	vc5: clock-generator@6a {
>> -		compatible = "idt,5p49v5923";
>> -		reg = <0x6a>;
>> -		#clock-cells = <1>;
>> -
>> -		/* Connect XIN input to 25MHz reference */
>> -		clocks = <&ref25m>;
>> -		clock-names = "xin";
>> -
>> -		OUT1 {
>> -			idt,mode = <VC5_CMOS>;
>> -			idt,voltage-microvolts = <1800000>;
>> -			idt,slew-percent = <80>;
>> -		};
>> -		OUT2 {
>> -			...
>> -		};
>> -		...
>> -	};
>> -};
>> -
>> -/* Consumer referencing the 5P49V5923 pin OUT1 */
>> -consumer {
>> -	...
>> -	clocks = <&vc5 1>;
>> -	...
>> -}
>> diff --git a/Documentation/devicetree/bindings/clock/idt,versaclock5.yaml b/Documentation/devicetree/bindings/clock/idt,versaclock5.yaml
>> new file mode 100644
>> index 000000000000..4bdfd6187b48
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/idt,versaclock5.yaml
>> @@ -0,0 +1,160 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/clock/idt,versaclock5.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Binding for IDT VersaClock 5 and 6 programmable I2C clock generators
>> +
>> +description: |
>> +  The IDT VersaClock 5 and VersaClock 6 are programmable I2C
>> +  clock generators providing from 3 to 12 output clocks.
>> +
>> +  When referencing the provided clock in the DT using phandle and clock
>> +  specifier, the following mapping applies:
>> +
>> +  - 5P49V5923:
>> +    0 -- OUT0_SEL_I2CB
>> +    1 -- OUT1
>> +    2 -- OUT2
>> +
>> +  - 5P49V5933:
>> +    0 -- OUT0_SEL_I2CB
>> +    1 -- OUT1
>> +    2 -- OUT4
>> +
>> +  - other parts:
>> +    0 -- OUT0_SEL_I2CB
>> +    1 -- OUT1
>> +    2 -- OUT2
>> +    3 -- OUT3
>> +    4 -- OUT4
>> +
>> +maintainers:
>> +  - Luca Ceresoli <luca@lucaceresoli.net>
>> +
>> +properties:
>> +  compatible:
>> +    enum:
>> +      - idt,5p49v5923
>> +      - idt,5p49v5925
>> +      - idt,5p49v5933
>> +      - idt,5p49v5935
>> +      - idt,5p49v6901
>> +      - idt,5p49v6965
>> +
>> +  reg:
>> +    maxItems: 1
>> +    description: I2C device address, shall be 0x68 or 0x6a.
> 
> Can be a schema:
> 
> enum: [ 0x68, 0x6a ]
> 
>> +
>> +  '#clock-cells':
>> +    const: 1
>> +
>> +patternProperties:
>> +  "^OUT[1-4]$":
>> +    type: object
>> +    description:
>> +      Description of one of the outputs (OUT1..OUT4). See "Clock1 Output
>> +      Configuration" in the Versaclock 5/6/6E Family Register Description
>> +      and Programming Guide.
>> +    properties:
>> +      idt,mode:
>> +        description:
>> +          The output drive mode. Values defined in dt-bindings/clk/versaclock.h
>> +        enum:
>> +          - VC5_LVPECL
> 
> This is defining a string. Can't use defines here.
> 
>> +          - VC5_CMOS
>> +          - VC5_HCSL33
>> +          - VC5_LVDS
>> +          - VC5_CMOS2
>> +          - VC5_CMOSD
>> +          - VC5_HCSL25
>> +      idt,voltage-microvolts:
>> +        description: The output drive voltage.
>> +        $ref: /schemas/types.yaml#/definitions/uint32
> 
> Standard unit suffixes have a type already, so drop.

After better studying json schema, v3 is coming with this change, but...

> 
>> +        enum: [ 1800000, 2500000, 3300000 ]
>> +      idt,slew-percent:
>> +        description: The Slew rate control for CMOS single-ended.
>> +        $ref: /schemas/types.yaml#/definitions/uint32
> 
> Here too.

...not this one. It doesn't look like "percent" or similar is a standard
unit, and reading [0] confirms that. Should it be added?

[0]
https://github.com/robherring/dt-schema/blob/master/schemas/property-units.yaml

Thanks.
-- 
Luca