From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, MENTIONS_GIT_HOSTING,MIME_BASE64_TEXT,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, UNPARSEABLE_RELAY,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9DAC8C433E2 for ; Fri, 10 Jul 2020 10:19:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 56A942077D for ; Fri, 10 Jul 2020 10:19:53 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="sdBmm+a+" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727033AbgGJKTw (ORCPT ); Fri, 10 Jul 2020 06:19:52 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:16743 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726840AbgGJKTw (ORCPT ); Fri, 10 Jul 2020 06:19:52 -0400 X-UUID: 5fe72dcc792e4331979bd81442f6b698-20200710 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=MivBBVxEJb72HxTrv6XGwM/S5e3vdMpQxQjDdF8m33I=; b=sdBmm+a+Ii8/7l/Ahi7zZSmmmLG1pDoe15X8PbBX8YdGHnWAWV9ZE/Wvi1nr8yYxAualpAfuRYqZ0tVuHJlGNEyZ8lvR6HeLE7aMWYyVn90NKQZEn14t05j0qp8Joc0krs4orZ/fcHmapFvpET50hC5U3pjAYNnQ/PvqJoNeJYg=; X-UUID: 5fe72dcc792e4331979bd81442f6b698-20200710 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 117367481; Fri, 10 Jul 2020 18:19:38 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 10 Jul 2020 18:19:37 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 10 Jul 2020 18:19:36 +0800 From: Dongchun Zhu To: , , , , , , , , CC: , , , , , , , , , <1095088256@qq.com>, Subject: [PATCH v13 2/2] media: i2c: Add OV02A10 image sensor driver Date: Fri, 10 Jul 2020 18:18:50 +0800 Message-ID: <20200710101850.4604-3-dongchun.zhu@mediatek.com> X-Mailer: git-send-email 2.9.2 In-Reply-To: <20200710101850.4604-1-dongchun.zhu@mediatek.com> References: <20200710101850.4604-1-dongchun.zhu@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Content-Transfer-Encoding: base64 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org QWRkIGEgVjRMMiBzdWItZGV2aWNlIGRyaXZlciBmb3IgT21uaVZpc2lvbiBPVjAyQTEwIGltYWdl IHNlbnNvci4NCg0KUmV2aWV3ZWQtYnk6IFRvbWFzeiBGaWdhIDx0ZmlnYUBjaHJvbWl1bS5vcmc+ DQpTaWduZWQtb2ZmLWJ5OiBEb25nY2h1biBaaHUgPGRvbmdjaHVuLnpodUBtZWRpYXRlay5jb20+ DQotLS0NCiBNQUlOVEFJTkVSUyAgICAgICAgICAgICAgICAgfCAgICAxICsNCiBkcml2ZXJzL21l ZGlhL2kyYy9LY29uZmlnICAgfCAgIDEzICsNCiBkcml2ZXJzL21lZGlhL2kyYy9NYWtlZmlsZSAg fCAgICAxICsNCiBkcml2ZXJzL21lZGlhL2kyYy9vdjAyYTEwLmMgfCAxMDUwICsrKysrKysrKysr KysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysNCiA0IGZpbGVzIGNoYW5nZWQsIDEwNjUg aW5zZXJ0aW9ucygrKQ0KIGNyZWF0ZSBtb2RlIDEwMDY0NCBkcml2ZXJzL21lZGlhL2kyYy9vdjAy YTEwLmMNCg0KZGlmZiAtLWdpdCBhL01BSU5UQUlORVJTIGIvTUFJTlRBSU5FUlMNCmluZGV4IDM3 OGM5NjEuLmE2YTJmOGIgMTAwNjQ0DQotLS0gYS9NQUlOVEFJTkVSUw0KKysrIGIvTUFJTlRBSU5F UlMNCkBAIC0xMjU2Niw2ICsxMjU2Niw3IEBAIEw6CWxpbnV4LW1lZGlhQHZnZXIua2VybmVsLm9y Zw0KIFM6CU1haW50YWluZWQNCiBUOglnaXQgZ2l0Oi8vbGludXh0di5vcmcvbWVkaWFfdHJlZS5n aXQNCiBGOglEb2N1bWVudGF0aW9uL2RldmljZXRyZWUvYmluZGluZ3MvbWVkaWEvaTJjL292dGks b3YwMmExMC55YW1sDQorRjoJZHJpdmVycy9tZWRpYS9pMmMvb3YwMmExMC5jDQogDQogT01OSVZJ U0lPTiBPVjEzODU4IFNFTlNPUiBEUklWRVINCiBNOglTYWthcmkgQWlsdXMgPHNha2FyaS5haWx1 c0BsaW51eC5pbnRlbC5jb20+DQpkaWZmIC0tZ2l0IGEvZHJpdmVycy9tZWRpYS9pMmMvS2NvbmZp ZyBiL2RyaXZlcnMvbWVkaWEvaTJjL0tjb25maWcNCmluZGV4IGRhMTEwMzYuLjY1NTE5Y2YgMTAw NjQ0DQotLS0gYS9kcml2ZXJzL21lZGlhL2kyYy9LY29uZmlnDQorKysgYi9kcml2ZXJzL21lZGlh L2kyYy9LY29uZmlnDQpAQCAtODEyLDYgKzgxMiwxOSBAQCBjb25maWcgVklERU9fSU1YMzU1DQog CSAgVG8gY29tcGlsZSB0aGlzIGRyaXZlciBhcyBhIG1vZHVsZSwgY2hvb3NlIE0gaGVyZTogdGhl DQogCSAgbW9kdWxlIHdpbGwgYmUgY2FsbGVkIGlteDM1NS4NCiANCitjb25maWcgVklERU9fT1Yw MkExMA0KKwl0cmlzdGF0ZSAiT21uaVZpc2lvbiBPVjAyQTEwIHNlbnNvciBzdXBwb3J0Ig0KKwlk ZXBlbmRzIG9uIEkyQyAmJiBWSURFT19WNEwyDQorCXNlbGVjdCBNRURJQV9DT05UUk9MTEVSDQor CXNlbGVjdCBWSURFT19WNEwyX1NVQkRFVl9BUEkNCisJc2VsZWN0IFY0TDJfRldOT0RFDQorCWhl bHANCisJICBUaGlzIGlzIGEgVmlkZW80TGludXgyIHNlbnNvciBkcml2ZXIgZm9yIHRoZSBPbW5p VmlzaW9uDQorCSAgT1YwMkExMCBjYW1lcmEuDQorDQorCSAgVG8gY29tcGlsZSB0aGlzIGRyaXZl ciBhcyBhIG1vZHVsZSwgY2hvb3NlIE0gaGVyZTogdGhlDQorCSAgbW9kdWxlIHdpbGwgYmUgY2Fs bGVkIG92MDJhMTAuDQorDQogY29uZmlnIFZJREVPX09WMjY0MA0KIAl0cmlzdGF0ZSAiT21uaVZp c2lvbiBPVjI2NDAgc2Vuc29yIHN1cHBvcnQiDQogCWRlcGVuZHMgb24gVklERU9fVjRMMiAmJiBJ MkMNCmRpZmYgLS1naXQgYS9kcml2ZXJzL21lZGlhL2kyYy9NYWtlZmlsZSBiL2RyaXZlcnMvbWVk aWEvaTJjL01ha2VmaWxlDQppbmRleCA5OTNhY2FiLi4zODRlNjc2IDEwMDY0NA0KLS0tIGEvZHJp dmVycy9tZWRpYS9pMmMvTWFrZWZpbGUNCisrKyBiL2RyaXZlcnMvbWVkaWEvaTJjL01ha2VmaWxl DQpAQCAtNjMsNiArNjMsNyBAQCBvYmotJChDT05GSUdfVklERU9fVlAyN1NNUFgpICs9IHZwMjdz bXB4Lm8NCiBvYmotJChDT05GSUdfVklERU9fU09OWV9CVEZfTVBYKSArPSBzb255LWJ0Zi1tcHgu bw0KIG9iai0kKENPTkZJR19WSURFT19VUEQ2NDAzMUEpICs9IHVwZDY0MDMxYS5vDQogb2JqLSQo Q09ORklHX1ZJREVPX1VQRDY0MDgzKSArPSB1cGQ2NDA4My5vDQorb2JqLSQoQ09ORklHX1ZJREVP X09WMDJBMTApICs9IG92MDJhMTAubw0KIG9iai0kKENPTkZJR19WSURFT19PVjI2NDApICs9IG92 MjY0MC5vDQogb2JqLSQoQ09ORklHX1ZJREVPX09WMjY4MCkgKz0gb3YyNjgwLm8NCiBvYmotJChD T05GSUdfVklERU9fT1YyNjg1KSArPSBvdjI2ODUubw0KZGlmZiAtLWdpdCBhL2RyaXZlcnMvbWVk aWEvaTJjL292MDJhMTAuYyBiL2RyaXZlcnMvbWVkaWEvaTJjL292MDJhMTAuYw0KbmV3IGZpbGUg bW9kZSAxMDA2NDQNCmluZGV4IDAwMDAwMDAuLjVmZmM5N2ENCi0tLSAvZGV2L251bGwNCisrKyBi L2RyaXZlcnMvbWVkaWEvaTJjL292MDJhMTAuYw0KQEAgLTAsMCArMSwxMDUwIEBADQorLy8gU1BE WC1MaWNlbnNlLUlkZW50aWZpZXI6IEdQTC0yLjANCisvLyBDb3B5cmlnaHQgKGMpIDIwMjAgTWVk aWFUZWsgSW5jLg0KKw0KKyNpbmNsdWRlIDxsaW51eC9jbGsuaD4NCisjaW5jbHVkZSA8bGludXgv ZGVsYXkuaD4NCisjaW5jbHVkZSA8bGludXgvZGV2aWNlLmg+DQorI2luY2x1ZGUgPGxpbnV4L2dw aW8vY29uc3VtZXIuaD4NCisjaW5jbHVkZSA8bGludXgvaTJjLmg+DQorI2luY2x1ZGUgPGxpbnV4 L21vZHVsZS5oPg0KKyNpbmNsdWRlIDxsaW51eC9wbV9ydW50aW1lLmg+DQorI2luY2x1ZGUgPGxp bnV4L3JlZ3VsYXRvci9jb25zdW1lci5oPg0KKyNpbmNsdWRlIDxtZWRpYS9tZWRpYS1lbnRpdHku aD4NCisjaW5jbHVkZSA8bWVkaWEvdjRsMi1hc3luYy5oPg0KKyNpbmNsdWRlIDxtZWRpYS92NGwy LWN0cmxzLmg+DQorI2luY2x1ZGUgPG1lZGlhL3Y0bDItc3ViZGV2Lmg+DQorI2luY2x1ZGUgPG1l ZGlhL3Y0bDItZndub2RlLmg+DQorDQorI2RlZmluZSBDSElQX0lECQkJCQkJMHgyNTA5DQorI2Rl ZmluZSBPVjAyQTEwX1JFR19DSElQX0lEX0gJCQkJMHgwMg0KKyNkZWZpbmUgT1YwMkExMF9SRUdf Q0hJUF9JRF9MCQkJCTB4MDMNCisNCisvKiBCaXRbMV0gdmVydGljYWwgdXBzaWRlIGRvd24gKi8N CisvKiBCaXRbMF0gaG9yaXpvbnRhbCBtaXJyb3IgKi8NCisjZGVmaW5lIFJFR19NSVJST1JfRkxJ UF9DT05UUk9MCQkJCTB4M2YNCisNCisvKiBPcmllbnRhdGlvbiAqLw0KKyNkZWZpbmUgUkVHX01J UlJPUl9GTElQX0VOQUJMRQkJCQkweDAzDQorDQorLyogQml0WzI6MF0gTUlQSSB0cmFuc21pc3Np b24gc3BlZWQgc2VsZWN0ICovDQorI2RlZmluZSBUWF9TUEVFRF9BUkVBX1NFTAkJCQkweGExDQor I2RlZmluZSBPVjAyQTEwX01JUElfVFhfU1BFRURfREVGQVVMVAkJCTB4MDMNCisNCisjZGVmaW5l IFJFR19QQUdFX1NXSVRDSAkJCQkJMHhmZA0KKyNkZWZpbmUgUkVHX0dMT0JBTF9FRkZFQ1RJVkUJ CQkJMHgwMQ0KKyNkZWZpbmUgUkVHX0VOQUJMRQkJCQkJQklUKDApDQorDQorI2RlZmluZSBSRUdf U0NfQ1RSTF9NT0RFCQkJCTB4YWMNCisjZGVmaW5lIFNDX0NUUkxfTU9ERV9TVEFOREJZCQkJCTB4 MDANCisjZGVmaW5lIFNDX0NUUkxfTU9ERV9TVFJFQU1JTkcJCQkJMHgwMQ0KKw0KKyNkZWZpbmUg T1YwMkExMF9FWFBfU0hJRlQJCQkJOA0KKyNkZWZpbmUgT1YwMkExMF9SRUdfRVhQT1NVUkVfSAkJ CQkweDAzDQorI2RlZmluZSBPVjAyQTEwX1JFR19FWFBPU1VSRV9MCQkJCTB4MDQNCisjZGVmaW5l CU9WMDJBMTBfRVhQT1NVUkVfTUlOCQkJCTQNCisjZGVmaW5lIE9WMDJBMTBfRVhQT1NVUkVfTUFY X01BUkdJTgkJCTQNCisjZGVmaW5lCU9WMDJBMTBfRVhQT1NVUkVfU1RFUAkJCQkxDQorDQorI2Rl ZmluZSBPVjAyQTEwX1ZUU19TSElGVAkJCQk4DQorI2RlZmluZSBPVjAyQTEwX1JFR19WVFNfSAkJ CQkweDA1DQorI2RlZmluZSBPVjAyQTEwX1JFR19WVFNfTAkJCQkweDA2DQorI2RlZmluZSBPVjAy QTEwX1ZUU19NQVgJCQkJCTB4MjA5Zg0KKyNkZWZpbmUgT1YwMkExMF9CQVNJQ19MSU5FCQkJCTEy MjQNCisNCisjZGVmaW5lIE9WMDJBMTBfUkVHX0dBSU4JCQkJMHgyNA0KKyNkZWZpbmUgT1YwMkEx MF9HQUlOX01JTgkJCQkweDEwDQorI2RlZmluZSBPVjAyQTEwX0dBSU5fTUFYCQkJCTB4ZjgNCisj ZGVmaW5lIE9WMDJBMTBfR0FJTl9TVEVQCQkJCTB4MDENCisjZGVmaW5lIE9WMDJBMTBfR0FJTl9E RUZBVUxUCQkJCTB4NDANCisNCisvKiBUZXN0IHBhdHRlcm4gY29udHJvbCAqLw0KKyNkZWZpbmUg T1YwMkExMF9SRUdfVEVTVF9QQVRURVJOCQkJMHhiNg0KKw0KKyNkZWZpbmUgSFpfUEVSX01IWgkJ CQkJMTAwMDAwMEwNCisjZGVmaW5lIE9WMDJBMTBfTElOS19GUkVRXzM5ME1IWgkJCSgzOTAgKiBI Wl9QRVJfTUhaKQ0KKyNkZWZpbmUgT1YwMkExMF9FQ0xLX0ZSRVEJCQkJKDI0ICogSFpfUEVSX01I WikNCisjZGVmaW5lIE9WMDJBMTBfREFUQV9MQU5FUwkJCQkxDQorI2RlZmluZSBPVjAyQTEwX0JJ VFNfUEVSX1NBTVBMRQkJCQkxMA0KKw0KK3N0YXRpYyBjb25zdCBjaGFyICogY29uc3Qgb3YwMmEx MF9zdXBwbHlfbmFtZXNbXSA9IHsNCisJImRvdmRkIiwJLyogRGlnaXRhbCBJL08gcG93ZXIgKi8N CisJImF2ZGQiLAkJLyogQW5hbG9nIHBvd2VyICovDQorCSJkdmRkIiwJCS8qIERpZ2l0YWwgY29y ZSBwb3dlciAqLw0KK307DQorDQorc3RydWN0IG92MDJhMTBfcmVnIHsNCisJdTggYWRkcjsNCisJ dTggdmFsOw0KK307DQorDQorc3RydWN0IG92MDJhMTBfcmVnX2xpc3Qgew0KKwl1MzIgbnVtX29m X3JlZ3M7DQorCWNvbnN0IHN0cnVjdCBvdjAyYTEwX3JlZyAqcmVnczsNCit9Ow0KKw0KK3N0cnVj dCBvdjAyYTEwX21vZGUgew0KKwl1MzIgd2lkdGg7DQorCXUzMiBoZWlnaHQ7DQorCXUzMiBleHBf ZGVmOw0KKwl1MzIgaHRzX2RlZjsNCisJdTMyIHZ0c19kZWY7DQorCWNvbnN0IHN0cnVjdCBvdjAy YTEwX3JlZ19saXN0IHJlZ19saXN0Ow0KK307DQorDQorc3RydWN0IG92MDJhMTAgew0KKwl1MzIg ZWNsa19mcmVxOw0KKwl1MzIgbWlwaV9jbG9ja190eF9zcGVlZDsNCisNCisJc3RydWN0IGNsayAq ZWNsazsNCisJc3RydWN0IGdwaW9fZGVzYyAqcGRfZ3BpbzsNCisJc3RydWN0IGdwaW9fZGVzYyAq cnN0X2dwaW87DQorCXN0cnVjdCByZWd1bGF0b3JfYnVsa19kYXRhIHN1cHBsaWVzW0FSUkFZX1NJ WkUob3YwMmExMF9zdXBwbHlfbmFtZXMpXTsNCisNCisJYm9vbCBzdHJlYW1pbmc7DQorCWJvb2wg dXBzaWRlX2Rvd247DQorDQorCS8qDQorCSAqIFNlcmlhbGl6ZSBjb250cm9sIGFjY2VzcywgZ2V0 L3NldCBmb3JtYXQsIGdldCBzZWxlY3Rpb24NCisJICogYW5kIHN0YXJ0IHN0cmVhbWluZy4NCisJ ICovDQorCXN0cnVjdCBtdXRleCBtdXRleDsNCisJc3RydWN0IHY0bDJfc3ViZGV2IHN1YmRldjsN CisJc3RydWN0IG1lZGlhX3BhZCBwYWQ7DQorCXN0cnVjdCB2NGwyX21idXNfZnJhbWVmbXQgZm10 Ow0KKwlzdHJ1Y3QgdjRsMl9jdHJsX2hhbmRsZXIgY3RybF9oYW5kbGVyOw0KKwlzdHJ1Y3QgdjRs Ml9jdHJsICpleHBvc3VyZTsNCisNCisJY29uc3Qgc3RydWN0IG92MDJhMTBfbW9kZSAqY3VyX21v ZGU7DQorfTsNCisNCitzdGF0aWMgaW5saW5lIHN0cnVjdCBvdjAyYTEwICp0b19vdjAyYTEwKHN0 cnVjdCB2NGwyX3N1YmRldiAqc2QpDQorew0KKwlyZXR1cm4gY29udGFpbmVyX29mKHNkLCBzdHJ1 Y3Qgb3YwMmExMCwgc3ViZGV2KTsNCit9DQorDQorLyoNCisgKiBlY2xrIDI0TWh6DQorICogcGNs ayAzOU1oeg0KKyAqIGxpbmVsZW5ndGggOTM0KDB4M2E2KQ0KKyAqIGZyYW1lbGVuZ3RoIDEzOTAo MHg1NkUpDQorICogZ3JhYndpbmRvd193aWR0aCAxNjAwDQorICogZ3JhYndpbmRvd19oZWlnaHQg MTIwMA0KKyAqIG1heF9mcmFtZXJhdGUgMzBmcHMNCisgKiBtaXBpX2RhdGFyYXRlIHBlciBsYW5l IDc4ME1icHMNCisgKi8NCitzdGF0aWMgY29uc3Qgc3RydWN0IG92MDJhMTBfcmVnIG92MDJhMTBf MTYwMHgxMjAwX3JlZ3NbXSA9IHsNCisJezB4ZmQsIDB4MDF9LA0KKwl7MHhhYywgMHgwMH0sDQor CXsweGZkLCAweDAwfSwNCisJezB4MmYsIDB4Mjl9LA0KKwl7MHgzNCwgMHgwMH0sDQorCXsweDM1 LCAweDIxfSwNCisJezB4MzAsIDB4MTV9LA0KKwl7MHgzMywgMHgwMX0sDQorCXsweGZkLCAweDAx fSwNCisJezB4NDQsIDB4MDB9LA0KKwl7MHgyYSwgMHg0Y30sDQorCXsweDJiLCAweDFlfSwNCisJ ezB4MmMsIDB4NjB9LA0KKwl7MHgyNSwgMHgxMX0sDQorCXsweDAzLCAweDAxfSwNCisJezB4MDQs IDB4YWV9LA0KKwl7MHgwOSwgMHgwMH0sDQorCXsweDBhLCAweDAyfSwNCisJezB4MDYsIDB4YTZ9 LA0KKwl7MHgzMSwgMHgwMH0sDQorCXsweDI0LCAweDQwfSwNCisJezB4MDEsIDB4MDF9LA0KKwl7 MHhmYiwgMHg3M30sDQorCXsweGZkLCAweDAxfSwNCisJezB4MTYsIDB4MDR9LA0KKwl7MHgxYywg MHgwOX0sDQorCXsweDIxLCAweDQyfSwNCisJezB4MTIsIDB4MDR9LA0KKwl7MHgxMywgMHgxMH0s DQorCXsweDExLCAweDQwfSwNCisJezB4MzMsIDB4ODF9LA0KKwl7MHhkMCwgMHgwMH0sDQorCXsw eGQxLCAweDAxfSwNCisJezB4ZDIsIDB4MDB9LA0KKwl7MHg1MCwgMHgxMH0sDQorCXsweDUxLCAw eDIzfSwNCisJezB4NTIsIDB4MjB9LA0KKwl7MHg1MywgMHgxMH0sDQorCXsweDU0LCAweDAyfSwN CisJezB4NTUsIDB4MjB9LA0KKwl7MHg1NiwgMHgwMn0sDQorCXsweDU4LCAweDQ4fSwNCisJezB4 NWQsIDB4MTV9LA0KKwl7MHg1ZSwgMHgwNX0sDQorCXsweDY2LCAweDY2fSwNCisJezB4NjgsIDB4 Njh9LA0KKwl7MHg2YiwgMHgwMH0sDQorCXsweDZjLCAweDAwfSwNCisJezB4NmYsIDB4NDB9LA0K Kwl7MHg3MCwgMHg0MH0sDQorCXsweDcxLCAweDBhfSwNCisJezB4NzIsIDB4ZjB9LA0KKwl7MHg3 MywgMHgxMH0sDQorCXsweDc1LCAweDgwfSwNCisJezB4NzYsIDB4MTB9LA0KKwl7MHg4NCwgMHgw MH0sDQorCXsweDg1LCAweDEwfSwNCisJezB4ODYsIDB4MTB9LA0KKwl7MHg4NywgMHgwMH0sDQor CXsweDhhLCAweDIyfSwNCisJezB4OGIsIDB4MjJ9LA0KKwl7MHgxOSwgMHhmMX0sDQorCXsweDI5 LCAweDAxfSwNCisJezB4ZmQsIDB4MDF9LA0KKwl7MHg5ZCwgMHgxNn0sDQorCXsweGEwLCAweDI5 fSwNCisJezB4YTEsIDB4MDN9LA0KKwl7MHhhZCwgMHg2Mn0sDQorCXsweGFlLCAweDAwfSwNCisJ ezB4YWYsIDB4ODV9LA0KKwl7MHhiMSwgMHgwMX0sDQorCXsweDhlLCAweDA2fSwNCisJezB4OGYs IDB4NDB9LA0KKwl7MHg5MCwgMHgwNH0sDQorCXsweDkxLCAweGIwfSwNCisJezB4NDUsIDB4MDF9 LA0KKwl7MHg0NiwgMHgwMH0sDQorCXsweDQ3LCAweDZjfSwNCisJezB4NDgsIDB4MDN9LA0KKwl7 MHg0OSwgMHg4Yn0sDQorCXsweDRhLCAweDAwfSwNCisJezB4NGIsIDB4MDd9LA0KKwl7MHg0Yywg MHgwNH0sDQorCXsweDRkLCAweGI3fSwNCisJezB4ZjAsIDB4NDB9LA0KKwl7MHhmMSwgMHg0MH0s DQorCXsweGYyLCAweDQwfSwNCisJezB4ZjMsIDB4NDB9LA0KKwl7MHgzZiwgMHgwMH0sDQorCXsw eGZkLCAweDAxfSwNCisJezB4MDUsIDB4MDB9LA0KKwl7MHgwNiwgMHhhNn0sDQorCXsweGZkLCAw eDAxfSwNCit9Ow0KKw0KK3N0YXRpYyBjb25zdCBjaGFyICogY29uc3Qgb3YwMmExMF90ZXN0X3Bh dHRlcm5fbWVudVtdID0gew0KKwkiRGlzYWJsZWQiLA0KKwkiRWlnaHQgVmVydGljYWwgQ29sb3Vy IEJhcnMiLA0KK307DQorDQorc3RhdGljIGNvbnN0IHM2NCBsaW5rX2ZyZXFfbWVudV9pdGVtc1td ID0gew0KKwlPVjAyQTEwX0xJTktfRlJFUV8zOTBNSFosDQorfTsNCisNCitzdGF0aWMgdTY0IHRv X3BpeGVsX3JhdGUodTMyIGZfaW5kZXgpDQorew0KKwl1NjQgcGl4ZWxfcmF0ZSA9IGxpbmtfZnJl cV9tZW51X2l0ZW1zW2ZfaW5kZXhdICogMiAqIE9WMDJBMTBfREFUQV9MQU5FUzsNCisNCisJZG9f ZGl2KHBpeGVsX3JhdGUsIE9WMDJBMTBfQklUU19QRVJfU0FNUExFKTsNCisNCisJcmV0dXJuIHBp eGVsX3JhdGU7DQorfQ0KKw0KK3N0YXRpYyBjb25zdCBzdHJ1Y3Qgb3YwMmExMF9tb2RlIHN1cHBv cnRlZF9tb2Rlc1tdID0gew0KKwl7DQorCQkud2lkdGggPSAxNjAwLA0KKwkJLmhlaWdodCA9IDEy MDAsDQorCQkuZXhwX2RlZiA9IDB4MDFhZSwNCisJCS5odHNfZGVmID0gMHgwM2E2LA0KKwkJLnZ0 c19kZWYgPSAweDA1NmUsDQorCQkucmVnX2xpc3QgPSB7DQorCQkJLm51bV9vZl9yZWdzID0gQVJS QVlfU0laRShvdjAyYTEwXzE2MDB4MTIwMF9yZWdzKSwNCisJCQkucmVncyA9IG92MDJhMTBfMTYw MHgxMjAwX3JlZ3MsDQorCQl9LA0KKwl9LA0KK307DQorDQorc3RhdGljIGludCBvdjAyYTEwX3dy aXRlX2FycmF5KHN0cnVjdCBvdjAyYTEwICpvdjAyYTEwLA0KKwkJCSAgICAgICBjb25zdCBzdHJ1 Y3Qgb3YwMmExMF9yZWdfbGlzdCAqcl9saXN0KQ0KK3sNCisJc3RydWN0IGkyY19jbGllbnQgKmNs aWVudCA9IHY0bDJfZ2V0X3N1YmRldmRhdGEoJm92MDJhMTAtPnN1YmRldik7DQorCXVuc2lnbmVk IGludCBpOw0KKwlpbnQgcmV0Ow0KKw0KKwlmb3IgKGkgPSAwOyBpIDwgcl9saXN0LT5udW1fb2Zf cmVnczsgaSsrKSB7DQorCQlyZXQgPSBpMmNfc21idXNfd3JpdGVfYnl0ZV9kYXRhKGNsaWVudCwg cl9saXN0LT5yZWdzW2ldLmFkZHIsDQorCQkJCQkJcl9saXN0LT5yZWdzW2ldLnZhbCk7DQorCQlp ZiAocmV0IDwgMCkNCisJCQlyZXR1cm4gcmV0Ow0KKwl9DQorDQorCXJldHVybiAwOw0KK30NCisN CitzdGF0aWMgaW50IG92MDJhMTBfcmVhZF9zbWJ1cyhzdHJ1Y3Qgb3YwMmExMCAqb3YwMmExMCwg dW5zaWduZWQgY2hhciByZWcsDQorCQkJICAgICAgdW5zaWduZWQgY2hhciAqdmFsKQ0KK3sNCisJ c3RydWN0IGkyY19jbGllbnQgKmNsaWVudCA9IHY0bDJfZ2V0X3N1YmRldmRhdGEoJm92MDJhMTAt PnN1YmRldik7DQorCWludCByZXQ7DQorDQorCXJldCA9IGkyY19zbWJ1c19yZWFkX2J5dGVfZGF0 YShjbGllbnQsIHJlZyk7DQorCWlmIChyZXQgPCAwKQ0KKwkJcmV0dXJuIHJldDsNCisNCisJKnZh bCA9ICh1bnNpZ25lZCBjaGFyKXJldDsNCisNCisJcmV0dXJuIDA7DQorfQ0KKw0KK3N0YXRpYyB2 b2lkIG92MDJhMTBfZmlsbF9mbXQoY29uc3Qgc3RydWN0IG92MDJhMTBfbW9kZSAqbW9kZSwNCisJ CQkgICAgIHN0cnVjdCB2NGwyX21idXNfZnJhbWVmbXQgKmZtdCkNCit7DQorCWZtdC0+d2lkdGgg PSBtb2RlLT53aWR0aDsNCisJZm10LT5oZWlnaHQgPSBtb2RlLT5oZWlnaHQ7DQorCWZtdC0+Zmll bGQgPSBWNEwyX0ZJRUxEX05PTkU7DQorfQ0KKw0KK3N0YXRpYyBpbnQgb3YwMmExMF9zZXRfZm10 KHN0cnVjdCB2NGwyX3N1YmRldiAqc2QsDQorCQkJICAgc3RydWN0IHY0bDJfc3ViZGV2X3BhZF9j b25maWcgKmNmZywNCisJCQkgICBzdHJ1Y3QgdjRsMl9zdWJkZXZfZm9ybWF0ICpmbXQpDQorew0K KwlzdHJ1Y3Qgb3YwMmExMCAqb3YwMmExMCA9IHRvX292MDJhMTAoc2QpOw0KKwlzdHJ1Y3QgdjRs Ml9tYnVzX2ZyYW1lZm10ICptYnVzX2ZtdCA9ICZmbXQtPmZvcm1hdDsNCisJc3RydWN0IHY0bDJf bWJ1c19mcmFtZWZtdCAqZnJhbWVfZm10Ow0KKwlpbnQgcmV0ID0gMDsNCisNCisJbXV0ZXhfbG9j aygmb3YwMmExMC0+bXV0ZXgpOw0KKw0KKwlpZiAob3YwMmExMC0+c3RyZWFtaW5nICYmIGZtdC0+ d2hpY2ggPT0gVjRMMl9TVUJERVZfRk9STUFUX0FDVElWRSkgew0KKwkJcmV0ID0gLUVCVVNZOw0K KwkJZ290byBlcnJvcjsNCisJfQ0KKw0KKwkvKiBPbmx5IG9uZSBzZW5zb3IgbW9kZSBzdXBwb3J0 ZWQgKi8NCisJbWJ1c19mbXQtPmNvZGUgPSBvdjAyYTEwLT5mbXQuY29kZTsNCisJb3YwMmExMF9m aWxsX2ZtdChvdjAyYTEwLT5jdXJfbW9kZSwgbWJ1c19mbXQpOw0KKw0KKwlpZiAoZm10LT53aGlj aCA9PSBWNEwyX1NVQkRFVl9GT1JNQVRfVFJZKQ0KKwkJZnJhbWVfZm10ID0gdjRsMl9zdWJkZXZf Z2V0X3RyeV9mb3JtYXQoc2QsIGNmZywgMCk7DQorCWVsc2UNCisJCWZyYW1lX2ZtdCA9ICZvdjAy YTEwLT5mbXQ7DQorDQorCSpmcmFtZV9mbXQgPSAqbWJ1c19mbXQ7DQorDQorZXJyb3I6DQorCW11 dGV4X3VubG9jaygmb3YwMmExMC0+bXV0ZXgpOw0KKwlyZXR1cm4gcmV0Ow0KK30NCisNCitzdGF0 aWMgaW50IG92MDJhMTBfZ2V0X2ZtdChzdHJ1Y3QgdjRsMl9zdWJkZXYgKnNkLA0KKwkJCSAgIHN0 cnVjdCB2NGwyX3N1YmRldl9wYWRfY29uZmlnICpjZmcsDQorCQkJICAgc3RydWN0IHY0bDJfc3Vi ZGV2X2Zvcm1hdCAqZm10KQ0KK3sNCisJc3RydWN0IG92MDJhMTAgKm92MDJhMTAgPSB0b19vdjAy YTEwKHNkKTsNCisJc3RydWN0IHY0bDJfbWJ1c19mcmFtZWZtdCAqbWJ1c19mbXQgPSAmZm10LT5m b3JtYXQ7DQorDQorCW11dGV4X2xvY2soJm92MDJhMTAtPm11dGV4KTsNCisNCisJaWYgKGZtdC0+ d2hpY2ggPT0gVjRMMl9TVUJERVZfRk9STUFUX1RSWSkgew0KKwkJZm10LT5mb3JtYXQgPSAqdjRs Ml9zdWJkZXZfZ2V0X3RyeV9mb3JtYXQoc2QsIGNmZywgZm10LT5wYWQpOw0KKwl9IGVsc2Ugew0K KwkJZm10LT5mb3JtYXQgPSBvdjAyYTEwLT5mbXQ7DQorCQltYnVzX2ZtdC0+Y29kZSA9IG92MDJh MTAtPmZtdC5jb2RlOw0KKwkJb3YwMmExMF9maWxsX2ZtdChvdjAyYTEwLT5jdXJfbW9kZSwgbWJ1 c19mbXQpOw0KKwl9DQorDQorCW11dGV4X3VubG9jaygmb3YwMmExMC0+bXV0ZXgpOw0KKw0KKwly ZXR1cm4gMDsNCit9DQorDQorc3RhdGljIGludCBvdjAyYTEwX2VudW1fbWJ1c19jb2RlKHN0cnVj dCB2NGwyX3N1YmRldiAqc2QsDQorCQkJCSAgc3RydWN0IHY0bDJfc3ViZGV2X3BhZF9jb25maWcg KmNmZywNCisJCQkJICBzdHJ1Y3QgdjRsMl9zdWJkZXZfbWJ1c19jb2RlX2VudW0gKmNvZGUpDQor ew0KKwlzdHJ1Y3Qgb3YwMmExMCAqb3YwMmExMCA9IHRvX292MDJhMTAoc2QpOw0KKw0KKwlpZiAo Y29kZS0+aW5kZXggIT0gMCkNCisJCXJldHVybiAtRUlOVkFMOw0KKw0KKwljb2RlLT5jb2RlID0g b3YwMmExMC0+Zm10LmNvZGU7DQorDQorCXJldHVybiAwOw0KK30NCisNCitzdGF0aWMgaW50IG92 MDJhMTBfZW51bV9mcmFtZV9zaXplcyhzdHJ1Y3QgdjRsMl9zdWJkZXYgKnNkLA0KKwkJCQkgICAg c3RydWN0IHY0bDJfc3ViZGV2X3BhZF9jb25maWcgKmNmZywNCisJCQkJICAgIHN0cnVjdCB2NGwy X3N1YmRldl9mcmFtZV9zaXplX2VudW0gKmZzZSkNCit7DQorCWlmIChmc2UtPmluZGV4ID49IEFS UkFZX1NJWkUoc3VwcG9ydGVkX21vZGVzKSkNCisJCXJldHVybiAtRUlOVkFMOw0KKw0KKwlmc2Ut Pm1pbl93aWR0aCAgPSBzdXBwb3J0ZWRfbW9kZXNbZnNlLT5pbmRleF0ud2lkdGg7DQorCWZzZS0+ bWF4X3dpZHRoICA9IHN1cHBvcnRlZF9tb2Rlc1tmc2UtPmluZGV4XS53aWR0aDsNCisJZnNlLT5t YXhfaGVpZ2h0ID0gc3VwcG9ydGVkX21vZGVzW2ZzZS0+aW5kZXhdLmhlaWdodDsNCisJZnNlLT5t aW5faGVpZ2h0ID0gc3VwcG9ydGVkX21vZGVzW2ZzZS0+aW5kZXhdLmhlaWdodDsNCisNCisJcmV0 dXJuIDA7DQorfQ0KKw0KK3N0YXRpYyBpbnQgb3YwMmExMF9jaGVja19zZW5zb3JfaWQoc3RydWN0 IG92MDJhMTAgKm92MDJhMTApDQorew0KKwlzdHJ1Y3QgaTJjX2NsaWVudCAqY2xpZW50ID0gdjRs Ml9nZXRfc3ViZGV2ZGF0YSgmb3YwMmExMC0+c3ViZGV2KTsNCisJdTE2IGlkOw0KKwl1OCBjaGlw X2lkX2g7DQorCXU4IGNoaXBfaWRfbDsNCisJaW50IHJldDsNCisNCisJLyogQ2hlY2sgc2Vuc29y IHJldmlzaW9uICovDQorCXJldCA9IG92MDJhMTBfcmVhZF9zbWJ1cyhvdjAyYTEwLCBPVjAyQTEw X1JFR19DSElQX0lEX0gsICZjaGlwX2lkX2gpOw0KKwlpZiAocmV0KQ0KKwkJcmV0dXJuIHJldDsN CisNCisJcmV0ID0gb3YwMmExMF9yZWFkX3NtYnVzKG92MDJhMTAsIE9WMDJBMTBfUkVHX0NISVBf SURfTCwgJmNoaXBfaWRfbCk7DQorCWlmIChyZXQpDQorCQlyZXR1cm4gcmV0Ow0KKw0KKwlpZCA9 IChjaGlwX2lkX2ggPDwgOCkgfCBjaGlwX2lkX2w7DQorCWlmIChpZCAhPSBDSElQX0lEKSB7DQor CQlkZXZfZXJyKCZjbGllbnQtPmRldiwgIlVuZXhwZWN0ZWQgc2Vuc29yIGlkKCUwNHgpXG4iLCBp ZCk7DQorCQlyZXR1cm4gLUVJTlZBTDsNCisJfQ0KKw0KKwlyZXR1cm4gMDsNCit9DQorDQorc3Rh dGljIGludCBvdjAyYTEwX3Bvd2VyX29uKHN0cnVjdCBkZXZpY2UgKmRldikNCit7DQorCXN0cnVj dCBpMmNfY2xpZW50ICpjbGllbnQgPSB0b19pMmNfY2xpZW50KGRldik7DQorCXN0cnVjdCB2NGwy X3N1YmRldiAqc2QgPSBpMmNfZ2V0X2NsaWVudGRhdGEoY2xpZW50KTsNCisJc3RydWN0IG92MDJh MTAgKm92MDJhMTAgPSB0b19vdjAyYTEwKHNkKTsNCisJaW50IHJldDsNCisNCisJZ3Bpb2Rfc2V0 X3ZhbHVlX2NhbnNsZWVwKG92MDJhMTAtPnJzdF9ncGlvLCAxKTsNCisJZ3Bpb2Rfc2V0X3ZhbHVl X2NhbnNsZWVwKG92MDJhMTAtPnBkX2dwaW8sIDEpOw0KKw0KKwlyZXQgPSBjbGtfcHJlcGFyZV9l bmFibGUob3YwMmExMC0+ZWNsayk7DQorCWlmIChyZXQgPCAwKSB7DQorCQlkZXZfZXJyKGRldiwg ImZhaWxlZCB0byBlbmFibGUgZWNsa1xuIik7DQorCQlyZXR1cm4gcmV0Ow0KKwl9DQorDQorCXJl dCA9IHJlZ3VsYXRvcl9idWxrX2VuYWJsZShBUlJBWV9TSVpFKG92MDJhMTBfc3VwcGx5X25hbWVz KSwNCisJCQkJICAgIG92MDJhMTAtPnN1cHBsaWVzKTsNCisJaWYgKHJldCA8IDApIHsNCisJCWRl dl9lcnIoZGV2LCAiZmFpbGVkIHRvIGVuYWJsZSByZWd1bGF0b3JzXG4iKTsNCisJCWdvdG8gZGlz YWJsZV9jbGs7DQorCX0NCisJdXNsZWVwX3JhbmdlKDUwMDAsIDYwMDApOw0KKw0KKwlncGlvZF9z ZXRfdmFsdWVfY2Fuc2xlZXAob3YwMmExMC0+cGRfZ3BpbywgMCk7DQorCXVzbGVlcF9yYW5nZSg1 MDAwLCA2MDAwKTsNCisNCisJZ3Bpb2Rfc2V0X3ZhbHVlX2NhbnNsZWVwKG92MDJhMTAtPnJzdF9n cGlvLCAwKTsNCisJdXNsZWVwX3JhbmdlKDUwMDAsIDYwMDApOw0KKw0KKwlyZXQgPSBvdjAyYTEw X2NoZWNrX3NlbnNvcl9pZChvdjAyYTEwKTsNCisJaWYgKHJldCkNCisJCWdvdG8gZGlzYWJsZV9y ZWd1bGF0b3I7DQorDQorCXJldHVybiAwOw0KKw0KK2Rpc2FibGVfcmVndWxhdG9yOg0KKwlyZWd1 bGF0b3JfYnVsa19kaXNhYmxlKEFSUkFZX1NJWkUob3YwMmExMF9zdXBwbHlfbmFtZXMpLA0KKwkJ CSAgICAgICBvdjAyYTEwLT5zdXBwbGllcyk7DQorZGlzYWJsZV9jbGs6DQorCWNsa19kaXNhYmxl X3VucHJlcGFyZShvdjAyYTEwLT5lY2xrKTsNCisNCisJcmV0dXJuIHJldDsNCit9DQorDQorc3Rh dGljIGludCBvdjAyYTEwX3Bvd2VyX29mZihzdHJ1Y3QgZGV2aWNlICpkZXYpDQorew0KKwlzdHJ1 Y3QgaTJjX2NsaWVudCAqY2xpZW50ID0gdG9faTJjX2NsaWVudChkZXYpOw0KKwlzdHJ1Y3QgdjRs Ml9zdWJkZXYgKnNkID0gaTJjX2dldF9jbGllbnRkYXRhKGNsaWVudCk7DQorCXN0cnVjdCBvdjAy YTEwICpvdjAyYTEwID0gdG9fb3YwMmExMChzZCk7DQorDQorCWdwaW9kX3NldF92YWx1ZV9jYW5z bGVlcChvdjAyYTEwLT5yc3RfZ3BpbywgMSk7DQorCWNsa19kaXNhYmxlX3VucHJlcGFyZShvdjAy YTEwLT5lY2xrKTsNCisJZ3Bpb2Rfc2V0X3ZhbHVlX2NhbnNsZWVwKG92MDJhMTAtPnBkX2dwaW8s IDEpOw0KKwlyZWd1bGF0b3JfYnVsa19kaXNhYmxlKEFSUkFZX1NJWkUob3YwMmExMF9zdXBwbHlf bmFtZXMpLA0KKwkJCSAgICAgICBvdjAyYTEwLT5zdXBwbGllcyk7DQorDQorCXJldHVybiAwOw0K K30NCisNCitzdGF0aWMgaW50IF9fb3YwMmExMF9zdGFydF9zdHJlYW0oc3RydWN0IG92MDJhMTAg Km92MDJhMTApDQorew0KKwlzdHJ1Y3QgaTJjX2NsaWVudCAqY2xpZW50ID0gdjRsMl9nZXRfc3Vi ZGV2ZGF0YSgmb3YwMmExMC0+c3ViZGV2KTsNCisJY29uc3Qgc3RydWN0IG92MDJhMTBfcmVnX2xp c3QgKnJlZ19saXN0Ow0KKwlpbnQgcmV0Ow0KKw0KKwkvKiBBcHBseSBkZWZhdWx0IHZhbHVlcyBv ZiBjdXJyZW50IG1vZGUgKi8NCisJcmVnX2xpc3QgPSAmb3YwMmExMC0+Y3VyX21vZGUtPnJlZ19s aXN0Ow0KKwlyZXQgPSBvdjAyYTEwX3dyaXRlX2FycmF5KG92MDJhMTAsIHJlZ19saXN0KTsNCisJ aWYgKHJldCkNCisJCXJldHVybiByZXQ7DQorDQorCS8qIEFwcGx5IGN1c3RvbWl6ZWQgdmFsdWVz IGZyb20gdXNlciAqLw0KKwlyZXQgPSBfX3Y0bDJfY3RybF9oYW5kbGVyX3NldHVwKG92MDJhMTAt PnN1YmRldi5jdHJsX2hhbmRsZXIpOw0KKwlpZiAocmV0KQ0KKwkJcmV0dXJuIHJldDsNCisNCisJ LyogU2V0IG9yaWVudGF0aW9uIHRvIDE4MCBkZWdyZWUgKi8NCisJaWYgKG92MDJhMTAtPnVwc2lk ZV9kb3duKSB7DQorCQlyZXQgPSBpMmNfc21idXNfd3JpdGVfYnl0ZV9kYXRhKGNsaWVudCwgUkVH X01JUlJPUl9GTElQX0NPTlRST0wsDQorCQkJCQkJUkVHX01JUlJPUl9GTElQX0VOQUJMRSk7DQor CQlpZiAocmV0KSB7DQorCQkJZGV2X2VycigmY2xpZW50LT5kZXYsICJmYWlsZWQgdG8gc2V0IG9y aWVudGF0aW9uXG4iKTsNCisJCQlyZXR1cm4gcmV0Ow0KKwkJfQ0KKwkJcmV0ID0gaTJjX3NtYnVz X3dyaXRlX2J5dGVfZGF0YShjbGllbnQsIFJFR19HTE9CQUxfRUZGRUNUSVZFLA0KKwkJCQkJCVJF R19FTkFCTEUpOw0KKwkJaWYgKHJldCA8IDApDQorCQkJcmV0dXJuIHJldDsNCisJfQ0KKw0KKwkv KiBTZXQgbWlwaSBUWCBzcGVlZCBhY2NvcmRpbmcgdG8gRFQgcHJvcGVydHkgKi8NCisJaWYgKG92 MDJhMTAtPm1pcGlfY2xvY2tfdHhfc3BlZWQgIT0gT1YwMkExMF9NSVBJX1RYX1NQRUVEX0RFRkFV TFQpIHsNCisJCXJldCA9IGkyY19zbWJ1c193cml0ZV9ieXRlX2RhdGEoY2xpZW50LCBUWF9TUEVF RF9BUkVBX1NFTCwNCisJCQkJCQlvdjAyYTEwLT5taXBpX2Nsb2NrX3R4X3NwZWVkKTsNCisJCWlm IChyZXQgPCAwKQ0KKwkJCXJldHVybiByZXQ7DQorCX0NCisNCisJLyogU2V0IHN0cmVhbSBvbiBy ZWdpc3RlciAqLw0KKwlyZXR1cm4gaTJjX3NtYnVzX3dyaXRlX2J5dGVfZGF0YShjbGllbnQsIFJF R19TQ19DVFJMX01PREUsDQorCQkJCQkgU0NfQ1RSTF9NT0RFX1NUUkVBTUlORyk7DQorfQ0KKw0K K3N0YXRpYyBpbnQgX19vdjAyYTEwX3N0b3Bfc3RyZWFtKHN0cnVjdCBvdjAyYTEwICpvdjAyYTEw KQ0KK3sNCisJc3RydWN0IGkyY19jbGllbnQgKmNsaWVudCA9IHY0bDJfZ2V0X3N1YmRldmRhdGEo Jm92MDJhMTAtPnN1YmRldik7DQorDQorCXJldHVybiBpMmNfc21idXNfd3JpdGVfYnl0ZV9kYXRh KGNsaWVudCwgUkVHX1NDX0NUUkxfTU9ERSwNCisJCQkJCSBTQ19DVFJMX01PREVfU1RBTkRCWSk7 DQorfQ0KKw0KK3N0YXRpYyBpbnQgb3YwMmExMF9lbnRpdHlfaW5pdF9jZmcoc3RydWN0IHY0bDJf c3ViZGV2ICpzZCwNCisJCQkJICAgc3RydWN0IHY0bDJfc3ViZGV2X3BhZF9jb25maWcgKmNmZykN Cit7DQorCXN0cnVjdCB2NGwyX3N1YmRldl9mb3JtYXQgZm10ID0gew0KKwkJLndoaWNoID0gVjRM Ml9TVUJERVZfRk9STUFUX1RSWSwNCisJCS5mb3JtYXQgPSB7DQorCQkJLndpZHRoID0gMTYwMCwN CisJCQkuaGVpZ2h0ID0gMTIwMCwNCisJCX0NCisJfTsNCisNCisJb3YwMmExMF9zZXRfZm10KHNk LCBjZmcsICZmbXQpOw0KKw0KKwlyZXR1cm4gMDsNCit9DQorDQorc3RhdGljIGludCBvdjAyYTEw X3Nfc3RyZWFtKHN0cnVjdCB2NGwyX3N1YmRldiAqc2QsIGludCBvbikNCit7DQorCXN0cnVjdCBv djAyYTEwICpvdjAyYTEwID0gdG9fb3YwMmExMChzZCk7DQorCXN0cnVjdCBpMmNfY2xpZW50ICpj bGllbnQgPSB2NGwyX2dldF9zdWJkZXZkYXRhKCZvdjAyYTEwLT5zdWJkZXYpOw0KKwlpbnQgcmV0 Ow0KKw0KKwltdXRleF9sb2NrKCZvdjAyYTEwLT5tdXRleCk7DQorDQorCWlmIChvdjAyYTEwLT5z dHJlYW1pbmcgPT0gb24pDQorCQlnb3RvIHVubG9ja19hbmRfcmV0dXJuOw0KKw0KKwlpZiAob24p IHsNCisJCXJldCA9IHBtX3J1bnRpbWVfZ2V0X3N5bmMoJmNsaWVudC0+ZGV2KTsNCisJCWlmIChy ZXQgPCAwKSB7DQorCQkJcG1fcnVudGltZV9wdXRfbm9pZGxlKCZjbGllbnQtPmRldik7DQorCQkJ Z290byB1bmxvY2tfYW5kX3JldHVybjsNCisJCX0NCisNCisJCXJldCA9IF9fb3YwMmExMF9zdGFy dF9zdHJlYW0ob3YwMmExMCk7DQorCQlpZiAocmV0KSB7DQorCQkJX19vdjAyYTEwX3N0b3Bfc3Ry ZWFtKG92MDJhMTApOw0KKwkJCW92MDJhMTAtPnN0cmVhbWluZyA9ICFvbjsNCisJCQlnb3RvIGVy cl9ycG1fcHV0Ow0KKwkJfQ0KKwl9IGVsc2Ugew0KKwkJX19vdjAyYTEwX3N0b3Bfc3RyZWFtKG92 MDJhMTApOw0KKwkJcG1fcnVudGltZV9wdXQoJmNsaWVudC0+ZGV2KTsNCisJfQ0KKw0KKwlvdjAy YTEwLT5zdHJlYW1pbmcgPSBvbjsNCisJbXV0ZXhfdW5sb2NrKCZvdjAyYTEwLT5tdXRleCk7DQor DQorCXJldHVybiAwOw0KKw0KK2Vycl9ycG1fcHV0Og0KKwlwbV9ydW50aW1lX3B1dCgmY2xpZW50 LT5kZXYpOw0KK3VubG9ja19hbmRfcmV0dXJuOg0KKwltdXRleF91bmxvY2soJm92MDJhMTAtPm11 dGV4KTsNCisNCisJcmV0dXJuIHJldDsNCit9DQorDQorc3RhdGljIGNvbnN0IHN0cnVjdCBkZXZf cG1fb3BzIG92MDJhMTBfcG1fb3BzID0gew0KKwlTRVRfU1lTVEVNX1NMRUVQX1BNX09QUyhwbV9y dW50aW1lX2ZvcmNlX3N1c3BlbmQsDQorCQkJCXBtX3J1bnRpbWVfZm9yY2VfcmVzdW1lKQ0KKwlT RVRfUlVOVElNRV9QTV9PUFMob3YwMmExMF9wb3dlcl9vZmYsIG92MDJhMTBfcG93ZXJfb24sIE5V TEwpDQorfTsNCisNCisvKg0KKyAqIG92MDJhMTBfc2V0X2V4cG9zdXJlIC0gRnVuY3Rpb24gY2Fs bGVkIHdoZW4gc2V0dGluZyBleHBvc3VyZSB0aW1lDQorICogQHByaXY6IFBvaW50ZXIgdG8gZGV2 aWNlIHN0cnVjdHVyZQ0KKyAqIEB2YWw6IFZhcmlhYmxlIGZvciBleHBvc3VyZSB0aW1lLCBpbiB0 aGUgdW5pdCBvZiBtaWNyby1zZWNvbmQNCisgKg0KKyAqIFNldCBleHBvc3VyZSB0aW1lIGJhc2Vk IG9uIGlucHV0IHZhbHVlLg0KKyAqDQorICogUmV0dXJuOiAwIG9uIHN1Y2Nlc3MNCisgKi8NCitz dGF0aWMgaW50IG92MDJhMTBfc2V0X2V4cG9zdXJlKHN0cnVjdCBvdjAyYTEwICpvdjAyYTEwLCBp bnQgdmFsKQ0KK3sNCisJc3RydWN0IGkyY19jbGllbnQgKmNsaWVudCA9IHY0bDJfZ2V0X3N1YmRl dmRhdGEoJm92MDJhMTAtPnN1YmRldik7DQorCWludCByZXQ7DQorDQorCXJldCA9IGkyY19zbWJ1 c193cml0ZV9ieXRlX2RhdGEoY2xpZW50LCBSRUdfUEFHRV9TV0lUQ0gsIFJFR19FTkFCTEUpOw0K KwlpZiAocmV0IDwgMCkNCisJCXJldHVybiByZXQ7DQorDQorCXJldCA9IGkyY19zbWJ1c193cml0 ZV9ieXRlX2RhdGEoY2xpZW50LCBPVjAyQTEwX1JFR19FWFBPU1VSRV9ILA0KKwkJCQkJdmFsID4+ IE9WMDJBMTBfRVhQX1NISUZUKTsNCisJaWYgKHJldCA8IDApDQorCQlyZXR1cm4gcmV0Ow0KKw0K KwlyZXQgPSBpMmNfc21idXNfd3JpdGVfYnl0ZV9kYXRhKGNsaWVudCwgT1YwMkExMF9SRUdfRVhQ T1NVUkVfTCwgdmFsKTsNCisJaWYgKHJldCA8IDApDQorCQlyZXR1cm4gcmV0Ow0KKw0KKwlyZXR1 cm4gaTJjX3NtYnVzX3dyaXRlX2J5dGVfZGF0YShjbGllbnQsIFJFR19HTE9CQUxfRUZGRUNUSVZF LA0KKwkJCQkJIFJFR19FTkFCTEUpOw0KK30NCisNCitzdGF0aWMgaW50IG92MDJhMTBfc2V0X2dh aW4oc3RydWN0IG92MDJhMTAgKm92MDJhMTAsIGludCB2YWwpDQorew0KKwlzdHJ1Y3QgaTJjX2Ns aWVudCAqY2xpZW50ID0gdjRsMl9nZXRfc3ViZGV2ZGF0YSgmb3YwMmExMC0+c3ViZGV2KTsNCisJ aW50IHJldDsNCisNCisJcmV0ID0gaTJjX3NtYnVzX3dyaXRlX2J5dGVfZGF0YShjbGllbnQsIFJF R19QQUdFX1NXSVRDSCwgUkVHX0VOQUJMRSk7DQorCWlmIChyZXQgPCAwKQ0KKwkJcmV0dXJuIHJl dDsNCisNCisJcmV0ID0gaTJjX3NtYnVzX3dyaXRlX2J5dGVfZGF0YShjbGllbnQsIE9WMDJBMTBf UkVHX0dBSU4sIHZhbCk7DQorCWlmIChyZXQgPCAwKQ0KKwkJcmV0dXJuIHJldDsNCisNCisJcmV0 dXJuIGkyY19zbWJ1c193cml0ZV9ieXRlX2RhdGEoY2xpZW50LCBSRUdfR0xPQkFMX0VGRkVDVElW RSwNCisJCQkJCSBSRUdfRU5BQkxFKTsNCit9DQorDQorc3RhdGljIGludCBvdjAyYTEwX3NldF92 Ymxhbmsoc3RydWN0IG92MDJhMTAgKm92MDJhMTAsIGludCB2YWwpDQorew0KKwlzdHJ1Y3QgaTJj X2NsaWVudCAqY2xpZW50ID0gdjRsMl9nZXRfc3ViZGV2ZGF0YSgmb3YwMmExMC0+c3ViZGV2KTsN CisJdTMyIHZ0cyA9IHZhbCArIG92MDJhMTAtPmN1cl9tb2RlLT5oZWlnaHQgLSBPVjAyQTEwX0JB U0lDX0xJTkU7DQorCWludCByZXQ7DQorDQorCXJldCA9IGkyY19zbWJ1c193cml0ZV9ieXRlX2Rh dGEoY2xpZW50LCBSRUdfUEFHRV9TV0lUQ0gsIFJFR19FTkFCTEUpOw0KKwlpZiAocmV0IDwgMCkN CisJCXJldHVybiByZXQ7DQorDQorCXJldCA9IGkyY19zbWJ1c193cml0ZV9ieXRlX2RhdGEoY2xp ZW50LCBPVjAyQTEwX1JFR19WVFNfSCwNCisJCQkJCXZ0cyA+PiBPVjAyQTEwX1ZUU19TSElGVCk7 DQorCWlmIChyZXQgPCAwKQ0KKwkJcmV0dXJuIHJldDsNCisNCisJcmV0ID0gaTJjX3NtYnVzX3dy aXRlX2J5dGVfZGF0YShjbGllbnQsIE9WMDJBMTBfUkVHX1ZUU19MLCB2dHMpOw0KKwlpZiAocmV0 IDwgMCkNCisJCXJldHVybiByZXQ7DQorDQorCXJldHVybiBpMmNfc21idXNfd3JpdGVfYnl0ZV9k YXRhKGNsaWVudCwgUkVHX0dMT0JBTF9FRkZFQ1RJVkUsDQorCQkJCQkgUkVHX0VOQUJMRSk7DQor fQ0KKw0KK3N0YXRpYyBpbnQgb3YwMmExMF9zZXRfdGVzdF9wYXR0ZXJuKHN0cnVjdCBvdjAyYTEw ICpvdjAyYTEwLCBpbnQgcGF0dGVybikNCit7DQorCXN0cnVjdCBpMmNfY2xpZW50ICpjbGllbnQg PSB2NGwyX2dldF9zdWJkZXZkYXRhKCZvdjAyYTEwLT5zdWJkZXYpOw0KKwlpbnQgcmV0Ow0KKw0K KwlyZXQgPSBpMmNfc21idXNfd3JpdGVfYnl0ZV9kYXRhKGNsaWVudCwgUkVHX1BBR0VfU1dJVENI LCBSRUdfRU5BQkxFKTsNCisJaWYgKHJldCA8IDApDQorCQlyZXR1cm4gcmV0Ow0KKw0KKwlyZXQg PSBpMmNfc21idXNfd3JpdGVfYnl0ZV9kYXRhKGNsaWVudCwgT1YwMkExMF9SRUdfVEVTVF9QQVRU RVJOLA0KKwkJCQkJcGF0dGVybik7DQorCWlmIChyZXQgPCAwKQ0KKwkJcmV0dXJuIHJldDsNCisN CisJcmV0ID0gaTJjX3NtYnVzX3dyaXRlX2J5dGVfZGF0YShjbGllbnQsIFJFR19HTE9CQUxfRUZG RUNUSVZFLA0KKwkJCQkJUkVHX0VOQUJMRSk7DQorCWlmIChyZXQgPCAwKQ0KKwkJcmV0dXJuIHJl dDsNCisNCisJcmV0dXJuIGkyY19zbWJ1c193cml0ZV9ieXRlX2RhdGEoY2xpZW50LCBSRUdfU0Nf Q1RSTF9NT0RFLA0KKwkJCQkJIFNDX0NUUkxfTU9ERV9TVFJFQU1JTkcpOw0KK30NCisNCitzdGF0 aWMgaW50IG92MDJhMTBfc2V0X2N0cmwoc3RydWN0IHY0bDJfY3RybCAqY3RybCkNCit7DQorCXN0 cnVjdCBvdjAyYTEwICpvdjAyYTEwID0gY29udGFpbmVyX29mKGN0cmwtPmhhbmRsZXIsDQorCQkJ CQkgICAgICAgc3RydWN0IG92MDJhMTAsIGN0cmxfaGFuZGxlcik7DQorCXN0cnVjdCBpMmNfY2xp ZW50ICpjbGllbnQgPSB2NGwyX2dldF9zdWJkZXZkYXRhKCZvdjAyYTEwLT5zdWJkZXYpOw0KKwlz NjQgbWF4X2V4cG87DQorCWludCByZXQ7DQorDQorCS8qIFByb3BhZ2F0ZSBjaGFuZ2Ugb2YgY3Vy cmVudCBjb250cm9sIHRvIGFsbCByZWxhdGVkIGNvbnRyb2xzICovDQorCWlmIChjdHJsLT5pZCA9 PSBWNEwyX0NJRF9WQkxBTkspIHsNCisJCS8qIFVwZGF0ZSBtYXggZXhwb3N1cmUgd2hpbGUgbWVl dGluZyBleHBlY3RlZCB2YmxhbmtpbmcgKi8NCisJCW1heF9leHBvID0gb3YwMmExMC0+Y3VyX21v ZGUtPmhlaWdodCArIGN0cmwtPnZhbCAtDQorCQkJICAgT1YwMkExMF9FWFBPU1VSRV9NQVhfTUFS R0lOOw0KKwkJX192NGwyX2N0cmxfbW9kaWZ5X3JhbmdlKG92MDJhMTAtPmV4cG9zdXJlLA0KKwkJ CQkJIG92MDJhMTAtPmV4cG9zdXJlLT5taW5pbXVtLCBtYXhfZXhwbywNCisJCQkJCSBvdjAyYTEw LT5leHBvc3VyZS0+c3RlcCwNCisJCQkJCSBvdjAyYTEwLT5leHBvc3VyZS0+ZGVmYXVsdF92YWx1 ZSk7DQorCX0NCisNCisJLyogVjRMMiBjb250cm9scyB2YWx1ZXMgd2lsbCBiZSBhcHBsaWVkIG9u bHkgd2hlbiBwb3dlciBpcyBhbHJlYWR5IHVwICovDQorCWlmICghcG1fcnVudGltZV9nZXRfaWZf aW5fdXNlKCZjbGllbnQtPmRldikpDQorCQlyZXR1cm4gMDsNCisNCisJc3dpdGNoIChjdHJsLT5p ZCkgew0KKwljYXNlIFY0TDJfQ0lEX0VYUE9TVVJFOg0KKwkJcmV0ID0gb3YwMmExMF9zZXRfZXhw b3N1cmUob3YwMmExMCwgY3RybC0+dmFsKTsNCisJCWJyZWFrOw0KKwljYXNlIFY0TDJfQ0lEX0FO QUxPR1VFX0dBSU46DQorCQlyZXQgPSBvdjAyYTEwX3NldF9nYWluKG92MDJhMTAsIGN0cmwtPnZh bCk7DQorCQlicmVhazsNCisJY2FzZSBWNEwyX0NJRF9WQkxBTks6DQorCQlyZXQgPSBvdjAyYTEw X3NldF92Ymxhbmsob3YwMmExMCwgY3RybC0+dmFsKTsNCisJCWJyZWFrOw0KKwljYXNlIFY0TDJf Q0lEX1RFU1RfUEFUVEVSTjoNCisJCXJldCA9IG92MDJhMTBfc2V0X3Rlc3RfcGF0dGVybihvdjAy YTEwLCBjdHJsLT52YWwpOw0KKwkJYnJlYWs7DQorCWRlZmF1bHQ6DQorCQlyZXQgPSAtRUlOVkFM Ow0KKwkJYnJlYWs7DQorCX07DQorDQorCXBtX3J1bnRpbWVfcHV0KCZjbGllbnQtPmRldik7DQor DQorCXJldHVybiByZXQ7DQorfQ0KKw0KK3N0YXRpYyBjb25zdCBzdHJ1Y3QgdjRsMl9zdWJkZXZf dmlkZW9fb3BzIG92MDJhMTBfdmlkZW9fb3BzID0gew0KKwkuc19zdHJlYW0gPSBvdjAyYTEwX3Nf c3RyZWFtLA0KK307DQorDQorc3RhdGljIGNvbnN0IHN0cnVjdCB2NGwyX3N1YmRldl9wYWRfb3Bz IG92MDJhMTBfcGFkX29wcyA9IHsNCisJLmluaXRfY2ZnID0gb3YwMmExMF9lbnRpdHlfaW5pdF9j ZmcsDQorCS5lbnVtX21idXNfY29kZSA9IG92MDJhMTBfZW51bV9tYnVzX2NvZGUsDQorCS5lbnVt X2ZyYW1lX3NpemUgPSBvdjAyYTEwX2VudW1fZnJhbWVfc2l6ZXMsDQorCS5nZXRfZm10ID0gb3Yw MmExMF9nZXRfZm10LA0KKwkuc2V0X2ZtdCA9IG92MDJhMTBfc2V0X2ZtdCwNCit9Ow0KKw0KK3N0 YXRpYyBjb25zdCBzdHJ1Y3QgdjRsMl9zdWJkZXZfb3BzIG92MDJhMTBfc3ViZGV2X29wcyA9IHsN CisJLnZpZGVvCT0gJm92MDJhMTBfdmlkZW9fb3BzLA0KKwkucGFkCT0gJm92MDJhMTBfcGFkX29w cywNCit9Ow0KKw0KK3N0YXRpYyBjb25zdCBzdHJ1Y3QgbWVkaWFfZW50aXR5X29wZXJhdGlvbnMg b3YwMmExMF9zdWJkZXZfZW50aXR5X29wcyA9IHsNCisJLmxpbmtfdmFsaWRhdGUgPSB2NGwyX3N1 YmRldl9saW5rX3ZhbGlkYXRlLA0KK307DQorDQorc3RhdGljIGNvbnN0IHN0cnVjdCB2NGwyX2N0 cmxfb3BzIG92MDJhMTBfY3RybF9vcHMgPSB7DQorCS5zX2N0cmwgPSBvdjAyYTEwX3NldF9jdHJs LA0KK307DQorDQorc3RhdGljIGludCBvdjAyYTEwX2luaXRpYWxpemVfY29udHJvbHMoc3RydWN0 IG92MDJhMTAgKm92MDJhMTApDQorew0KKwlzdHJ1Y3QgaTJjX2NsaWVudCAqY2xpZW50ID0gdjRs Ml9nZXRfc3ViZGV2ZGF0YSgmb3YwMmExMC0+c3ViZGV2KTsNCisJY29uc3Qgc3RydWN0IG92MDJh MTBfbW9kZSAqbW9kZTsNCisJc3RydWN0IHY0bDJfY3RybF9oYW5kbGVyICpoYW5kbGVyOw0KKwlz dHJ1Y3QgdjRsMl9jdHJsICpjdHJsOw0KKwlzNjQgZXhwb3N1cmVfbWF4Ow0KKwlzNjQgdmJsYW5r X2RlZjsNCisJczY0IHBpeGVsX3JhdGU7DQorCXM2NCBoX2JsYW5rOw0KKwlpbnQgcmV0Ow0KKw0K KwloYW5kbGVyID0gJm92MDJhMTAtPmN0cmxfaGFuZGxlcjsNCisJbW9kZSA9IG92MDJhMTAtPmN1 cl9tb2RlOw0KKwlyZXQgPSB2NGwyX2N0cmxfaGFuZGxlcl9pbml0KGhhbmRsZXIsIDcpOw0KKwlp ZiAocmV0KQ0KKwkJcmV0dXJuIHJldDsNCisNCisJaGFuZGxlci0+bG9jayA9ICZvdjAyYTEwLT5t dXRleDsNCisNCisJY3RybCA9IHY0bDJfY3RybF9uZXdfaW50X21lbnUoaGFuZGxlciwgTlVMTCwg VjRMMl9DSURfTElOS19GUkVRLCAwLCAwLA0KKwkJCQkgICAgICBsaW5rX2ZyZXFfbWVudV9pdGVt cyk7DQorCWlmIChjdHJsKQ0KKwkJY3RybC0+ZmxhZ3MgfD0gVjRMMl9DVFJMX0ZMQUdfUkVBRF9P TkxZOw0KKw0KKwlwaXhlbF9yYXRlID0gdG9fcGl4ZWxfcmF0ZSgwKTsNCisJdjRsMl9jdHJsX25l d19zdGQoaGFuZGxlciwgTlVMTCwgVjRMMl9DSURfUElYRUxfUkFURSwgMCwgcGl4ZWxfcmF0ZSwg MSwNCisJCQkgIHBpeGVsX3JhdGUpOw0KKw0KKwloX2JsYW5rID0gbW9kZS0+aHRzX2RlZiAtIG1v ZGUtPndpZHRoOw0KKwl2NGwyX2N0cmxfbmV3X3N0ZChoYW5kbGVyLCBOVUxMLCBWNEwyX0NJRF9I QkxBTkssIGhfYmxhbmssIGhfYmxhbmssIDEsDQorCQkJICBoX2JsYW5rKTsNCisNCisJdmJsYW5r X2RlZiA9IG1vZGUtPnZ0c19kZWYgLSBtb2RlLT5oZWlnaHQ7DQorCXY0bDJfY3RybF9uZXdfc3Rk KGhhbmRsZXIsICZvdjAyYTEwX2N0cmxfb3BzLCBWNEwyX0NJRF9WQkxBTkssDQorCQkJICB2Ymxh bmtfZGVmLCBPVjAyQTEwX1ZUU19NQVggLSBtb2RlLT5oZWlnaHQsIDEsDQorCQkJICB2Ymxhbmtf ZGVmKTsNCisNCisJZXhwb3N1cmVfbWF4ID0gbW9kZS0+dnRzX2RlZiAtIDQ7DQorCW92MDJhMTAt PmV4cG9zdXJlID0gdjRsMl9jdHJsX25ld19zdGQoaGFuZGxlciwgJm92MDJhMTBfY3RybF9vcHMs DQorCQkJCQkgICAgICBWNEwyX0NJRF9FWFBPU1VSRSwNCisJCQkJCSAgICAgIE9WMDJBMTBfRVhQ T1NVUkVfTUlOLA0KKwkJCQkJICAgICAgZXhwb3N1cmVfbWF4LA0KKwkJCQkJICAgICAgT1YwMkEx MF9FWFBPU1VSRV9TVEVQLA0KKwkJCQkJICAgICAgbW9kZS0+ZXhwX2RlZik7DQorDQorCXY0bDJf Y3RybF9uZXdfc3RkKGhhbmRsZXIsICZvdjAyYTEwX2N0cmxfb3BzLA0KKwkJCSAgVjRMMl9DSURf QU5BTE9HVUVfR0FJTiwgT1YwMkExMF9HQUlOX01JTiwNCisJCQkgIE9WMDJBMTBfR0FJTl9NQVgs IE9WMDJBMTBfR0FJTl9TVEVQLA0KKwkJCSAgT1YwMkExMF9HQUlOX0RFRkFVTFQpOw0KKw0KKwl2 NGwyX2N0cmxfbmV3X3N0ZF9tZW51X2l0ZW1zKGhhbmRsZXIsICZvdjAyYTEwX2N0cmxfb3BzLA0K KwkJCQkgICAgIFY0TDJfQ0lEX1RFU1RfUEFUVEVSTiwNCisJCQkJICAgICBBUlJBWV9TSVpFKG92 MDJhMTBfdGVzdF9wYXR0ZXJuX21lbnUpIC0gMSwNCisJCQkJICAgICAwLCAwLCBvdjAyYTEwX3Rl c3RfcGF0dGVybl9tZW51KTsNCisNCisJaWYgKGhhbmRsZXItPmVycm9yKSB7DQorCQlyZXQgPSBo YW5kbGVyLT5lcnJvcjsNCisJCWRldl9lcnIoJmNsaWVudC0+ZGV2LCAiZmFpbGVkIHRvIGluaXQg Y29udHJvbHMoJWQpXG4iLCByZXQpOw0KKwkJZ290byBlcnJfZnJlZV9oYW5kbGVyOw0KKwl9DQor DQorCW92MDJhMTAtPnN1YmRldi5jdHJsX2hhbmRsZXIgPSBoYW5kbGVyOw0KKw0KKwlyZXR1cm4g MDsNCisNCitlcnJfZnJlZV9oYW5kbGVyOg0KKwl2NGwyX2N0cmxfaGFuZGxlcl9mcmVlKGhhbmRs ZXIpOw0KKw0KKwlyZXR1cm4gcmV0Ow0KK30NCisNCitzdGF0aWMgaW50IG92MDJhMTBfY2hlY2tf aHdjZmcoc3RydWN0IGRldmljZSAqZGV2LCBzdHJ1Y3Qgb3YwMmExMCAqb3YwMmExMCkNCit7DQor CXN0cnVjdCBmd25vZGVfaGFuZGxlICplcDsNCisJc3RydWN0IGZ3bm9kZV9oYW5kbGUgKmZ3bm9k ZSA9IGRldl9md25vZGUoZGV2KTsNCisJc3RydWN0IHY0bDJfZndub2RlX2VuZHBvaW50IGJ1c19j ZmcgPSB7DQorCQkuYnVzX3R5cGUgPSBWNEwyX01CVVNfQ1NJMl9EUEhZLA0KKwl9Ow0KKwl1bnNp Z25lZCBpbnQgaSwgajsNCisJaW50IHJldDsNCisNCisJaWYgKCFmd25vZGUpDQorCQlyZXR1cm4g LUVJTlZBTDsNCisNCisJZXAgPSBmd25vZGVfZ3JhcGhfZ2V0X25leHRfZW5kcG9pbnQoZndub2Rl LCBOVUxMKTsNCisJaWYgKCFlcCkNCisJCXJldHVybiAtRU5YSU87DQorDQorCXJldCA9IHY0bDJf Zndub2RlX2VuZHBvaW50X2FsbG9jX3BhcnNlKGVwLCAmYnVzX2NmZyk7DQorCWZ3bm9kZV9oYW5k bGVfcHV0KGVwKTsNCisJaWYgKHJldCkNCisJCXJldHVybiByZXQ7DQorDQorCWlmICghYnVzX2Nm Zy5ucl9vZl9saW5rX2ZyZXF1ZW5jaWVzKSB7DQorCQlkZXZfZXJyKGRldiwgIm5vIGxpbmsgZnJl cXVlbmNpZXMgZGVmaW5lZCIpOw0KKwkJcmV0ID0gLUVJTlZBTDsNCisJCWdvdG8gY2hlY2tfaHdj ZmdfZXJyb3I7DQorCX0NCisNCisJZm9yIChpID0gMDsgaSA8IEFSUkFZX1NJWkUobGlua19mcmVx X21lbnVfaXRlbXMpOyBpKyspIHsNCisJCWZvciAoaiA9IDA7IGogPCBidXNfY2ZnLm5yX29mX2xp bmtfZnJlcXVlbmNpZXM7IGorKykgew0KKwkJCWlmIChsaW5rX2ZyZXFfbWVudV9pdGVtc1tpXSA9 PQ0KKwkJCQlidXNfY2ZnLmxpbmtfZnJlcXVlbmNpZXNbal0pDQorCQkJCWJyZWFrOw0KKwkJfQ0K Kw0KKwkJaWYgKGogPT0gYnVzX2NmZy5ucl9vZl9saW5rX2ZyZXF1ZW5jaWVzKSB7DQorCQkJZGV2 X2VycihkZXYsICJubyBsaW5rIGZyZXF1ZW5jeSAlbGxkIHN1cHBvcnRlZCIsDQorCQkJCWxpbmtf ZnJlcV9tZW51X2l0ZW1zW2ldKTsNCisJCQlyZXQgPSAtRUlOVkFMOw0KKwkJCWdvdG8gY2hlY2tf aHdjZmdfZXJyb3I7DQorCQl9DQorCX0NCisNCitjaGVja19od2NmZ19lcnJvcjoNCisJdjRsMl9m d25vZGVfZW5kcG9pbnRfZnJlZSgmYnVzX2NmZyk7DQorDQorCXJldHVybiByZXQ7DQorfQ0KKw0K K3N0YXRpYyBpbnQgb3YwMmExMF9wcm9iZShzdHJ1Y3QgaTJjX2NsaWVudCAqY2xpZW50KQ0KK3sN CisJc3RydWN0IGRldmljZSAqZGV2ID0gJmNsaWVudC0+ZGV2Ow0KKwlzdHJ1Y3Qgb3YwMmExMCAq b3YwMmExMDsNCisJdW5zaWduZWQgaW50IHJvdGF0aW9uOw0KKwl1bnNpZ25lZCBpbnQgY2xvY2tf bGFuZV90eF9zcGVlZDsNCisJdW5zaWduZWQgaW50IGk7DQorCWludCByZXQ7DQorDQorCW92MDJh MTAgPSBkZXZtX2t6YWxsb2MoZGV2LCBzaXplb2YoKm92MDJhMTApLCBHRlBfS0VSTkVMKTsNCisJ aWYgKCFvdjAyYTEwKQ0KKwkJcmV0dXJuIC1FTk9NRU07DQorDQorCXJldCA9IG92MDJhMTBfY2hl Y2tfaHdjZmcoZGV2LCBvdjAyYTEwKTsNCisJaWYgKHJldCkgew0KKwkJZGV2X2VycihkZXYsICJm YWlsZWQgdG8gY2hlY2sgSFcgY29uZmlndXJhdGlvbjogJWQiLCByZXQpOw0KKwkJcmV0dXJuIHJl dDsNCisJfQ0KKw0KKwl2NGwyX2kyY19zdWJkZXZfaW5pdCgmb3YwMmExMC0+c3ViZGV2LCBjbGll bnQsICZvdjAyYTEwX3N1YmRldl9vcHMpOw0KKwlvdjAyYTEwLT5taXBpX2Nsb2NrX3R4X3NwZWVk ID0gT1YwMkExMF9NSVBJX1RYX1NQRUVEX0RFRkFVTFQ7DQorCW92MDJhMTAtPmZtdC5jb2RlID0g TUVESUFfQlVTX0ZNVF9TQkdHUjEwXzFYMTA7DQorDQorCS8qIE9wdGlvbmFsIGluZGljYXRpb24g b2YgcGh5c2ljYWwgcm90YXRpb24gb2Ygc2Vuc29yICovDQorCXJldCA9IGZ3bm9kZV9wcm9wZXJ0 eV9yZWFkX3UzMihkZXZfZndub2RlKGRldiksICJyb3RhdGlvbiIsICZyb3RhdGlvbik7DQorCWlm ICghcmV0ICYmIHJvdGF0aW9uID09IDE4MCkgew0KKwkJb3YwMmExMC0+dXBzaWRlX2Rvd24gPSB0 cnVlOw0KKwkJb3YwMmExMC0+Zm10LmNvZGUgPSBNRURJQV9CVVNfRk1UX1NSR0dCMTBfMVgxMDsN CisJfQ0KKw0KKwkvKiBPcHRpb25hbCBpbmRpY2F0aW9uIG9mIG1pcGkgVFggc3BlZWQgKi8NCisJ cmV0ID0gZndub2RlX3Byb3BlcnR5X3JlYWRfdTMyKGRldl9md25vZGUoZGV2KSwgIm92dGksbWlw aS10eC1zcGVlZCIsDQorCQkJCSAgICAgICAmY2xvY2tfbGFuZV90eF9zcGVlZCk7DQorDQorCWlm ICghcmV0KQ0KKwkJb3YwMmExMC0+bWlwaV9jbG9ja190eF9zcGVlZCA9IGNsb2NrX2xhbmVfdHhf c3BlZWQ7DQorDQorCS8qIEdldCBzeXN0ZW0gY2xvY2sgKGVjbGspICovDQorCW92MDJhMTAtPmVj bGsgPSBkZXZtX2Nsa19nZXQoZGV2LCAiZWNsayIpOw0KKwlpZiAoSVNfRVJSKG92MDJhMTAtPmVj bGspKSB7DQorCQlyZXQgPSBQVFJfRVJSKG92MDJhMTAtPmVjbGspOw0KKwkJZGV2X2VycihkZXYs ICJmYWlsZWQgdG8gZ2V0IGVjbGsgJWRcbiIsIHJldCk7DQorCQlyZXR1cm4gcmV0Ow0KKwl9DQor DQorCXJldCA9IGZ3bm9kZV9wcm9wZXJ0eV9yZWFkX3UzMihkZXZfZndub2RlKGRldiksICJjbG9j ay1mcmVxdWVuY3kiLA0KKwkJCQkgICAgICAgJm92MDJhMTAtPmVjbGtfZnJlcSk7DQorCWlmIChy ZXQpIHsNCisJCWRldl9lcnIoZGV2LCAiZmFpbGVkIHRvIGdldCBlY2xrIGZyZXF1ZW5jeVxuIik7 DQorCQlyZXR1cm4gcmV0Ow0KKwl9DQorDQorCXJldCA9IGNsa19zZXRfcmF0ZShvdjAyYTEwLT5l Y2xrLCBvdjAyYTEwLT5lY2xrX2ZyZXEpOw0KKwlpZiAocmV0KSB7DQorCQlkZXZfZXJyKGRldiwg ImZhaWxlZCB0byBzZXQgZWNsayBmcmVxdWVuY3kgKDI0TUh6KVxuIik7DQorCQlyZXR1cm4gcmV0 Ow0KKwl9DQorDQorCWlmIChjbGtfZ2V0X3JhdGUob3YwMmExMC0+ZWNsaykgIT0gT1YwMkExMF9F Q0xLX0ZSRVEpIHsNCisJCWRldl93YXJuKGRldiwgImVjbGsgbWlzbWF0Y2hlZCwgbW9kZSBpcyBi YXNlZCBvbiAyNE1IelxuIik7DQorCQlyZXR1cm4gLUVJTlZBTDsNCisJfQ0KKw0KKwlvdjAyYTEw LT5wZF9ncGlvID0gZGV2bV9ncGlvZF9nZXQoZGV2LCAicG93ZXJkb3duIiwgR1BJT0RfT1VUX0hJ R0gpOw0KKwlpZiAoSVNfRVJSKG92MDJhMTAtPnBkX2dwaW8pKSB7DQorCQlyZXQgPSBQVFJfRVJS KG92MDJhMTAtPnBkX2dwaW8pOw0KKwkJZGV2X2VycihkZXYsICJmYWlsZWQgdG8gZ2V0IHBvd2Vy ZG93bi1ncGlvcyAlZFxuIiwgcmV0KTsNCisJCXJldHVybiByZXQ7DQorCX0NCisNCisJb3YwMmEx MC0+cnN0X2dwaW8gPSBkZXZtX2dwaW9kX2dldChkZXYsICJyZXNldCIsIEdQSU9EX09VVF9ISUdI KTsNCisJaWYgKElTX0VSUihvdjAyYTEwLT5yc3RfZ3BpbykpIHsNCisJCXJldCA9IFBUUl9FUlIo b3YwMmExMC0+cnN0X2dwaW8pOw0KKwkJZGV2X2VycihkZXYsICJmYWlsZWQgdG8gZ2V0IHJlc2V0 LWdwaW9zICVkXG4iLCByZXQpOw0KKwkJcmV0dXJuIHJldDsNCisJfQ0KKw0KKwlmb3IgKGkgPSAw OyBpIDwgQVJSQVlfU0laRShvdjAyYTEwX3N1cHBseV9uYW1lcyk7IGkrKykNCisJCW92MDJhMTAt PnN1cHBsaWVzW2ldLnN1cHBseSA9IG92MDJhMTBfc3VwcGx5X25hbWVzW2ldOw0KKw0KKwlyZXQg PSBkZXZtX3JlZ3VsYXRvcl9idWxrX2dldChkZXYsIEFSUkFZX1NJWkUob3YwMmExMF9zdXBwbHlf bmFtZXMpLA0KKwkJCQkgICAgICBvdjAyYTEwLT5zdXBwbGllcyk7DQorCWlmIChyZXQpIHsNCisJ CWRldl9lcnIoZGV2LCAiZmFpbGVkIHRvIGdldCByZWd1bGF0b3JzXG4iKTsNCisJCXJldHVybiBy ZXQ7DQorCX0NCisNCisJbXV0ZXhfaW5pdCgmb3YwMmExMC0+bXV0ZXgpOw0KKwlvdjAyYTEwLT5j dXJfbW9kZSA9ICZzdXBwb3J0ZWRfbW9kZXNbMF07DQorDQorCXJldCA9IG92MDJhMTBfaW5pdGlh bGl6ZV9jb250cm9scyhvdjAyYTEwKTsNCisJaWYgKHJldCkgew0KKwkJZGV2X2VycihkZXYsICJm YWlsZWQgdG8gaW5pdGlhbGl6ZSBjb250cm9sc1xuIik7DQorCQlnb3RvIGVycl9kZXN0cm95X211 dGV4Ow0KKwl9DQorDQorCW92MDJhMTAtPnN1YmRldi5mbGFncyB8PSBWNEwyX1NVQkRFVl9GTF9I QVNfREVWTk9ERTsNCisJb3YwMmExMC0+c3ViZGV2LmVudGl0eS5vcHMgPSAmb3YwMmExMF9zdWJk ZXZfZW50aXR5X29wczsNCisJb3YwMmExMC0+c3ViZGV2LmVudGl0eS5mdW5jdGlvbiA9IE1FRElB X0VOVF9GX0NBTV9TRU5TT1I7DQorCW92MDJhMTAtPnBhZC5mbGFncyA9IE1FRElBX1BBRF9GTF9T T1VSQ0U7DQorDQorCXJldCA9IG1lZGlhX2VudGl0eV9wYWRzX2luaXQoJm92MDJhMTAtPnN1YmRl di5lbnRpdHksIDEsICZvdjAyYTEwLT5wYWQpOw0KKwlpZiAocmV0IDwgMCkgew0KKwkJZGV2X2Vy cihkZXYsICJmYWlsZWQgdG8gaW5pdCBlbnRpdHkgcGFkczogJWQiLCByZXQpOw0KKwkJZ290byBl cnJfZnJlZV9oYW5kbGVyOw0KKwl9DQorDQorCXBtX3J1bnRpbWVfZW5hYmxlKGRldik7DQorCWlm ICghcG1fcnVudGltZV9lbmFibGVkKGRldikpIHsNCisJCXJldCA9IG92MDJhMTBfcG93ZXJfb24o ZGV2KTsNCisJCWlmIChyZXQgPCAwKSB7DQorCQkJZGV2X2VycihkZXYsICJmYWlsZWQgdG8gcG93 ZXIgb246ICVkXG4iLCByZXQpOw0KKwkJCWdvdG8gZXJyX2NsZWFuX2VudGl0eTsNCisJCX0NCisJ fQ0KKw0KKwlyZXQgPSB2NGwyX2FzeW5jX3JlZ2lzdGVyX3N1YmRldigmb3YwMmExMC0+c3ViZGV2 KTsNCisJaWYgKHJldCkgew0KKwkJZGV2X2VycihkZXYsICJmYWlsZWQgdG8gcmVnaXN0ZXIgVjRM MiBzdWJkZXY6ICVkIiwgcmV0KTsNCisJCWdvdG8gZXJyX3Bvd2VyX29mZjsNCisJfQ0KKw0KKwly ZXR1cm4gMDsNCisNCitlcnJfcG93ZXJfb2ZmOg0KKwlpZiAocG1fcnVudGltZV9lbmFibGVkKGRl dikpDQorCQlwbV9ydW50aW1lX2Rpc2FibGUoZGV2KTsNCisJZWxzZQ0KKwkJb3YwMmExMF9wb3dl cl9vZmYoZGV2KTsNCitlcnJfY2xlYW5fZW50aXR5Og0KKwltZWRpYV9lbnRpdHlfY2xlYW51cCgm b3YwMmExMC0+c3ViZGV2LmVudGl0eSk7DQorZXJyX2ZyZWVfaGFuZGxlcjoNCisJdjRsMl9jdHJs X2hhbmRsZXJfZnJlZShvdjAyYTEwLT5zdWJkZXYuY3RybF9oYW5kbGVyKTsNCitlcnJfZGVzdHJv eV9tdXRleDoNCisJbXV0ZXhfZGVzdHJveSgmb3YwMmExMC0+bXV0ZXgpOw0KKw0KKwlyZXR1cm4g cmV0Ow0KK30NCisNCitzdGF0aWMgaW50IG92MDJhMTBfcmVtb3ZlKHN0cnVjdCBpMmNfY2xpZW50 ICpjbGllbnQpDQorew0KKwlzdHJ1Y3QgdjRsMl9zdWJkZXYgKnNkID0gaTJjX2dldF9jbGllbnRk YXRhKGNsaWVudCk7DQorCXN0cnVjdCBvdjAyYTEwICpvdjAyYTEwID0gdG9fb3YwMmExMChzZCk7 DQorDQorCXY0bDJfYXN5bmNfdW5yZWdpc3Rlcl9zdWJkZXYoc2QpOw0KKwltZWRpYV9lbnRpdHlf Y2xlYW51cCgmc2QtPmVudGl0eSk7DQorCXY0bDJfY3RybF9oYW5kbGVyX2ZyZWUoc2QtPmN0cmxf aGFuZGxlcik7DQorCXBtX3J1bnRpbWVfZGlzYWJsZSgmY2xpZW50LT5kZXYpOw0KKwlpZiAoIXBt X3J1bnRpbWVfc3RhdHVzX3N1c3BlbmRlZCgmY2xpZW50LT5kZXYpKQ0KKwkJb3YwMmExMF9wb3dl cl9vZmYoJmNsaWVudC0+ZGV2KTsNCisJcG1fcnVudGltZV9zZXRfc3VzcGVuZGVkKCZjbGllbnQt PmRldik7DQorCW11dGV4X2Rlc3Ryb3koJm92MDJhMTAtPm11dGV4KTsNCisNCisJcmV0dXJuIDA7 DQorfQ0KKw0KK3N0YXRpYyBjb25zdCBzdHJ1Y3Qgb2ZfZGV2aWNlX2lkIG92MDJhMTBfb2ZfbWF0 Y2hbXSA9IHsNCisJeyAuY29tcGF0aWJsZSA9ICJvdnRpLG92MDJhMTAiIH0sDQorCXt9DQorfTsN CitNT0RVTEVfREVWSUNFX1RBQkxFKG9mLCBvdjAyYTEwX29mX21hdGNoKTsNCisNCitzdGF0aWMg c3RydWN0IGkyY19kcml2ZXIgb3YwMmExMF9pMmNfZHJpdmVyID0gew0KKwkuZHJpdmVyID0gew0K KwkJLm5hbWUgPSAib3YwMmExMCIsDQorCQkucG0gPSAmb3YwMmExMF9wbV9vcHMsDQorCQkub2Zf bWF0Y2hfdGFibGUgPSBvdjAyYTEwX29mX21hdGNoLA0KKwl9LA0KKwkucHJvYmVfbmV3CT0gJm92 MDJhMTBfcHJvYmUsDQorCS5yZW1vdmUJCT0gJm92MDJhMTBfcmVtb3ZlLA0KK307DQorDQorbW9k dWxlX2kyY19kcml2ZXIob3YwMmExMF9pMmNfZHJpdmVyKTsNCisNCitNT0RVTEVfQVVUSE9SKCJE b25nY2h1biBaaHUgPGRvbmdjaHVuLnpodUBtZWRpYXRlay5jb20+Iik7DQorTU9EVUxFX0RFU0NS SVBUSU9OKCJPbW5pVmlzaW9uIE9WMDJBMTAgc2Vuc29yIGRyaXZlciIpOw0KK01PRFVMRV9MSUNF TlNFKCJHUEwgdjIiKTsNCi0tIA0KMi45LjINCg== From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.8 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, MENTIONS_GIT_HOSTING,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A9360C433E0 for ; Fri, 10 Jul 2020 10:20:06 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 57CD32077D for ; Fri, 10 Jul 2020 10:20:06 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="Od3S8UkX"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="sdBmm+a+" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 57CD32077D Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-ID:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=i+TCRM+jS8jxdQ7hSg8QhiPFoJ30e8O9G9k0Wy+dMCI=; b=Od3S8UkX0uAdyLWUhwIa2dG8k 8uyb0fimNl55A5DYX51NXDO4dgbsPvPsAZ7339JQnIbIeTOL+HfkT86dozRu9vjCRq2vdIQ/pkOrs aCu9hnsJSCROwzFiX0IA2a/BkZrBSPSTeW11zYqYP87VSQZjjL4JR8GyNcQmp+36riY4d9onA7H3d Ak7Ff0t5ua2JrrkvjpseFfIAskRthIPltMSlXszQ1MIHhfglkOPFmrU7F1IyxQhYLe1LyxKbuNdmT 6j0f5Z6gqKutU1VdTDQ9g3C4/p1C0s6he8zSDNmgATWD+3ntaif7TvMNRbTn2L3rt3DX46flfaxGM kx9OozUPA==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jtq8I-0002oz-4w; Fri, 10 Jul 2020 10:19:54 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1jtq88-0002k3-PQ; Fri, 10 Jul 2020 10:19:50 +0000 X-UUID: 0d34c3a7a34643b1ba5aab326c900cfc-20200710 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=MivBBVxEJb72HxTrv6XGwM/S5e3vdMpQxQjDdF8m33I=; b=sdBmm+a+Ii8/7l/Ahi7zZSmmmLG1pDoe15X8PbBX8YdGHnWAWV9ZE/Wvi1nr8yYxAualpAfuRYqZ0tVuHJlGNEyZ8lvR6HeLE7aMWYyVn90NKQZEn14t05j0qp8Joc0krs4orZ/fcHmapFvpET50hC5U3pjAYNnQ/PvqJoNeJYg=; X-UUID: 0d34c3a7a34643b1ba5aab326c900cfc-20200710 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLS) with ESMTP id 1180823192; Fri, 10 Jul 2020 02:19:40 -0800 Received: from MTKMBS07N2.mediatek.inc (172.21.101.141) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 10 Jul 2020 03:19:38 -0700 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 10 Jul 2020 18:19:37 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 10 Jul 2020 18:19:36 +0800 From: Dongchun Zhu To: , , , , , , , , Subject: [PATCH v13 2/2] media: i2c: Add OV02A10 image sensor driver Date: Fri, 10 Jul 2020 18:18:50 +0800 Message-ID: <20200710101850.4604-3-dongchun.zhu@mediatek.com> X-Mailer: git-send-email 2.9.2 In-Reply-To: <20200710101850.4604-1-dongchun.zhu@mediatek.com> References: <20200710101850.4604-1-dongchun.zhu@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200710_061945_088061_9A439554 X-CRM114-Status: GOOD ( 21.46 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, srv_heupstream@mediatek.com, shengnan.wang@mediatek.com, sj.huang@mediatek.com, linux-mediatek@lists.infradead.org, dongchun.zhu@mediatek.com, louis.kuo@mediatek.com, matrix.zhu@aliyun.com, 1095088256@qq.com, linux-arm-kernel@lists.infradead.org, linux-media@vger.kernel.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Add a V4L2 sub-device driver for OmniVision OV02A10 image sensor. Reviewed-by: Tomasz Figa Signed-off-by: Dongchun Zhu --- MAINTAINERS | 1 + drivers/media/i2c/Kconfig | 13 + drivers/media/i2c/Makefile | 1 + drivers/media/i2c/ov02a10.c | 1050 +++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 1065 insertions(+) create mode 100644 drivers/media/i2c/ov02a10.c diff --git a/MAINTAINERS b/MAINTAINERS index 378c961..a6a2f8b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12566,6 +12566,7 @@ L: linux-media@vger.kernel.org S: Maintained T: git git://linuxtv.org/media_tree.git F: Documentation/devicetree/bindings/media/i2c/ovti,ov02a10.yaml +F: drivers/media/i2c/ov02a10.c OMNIVISION OV13858 SENSOR DRIVER M: Sakari Ailus diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig index da11036..65519cf 100644 --- a/drivers/media/i2c/Kconfig +++ b/drivers/media/i2c/Kconfig @@ -812,6 +812,19 @@ config VIDEO_IMX355 To compile this driver as a module, choose M here: the module will be called imx355. +config VIDEO_OV02A10 + tristate "OmniVision OV02A10 sensor support" + depends on I2C && VIDEO_V4L2 + select MEDIA_CONTROLLER + select VIDEO_V4L2_SUBDEV_API + select V4L2_FWNODE + help + This is a Video4Linux2 sensor driver for the OmniVision + OV02A10 camera. + + To compile this driver as a module, choose M here: the + module will be called ov02a10. + config VIDEO_OV2640 tristate "OmniVision OV2640 sensor support" depends on VIDEO_V4L2 && I2C diff --git a/drivers/media/i2c/Makefile b/drivers/media/i2c/Makefile index 993acab..384e676 100644 --- a/drivers/media/i2c/Makefile +++ b/drivers/media/i2c/Makefile @@ -63,6 +63,7 @@ obj-$(CONFIG_VIDEO_VP27SMPX) += vp27smpx.o obj-$(CONFIG_VIDEO_SONY_BTF_MPX) += sony-btf-mpx.o obj-$(CONFIG_VIDEO_UPD64031A) += upd64031a.o obj-$(CONFIG_VIDEO_UPD64083) += upd64083.o +obj-$(CONFIG_VIDEO_OV02A10) += ov02a10.o obj-$(CONFIG_VIDEO_OV2640) += ov2640.o obj-$(CONFIG_VIDEO_OV2680) += ov2680.o obj-$(CONFIG_VIDEO_OV2685) += ov2685.o diff --git a/drivers/media/i2c/ov02a10.c b/drivers/media/i2c/ov02a10.c new file mode 100644 index 0000000..5ffc97a --- /dev/null +++ b/drivers/media/i2c/ov02a10.c @@ -0,0 +1,1050 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2020 MediaTek Inc. + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define CHIP_ID 0x2509 +#define OV02A10_REG_CHIP_ID_H 0x02 +#define OV02A10_REG_CHIP_ID_L 0x03 + +/* Bit[1] vertical upside down */ +/* Bit[0] horizontal mirror */ +#define REG_MIRROR_FLIP_CONTROL 0x3f + +/* Orientation */ +#define REG_MIRROR_FLIP_ENABLE 0x03 + +/* Bit[2:0] MIPI transmission speed select */ +#define TX_SPEED_AREA_SEL 0xa1 +#define OV02A10_MIPI_TX_SPEED_DEFAULT 0x03 + +#define REG_PAGE_SWITCH 0xfd +#define REG_GLOBAL_EFFECTIVE 0x01 +#define REG_ENABLE BIT(0) + +#define REG_SC_CTRL_MODE 0xac +#define SC_CTRL_MODE_STANDBY 0x00 +#define SC_CTRL_MODE_STREAMING 0x01 + +#define OV02A10_EXP_SHIFT 8 +#define OV02A10_REG_EXPOSURE_H 0x03 +#define OV02A10_REG_EXPOSURE_L 0x04 +#define OV02A10_EXPOSURE_MIN 4 +#define OV02A10_EXPOSURE_MAX_MARGIN 4 +#define OV02A10_EXPOSURE_STEP 1 + +#define OV02A10_VTS_SHIFT 8 +#define OV02A10_REG_VTS_H 0x05 +#define OV02A10_REG_VTS_L 0x06 +#define OV02A10_VTS_MAX 0x209f +#define OV02A10_BASIC_LINE 1224 + +#define OV02A10_REG_GAIN 0x24 +#define OV02A10_GAIN_MIN 0x10 +#define OV02A10_GAIN_MAX 0xf8 +#define OV02A10_GAIN_STEP 0x01 +#define OV02A10_GAIN_DEFAULT 0x40 + +/* Test pattern control */ +#define OV02A10_REG_TEST_PATTERN 0xb6 + +#define HZ_PER_MHZ 1000000L +#define OV02A10_LINK_FREQ_390MHZ (390 * HZ_PER_MHZ) +#define OV02A10_ECLK_FREQ (24 * HZ_PER_MHZ) +#define OV02A10_DATA_LANES 1 +#define OV02A10_BITS_PER_SAMPLE 10 + +static const char * const ov02a10_supply_names[] = { + "dovdd", /* Digital I/O power */ + "avdd", /* Analog power */ + "dvdd", /* Digital core power */ +}; + +struct ov02a10_reg { + u8 addr; + u8 val; +}; + +struct ov02a10_reg_list { + u32 num_of_regs; + const struct ov02a10_reg *regs; +}; + +struct ov02a10_mode { + u32 width; + u32 height; + u32 exp_def; + u32 hts_def; + u32 vts_def; + const struct ov02a10_reg_list reg_list; +}; + +struct ov02a10 { + u32 eclk_freq; + u32 mipi_clock_tx_speed; + + struct clk *eclk; + struct gpio_desc *pd_gpio; + struct gpio_desc *rst_gpio; + struct regulator_bulk_data supplies[ARRAY_SIZE(ov02a10_supply_names)]; + + bool streaming; + bool upside_down; + + /* + * Serialize control access, get/set format, get selection + * and start streaming. + */ + struct mutex mutex; + struct v4l2_subdev subdev; + struct media_pad pad; + struct v4l2_mbus_framefmt fmt; + struct v4l2_ctrl_handler ctrl_handler; + struct v4l2_ctrl *exposure; + + const struct ov02a10_mode *cur_mode; +}; + +static inline struct ov02a10 *to_ov02a10(struct v4l2_subdev *sd) +{ + return container_of(sd, struct ov02a10, subdev); +} + +/* + * eclk 24Mhz + * pclk 39Mhz + * linelength 934(0x3a6) + * framelength 1390(0x56E) + * grabwindow_width 1600 + * grabwindow_height 1200 + * max_framerate 30fps + * mipi_datarate per lane 780Mbps + */ +static const struct ov02a10_reg ov02a10_1600x1200_regs[] = { + {0xfd, 0x01}, + {0xac, 0x00}, + {0xfd, 0x00}, + {0x2f, 0x29}, + {0x34, 0x00}, + {0x35, 0x21}, + {0x30, 0x15}, + {0x33, 0x01}, + {0xfd, 0x01}, + {0x44, 0x00}, + {0x2a, 0x4c}, + {0x2b, 0x1e}, + {0x2c, 0x60}, + {0x25, 0x11}, + {0x03, 0x01}, + {0x04, 0xae}, + {0x09, 0x00}, + {0x0a, 0x02}, + {0x06, 0xa6}, + {0x31, 0x00}, + {0x24, 0x40}, + {0x01, 0x01}, + {0xfb, 0x73}, + {0xfd, 0x01}, + {0x16, 0x04}, + {0x1c, 0x09}, + {0x21, 0x42}, + {0x12, 0x04}, + {0x13, 0x10}, + {0x11, 0x40}, + {0x33, 0x81}, + {0xd0, 0x00}, + {0xd1, 0x01}, + {0xd2, 0x00}, + {0x50, 0x10}, + {0x51, 0x23}, + {0x52, 0x20}, + {0x53, 0x10}, + {0x54, 0x02}, + {0x55, 0x20}, + {0x56, 0x02}, + {0x58, 0x48}, + {0x5d, 0x15}, + {0x5e, 0x05}, + {0x66, 0x66}, + {0x68, 0x68}, + {0x6b, 0x00}, + {0x6c, 0x00}, + {0x6f, 0x40}, + {0x70, 0x40}, + {0x71, 0x0a}, + {0x72, 0xf0}, + {0x73, 0x10}, + {0x75, 0x80}, + {0x76, 0x10}, + {0x84, 0x00}, + {0x85, 0x10}, + {0x86, 0x10}, + {0x87, 0x00}, + {0x8a, 0x22}, + {0x8b, 0x22}, + {0x19, 0xf1}, + {0x29, 0x01}, + {0xfd, 0x01}, + {0x9d, 0x16}, + {0xa0, 0x29}, + {0xa1, 0x03}, + {0xad, 0x62}, + {0xae, 0x00}, + {0xaf, 0x85}, + {0xb1, 0x01}, + {0x8e, 0x06}, + {0x8f, 0x40}, + {0x90, 0x04}, + {0x91, 0xb0}, + {0x45, 0x01}, + {0x46, 0x00}, + {0x47, 0x6c}, + {0x48, 0x03}, + {0x49, 0x8b}, + {0x4a, 0x00}, + {0x4b, 0x07}, + {0x4c, 0x04}, + {0x4d, 0xb7}, + {0xf0, 0x40}, + {0xf1, 0x40}, + {0xf2, 0x40}, + {0xf3, 0x40}, + {0x3f, 0x00}, + {0xfd, 0x01}, + {0x05, 0x00}, + {0x06, 0xa6}, + {0xfd, 0x01}, +}; + +static const char * const ov02a10_test_pattern_menu[] = { + "Disabled", + "Eight Vertical Colour Bars", +}; + +static const s64 link_freq_menu_items[] = { + OV02A10_LINK_FREQ_390MHZ, +}; + +static u64 to_pixel_rate(u32 f_index) +{ + u64 pixel_rate = link_freq_menu_items[f_index] * 2 * OV02A10_DATA_LANES; + + do_div(pixel_rate, OV02A10_BITS_PER_SAMPLE); + + return pixel_rate; +} + +static const struct ov02a10_mode supported_modes[] = { + { + .width = 1600, + .height = 1200, + .exp_def = 0x01ae, + .hts_def = 0x03a6, + .vts_def = 0x056e, + .reg_list = { + .num_of_regs = ARRAY_SIZE(ov02a10_1600x1200_regs), + .regs = ov02a10_1600x1200_regs, + }, + }, +}; + +static int ov02a10_write_array(struct ov02a10 *ov02a10, + const struct ov02a10_reg_list *r_list) +{ + struct i2c_client *client = v4l2_get_subdevdata(&ov02a10->subdev); + unsigned int i; + int ret; + + for (i = 0; i < r_list->num_of_regs; i++) { + ret = i2c_smbus_write_byte_data(client, r_list->regs[i].addr, + r_list->regs[i].val); + if (ret < 0) + return ret; + } + + return 0; +} + +static int ov02a10_read_smbus(struct ov02a10 *ov02a10, unsigned char reg, + unsigned char *val) +{ + struct i2c_client *client = v4l2_get_subdevdata(&ov02a10->subdev); + int ret; + + ret = i2c_smbus_read_byte_data(client, reg); + if (ret < 0) + return ret; + + *val = (unsigned char)ret; + + return 0; +} + +static void ov02a10_fill_fmt(const struct ov02a10_mode *mode, + struct v4l2_mbus_framefmt *fmt) +{ + fmt->width = mode->width; + fmt->height = mode->height; + fmt->field = V4L2_FIELD_NONE; +} + +static int ov02a10_set_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *fmt) +{ + struct ov02a10 *ov02a10 = to_ov02a10(sd); + struct v4l2_mbus_framefmt *mbus_fmt = &fmt->format; + struct v4l2_mbus_framefmt *frame_fmt; + int ret = 0; + + mutex_lock(&ov02a10->mutex); + + if (ov02a10->streaming && fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE) { + ret = -EBUSY; + goto error; + } + + /* Only one sensor mode supported */ + mbus_fmt->code = ov02a10->fmt.code; + ov02a10_fill_fmt(ov02a10->cur_mode, mbus_fmt); + + if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) + frame_fmt = v4l2_subdev_get_try_format(sd, cfg, 0); + else + frame_fmt = &ov02a10->fmt; + + *frame_fmt = *mbus_fmt; + +error: + mutex_unlock(&ov02a10->mutex); + return ret; +} + +static int ov02a10_get_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *fmt) +{ + struct ov02a10 *ov02a10 = to_ov02a10(sd); + struct v4l2_mbus_framefmt *mbus_fmt = &fmt->format; + + mutex_lock(&ov02a10->mutex); + + if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { + fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad); + } else { + fmt->format = ov02a10->fmt; + mbus_fmt->code = ov02a10->fmt.code; + ov02a10_fill_fmt(ov02a10->cur_mode, mbus_fmt); + } + + mutex_unlock(&ov02a10->mutex); + + return 0; +} + +static int ov02a10_enum_mbus_code(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_mbus_code_enum *code) +{ + struct ov02a10 *ov02a10 = to_ov02a10(sd); + + if (code->index != 0) + return -EINVAL; + + code->code = ov02a10->fmt.code; + + return 0; +} + +static int ov02a10_enum_frame_sizes(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_frame_size_enum *fse) +{ + if (fse->index >= ARRAY_SIZE(supported_modes)) + return -EINVAL; + + fse->min_width = supported_modes[fse->index].width; + fse->max_width = supported_modes[fse->index].width; + fse->max_height = supported_modes[fse->index].height; + fse->min_height = supported_modes[fse->index].height; + + return 0; +} + +static int ov02a10_check_sensor_id(struct ov02a10 *ov02a10) +{ + struct i2c_client *client = v4l2_get_subdevdata(&ov02a10->subdev); + u16 id; + u8 chip_id_h; + u8 chip_id_l; + int ret; + + /* Check sensor revision */ + ret = ov02a10_read_smbus(ov02a10, OV02A10_REG_CHIP_ID_H, &chip_id_h); + if (ret) + return ret; + + ret = ov02a10_read_smbus(ov02a10, OV02A10_REG_CHIP_ID_L, &chip_id_l); + if (ret) + return ret; + + id = (chip_id_h << 8) | chip_id_l; + if (id != CHIP_ID) { + dev_err(&client->dev, "Unexpected sensor id(%04x)\n", id); + return -EINVAL; + } + + return 0; +} + +static int ov02a10_power_on(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct ov02a10 *ov02a10 = to_ov02a10(sd); + int ret; + + gpiod_set_value_cansleep(ov02a10->rst_gpio, 1); + gpiod_set_value_cansleep(ov02a10->pd_gpio, 1); + + ret = clk_prepare_enable(ov02a10->eclk); + if (ret < 0) { + dev_err(dev, "failed to enable eclk\n"); + return ret; + } + + ret = regulator_bulk_enable(ARRAY_SIZE(ov02a10_supply_names), + ov02a10->supplies); + if (ret < 0) { + dev_err(dev, "failed to enable regulators\n"); + goto disable_clk; + } + usleep_range(5000, 6000); + + gpiod_set_value_cansleep(ov02a10->pd_gpio, 0); + usleep_range(5000, 6000); + + gpiod_set_value_cansleep(ov02a10->rst_gpio, 0); + usleep_range(5000, 6000); + + ret = ov02a10_check_sensor_id(ov02a10); + if (ret) + goto disable_regulator; + + return 0; + +disable_regulator: + regulator_bulk_disable(ARRAY_SIZE(ov02a10_supply_names), + ov02a10->supplies); +disable_clk: + clk_disable_unprepare(ov02a10->eclk); + + return ret; +} + +static int ov02a10_power_off(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct ov02a10 *ov02a10 = to_ov02a10(sd); + + gpiod_set_value_cansleep(ov02a10->rst_gpio, 1); + clk_disable_unprepare(ov02a10->eclk); + gpiod_set_value_cansleep(ov02a10->pd_gpio, 1); + regulator_bulk_disable(ARRAY_SIZE(ov02a10_supply_names), + ov02a10->supplies); + + return 0; +} + +static int __ov02a10_start_stream(struct ov02a10 *ov02a10) +{ + struct i2c_client *client = v4l2_get_subdevdata(&ov02a10->subdev); + const struct ov02a10_reg_list *reg_list; + int ret; + + /* Apply default values of current mode */ + reg_list = &ov02a10->cur_mode->reg_list; + ret = ov02a10_write_array(ov02a10, reg_list); + if (ret) + return ret; + + /* Apply customized values from user */ + ret = __v4l2_ctrl_handler_setup(ov02a10->subdev.ctrl_handler); + if (ret) + return ret; + + /* Set orientation to 180 degree */ + if (ov02a10->upside_down) { + ret = i2c_smbus_write_byte_data(client, REG_MIRROR_FLIP_CONTROL, + REG_MIRROR_FLIP_ENABLE); + if (ret) { + dev_err(&client->dev, "failed to set orientation\n"); + return ret; + } + ret = i2c_smbus_write_byte_data(client, REG_GLOBAL_EFFECTIVE, + REG_ENABLE); + if (ret < 0) + return ret; + } + + /* Set mipi TX speed according to DT property */ + if (ov02a10->mipi_clock_tx_speed != OV02A10_MIPI_TX_SPEED_DEFAULT) { + ret = i2c_smbus_write_byte_data(client, TX_SPEED_AREA_SEL, + ov02a10->mipi_clock_tx_speed); + if (ret < 0) + return ret; + } + + /* Set stream on register */ + return i2c_smbus_write_byte_data(client, REG_SC_CTRL_MODE, + SC_CTRL_MODE_STREAMING); +} + +static int __ov02a10_stop_stream(struct ov02a10 *ov02a10) +{ + struct i2c_client *client = v4l2_get_subdevdata(&ov02a10->subdev); + + return i2c_smbus_write_byte_data(client, REG_SC_CTRL_MODE, + SC_CTRL_MODE_STANDBY); +} + +static int ov02a10_entity_init_cfg(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg) +{ + struct v4l2_subdev_format fmt = { + .which = V4L2_SUBDEV_FORMAT_TRY, + .format = { + .width = 1600, + .height = 1200, + } + }; + + ov02a10_set_fmt(sd, cfg, &fmt); + + return 0; +} + +static int ov02a10_s_stream(struct v4l2_subdev *sd, int on) +{ + struct ov02a10 *ov02a10 = to_ov02a10(sd); + struct i2c_client *client = v4l2_get_subdevdata(&ov02a10->subdev); + int ret; + + mutex_lock(&ov02a10->mutex); + + if (ov02a10->streaming == on) + goto unlock_and_return; + + if (on) { + ret = pm_runtime_get_sync(&client->dev); + if (ret < 0) { + pm_runtime_put_noidle(&client->dev); + goto unlock_and_return; + } + + ret = __ov02a10_start_stream(ov02a10); + if (ret) { + __ov02a10_stop_stream(ov02a10); + ov02a10->streaming = !on; + goto err_rpm_put; + } + } else { + __ov02a10_stop_stream(ov02a10); + pm_runtime_put(&client->dev); + } + + ov02a10->streaming = on; + mutex_unlock(&ov02a10->mutex); + + return 0; + +err_rpm_put: + pm_runtime_put(&client->dev); +unlock_and_return: + mutex_unlock(&ov02a10->mutex); + + return ret; +} + +static const struct dev_pm_ops ov02a10_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, + pm_runtime_force_resume) + SET_RUNTIME_PM_OPS(ov02a10_power_off, ov02a10_power_on, NULL) +}; + +/* + * ov02a10_set_exposure - Function called when setting exposure time + * @priv: Pointer to device structure + * @val: Variable for exposure time, in the unit of micro-second + * + * Set exposure time based on input value. + * + * Return: 0 on success + */ +static int ov02a10_set_exposure(struct ov02a10 *ov02a10, int val) +{ + struct i2c_client *client = v4l2_get_subdevdata(&ov02a10->subdev); + int ret; + + ret = i2c_smbus_write_byte_data(client, REG_PAGE_SWITCH, REG_ENABLE); + if (ret < 0) + return ret; + + ret = i2c_smbus_write_byte_data(client, OV02A10_REG_EXPOSURE_H, + val >> OV02A10_EXP_SHIFT); + if (ret < 0) + return ret; + + ret = i2c_smbus_write_byte_data(client, OV02A10_REG_EXPOSURE_L, val); + if (ret < 0) + return ret; + + return i2c_smbus_write_byte_data(client, REG_GLOBAL_EFFECTIVE, + REG_ENABLE); +} + +static int ov02a10_set_gain(struct ov02a10 *ov02a10, int val) +{ + struct i2c_client *client = v4l2_get_subdevdata(&ov02a10->subdev); + int ret; + + ret = i2c_smbus_write_byte_data(client, REG_PAGE_SWITCH, REG_ENABLE); + if (ret < 0) + return ret; + + ret = i2c_smbus_write_byte_data(client, OV02A10_REG_GAIN, val); + if (ret < 0) + return ret; + + return i2c_smbus_write_byte_data(client, REG_GLOBAL_EFFECTIVE, + REG_ENABLE); +} + +static int ov02a10_set_vblank(struct ov02a10 *ov02a10, int val) +{ + struct i2c_client *client = v4l2_get_subdevdata(&ov02a10->subdev); + u32 vts = val + ov02a10->cur_mode->height - OV02A10_BASIC_LINE; + int ret; + + ret = i2c_smbus_write_byte_data(client, REG_PAGE_SWITCH, REG_ENABLE); + if (ret < 0) + return ret; + + ret = i2c_smbus_write_byte_data(client, OV02A10_REG_VTS_H, + vts >> OV02A10_VTS_SHIFT); + if (ret < 0) + return ret; + + ret = i2c_smbus_write_byte_data(client, OV02A10_REG_VTS_L, vts); + if (ret < 0) + return ret; + + return i2c_smbus_write_byte_data(client, REG_GLOBAL_EFFECTIVE, + REG_ENABLE); +} + +static int ov02a10_set_test_pattern(struct ov02a10 *ov02a10, int pattern) +{ + struct i2c_client *client = v4l2_get_subdevdata(&ov02a10->subdev); + int ret; + + ret = i2c_smbus_write_byte_data(client, REG_PAGE_SWITCH, REG_ENABLE); + if (ret < 0) + return ret; + + ret = i2c_smbus_write_byte_data(client, OV02A10_REG_TEST_PATTERN, + pattern); + if (ret < 0) + return ret; + + ret = i2c_smbus_write_byte_data(client, REG_GLOBAL_EFFECTIVE, + REG_ENABLE); + if (ret < 0) + return ret; + + return i2c_smbus_write_byte_data(client, REG_SC_CTRL_MODE, + SC_CTRL_MODE_STREAMING); +} + +static int ov02a10_set_ctrl(struct v4l2_ctrl *ctrl) +{ + struct ov02a10 *ov02a10 = container_of(ctrl->handler, + struct ov02a10, ctrl_handler); + struct i2c_client *client = v4l2_get_subdevdata(&ov02a10->subdev); + s64 max_expo; + int ret; + + /* Propagate change of current control to all related controls */ + if (ctrl->id == V4L2_CID_VBLANK) { + /* Update max exposure while meeting expected vblanking */ + max_expo = ov02a10->cur_mode->height + ctrl->val - + OV02A10_EXPOSURE_MAX_MARGIN; + __v4l2_ctrl_modify_range(ov02a10->exposure, + ov02a10->exposure->minimum, max_expo, + ov02a10->exposure->step, + ov02a10->exposure->default_value); + } + + /* V4L2 controls values will be applied only when power is already up */ + if (!pm_runtime_get_if_in_use(&client->dev)) + return 0; + + switch (ctrl->id) { + case V4L2_CID_EXPOSURE: + ret = ov02a10_set_exposure(ov02a10, ctrl->val); + break; + case V4L2_CID_ANALOGUE_GAIN: + ret = ov02a10_set_gain(ov02a10, ctrl->val); + break; + case V4L2_CID_VBLANK: + ret = ov02a10_set_vblank(ov02a10, ctrl->val); + break; + case V4L2_CID_TEST_PATTERN: + ret = ov02a10_set_test_pattern(ov02a10, ctrl->val); + break; + default: + ret = -EINVAL; + break; + }; + + pm_runtime_put(&client->dev); + + return ret; +} + +static const struct v4l2_subdev_video_ops ov02a10_video_ops = { + .s_stream = ov02a10_s_stream, +}; + +static const struct v4l2_subdev_pad_ops ov02a10_pad_ops = { + .init_cfg = ov02a10_entity_init_cfg, + .enum_mbus_code = ov02a10_enum_mbus_code, + .enum_frame_size = ov02a10_enum_frame_sizes, + .get_fmt = ov02a10_get_fmt, + .set_fmt = ov02a10_set_fmt, +}; + +static const struct v4l2_subdev_ops ov02a10_subdev_ops = { + .video = &ov02a10_video_ops, + .pad = &ov02a10_pad_ops, +}; + +static const struct media_entity_operations ov02a10_subdev_entity_ops = { + .link_validate = v4l2_subdev_link_validate, +}; + +static const struct v4l2_ctrl_ops ov02a10_ctrl_ops = { + .s_ctrl = ov02a10_set_ctrl, +}; + +static int ov02a10_initialize_controls(struct ov02a10 *ov02a10) +{ + struct i2c_client *client = v4l2_get_subdevdata(&ov02a10->subdev); + const struct ov02a10_mode *mode; + struct v4l2_ctrl_handler *handler; + struct v4l2_ctrl *ctrl; + s64 exposure_max; + s64 vblank_def; + s64 pixel_rate; + s64 h_blank; + int ret; + + handler = &ov02a10->ctrl_handler; + mode = ov02a10->cur_mode; + ret = v4l2_ctrl_handler_init(handler, 7); + if (ret) + return ret; + + handler->lock = &ov02a10->mutex; + + ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ, 0, 0, + link_freq_menu_items); + if (ctrl) + ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY; + + pixel_rate = to_pixel_rate(0); + v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE, 0, pixel_rate, 1, + pixel_rate); + + h_blank = mode->hts_def - mode->width; + v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK, h_blank, h_blank, 1, + h_blank); + + vblank_def = mode->vts_def - mode->height; + v4l2_ctrl_new_std(handler, &ov02a10_ctrl_ops, V4L2_CID_VBLANK, + vblank_def, OV02A10_VTS_MAX - mode->height, 1, + vblank_def); + + exposure_max = mode->vts_def - 4; + ov02a10->exposure = v4l2_ctrl_new_std(handler, &ov02a10_ctrl_ops, + V4L2_CID_EXPOSURE, + OV02A10_EXPOSURE_MIN, + exposure_max, + OV02A10_EXPOSURE_STEP, + mode->exp_def); + + v4l2_ctrl_new_std(handler, &ov02a10_ctrl_ops, + V4L2_CID_ANALOGUE_GAIN, OV02A10_GAIN_MIN, + OV02A10_GAIN_MAX, OV02A10_GAIN_STEP, + OV02A10_GAIN_DEFAULT); + + v4l2_ctrl_new_std_menu_items(handler, &ov02a10_ctrl_ops, + V4L2_CID_TEST_PATTERN, + ARRAY_SIZE(ov02a10_test_pattern_menu) - 1, + 0, 0, ov02a10_test_pattern_menu); + + if (handler->error) { + ret = handler->error; + dev_err(&client->dev, "failed to init controls(%d)\n", ret); + goto err_free_handler; + } + + ov02a10->subdev.ctrl_handler = handler; + + return 0; + +err_free_handler: + v4l2_ctrl_handler_free(handler); + + return ret; +} + +static int ov02a10_check_hwcfg(struct device *dev, struct ov02a10 *ov02a10) +{ + struct fwnode_handle *ep; + struct fwnode_handle *fwnode = dev_fwnode(dev); + struct v4l2_fwnode_endpoint bus_cfg = { + .bus_type = V4L2_MBUS_CSI2_DPHY, + }; + unsigned int i, j; + int ret; + + if (!fwnode) + return -EINVAL; + + ep = fwnode_graph_get_next_endpoint(fwnode, NULL); + if (!ep) + return -ENXIO; + + ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg); + fwnode_handle_put(ep); + if (ret) + return ret; + + if (!bus_cfg.nr_of_link_frequencies) { + dev_err(dev, "no link frequencies defined"); + ret = -EINVAL; + goto check_hwcfg_error; + } + + for (i = 0; i < ARRAY_SIZE(link_freq_menu_items); i++) { + for (j = 0; j < bus_cfg.nr_of_link_frequencies; j++) { + if (link_freq_menu_items[i] == + bus_cfg.link_frequencies[j]) + break; + } + + if (j == bus_cfg.nr_of_link_frequencies) { + dev_err(dev, "no link frequency %lld supported", + link_freq_menu_items[i]); + ret = -EINVAL; + goto check_hwcfg_error; + } + } + +check_hwcfg_error: + v4l2_fwnode_endpoint_free(&bus_cfg); + + return ret; +} + +static int ov02a10_probe(struct i2c_client *client) +{ + struct device *dev = &client->dev; + struct ov02a10 *ov02a10; + unsigned int rotation; + unsigned int clock_lane_tx_speed; + unsigned int i; + int ret; + + ov02a10 = devm_kzalloc(dev, sizeof(*ov02a10), GFP_KERNEL); + if (!ov02a10) + return -ENOMEM; + + ret = ov02a10_check_hwcfg(dev, ov02a10); + if (ret) { + dev_err(dev, "failed to check HW configuration: %d", ret); + return ret; + } + + v4l2_i2c_subdev_init(&ov02a10->subdev, client, &ov02a10_subdev_ops); + ov02a10->mipi_clock_tx_speed = OV02A10_MIPI_TX_SPEED_DEFAULT; + ov02a10->fmt.code = MEDIA_BUS_FMT_SBGGR10_1X10; + + /* Optional indication of physical rotation of sensor */ + ret = fwnode_property_read_u32(dev_fwnode(dev), "rotation", &rotation); + if (!ret && rotation == 180) { + ov02a10->upside_down = true; + ov02a10->fmt.code = MEDIA_BUS_FMT_SRGGB10_1X10; + } + + /* Optional indication of mipi TX speed */ + ret = fwnode_property_read_u32(dev_fwnode(dev), "ovti,mipi-tx-speed", + &clock_lane_tx_speed); + + if (!ret) + ov02a10->mipi_clock_tx_speed = clock_lane_tx_speed; + + /* Get system clock (eclk) */ + ov02a10->eclk = devm_clk_get(dev, "eclk"); + if (IS_ERR(ov02a10->eclk)) { + ret = PTR_ERR(ov02a10->eclk); + dev_err(dev, "failed to get eclk %d\n", ret); + return ret; + } + + ret = fwnode_property_read_u32(dev_fwnode(dev), "clock-frequency", + &ov02a10->eclk_freq); + if (ret) { + dev_err(dev, "failed to get eclk frequency\n"); + return ret; + } + + ret = clk_set_rate(ov02a10->eclk, ov02a10->eclk_freq); + if (ret) { + dev_err(dev, "failed to set eclk frequency (24MHz)\n"); + return ret; + } + + if (clk_get_rate(ov02a10->eclk) != OV02A10_ECLK_FREQ) { + dev_warn(dev, "eclk mismatched, mode is based on 24MHz\n"); + return -EINVAL; + } + + ov02a10->pd_gpio = devm_gpiod_get(dev, "powerdown", GPIOD_OUT_HIGH); + if (IS_ERR(ov02a10->pd_gpio)) { + ret = PTR_ERR(ov02a10->pd_gpio); + dev_err(dev, "failed to get powerdown-gpios %d\n", ret); + return ret; + } + + ov02a10->rst_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH); + if (IS_ERR(ov02a10->rst_gpio)) { + ret = PTR_ERR(ov02a10->rst_gpio); + dev_err(dev, "failed to get reset-gpios %d\n", ret); + return ret; + } + + for (i = 0; i < ARRAY_SIZE(ov02a10_supply_names); i++) + ov02a10->supplies[i].supply = ov02a10_supply_names[i]; + + ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(ov02a10_supply_names), + ov02a10->supplies); + if (ret) { + dev_err(dev, "failed to get regulators\n"); + return ret; + } + + mutex_init(&ov02a10->mutex); + ov02a10->cur_mode = &supported_modes[0]; + + ret = ov02a10_initialize_controls(ov02a10); + if (ret) { + dev_err(dev, "failed to initialize controls\n"); + goto err_destroy_mutex; + } + + ov02a10->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + ov02a10->subdev.entity.ops = &ov02a10_subdev_entity_ops; + ov02a10->subdev.entity.function = MEDIA_ENT_F_CAM_SENSOR; + ov02a10->pad.flags = MEDIA_PAD_FL_SOURCE; + + ret = media_entity_pads_init(&ov02a10->subdev.entity, 1, &ov02a10->pad); + if (ret < 0) { + dev_err(dev, "failed to init entity pads: %d", ret); + goto err_free_handler; + } + + pm_runtime_enable(dev); + if (!pm_runtime_enabled(dev)) { + ret = ov02a10_power_on(dev); + if (ret < 0) { + dev_err(dev, "failed to power on: %d\n", ret); + goto err_clean_entity; + } + } + + ret = v4l2_async_register_subdev(&ov02a10->subdev); + if (ret) { + dev_err(dev, "failed to register V4L2 subdev: %d", ret); + goto err_power_off; + } + + return 0; + +err_power_off: + if (pm_runtime_enabled(dev)) + pm_runtime_disable(dev); + else + ov02a10_power_off(dev); +err_clean_entity: + media_entity_cleanup(&ov02a10->subdev.entity); +err_free_handler: + v4l2_ctrl_handler_free(ov02a10->subdev.ctrl_handler); +err_destroy_mutex: + mutex_destroy(&ov02a10->mutex); + + return ret; +} + +static int ov02a10_remove(struct i2c_client *client) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct ov02a10 *ov02a10 = to_ov02a10(sd); + + v4l2_async_unregister_subdev(sd); + media_entity_cleanup(&sd->entity); + v4l2_ctrl_handler_free(sd->ctrl_handler); + pm_runtime_disable(&client->dev); + if (!pm_runtime_status_suspended(&client->dev)) + ov02a10_power_off(&client->dev); + pm_runtime_set_suspended(&client->dev); + mutex_destroy(&ov02a10->mutex); + + return 0; +} + +static const struct of_device_id ov02a10_of_match[] = { + { .compatible = "ovti,ov02a10" }, + {} +}; +MODULE_DEVICE_TABLE(of, ov02a10_of_match); + +static struct i2c_driver ov02a10_i2c_driver = { + .driver = { + .name = "ov02a10", + .pm = &ov02a10_pm_ops, + .of_match_table = ov02a10_of_match, + }, + .probe_new = &ov02a10_probe, + .remove = &ov02a10_remove, +}; + +module_i2c_driver(ov02a10_i2c_driver); + +MODULE_AUTHOR("Dongchun Zhu "); +MODULE_DESCRIPTION("OmniVision OV02A10 sensor driver"); +MODULE_LICENSE("GPL v2"); -- 2.9.2 _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.7 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, MENTIONS_GIT_HOSTING,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AD7D3C433DF for ; Fri, 10 Jul 2020 10:21:20 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6CB5820748 for ; Fri, 10 Jul 2020 10:21:20 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="2HoqfTyw"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="sdBmm+a+" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 6CB5820748 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-ID:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=hIBoEFC4drPDnVzES95s/hbCBgouPZiimpce90MOk78=; b=2HoqfTyw5uaaRqfS/CvEer5ek o4ZuyfL3ceBWiDXxH3PVkiY21q7/VlZu5JkkqA9bCqgSB2AoOS+sSHxr2seg4CoFDqaelKL7nOBNz o52uG4iiMYb4IL2vtPwublCYAp/zoBq2AO/8QBB0alxIzRns/ENnJ6n4iKwrR4SF3lKSq95q58ryl zl9p+2rzGZi6lW2ZMQk2eRD1k7NQ/Jf0VfCxqx3H6z+8k4eNSFAOa0lb4P4yT8aygqIb6PLC/mgn8 7wzzSzjgKaOOq5YqWmqVhrcDiBtUCJFAjBi6fsk97lcOtmi3oHffGPSsALcJ9IEW8EZ/Hvj+GcDQz OYFwZhiWQ==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jtq8K-0002pZ-8k; Fri, 10 Jul 2020 10:19:56 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1jtq88-0002k3-PQ; Fri, 10 Jul 2020 10:19:50 +0000 X-UUID: 0d34c3a7a34643b1ba5aab326c900cfc-20200710 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=MivBBVxEJb72HxTrv6XGwM/S5e3vdMpQxQjDdF8m33I=; b=sdBmm+a+Ii8/7l/Ahi7zZSmmmLG1pDoe15X8PbBX8YdGHnWAWV9ZE/Wvi1nr8yYxAualpAfuRYqZ0tVuHJlGNEyZ8lvR6HeLE7aMWYyVn90NKQZEn14t05j0qp8Joc0krs4orZ/fcHmapFvpET50hC5U3pjAYNnQ/PvqJoNeJYg=; X-UUID: 0d34c3a7a34643b1ba5aab326c900cfc-20200710 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLS) with ESMTP id 1180823192; Fri, 10 Jul 2020 02:19:40 -0800 Received: from MTKMBS07N2.mediatek.inc (172.21.101.141) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 10 Jul 2020 03:19:38 -0700 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 10 Jul 2020 18:19:37 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 10 Jul 2020 18:19:36 +0800 From: Dongchun Zhu To: , , , , , , , , Subject: [PATCH v13 2/2] media: i2c: Add OV02A10 image sensor driver Date: Fri, 10 Jul 2020 18:18:50 +0800 Message-ID: <20200710101850.4604-3-dongchun.zhu@mediatek.com> X-Mailer: git-send-email 2.9.2 In-Reply-To: <20200710101850.4604-1-dongchun.zhu@mediatek.com> References: <20200710101850.4604-1-dongchun.zhu@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200710_061945_088061_9A439554 X-CRM114-Status: GOOD ( 21.46 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, srv_heupstream@mediatek.com, shengnan.wang@mediatek.com, sj.huang@mediatek.com, linux-mediatek@lists.infradead.org, dongchun.zhu@mediatek.com, louis.kuo@mediatek.com, matrix.zhu@aliyun.com, 1095088256@qq.com, linux-arm-kernel@lists.infradead.org, linux-media@vger.kernel.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add a V4L2 sub-device driver for OmniVision OV02A10 image sensor. Reviewed-by: Tomasz Figa Signed-off-by: Dongchun Zhu --- MAINTAINERS | 1 + drivers/media/i2c/Kconfig | 13 + drivers/media/i2c/Makefile | 1 + drivers/media/i2c/ov02a10.c | 1050 +++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 1065 insertions(+) create mode 100644 drivers/media/i2c/ov02a10.c diff --git a/MAINTAINERS b/MAINTAINERS index 378c961..a6a2f8b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12566,6 +12566,7 @@ L: linux-media@vger.kernel.org S: Maintained T: git git://linuxtv.org/media_tree.git F: Documentation/devicetree/bindings/media/i2c/ovti,ov02a10.yaml +F: drivers/media/i2c/ov02a10.c OMNIVISION OV13858 SENSOR DRIVER M: Sakari Ailus diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig index da11036..65519cf 100644 --- a/drivers/media/i2c/Kconfig +++ b/drivers/media/i2c/Kconfig @@ -812,6 +812,19 @@ config VIDEO_IMX355 To compile this driver as a module, choose M here: the module will be called imx355. +config VIDEO_OV02A10 + tristate "OmniVision OV02A10 sensor support" + depends on I2C && VIDEO_V4L2 + select MEDIA_CONTROLLER + select VIDEO_V4L2_SUBDEV_API + select V4L2_FWNODE + help + This is a Video4Linux2 sensor driver for the OmniVision + OV02A10 camera. + + To compile this driver as a module, choose M here: the + module will be called ov02a10. + config VIDEO_OV2640 tristate "OmniVision OV2640 sensor support" depends on VIDEO_V4L2 && I2C diff --git a/drivers/media/i2c/Makefile b/drivers/media/i2c/Makefile index 993acab..384e676 100644 --- a/drivers/media/i2c/Makefile +++ b/drivers/media/i2c/Makefile @@ -63,6 +63,7 @@ obj-$(CONFIG_VIDEO_VP27SMPX) += vp27smpx.o obj-$(CONFIG_VIDEO_SONY_BTF_MPX) += sony-btf-mpx.o obj-$(CONFIG_VIDEO_UPD64031A) += upd64031a.o obj-$(CONFIG_VIDEO_UPD64083) += upd64083.o +obj-$(CONFIG_VIDEO_OV02A10) += ov02a10.o obj-$(CONFIG_VIDEO_OV2640) += ov2640.o obj-$(CONFIG_VIDEO_OV2680) += ov2680.o obj-$(CONFIG_VIDEO_OV2685) += ov2685.o diff --git a/drivers/media/i2c/ov02a10.c b/drivers/media/i2c/ov02a10.c new file mode 100644 index 0000000..5ffc97a --- /dev/null +++ b/drivers/media/i2c/ov02a10.c @@ -0,0 +1,1050 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2020 MediaTek Inc. + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define CHIP_ID 0x2509 +#define OV02A10_REG_CHIP_ID_H 0x02 +#define OV02A10_REG_CHIP_ID_L 0x03 + +/* Bit[1] vertical upside down */ +/* Bit[0] horizontal mirror */ +#define REG_MIRROR_FLIP_CONTROL 0x3f + +/* Orientation */ +#define REG_MIRROR_FLIP_ENABLE 0x03 + +/* Bit[2:0] MIPI transmission speed select */ +#define TX_SPEED_AREA_SEL 0xa1 +#define OV02A10_MIPI_TX_SPEED_DEFAULT 0x03 + +#define REG_PAGE_SWITCH 0xfd +#define REG_GLOBAL_EFFECTIVE 0x01 +#define REG_ENABLE BIT(0) + +#define REG_SC_CTRL_MODE 0xac +#define SC_CTRL_MODE_STANDBY 0x00 +#define SC_CTRL_MODE_STREAMING 0x01 + +#define OV02A10_EXP_SHIFT 8 +#define OV02A10_REG_EXPOSURE_H 0x03 +#define OV02A10_REG_EXPOSURE_L 0x04 +#define OV02A10_EXPOSURE_MIN 4 +#define OV02A10_EXPOSURE_MAX_MARGIN 4 +#define OV02A10_EXPOSURE_STEP 1 + +#define OV02A10_VTS_SHIFT 8 +#define OV02A10_REG_VTS_H 0x05 +#define OV02A10_REG_VTS_L 0x06 +#define OV02A10_VTS_MAX 0x209f +#define OV02A10_BASIC_LINE 1224 + +#define OV02A10_REG_GAIN 0x24 +#define OV02A10_GAIN_MIN 0x10 +#define OV02A10_GAIN_MAX 0xf8 +#define OV02A10_GAIN_STEP 0x01 +#define OV02A10_GAIN_DEFAULT 0x40 + +/* Test pattern control */ +#define OV02A10_REG_TEST_PATTERN 0xb6 + +#define HZ_PER_MHZ 1000000L +#define OV02A10_LINK_FREQ_390MHZ (390 * HZ_PER_MHZ) +#define OV02A10_ECLK_FREQ (24 * HZ_PER_MHZ) +#define OV02A10_DATA_LANES 1 +#define OV02A10_BITS_PER_SAMPLE 10 + +static const char * const ov02a10_supply_names[] = { + "dovdd", /* Digital I/O power */ + "avdd", /* Analog power */ + "dvdd", /* Digital core power */ +}; + +struct ov02a10_reg { + u8 addr; + u8 val; +}; + +struct ov02a10_reg_list { + u32 num_of_regs; + const struct ov02a10_reg *regs; +}; + +struct ov02a10_mode { + u32 width; + u32 height; + u32 exp_def; + u32 hts_def; + u32 vts_def; + const struct ov02a10_reg_list reg_list; +}; + +struct ov02a10 { + u32 eclk_freq; + u32 mipi_clock_tx_speed; + + struct clk *eclk; + struct gpio_desc *pd_gpio; + struct gpio_desc *rst_gpio; + struct regulator_bulk_data supplies[ARRAY_SIZE(ov02a10_supply_names)]; + + bool streaming; + bool upside_down; + + /* + * Serialize control access, get/set format, get selection + * and start streaming. + */ + struct mutex mutex; + struct v4l2_subdev subdev; + struct media_pad pad; + struct v4l2_mbus_framefmt fmt; + struct v4l2_ctrl_handler ctrl_handler; + struct v4l2_ctrl *exposure; + + const struct ov02a10_mode *cur_mode; +}; + +static inline struct ov02a10 *to_ov02a10(struct v4l2_subdev *sd) +{ + return container_of(sd, struct ov02a10, subdev); +} + +/* + * eclk 24Mhz + * pclk 39Mhz + * linelength 934(0x3a6) + * framelength 1390(0x56E) + * grabwindow_width 1600 + * grabwindow_height 1200 + * max_framerate 30fps + * mipi_datarate per lane 780Mbps + */ +static const struct ov02a10_reg ov02a10_1600x1200_regs[] = { + {0xfd, 0x01}, + {0xac, 0x00}, + {0xfd, 0x00}, + {0x2f, 0x29}, + {0x34, 0x00}, + {0x35, 0x21}, + {0x30, 0x15}, + {0x33, 0x01}, + {0xfd, 0x01}, + {0x44, 0x00}, + {0x2a, 0x4c}, + {0x2b, 0x1e}, + {0x2c, 0x60}, + {0x25, 0x11}, + {0x03, 0x01}, + {0x04, 0xae}, + {0x09, 0x00}, + {0x0a, 0x02}, + {0x06, 0xa6}, + {0x31, 0x00}, + {0x24, 0x40}, + {0x01, 0x01}, + {0xfb, 0x73}, + {0xfd, 0x01}, + {0x16, 0x04}, + {0x1c, 0x09}, + {0x21, 0x42}, + {0x12, 0x04}, + {0x13, 0x10}, + {0x11, 0x40}, + {0x33, 0x81}, + {0xd0, 0x00}, + {0xd1, 0x01}, + {0xd2, 0x00}, + {0x50, 0x10}, + {0x51, 0x23}, + {0x52, 0x20}, + {0x53, 0x10}, + {0x54, 0x02}, + {0x55, 0x20}, + {0x56, 0x02}, + {0x58, 0x48}, + {0x5d, 0x15}, + {0x5e, 0x05}, + {0x66, 0x66}, + {0x68, 0x68}, + {0x6b, 0x00}, + {0x6c, 0x00}, + {0x6f, 0x40}, + {0x70, 0x40}, + {0x71, 0x0a}, + {0x72, 0xf0}, + {0x73, 0x10}, + {0x75, 0x80}, + {0x76, 0x10}, + {0x84, 0x00}, + {0x85, 0x10}, + {0x86, 0x10}, + {0x87, 0x00}, + {0x8a, 0x22}, + {0x8b, 0x22}, + {0x19, 0xf1}, + {0x29, 0x01}, + {0xfd, 0x01}, + {0x9d, 0x16}, + {0xa0, 0x29}, + {0xa1, 0x03}, + {0xad, 0x62}, + {0xae, 0x00}, + {0xaf, 0x85}, + {0xb1, 0x01}, + {0x8e, 0x06}, + {0x8f, 0x40}, + {0x90, 0x04}, + {0x91, 0xb0}, + {0x45, 0x01}, + {0x46, 0x00}, + {0x47, 0x6c}, + {0x48, 0x03}, + {0x49, 0x8b}, + {0x4a, 0x00}, + {0x4b, 0x07}, + {0x4c, 0x04}, + {0x4d, 0xb7}, + {0xf0, 0x40}, + {0xf1, 0x40}, + {0xf2, 0x40}, + {0xf3, 0x40}, + {0x3f, 0x00}, + {0xfd, 0x01}, + {0x05, 0x00}, + {0x06, 0xa6}, + {0xfd, 0x01}, +}; + +static const char * const ov02a10_test_pattern_menu[] = { + "Disabled", + "Eight Vertical Colour Bars", +}; + +static const s64 link_freq_menu_items[] = { + OV02A10_LINK_FREQ_390MHZ, +}; + +static u64 to_pixel_rate(u32 f_index) +{ + u64 pixel_rate = link_freq_menu_items[f_index] * 2 * OV02A10_DATA_LANES; + + do_div(pixel_rate, OV02A10_BITS_PER_SAMPLE); + + return pixel_rate; +} + +static const struct ov02a10_mode supported_modes[] = { + { + .width = 1600, + .height = 1200, + .exp_def = 0x01ae, + .hts_def = 0x03a6, + .vts_def = 0x056e, + .reg_list = { + .num_of_regs = ARRAY_SIZE(ov02a10_1600x1200_regs), + .regs = ov02a10_1600x1200_regs, + }, + }, +}; + +static int ov02a10_write_array(struct ov02a10 *ov02a10, + const struct ov02a10_reg_list *r_list) +{ + struct i2c_client *client = v4l2_get_subdevdata(&ov02a10->subdev); + unsigned int i; + int ret; + + for (i = 0; i < r_list->num_of_regs; i++) { + ret = i2c_smbus_write_byte_data(client, r_list->regs[i].addr, + r_list->regs[i].val); + if (ret < 0) + return ret; + } + + return 0; +} + +static int ov02a10_read_smbus(struct ov02a10 *ov02a10, unsigned char reg, + unsigned char *val) +{ + struct i2c_client *client = v4l2_get_subdevdata(&ov02a10->subdev); + int ret; + + ret = i2c_smbus_read_byte_data(client, reg); + if (ret < 0) + return ret; + + *val = (unsigned char)ret; + + return 0; +} + +static void ov02a10_fill_fmt(const struct ov02a10_mode *mode, + struct v4l2_mbus_framefmt *fmt) +{ + fmt->width = mode->width; + fmt->height = mode->height; + fmt->field = V4L2_FIELD_NONE; +} + +static int ov02a10_set_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *fmt) +{ + struct ov02a10 *ov02a10 = to_ov02a10(sd); + struct v4l2_mbus_framefmt *mbus_fmt = &fmt->format; + struct v4l2_mbus_framefmt *frame_fmt; + int ret = 0; + + mutex_lock(&ov02a10->mutex); + + if (ov02a10->streaming && fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE) { + ret = -EBUSY; + goto error; + } + + /* Only one sensor mode supported */ + mbus_fmt->code = ov02a10->fmt.code; + ov02a10_fill_fmt(ov02a10->cur_mode, mbus_fmt); + + if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) + frame_fmt = v4l2_subdev_get_try_format(sd, cfg, 0); + else + frame_fmt = &ov02a10->fmt; + + *frame_fmt = *mbus_fmt; + +error: + mutex_unlock(&ov02a10->mutex); + return ret; +} + +static int ov02a10_get_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *fmt) +{ + struct ov02a10 *ov02a10 = to_ov02a10(sd); + struct v4l2_mbus_framefmt *mbus_fmt = &fmt->format; + + mutex_lock(&ov02a10->mutex); + + if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { + fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad); + } else { + fmt->format = ov02a10->fmt; + mbus_fmt->code = ov02a10->fmt.code; + ov02a10_fill_fmt(ov02a10->cur_mode, mbus_fmt); + } + + mutex_unlock(&ov02a10->mutex); + + return 0; +} + +static int ov02a10_enum_mbus_code(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_mbus_code_enum *code) +{ + struct ov02a10 *ov02a10 = to_ov02a10(sd); + + if (code->index != 0) + return -EINVAL; + + code->code = ov02a10->fmt.code; + + return 0; +} + +static int ov02a10_enum_frame_sizes(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_frame_size_enum *fse) +{ + if (fse->index >= ARRAY_SIZE(supported_modes)) + return -EINVAL; + + fse->min_width = supported_modes[fse->index].width; + fse->max_width = supported_modes[fse->index].width; + fse->max_height = supported_modes[fse->index].height; + fse->min_height = supported_modes[fse->index].height; + + return 0; +} + +static int ov02a10_check_sensor_id(struct ov02a10 *ov02a10) +{ + struct i2c_client *client = v4l2_get_subdevdata(&ov02a10->subdev); + u16 id; + u8 chip_id_h; + u8 chip_id_l; + int ret; + + /* Check sensor revision */ + ret = ov02a10_read_smbus(ov02a10, OV02A10_REG_CHIP_ID_H, &chip_id_h); + if (ret) + return ret; + + ret = ov02a10_read_smbus(ov02a10, OV02A10_REG_CHIP_ID_L, &chip_id_l); + if (ret) + return ret; + + id = (chip_id_h << 8) | chip_id_l; + if (id != CHIP_ID) { + dev_err(&client->dev, "Unexpected sensor id(%04x)\n", id); + return -EINVAL; + } + + return 0; +} + +static int ov02a10_power_on(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct ov02a10 *ov02a10 = to_ov02a10(sd); + int ret; + + gpiod_set_value_cansleep(ov02a10->rst_gpio, 1); + gpiod_set_value_cansleep(ov02a10->pd_gpio, 1); + + ret = clk_prepare_enable(ov02a10->eclk); + if (ret < 0) { + dev_err(dev, "failed to enable eclk\n"); + return ret; + } + + ret = regulator_bulk_enable(ARRAY_SIZE(ov02a10_supply_names), + ov02a10->supplies); + if (ret < 0) { + dev_err(dev, "failed to enable regulators\n"); + goto disable_clk; + } + usleep_range(5000, 6000); + + gpiod_set_value_cansleep(ov02a10->pd_gpio, 0); + usleep_range(5000, 6000); + + gpiod_set_value_cansleep(ov02a10->rst_gpio, 0); + usleep_range(5000, 6000); + + ret = ov02a10_check_sensor_id(ov02a10); + if (ret) + goto disable_regulator; + + return 0; + +disable_regulator: + regulator_bulk_disable(ARRAY_SIZE(ov02a10_supply_names), + ov02a10->supplies); +disable_clk: + clk_disable_unprepare(ov02a10->eclk); + + return ret; +} + +static int ov02a10_power_off(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct ov02a10 *ov02a10 = to_ov02a10(sd); + + gpiod_set_value_cansleep(ov02a10->rst_gpio, 1); + clk_disable_unprepare(ov02a10->eclk); + gpiod_set_value_cansleep(ov02a10->pd_gpio, 1); + regulator_bulk_disable(ARRAY_SIZE(ov02a10_supply_names), + ov02a10->supplies); + + return 0; +} + +static int __ov02a10_start_stream(struct ov02a10 *ov02a10) +{ + struct i2c_client *client = v4l2_get_subdevdata(&ov02a10->subdev); + const struct ov02a10_reg_list *reg_list; + int ret; + + /* Apply default values of current mode */ + reg_list = &ov02a10->cur_mode->reg_list; + ret = ov02a10_write_array(ov02a10, reg_list); + if (ret) + return ret; + + /* Apply customized values from user */ + ret = __v4l2_ctrl_handler_setup(ov02a10->subdev.ctrl_handler); + if (ret) + return ret; + + /* Set orientation to 180 degree */ + if (ov02a10->upside_down) { + ret = i2c_smbus_write_byte_data(client, REG_MIRROR_FLIP_CONTROL, + REG_MIRROR_FLIP_ENABLE); + if (ret) { + dev_err(&client->dev, "failed to set orientation\n"); + return ret; + } + ret = i2c_smbus_write_byte_data(client, REG_GLOBAL_EFFECTIVE, + REG_ENABLE); + if (ret < 0) + return ret; + } + + /* Set mipi TX speed according to DT property */ + if (ov02a10->mipi_clock_tx_speed != OV02A10_MIPI_TX_SPEED_DEFAULT) { + ret = i2c_smbus_write_byte_data(client, TX_SPEED_AREA_SEL, + ov02a10->mipi_clock_tx_speed); + if (ret < 0) + return ret; + } + + /* Set stream on register */ + return i2c_smbus_write_byte_data(client, REG_SC_CTRL_MODE, + SC_CTRL_MODE_STREAMING); +} + +static int __ov02a10_stop_stream(struct ov02a10 *ov02a10) +{ + struct i2c_client *client = v4l2_get_subdevdata(&ov02a10->subdev); + + return i2c_smbus_write_byte_data(client, REG_SC_CTRL_MODE, + SC_CTRL_MODE_STANDBY); +} + +static int ov02a10_entity_init_cfg(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg) +{ + struct v4l2_subdev_format fmt = { + .which = V4L2_SUBDEV_FORMAT_TRY, + .format = { + .width = 1600, + .height = 1200, + } + }; + + ov02a10_set_fmt(sd, cfg, &fmt); + + return 0; +} + +static int ov02a10_s_stream(struct v4l2_subdev *sd, int on) +{ + struct ov02a10 *ov02a10 = to_ov02a10(sd); + struct i2c_client *client = v4l2_get_subdevdata(&ov02a10->subdev); + int ret; + + mutex_lock(&ov02a10->mutex); + + if (ov02a10->streaming == on) + goto unlock_and_return; + + if (on) { + ret = pm_runtime_get_sync(&client->dev); + if (ret < 0) { + pm_runtime_put_noidle(&client->dev); + goto unlock_and_return; + } + + ret = __ov02a10_start_stream(ov02a10); + if (ret) { + __ov02a10_stop_stream(ov02a10); + ov02a10->streaming = !on; + goto err_rpm_put; + } + } else { + __ov02a10_stop_stream(ov02a10); + pm_runtime_put(&client->dev); + } + + ov02a10->streaming = on; + mutex_unlock(&ov02a10->mutex); + + return 0; + +err_rpm_put: + pm_runtime_put(&client->dev); +unlock_and_return: + mutex_unlock(&ov02a10->mutex); + + return ret; +} + +static const struct dev_pm_ops ov02a10_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, + pm_runtime_force_resume) + SET_RUNTIME_PM_OPS(ov02a10_power_off, ov02a10_power_on, NULL) +}; + +/* + * ov02a10_set_exposure - Function called when setting exposure time + * @priv: Pointer to device structure + * @val: Variable for exposure time, in the unit of micro-second + * + * Set exposure time based on input value. + * + * Return: 0 on success + */ +static int ov02a10_set_exposure(struct ov02a10 *ov02a10, int val) +{ + struct i2c_client *client = v4l2_get_subdevdata(&ov02a10->subdev); + int ret; + + ret = i2c_smbus_write_byte_data(client, REG_PAGE_SWITCH, REG_ENABLE); + if (ret < 0) + return ret; + + ret = i2c_smbus_write_byte_data(client, OV02A10_REG_EXPOSURE_H, + val >> OV02A10_EXP_SHIFT); + if (ret < 0) + return ret; + + ret = i2c_smbus_write_byte_data(client, OV02A10_REG_EXPOSURE_L, val); + if (ret < 0) + return ret; + + return i2c_smbus_write_byte_data(client, REG_GLOBAL_EFFECTIVE, + REG_ENABLE); +} + +static int ov02a10_set_gain(struct ov02a10 *ov02a10, int val) +{ + struct i2c_client *client = v4l2_get_subdevdata(&ov02a10->subdev); + int ret; + + ret = i2c_smbus_write_byte_data(client, REG_PAGE_SWITCH, REG_ENABLE); + if (ret < 0) + return ret; + + ret = i2c_smbus_write_byte_data(client, OV02A10_REG_GAIN, val); + if (ret < 0) + return ret; + + return i2c_smbus_write_byte_data(client, REG_GLOBAL_EFFECTIVE, + REG_ENABLE); +} + +static int ov02a10_set_vblank(struct ov02a10 *ov02a10, int val) +{ + struct i2c_client *client = v4l2_get_subdevdata(&ov02a10->subdev); + u32 vts = val + ov02a10->cur_mode->height - OV02A10_BASIC_LINE; + int ret; + + ret = i2c_smbus_write_byte_data(client, REG_PAGE_SWITCH, REG_ENABLE); + if (ret < 0) + return ret; + + ret = i2c_smbus_write_byte_data(client, OV02A10_REG_VTS_H, + vts >> OV02A10_VTS_SHIFT); + if (ret < 0) + return ret; + + ret = i2c_smbus_write_byte_data(client, OV02A10_REG_VTS_L, vts); + if (ret < 0) + return ret; + + return i2c_smbus_write_byte_data(client, REG_GLOBAL_EFFECTIVE, + REG_ENABLE); +} + +static int ov02a10_set_test_pattern(struct ov02a10 *ov02a10, int pattern) +{ + struct i2c_client *client = v4l2_get_subdevdata(&ov02a10->subdev); + int ret; + + ret = i2c_smbus_write_byte_data(client, REG_PAGE_SWITCH, REG_ENABLE); + if (ret < 0) + return ret; + + ret = i2c_smbus_write_byte_data(client, OV02A10_REG_TEST_PATTERN, + pattern); + if (ret < 0) + return ret; + + ret = i2c_smbus_write_byte_data(client, REG_GLOBAL_EFFECTIVE, + REG_ENABLE); + if (ret < 0) + return ret; + + return i2c_smbus_write_byte_data(client, REG_SC_CTRL_MODE, + SC_CTRL_MODE_STREAMING); +} + +static int ov02a10_set_ctrl(struct v4l2_ctrl *ctrl) +{ + struct ov02a10 *ov02a10 = container_of(ctrl->handler, + struct ov02a10, ctrl_handler); + struct i2c_client *client = v4l2_get_subdevdata(&ov02a10->subdev); + s64 max_expo; + int ret; + + /* Propagate change of current control to all related controls */ + if (ctrl->id == V4L2_CID_VBLANK) { + /* Update max exposure while meeting expected vblanking */ + max_expo = ov02a10->cur_mode->height + ctrl->val - + OV02A10_EXPOSURE_MAX_MARGIN; + __v4l2_ctrl_modify_range(ov02a10->exposure, + ov02a10->exposure->minimum, max_expo, + ov02a10->exposure->step, + ov02a10->exposure->default_value); + } + + /* V4L2 controls values will be applied only when power is already up */ + if (!pm_runtime_get_if_in_use(&client->dev)) + return 0; + + switch (ctrl->id) { + case V4L2_CID_EXPOSURE: + ret = ov02a10_set_exposure(ov02a10, ctrl->val); + break; + case V4L2_CID_ANALOGUE_GAIN: + ret = ov02a10_set_gain(ov02a10, ctrl->val); + break; + case V4L2_CID_VBLANK: + ret = ov02a10_set_vblank(ov02a10, ctrl->val); + break; + case V4L2_CID_TEST_PATTERN: + ret = ov02a10_set_test_pattern(ov02a10, ctrl->val); + break; + default: + ret = -EINVAL; + break; + }; + + pm_runtime_put(&client->dev); + + return ret; +} + +static const struct v4l2_subdev_video_ops ov02a10_video_ops = { + .s_stream = ov02a10_s_stream, +}; + +static const struct v4l2_subdev_pad_ops ov02a10_pad_ops = { + .init_cfg = ov02a10_entity_init_cfg, + .enum_mbus_code = ov02a10_enum_mbus_code, + .enum_frame_size = ov02a10_enum_frame_sizes, + .get_fmt = ov02a10_get_fmt, + .set_fmt = ov02a10_set_fmt, +}; + +static const struct v4l2_subdev_ops ov02a10_subdev_ops = { + .video = &ov02a10_video_ops, + .pad = &ov02a10_pad_ops, +}; + +static const struct media_entity_operations ov02a10_subdev_entity_ops = { + .link_validate = v4l2_subdev_link_validate, +}; + +static const struct v4l2_ctrl_ops ov02a10_ctrl_ops = { + .s_ctrl = ov02a10_set_ctrl, +}; + +static int ov02a10_initialize_controls(struct ov02a10 *ov02a10) +{ + struct i2c_client *client = v4l2_get_subdevdata(&ov02a10->subdev); + const struct ov02a10_mode *mode; + struct v4l2_ctrl_handler *handler; + struct v4l2_ctrl *ctrl; + s64 exposure_max; + s64 vblank_def; + s64 pixel_rate; + s64 h_blank; + int ret; + + handler = &ov02a10->ctrl_handler; + mode = ov02a10->cur_mode; + ret = v4l2_ctrl_handler_init(handler, 7); + if (ret) + return ret; + + handler->lock = &ov02a10->mutex; + + ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ, 0, 0, + link_freq_menu_items); + if (ctrl) + ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY; + + pixel_rate = to_pixel_rate(0); + v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE, 0, pixel_rate, 1, + pixel_rate); + + h_blank = mode->hts_def - mode->width; + v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK, h_blank, h_blank, 1, + h_blank); + + vblank_def = mode->vts_def - mode->height; + v4l2_ctrl_new_std(handler, &ov02a10_ctrl_ops, V4L2_CID_VBLANK, + vblank_def, OV02A10_VTS_MAX - mode->height, 1, + vblank_def); + + exposure_max = mode->vts_def - 4; + ov02a10->exposure = v4l2_ctrl_new_std(handler, &ov02a10_ctrl_ops, + V4L2_CID_EXPOSURE, + OV02A10_EXPOSURE_MIN, + exposure_max, + OV02A10_EXPOSURE_STEP, + mode->exp_def); + + v4l2_ctrl_new_std(handler, &ov02a10_ctrl_ops, + V4L2_CID_ANALOGUE_GAIN, OV02A10_GAIN_MIN, + OV02A10_GAIN_MAX, OV02A10_GAIN_STEP, + OV02A10_GAIN_DEFAULT); + + v4l2_ctrl_new_std_menu_items(handler, &ov02a10_ctrl_ops, + V4L2_CID_TEST_PATTERN, + ARRAY_SIZE(ov02a10_test_pattern_menu) - 1, + 0, 0, ov02a10_test_pattern_menu); + + if (handler->error) { + ret = handler->error; + dev_err(&client->dev, "failed to init controls(%d)\n", ret); + goto err_free_handler; + } + + ov02a10->subdev.ctrl_handler = handler; + + return 0; + +err_free_handler: + v4l2_ctrl_handler_free(handler); + + return ret; +} + +static int ov02a10_check_hwcfg(struct device *dev, struct ov02a10 *ov02a10) +{ + struct fwnode_handle *ep; + struct fwnode_handle *fwnode = dev_fwnode(dev); + struct v4l2_fwnode_endpoint bus_cfg = { + .bus_type = V4L2_MBUS_CSI2_DPHY, + }; + unsigned int i, j; + int ret; + + if (!fwnode) + return -EINVAL; + + ep = fwnode_graph_get_next_endpoint(fwnode, NULL); + if (!ep) + return -ENXIO; + + ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg); + fwnode_handle_put(ep); + if (ret) + return ret; + + if (!bus_cfg.nr_of_link_frequencies) { + dev_err(dev, "no link frequencies defined"); + ret = -EINVAL; + goto check_hwcfg_error; + } + + for (i = 0; i < ARRAY_SIZE(link_freq_menu_items); i++) { + for (j = 0; j < bus_cfg.nr_of_link_frequencies; j++) { + if (link_freq_menu_items[i] == + bus_cfg.link_frequencies[j]) + break; + } + + if (j == bus_cfg.nr_of_link_frequencies) { + dev_err(dev, "no link frequency %lld supported", + link_freq_menu_items[i]); + ret = -EINVAL; + goto check_hwcfg_error; + } + } + +check_hwcfg_error: + v4l2_fwnode_endpoint_free(&bus_cfg); + + return ret; +} + +static int ov02a10_probe(struct i2c_client *client) +{ + struct device *dev = &client->dev; + struct ov02a10 *ov02a10; + unsigned int rotation; + unsigned int clock_lane_tx_speed; + unsigned int i; + int ret; + + ov02a10 = devm_kzalloc(dev, sizeof(*ov02a10), GFP_KERNEL); + if (!ov02a10) + return -ENOMEM; + + ret = ov02a10_check_hwcfg(dev, ov02a10); + if (ret) { + dev_err(dev, "failed to check HW configuration: %d", ret); + return ret; + } + + v4l2_i2c_subdev_init(&ov02a10->subdev, client, &ov02a10_subdev_ops); + ov02a10->mipi_clock_tx_speed = OV02A10_MIPI_TX_SPEED_DEFAULT; + ov02a10->fmt.code = MEDIA_BUS_FMT_SBGGR10_1X10; + + /* Optional indication of physical rotation of sensor */ + ret = fwnode_property_read_u32(dev_fwnode(dev), "rotation", &rotation); + if (!ret && rotation == 180) { + ov02a10->upside_down = true; + ov02a10->fmt.code = MEDIA_BUS_FMT_SRGGB10_1X10; + } + + /* Optional indication of mipi TX speed */ + ret = fwnode_property_read_u32(dev_fwnode(dev), "ovti,mipi-tx-speed", + &clock_lane_tx_speed); + + if (!ret) + ov02a10->mipi_clock_tx_speed = clock_lane_tx_speed; + + /* Get system clock (eclk) */ + ov02a10->eclk = devm_clk_get(dev, "eclk"); + if (IS_ERR(ov02a10->eclk)) { + ret = PTR_ERR(ov02a10->eclk); + dev_err(dev, "failed to get eclk %d\n", ret); + return ret; + } + + ret = fwnode_property_read_u32(dev_fwnode(dev), "clock-frequency", + &ov02a10->eclk_freq); + if (ret) { + dev_err(dev, "failed to get eclk frequency\n"); + return ret; + } + + ret = clk_set_rate(ov02a10->eclk, ov02a10->eclk_freq); + if (ret) { + dev_err(dev, "failed to set eclk frequency (24MHz)\n"); + return ret; + } + + if (clk_get_rate(ov02a10->eclk) != OV02A10_ECLK_FREQ) { + dev_warn(dev, "eclk mismatched, mode is based on 24MHz\n"); + return -EINVAL; + } + + ov02a10->pd_gpio = devm_gpiod_get(dev, "powerdown", GPIOD_OUT_HIGH); + if (IS_ERR(ov02a10->pd_gpio)) { + ret = PTR_ERR(ov02a10->pd_gpio); + dev_err(dev, "failed to get powerdown-gpios %d\n", ret); + return ret; + } + + ov02a10->rst_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH); + if (IS_ERR(ov02a10->rst_gpio)) { + ret = PTR_ERR(ov02a10->rst_gpio); + dev_err(dev, "failed to get reset-gpios %d\n", ret); + return ret; + } + + for (i = 0; i < ARRAY_SIZE(ov02a10_supply_names); i++) + ov02a10->supplies[i].supply = ov02a10_supply_names[i]; + + ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(ov02a10_supply_names), + ov02a10->supplies); + if (ret) { + dev_err(dev, "failed to get regulators\n"); + return ret; + } + + mutex_init(&ov02a10->mutex); + ov02a10->cur_mode = &supported_modes[0]; + + ret = ov02a10_initialize_controls(ov02a10); + if (ret) { + dev_err(dev, "failed to initialize controls\n"); + goto err_destroy_mutex; + } + + ov02a10->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + ov02a10->subdev.entity.ops = &ov02a10_subdev_entity_ops; + ov02a10->subdev.entity.function = MEDIA_ENT_F_CAM_SENSOR; + ov02a10->pad.flags = MEDIA_PAD_FL_SOURCE; + + ret = media_entity_pads_init(&ov02a10->subdev.entity, 1, &ov02a10->pad); + if (ret < 0) { + dev_err(dev, "failed to init entity pads: %d", ret); + goto err_free_handler; + } + + pm_runtime_enable(dev); + if (!pm_runtime_enabled(dev)) { + ret = ov02a10_power_on(dev); + if (ret < 0) { + dev_err(dev, "failed to power on: %d\n", ret); + goto err_clean_entity; + } + } + + ret = v4l2_async_register_subdev(&ov02a10->subdev); + if (ret) { + dev_err(dev, "failed to register V4L2 subdev: %d", ret); + goto err_power_off; + } + + return 0; + +err_power_off: + if (pm_runtime_enabled(dev)) + pm_runtime_disable(dev); + else + ov02a10_power_off(dev); +err_clean_entity: + media_entity_cleanup(&ov02a10->subdev.entity); +err_free_handler: + v4l2_ctrl_handler_free(ov02a10->subdev.ctrl_handler); +err_destroy_mutex: + mutex_destroy(&ov02a10->mutex); + + return ret; +} + +static int ov02a10_remove(struct i2c_client *client) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct ov02a10 *ov02a10 = to_ov02a10(sd); + + v4l2_async_unregister_subdev(sd); + media_entity_cleanup(&sd->entity); + v4l2_ctrl_handler_free(sd->ctrl_handler); + pm_runtime_disable(&client->dev); + if (!pm_runtime_status_suspended(&client->dev)) + ov02a10_power_off(&client->dev); + pm_runtime_set_suspended(&client->dev); + mutex_destroy(&ov02a10->mutex); + + return 0; +} + +static const struct of_device_id ov02a10_of_match[] = { + { .compatible = "ovti,ov02a10" }, + {} +}; +MODULE_DEVICE_TABLE(of, ov02a10_of_match); + +static struct i2c_driver ov02a10_i2c_driver = { + .driver = { + .name = "ov02a10", + .pm = &ov02a10_pm_ops, + .of_match_table = ov02a10_of_match, + }, + .probe_new = &ov02a10_probe, + .remove = &ov02a10_remove, +}; + +module_i2c_driver(ov02a10_i2c_driver); + +MODULE_AUTHOR("Dongchun Zhu "); +MODULE_DESCRIPTION("OmniVision OV02A10 sensor driver"); +MODULE_LICENSE("GPL v2"); -- 2.9.2 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel