From: Mark Brown <broonie@kernel.org>
To: Shreyas Joshi <shreyas.joshi@biamp.com>
Cc: linux-spi@vger.kernel.org, shreyasjoshi15@gmail.com,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH] spi: spi-cadence: add support for chip select high
Date: Fri, 10 Jul 2020 16:35:31 +0100 [thread overview]
Message-ID: <20200710153530.GA46888@sirena.org.uk> (raw)
In-Reply-To: <20200710045140.458-1-shreyas.joshi@biamp.com>
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On Fri, Jul 10, 2020 at 02:51:40PM +1000, Shreyas Joshi wrote:
> spi cadence driver should support spi-cs-high in mode bits
> so that the peripherals that needs the chip select to be high active can
> use it. Add the SPI-CS-HIGH flag in the supported mode bits.
This doesn't apply against current code, please check and resend:
HEAD is now at 3ea4eac3e29f SPI SUBSYSTEM: Replace HTTP links with HTTPS ones
Applying: spi: spi-cadence: add support for chip select high
error: corrupt patch at line 18
error: could not build fake ancestor
Patch failed at 0001 spi: spi-cadence: add support for chip select high
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next prev parent reply other threads:[~2020-07-10 15:35 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-10 4:51 [PATCH] spi: spi-cadence: add support for chip select high Shreyas Joshi
2020-07-10 15:35 ` Mark Brown [this message]
2020-07-10 21:16 ` Shreyas Joshi
2020-07-20 3:55 ` Shreyas Joshi
2020-07-20 12:54 ` Mark Brown
2020-07-21 0:08 ` Shreyas Joshi
2020-07-22 13:45 ` Mark Brown
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