From: Max Filippov <jcmvbkbc@gmail.com>
To: qemu-devel@nongnu.org
Cc: Max Filippov <jcmvbkbc@gmail.com>,
Richard Henderson <richard.henderson@linaro.org>
Subject: [PATCH v4 00/22] target/xtensa: implement double precision FPU
Date: Sat, 11 Jul 2020 04:06:35 -0700 [thread overview]
Message-ID: <20200711110655.20287-1-jcmvbkbc@gmail.com> (raw)
Hello,
this series implements double precision floating point unit option for
target/xtensa, updates FPU tests and adds two new CPU cores, one with
FPU2000 option and one with DFPU option.
It is tagged xtensa-5.1-dfp-v4 in the qemu-xtensa tree at
git://github.com/OSLL/qemu-xtensa.git
I don't post the last two patches as they are too big for the list,
they can be found in the git tree mentioned above.
Changes v3->v4:
- split DFPU option addition into a separate patch, change DFP unit
detection logic
- avoid calling set_use_first_nan on every FPU operation in FPU2000
and single-precision only DFPU configurations
Changes v2->v3:
- handle infzero case in pickNaNMulAdd properly and reword commit
message
- add more infzero tests for FPU2000 and DFPU
- fix test names in test_dfp0_arith.S
- add licenses to newly imported cores
- rename DE_233L_FPU to de233_fpu to be more consistent with other
core names
Changes v1->v2:
- use inline function for no_signaling_nans property to allow for
constant folding on architectures that have this property fixed.
Max Filippov (22):
softfloat: make NO_SIGNALING_NANS runtime property
softfloat: pass float_status pointer to pickNaN
softfloat: add xtensa specialization for pickNaNMulAdd
target/xtensa: add geometry to xtensa_get_regfile_by_name
target/xtensa: support copying registers up to 64 bits wide
target/xtensa: rename FPU2000 translators and helpers
target/xtensa: move FSR/FCR register accessors
target/xtensa: don't access BR regfile directly
target/xtensa: add DFPU option
target/xtensa: add DFPU registers and opcodes
target/xtensa: implement FPU division and square root
tests/tcg/xtensa: fix test execution on ISS
tests/tcg/xtensa: update test_fp0_arith for DFPU
tests/tcg/xtensa: expand madd tests
tests/tcg/xtensa: update test_fp0_conv for DFPU
tests/tcg/xtensa: update test_fp1 for DFPU
tests/tcg/xtensa: update test_lsc for DFPU
tests/tcg/xtensa: add fp0 div and sqrt tests
tests/tcg/xtensa: test double precision load/store
tests/tcg/xtensa: add DFP0 arithmetic tests
target/xtensa: import de233_fpu core
target/xtensa: import DSP3400 core
fpu/softfloat-specialize.inc.c | 285 +-
fpu/softfloat.c | 2 +-
include/fpu/softfloat-helpers.h | 10 +
include/fpu/softfloat-types.h | 8 +-
target/xtensa/Makefile.objs | 2 +
target/xtensa/core-de233_fpu.c | 58 +
target/xtensa/core-de233_fpu/core-isa.h | 727 +
target/xtensa/core-de233_fpu/core-matmap.h | 717 +
target/xtensa/core-de233_fpu/gdb-config.inc.c | 277 +
.../core-de233_fpu/xtensa-modules.inc.c | 20758 ++
target/xtensa/core-dsp3400.c | 58 +
target/xtensa/core-dsp3400/core-isa.h | 452 +
target/xtensa/core-dsp3400/core-matmap.h | 312 +
target/xtensa/core-dsp3400/gdb-config.inc.c | 400 +
.../xtensa/core-dsp3400/xtensa-modules.inc.c | 171906 +++++++++++++++
target/xtensa/cpu.c | 5 +
target/xtensa/cpu.h | 8 +-
target/xtensa/fpu_helper.c | 342 +-
target/xtensa/helper.c | 4 +-
target/xtensa/helper.h | 58 +-
target/xtensa/overlay_tool.h | 24 +
target/xtensa/translate.c | 1437 +-
tests/tcg/xtensa/fpu.h | 142 +
tests/tcg/xtensa/macros.inc | 10 +-
tests/tcg/xtensa/test_dfp0_arith.S | 162 +
tests/tcg/xtensa/test_fp0_arith.S | 282 +-
tests/tcg/xtensa/test_fp0_conv.S | 299 +-
tests/tcg/xtensa/test_fp0_div.S | 82 +
tests/tcg/xtensa/test_fp0_sqrt.S | 76 +
tests/tcg/xtensa/test_fp1.S | 62 +-
tests/tcg/xtensa/test_lsc.S | 170 +-
31 files changed, 198581 insertions(+), 554 deletions(-)
create mode 100644 target/xtensa/core-de233_fpu.c
create mode 100644 target/xtensa/core-de233_fpu/core-isa.h
create mode 100644 target/xtensa/core-de233_fpu/core-matmap.h
create mode 100644 target/xtensa/core-de233_fpu/gdb-config.inc.c
create mode 100644 target/xtensa/core-de233_fpu/xtensa-modules.inc.c
create mode 100644 target/xtensa/core-dsp3400.c
create mode 100644 target/xtensa/core-dsp3400/core-isa.h
create mode 100644 target/xtensa/core-dsp3400/core-matmap.h
create mode 100644 target/xtensa/core-dsp3400/gdb-config.inc.c
create mode 100644 target/xtensa/core-dsp3400/xtensa-modules.inc.c
create mode 100644 tests/tcg/xtensa/fpu.h
create mode 100644 tests/tcg/xtensa/test_dfp0_arith.S
create mode 100644 tests/tcg/xtensa/test_fp0_div.S
create mode 100644 tests/tcg/xtensa/test_fp0_sqrt.S
--
2.20.1
next reply other threads:[~2020-07-11 11:08 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-11 11:06 Max Filippov [this message]
2020-07-11 11:06 ` [PATCH v4 01/22] softfloat: make NO_SIGNALING_NANS runtime property Max Filippov
2020-07-11 11:06 ` [PATCH v4 02/22] softfloat: pass float_status pointer to pickNaN Max Filippov
2020-07-11 11:06 ` [PATCH v4 03/22] softfloat: add xtensa specialization for pickNaNMulAdd Max Filippov
2020-07-11 11:06 ` [PATCH v4 04/22] target/xtensa: add geometry to xtensa_get_regfile_by_name Max Filippov
2020-07-11 11:06 ` [PATCH v4 05/22] target/xtensa: support copying registers up to 64 bits wide Max Filippov
2020-07-11 11:06 ` [PATCH v4 06/22] target/xtensa: rename FPU2000 translators and helpers Max Filippov
2020-07-11 11:06 ` [PATCH v4 07/22] target/xtensa: move FSR/FCR register accessors Max Filippov
2020-07-11 11:06 ` [PATCH v4 08/22] target/xtensa: don't access BR regfile directly Max Filippov
2020-07-11 11:06 ` [PATCH v4 09/22] target/xtensa: add DFPU option Max Filippov
2020-07-11 11:06 ` [PATCH v4 10/22] target/xtensa: add DFPU registers and opcodes Max Filippov
2020-07-11 11:06 ` [PATCH v4 11/22] target/xtensa: implement FPU division and square root Max Filippov
2020-07-11 11:06 ` [PATCH v4 12/22] tests/tcg/xtensa: fix test execution on ISS Max Filippov
2020-07-11 11:06 ` [PATCH v4 13/22] tests/tcg/xtensa: update test_fp0_arith for DFPU Max Filippov
2020-07-11 11:06 ` [PATCH v4 14/22] tests/tcg/xtensa: expand madd tests Max Filippov
2020-07-11 11:06 ` [PATCH v4 15/22] tests/tcg/xtensa: update test_fp0_conv for DFPU Max Filippov
2020-07-11 11:06 ` [PATCH v4 16/22] tests/tcg/xtensa: update test_fp1 " Max Filippov
2020-07-11 11:06 ` [PATCH v4 17/22] tests/tcg/xtensa: update test_lsc " Max Filippov
2020-07-11 11:06 ` [PATCH v4 18/22] tests/tcg/xtensa: add fp0 div and sqrt tests Max Filippov
2020-07-11 11:06 ` [PATCH v4 19/22] tests/tcg/xtensa: test double precision load/store Max Filippov
2020-07-11 11:06 ` [PATCH v4 20/22] tests/tcg/xtensa: add DFP0 arithmetic tests Max Filippov
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20200711110655.20287-1-jcmvbkbc@gmail.com \
--to=jcmvbkbc@gmail.com \
--cc=qemu-devel@nongnu.org \
--cc=richard.henderson@linaro.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.