* [PATCH v2 0/3] Add USB PHY support for new Ingenic SoCs.
@ 2020-07-13 14:32 周琰杰 (Zhou Yanjie)
2020-07-13 14:32 ` [PATCH v2 1/3] dt-bindings: USB: Add bindings " 周琰杰 (Zhou Yanjie)
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: 周琰杰 (Zhou Yanjie) @ 2020-07-13 14:32 UTC (permalink / raw)
To: balbi, robh+dt
Cc: linux-usb, devicetree, linux-kernel, gregkh, dongsheng.qiu,
aric.pzqi, rick.tyliu, yanfei.li, sernia.zhou, zhenwenjin, paul
v1->v2:
Add support for the JZ4780 SoC.
周琰杰 (Zhou Yanjie) (3):
dt-bindings: USB: Add bindings for new Ingenic SoCs.
USB: PHY: JZ4770: Add support for new Ingenic SoCs.
USB: PHY: JZ4770: Reformat the code to align it.
.../bindings/usb/ingenic,jz4770-phy.yaml | 6 +-
drivers/usb/phy/Kconfig | 4 +-
drivers/usb/phy/phy-jz4770.c | 256 ++++++++++++++-------
3 files changed, 181 insertions(+), 85 deletions(-)
--
2.11.0
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v2 1/3] dt-bindings: USB: Add bindings for new Ingenic SoCs.
2020-07-13 14:32 [PATCH v2 0/3] Add USB PHY support for new Ingenic SoCs 周琰杰 (Zhou Yanjie)
@ 2020-07-13 14:32 ` 周琰杰 (Zhou Yanjie)
2020-07-13 14:32 ` [PATCH v2 2/3] USB: PHY: JZ4770: Add support " 周琰杰 (Zhou Yanjie)
2020-07-13 14:32 ` [PATCH v2 3/3] USB: PHY: JZ4770: Reformat the code to align it 周琰杰 (Zhou Yanjie)
2 siblings, 0 replies; 6+ messages in thread
From: 周琰杰 (Zhou Yanjie) @ 2020-07-13 14:32 UTC (permalink / raw)
To: balbi, robh+dt
Cc: linux-usb, devicetree, linux-kernel, gregkh, dongsheng.qiu,
aric.pzqi, rick.tyliu, yanfei.li, sernia.zhou, zhenwenjin, paul
Add the USB PHY bindings for the JZ4780 SoC, the X1000 SoC and
the X1830 SoC from Ingenic.
Tested-by: 周正 (Zhou Zheng) <sernia.zhou@foxmail.com>
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Acked-by: Rob Herring <robh@kernel.org>
---
Notes:
v1->v2:
Add bindings for the JZ4780 SoC.
Documentation/devicetree/bindings/usb/ingenic,jz4770-phy.yaml | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/usb/ingenic,jz4770-phy.yaml b/Documentation/devicetree/bindings/usb/ingenic,jz4770-phy.yaml
index a81b0b1a2226..2d61166ea5cf 100644
--- a/Documentation/devicetree/bindings/usb/ingenic,jz4770-phy.yaml
+++ b/Documentation/devicetree/bindings/usb/ingenic,jz4770-phy.yaml
@@ -4,10 +4,11 @@
$id: http://devicetree.org/schemas/usb/ingenic,jz4770-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Ingenic JZ4770 USB PHY devicetree bindings
+title: Ingenic SoCs USB PHY devicetree bindings
maintainers:
- Paul Cercueil <paul@crapouillou.net>
+ - 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
properties:
$nodename:
@@ -16,6 +17,9 @@ properties:
compatible:
enum:
- ingenic,jz4770-phy
+ - ingenic,jz4780-phy
+ - ingenic,x1000-phy
+ - ingenic,x1830-phy
reg:
maxItems: 1
--
2.11.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v2 2/3] USB: PHY: JZ4770: Add support for new Ingenic SoCs.
2020-07-13 14:32 [PATCH v2 0/3] Add USB PHY support for new Ingenic SoCs 周琰杰 (Zhou Yanjie)
2020-07-13 14:32 ` [PATCH v2 1/3] dt-bindings: USB: Add bindings " 周琰杰 (Zhou Yanjie)
@ 2020-07-13 14:32 ` 周琰杰 (Zhou Yanjie)
2020-07-13 18:46 ` kernel test robot
2020-07-13 14:32 ` [PATCH v2 3/3] USB: PHY: JZ4770: Reformat the code to align it 周琰杰 (Zhou Yanjie)
2 siblings, 1 reply; 6+ messages in thread
From: 周琰杰 (Zhou Yanjie) @ 2020-07-13 14:32 UTC (permalink / raw)
To: balbi, robh+dt
Cc: linux-usb, devicetree, linux-kernel, gregkh, dongsheng.qiu,
aric.pzqi, rick.tyliu, yanfei.li, sernia.zhou, zhenwenjin, paul
Add support for probing the phy-jz4770 driver on the JZ4780 SoC,
the X1000 SoC and the X1830 SoC from Ingenic.
Tested-by: 周正 (Zhou Zheng) <sernia.zhou@foxmail.com>
Co-developed-by: 漆鹏振 (Qi Pengzhen) <aric.pzqi@ingenic.com>
Signed-off-by: 漆鹏振 (Qi Pengzhen) <aric.pzqi@ingenic.com>
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
---
Notes:
v1->v2:
Add support for the JZ4780 SoC.
drivers/usb/phy/Kconfig | 4 +-
drivers/usb/phy/phy-jz4770.c | 178 ++++++++++++++++++++++++++++++++-----------
2 files changed, 137 insertions(+), 45 deletions(-)
diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig
index 4b3fa78995cf..775f0dd7b5f5 100644
--- a/drivers/usb/phy/Kconfig
+++ b/drivers/usb/phy/Kconfig
@@ -185,11 +185,11 @@ config USB_ULPI_VIEWPORT
controllers with a viewport register (e.g. Chipidea/ARC controllers).
config JZ4770_PHY
- tristate "Ingenic JZ4770 Transceiver Driver"
+ tristate "Ingenic SoCs Transceiver Driver"
depends on MIPS || COMPILE_TEST
select USB_PHY
help
This driver provides PHY support for the USB controller found
- on the JZ4770 SoC from Ingenic.
+ on the JZ4770/JZ4780/X1000/X1830 SoC from Ingenic.
endmenu
diff --git a/drivers/usb/phy/phy-jz4770.c b/drivers/usb/phy/phy-jz4770.c
index 8f62dc2a90ff..d1055c908943 100644
--- a/drivers/usb/phy/phy-jz4770.c
+++ b/drivers/usb/phy/phy-jz4770.c
@@ -1,12 +1,15 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Ingenic JZ4770 USB PHY driver
+ * Ingenic SoCs USB PHY driver
* Copyright (c) Paul Cercueil <paul@crapouillou.net>
+ * Copyright (c) 漆鹏振 (Qi Pengzhen) <aric.pzqi@ingenic.com>
+ * Copyright (c) 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
*/
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/module.h>
+#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>
#include <linux/usb/otg.h>
@@ -17,11 +20,10 @@
#define REG_USBVBFIL_OFFSET 0x08
#define REG_USBPCR1_OFFSET 0x0c
-/* USBPCR */
+/*USB Parameter Control Register*/
#define USBPCR_USB_MODE BIT(31)
#define USBPCR_AVLD_REG BIT(30)
-#define USBPCR_INCRM BIT(27)
-#define USBPCR_CLK12_EN BIT(26)
+#define USBPCR_INCR_MASK BIT(27)
#define USBPCR_COMMONONN BIT(25)
#define USBPCR_VBUSVLDEXT BIT(24)
#define USBPCR_VBUSVLDEXTSEL BIT(23)
@@ -32,46 +34,80 @@
#define USBPCR_IDPULLUP_LSB 28
#define USBPCR_IDPULLUP_MASK GENMASK(29, USBPCR_IDPULLUP_LSB)
-#define USBPCR_IDPULLUP_ALWAYS (3 << USBPCR_IDPULLUP_LSB)
-#define USBPCR_IDPULLUP_SUSPEND (1 << USBPCR_IDPULLUP_LSB)
-#define USBPCR_IDPULLUP_OTG (0 << USBPCR_IDPULLUP_LSB)
+#define USBPCR_IDPULLUP_ALWAYS (0x2 << USBPCR_IDPULLUP_LSB)
+#define USBPCR_IDPULLUP_SUSPEND (0x1 << USBPCR_IDPULLUP_LSB)
+#define USBPCR_IDPULLUP_OTG (0x0 << USBPCR_IDPULLUP_LSB)
#define USBPCR_COMPDISTUNE_LSB 17
#define USBPCR_COMPDISTUNE_MASK GENMASK(19, USBPCR_COMPDISTUNE_LSB)
-#define USBPCR_COMPDISTUNE_DFT 4
+#define USBPCR_COMPDISTUNE_DFT (0x4 << USBPCR_COMPDISTUNE_LSB)
#define USBPCR_OTGTUNE_LSB 14
#define USBPCR_OTGTUNE_MASK GENMASK(16, USBPCR_OTGTUNE_LSB)
-#define USBPCR_OTGTUNE_DFT 4
+#define USBPCR_OTGTUNE_DFT (0x4 << USBPCR_OTGTUNE_LSB)
#define USBPCR_SQRXTUNE_LSB 11
#define USBPCR_SQRXTUNE_MASK GENMASK(13, USBPCR_SQRXTUNE_LSB)
-#define USBPCR_SQRXTUNE_DFT 3
+#define USBPCR_SQRXTUNE_DCR_20PCT (0x7 << USBPCR_SQRXTUNE_LSB)
+#define USBPCR_SQRXTUNE_DFT (0x3 << USBPCR_SQRXTUNE_LSB)
#define USBPCR_TXFSLSTUNE_LSB 7
#define USBPCR_TXFSLSTUNE_MASK GENMASK(10, USBPCR_TXFSLSTUNE_LSB)
-#define USBPCR_TXFSLSTUNE_DFT 3
+#define USBPCR_TXFSLSTUNE_DCR_50PPT (0xf << USBPCR_TXFSLSTUNE_LSB)
+#define USBPCR_TXFSLSTUNE_DCR_25PPT (0x7 << USBPCR_TXFSLSTUNE_LSB)
+#define USBPCR_TXFSLSTUNE_DFT (0x3 << USBPCR_TXFSLSTUNE_LSB)
+#define USBPCR_TXFSLSTUNE_INC_25PPT (0x1 << USBPCR_TXFSLSTUNE_LSB)
+#define USBPCR_TXFSLSTUNE_INC_50PPT (0x0 << USBPCR_TXFSLSTUNE_LSB)
+
+#define USBPCR_TXHSXVTUNE_LSB 4
+#define USBPCR_TXHSXVTUNE_MASK GENMASK(5, USBPCR_TXHSXVTUNE_LSB)
+#define USBPCR_TXHSXVTUNE_DFT (0x3 << USBPCR_TXHSXVTUNE_LSB)
+#define USBPCR_TXHSXVTUNE_DCR_15MV (0x1 << USBPCR_TXHSXVTUNE_LSB)
#define USBPCR_TXRISETUNE_LSB 4
#define USBPCR_TXRISETUNE_MASK GENMASK(5, USBPCR_TXRISETUNE_LSB)
-#define USBPCR_TXRISETUNE_DFT 3
+#define USBPCR_TXRISETUNE_DFT (0x3 << USBPCR_TXRISETUNE_LSB)
#define USBPCR_TXVREFTUNE_LSB 0
#define USBPCR_TXVREFTUNE_MASK GENMASK(3, USBPCR_TXVREFTUNE_LSB)
-#define USBPCR_TXVREFTUNE_DFT 5
+#define USBPCR_TXVREFTUNE_INC_25PPT (0x7 << USBPCR_TXVREFTUNE_LSB)
+#define USBPCR_TXVREFTUNE_DFT (0x5 << USBPCR_TXVREFTUNE_LSB)
-/* USBRDT */
+/*USB Reset Detect Timer Register*/
+#define USBRDT_UTMI_RST BIT(27)
+#define USBRDT_HB_MASK BIT(26)
#define USBRDT_VBFIL_LD_EN BIT(25)
#define USBRDT_IDDIG_EN BIT(24)
#define USBRDT_IDDIG_REG BIT(23)
-
-#define USBRDT_USBRDT_LSB 0
-#define USBRDT_USBRDT_MASK GENMASK(22, USBRDT_USBRDT_LSB)
-
-/* USBPCR1 */
-#define USBPCR1_UHC_POWON BIT(5)
+#define USBRDT_VBFIL_EN BIT(2)
+
+/*USB Parameter Control Register 1*/
+#define USBPCR1_BVLD_REG BIT(31)
+#define USBPCR1_DPPD BIT(29)
+#define USBPCR1_DMPD BIT(28)
+#define USBPCR1_USB_SEL BIT(28)
+#define USBPCR1_WORD_IF_16BIT BIT(19)
+
+#define USBPCR1_REFCLKSEL_LSB 26
+#define USBPCR1_REFCLKSEL_MASK GENMASK(27, USBPCR1_REFCLKDIV_LSB)
+#define USBPCR1_REFCLKSEL_CLKCORE (0x3 << USBPCR1_REFCLKSEL_LSB)
+
+#define USBPCR1_REFCLKDIV_LSB 24
+#define USBPCR1_REFCLKDIV_MASK GENMASK(25, USBPCR1_REFCLKDIV_LSB)
+#define USBPCR1_REFCLKDIV_48M (0x2 << USBPCR1_REFCLKDIV_LSB)
+#define USBPCR1_REFCLKDIV_24M (0x1 << USBPCR1_REFCLKDIV_LSB)
+#define USBPCR1_REFCLKDIV_12M (0x0 << USBPCR1_REFCLKDIV_LSB)
+
+enum ingenic_usb_phy_version {
+ ID_JZ4770,
+ ID_JZ4780,
+ ID_X1000,
+ ID_X1830,
+};
struct jz4770_phy {
+ enum ingenic_usb_phy_version version;
+
struct usb_phy phy;
struct usb_otg otg;
struct device *dev;
@@ -96,6 +132,12 @@ static int jz4770_phy_set_peripheral(struct usb_otg *otg,
struct jz4770_phy *priv = otg_to_jz4770_phy(otg);
u32 reg;
+ if (priv->version >= ID_X1000) {
+ reg = readl(priv->base + REG_USBPCR1_OFFSET);
+ reg |= USBPCR1_BVLD_REG;
+ writel(reg, priv->base + REG_USBPCR1_OFFSET);
+ }
+
reg = readl(priv->base + REG_USBPCR_OFFSET);
reg &= ~USBPCR_USB_MODE;
reg |= USBPCR_VBUSVLDEXT | USBPCR_VBUSVLDEXTSEL | USBPCR_OTG_DISABLE;
@@ -135,17 +177,59 @@ static int jz4770_phy_init(struct usb_phy *phy)
return err;
}
- reg = USBPCR_AVLD_REG | USBPCR_COMMONONN | USBPCR_IDPULLUP_ALWAYS |
- (USBPCR_COMPDISTUNE_DFT << USBPCR_COMPDISTUNE_LSB) |
- (USBPCR_OTGTUNE_DFT << USBPCR_OTGTUNE_LSB) |
- (USBPCR_SQRXTUNE_DFT << USBPCR_SQRXTUNE_LSB) |
- (USBPCR_TXFSLSTUNE_DFT << USBPCR_TXFSLSTUNE_LSB) |
- (USBPCR_TXRISETUNE_DFT << USBPCR_TXRISETUNE_LSB) |
- (USBPCR_TXVREFTUNE_DFT << USBPCR_TXVREFTUNE_LSB) |
- USBPCR_POR;
+ if (priv->version >= ID_X1830) {
+ /* rdt */
+ writel(USBRDT_VBFIL_EN | USBRDT_UTMI_RST, priv->base + REG_USBRDT_OFFSET);
+
+ reg = readl(priv->base + REG_USBPCR1_OFFSET) | USBPCR1_WORD_IF_16BIT |
+ USBPCR1_DMPD | USBPCR1_DPPD;
+ writel(reg, priv->base + REG_USBPCR1_OFFSET);
+
+ reg = USBPCR_IDPULLUP_OTG | USBPCR_VBUSVLDEXT | USBPCR_TXPREEMPHTUNE;
+ } else if (priv->version >= ID_X1000) {
+ reg = readl(priv->base + REG_USBPCR1_OFFSET) | USBPCR1_WORD_IF_16BIT;
+ writel(reg, priv->base + REG_USBPCR1_OFFSET);
+
+ reg = USBPCR_SQRXTUNE_DCR_20PCT | USBPCR_TXPREEMPHTUNE |
+ USBPCR_TXHSXVTUNE_DCR_15MV | USBPCR_TXVREFTUNE_INC_25PPT;
+ } else if (priv->version >= ID_JZ4780) {
+ reg = readl(priv->base + REG_USBPCR1_OFFSET) | USBPCR1_USB_SEL |
+ USBPCR1_WORD_IF_16BIT;
+ writel(reg, priv->base + REG_USBPCR1_OFFSET);
+
+ reg = USBPCR_TXPREEMPHTUNE;
+ } else {
+ reg = USBPCR_AVLD_REG | USBPCR_IDPULLUP_ALWAYS |
+ USBPCR_COMPDISTUNE_DFT | USBPCR_OTGTUNE_DFT |
+ USBPCR_SQRXTUNE_DFT | USBPCR_TXFSLSTUNE_DFT |
+ USBPCR_TXRISETUNE_DFT | USBPCR_TXVREFTUNE_DFT;
+ }
+
+ reg |= USBPCR_COMMONONN | USBPCR_POR;
writel(reg, priv->base + REG_USBPCR_OFFSET);
- /* Wait for PHY to reset */
+ /*
+ * Power-On Reset(POR)
+ * Function:This customer-specific signal resets all test registers
+ * and state machines in the USB 2.0 nanoPHY.
+ * The POR signal must be asserted for a minimum of 10 μs.
+ * For POR timing information:
+ *
+ * T0: Power-on reset (POR) is initiated. 0 (reference).
+ * T1: T1 indicates when POR can be set to 1’b0. (To provide examples,
+ * values for T2 and T3 are also shown where T1 = T0 + 30 μs.);
+ * In general, T1 must be ≥ T0 + 10 μs. T0 + 10 μs ≤ T1.
+ * T2: T2 indicates when PHYCLOCK, CLK48MOHCI, and CLK12MOHCI are
+ * available at the macro output, based on the USB 2.0 nanoPHY
+ * reference clock source.
+ * Crystal:
+ * • When T1 = T0 + 10 μs:
+ * T2 < T1 + 805 μs = T0 + 815 μs
+ * • When T1 = T0 + 30 μs:
+ * T2 < T1 + 805 μs = T0 + 835 μs
+ * see "Reset and Power-Saving Signals" on page 60 an “Powering Up
+ * and Powering Down the USB 2.0 nanoPHY” on page 73.
+ */
usleep_range(30, 300);
writel(reg & ~USBPCR_POR, priv->base + REG_USBPCR_OFFSET);
usleep_range(300, 1000);
@@ -166,21 +250,37 @@ static void jz4770_phy_remove(void *phy)
usb_remove_phy(phy);
}
+static const struct of_device_id ingenic_usb_phy_of_matches[] = {
+ { .compatible = "ingenic,jz4770-phy", .data = (void *) ID_JZ4770 },
+ { .compatible = "ingenic,jz4780-phy", .data = (void *) ID_JZ4780 },
+ { .compatible = "ingenic,x1000-phy", .data = (void *) ID_X1000 },
+ { .compatible = "ingenic,x1830-phy", .data = (void *) ID_X1830 },
+ { }
+};
+MODULE_DEVICE_TABLE(of, ingenic_usb_phy_of_matches);
+
static int jz4770_phy_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct jz4770_phy *priv;
+ const struct of_device_id *match;
int err;
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
+ match = of_match_device(ingenic_usb_phy_of_matches, dev);
+ if (match)
+ priv->version = (enum ingenic_usb_phy_version)match->data;
+ else
+ return -ENODEV;
+
platform_set_drvdata(pdev, priv);
priv->dev = dev;
priv->phy.dev = dev;
priv->phy.otg = &priv->otg;
- priv->phy.label = "jz4770-phy";
+ priv->phy.label = "ingenic-usb-phy";
priv->phy.init = jz4770_phy_init;
priv->phy.shutdown = jz4770_phy_shutdown;
@@ -221,23 +321,15 @@ static int jz4770_phy_probe(struct platform_device *pdev)
return devm_add_action_or_reset(dev, jz4770_phy_remove, &priv->phy);
}
-#ifdef CONFIG_OF
-static const struct of_device_id jz4770_phy_of_matches[] = {
- { .compatible = "ingenic,jz4770-phy" },
- { }
-};
-MODULE_DEVICE_TABLE(of, jz4770_phy_of_matches);
-#endif
-
-static struct platform_driver jz4770_phy_driver = {
+static struct platform_driver ingenic_usb_phy_driver = {
.probe = jz4770_phy_probe,
.driver = {
- .name = "jz4770-phy",
- .of_match_table = of_match_ptr(jz4770_phy_of_matches),
+ .name = "ingenic-usb-phy",
+ .of_match_table = of_match_ptr(ingenic_usb_phy_of_matches),
},
};
-module_platform_driver(jz4770_phy_driver);
+module_platform_driver(ingenic_usb_phy_driver);
MODULE_AUTHOR("Paul Cercueil <paul@crapouillou.net>");
-MODULE_DESCRIPTION("Ingenic JZ4770 USB PHY driver");
+MODULE_DESCRIPTION("Ingenic SoCs USB PHY driver");
MODULE_LICENSE("GPL");
--
2.11.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v2 3/3] USB: PHY: JZ4770: Reformat the code to align it.
2020-07-13 14:32 [PATCH v2 0/3] Add USB PHY support for new Ingenic SoCs 周琰杰 (Zhou Yanjie)
2020-07-13 14:32 ` [PATCH v2 1/3] dt-bindings: USB: Add bindings " 周琰杰 (Zhou Yanjie)
2020-07-13 14:32 ` [PATCH v2 2/3] USB: PHY: JZ4770: Add support " 周琰杰 (Zhou Yanjie)
@ 2020-07-13 14:32 ` 周琰杰 (Zhou Yanjie)
2 siblings, 0 replies; 6+ messages in thread
From: 周琰杰 (Zhou Yanjie) @ 2020-07-13 14:32 UTC (permalink / raw)
To: balbi, robh+dt
Cc: linux-usb, devicetree, linux-kernel, gregkh, dongsheng.qiu,
aric.pzqi, rick.tyliu, yanfei.li, sernia.zhou, zhenwenjin, paul
Reformat the code (add one level of indentation before the values),
to align the code in the macro definition section.
Tested-by: 周正 (Zhou Zheng) <sernia.zhou@foxmail.com>
Co-developed-by: 漆鹏振 (Qi Pengzhen) <aric.pzqi@ingenic.com>
Signed-off-by: 漆鹏振 (Qi Pengzhen) <aric.pzqi@ingenic.com>
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
---
Notes:
v2:
New patch.
drivers/usb/phy/phy-jz4770.c | 100 +++++++++++++++++++++----------------------
1 file changed, 50 insertions(+), 50 deletions(-)
diff --git a/drivers/usb/phy/phy-jz4770.c b/drivers/usb/phy/phy-jz4770.c
index d1055c908943..65e517290912 100644
--- a/drivers/usb/phy/phy-jz4770.c
+++ b/drivers/usb/phy/phy-jz4770.c
@@ -15,71 +15,71 @@
#include <linux/usb/otg.h>
#include <linux/usb/phy.h>
-#define REG_USBPCR_OFFSET 0x00
-#define REG_USBRDT_OFFSET 0x04
-#define REG_USBVBFIL_OFFSET 0x08
-#define REG_USBPCR1_OFFSET 0x0c
+#define REG_USBPCR_OFFSET 0x00
+#define REG_USBRDT_OFFSET 0x04
+#define REG_USBVBFIL_OFFSET 0x08
+#define REG_USBPCR1_OFFSET 0x0c
/*USB Parameter Control Register*/
-#define USBPCR_USB_MODE BIT(31)
-#define USBPCR_AVLD_REG BIT(30)
-#define USBPCR_INCR_MASK BIT(27)
-#define USBPCR_COMMONONN BIT(25)
-#define USBPCR_VBUSVLDEXT BIT(24)
-#define USBPCR_VBUSVLDEXTSEL BIT(23)
-#define USBPCR_POR BIT(22)
-#define USBPCR_SIDDQ BIT(21)
-#define USBPCR_OTG_DISABLE BIT(20)
-#define USBPCR_TXPREEMPHTUNE BIT(6)
-
-#define USBPCR_IDPULLUP_LSB 28
-#define USBPCR_IDPULLUP_MASK GENMASK(29, USBPCR_IDPULLUP_LSB)
-#define USBPCR_IDPULLUP_ALWAYS (0x2 << USBPCR_IDPULLUP_LSB)
-#define USBPCR_IDPULLUP_SUSPEND (0x1 << USBPCR_IDPULLUP_LSB)
-#define USBPCR_IDPULLUP_OTG (0x0 << USBPCR_IDPULLUP_LSB)
-
-#define USBPCR_COMPDISTUNE_LSB 17
-#define USBPCR_COMPDISTUNE_MASK GENMASK(19, USBPCR_COMPDISTUNE_LSB)
-#define USBPCR_COMPDISTUNE_DFT (0x4 << USBPCR_COMPDISTUNE_LSB)
-
-#define USBPCR_OTGTUNE_LSB 14
-#define USBPCR_OTGTUNE_MASK GENMASK(16, USBPCR_OTGTUNE_LSB)
-#define USBPCR_OTGTUNE_DFT (0x4 << USBPCR_OTGTUNE_LSB)
-
-#define USBPCR_SQRXTUNE_LSB 11
-#define USBPCR_SQRXTUNE_MASK GENMASK(13, USBPCR_SQRXTUNE_LSB)
+#define USBPCR_USB_MODE BIT(31)
+#define USBPCR_AVLD_REG BIT(30)
+#define USBPCR_INCR_MASK BIT(27)
+#define USBPCR_COMMONONN BIT(25)
+#define USBPCR_VBUSVLDEXT BIT(24)
+#define USBPCR_VBUSVLDEXTSEL BIT(23)
+#define USBPCR_POR BIT(22)
+#define USBPCR_SIDDQ BIT(21)
+#define USBPCR_OTG_DISABLE BIT(20)
+#define USBPCR_TXPREEMPHTUNE BIT(6)
+
+#define USBPCR_IDPULLUP_LSB 28
+#define USBPCR_IDPULLUP_MASK GENMASK(29, USBPCR_IDPULLUP_LSB)
+#define USBPCR_IDPULLUP_ALWAYS (0x2 << USBPCR_IDPULLUP_LSB)
+#define USBPCR_IDPULLUP_SUSPEND (0x1 << USBPCR_IDPULLUP_LSB)
+#define USBPCR_IDPULLUP_OTG (0x0 << USBPCR_IDPULLUP_LSB)
+
+#define USBPCR_COMPDISTUNE_LSB 17
+#define USBPCR_COMPDISTUNE_MASK GENMASK(19, USBPCR_COMPDISTUNE_LSB)
+#define USBPCR_COMPDISTUNE_DFT (0x4 << USBPCR_COMPDISTUNE_LSB)
+
+#define USBPCR_OTGTUNE_LSB 14
+#define USBPCR_OTGTUNE_MASK GENMASK(16, USBPCR_OTGTUNE_LSB)
+#define USBPCR_OTGTUNE_DFT (0x4 << USBPCR_OTGTUNE_LSB)
+
+#define USBPCR_SQRXTUNE_LSB 11
+#define USBPCR_SQRXTUNE_MASK GENMASK(13, USBPCR_SQRXTUNE_LSB)
#define USBPCR_SQRXTUNE_DCR_20PCT (0x7 << USBPCR_SQRXTUNE_LSB)
-#define USBPCR_SQRXTUNE_DFT (0x3 << USBPCR_SQRXTUNE_LSB)
+#define USBPCR_SQRXTUNE_DFT (0x3 << USBPCR_SQRXTUNE_LSB)
-#define USBPCR_TXFSLSTUNE_LSB 7
-#define USBPCR_TXFSLSTUNE_MASK GENMASK(10, USBPCR_TXFSLSTUNE_LSB)
+#define USBPCR_TXFSLSTUNE_LSB 7
+#define USBPCR_TXFSLSTUNE_MASK GENMASK(10, USBPCR_TXFSLSTUNE_LSB)
#define USBPCR_TXFSLSTUNE_DCR_50PPT (0xf << USBPCR_TXFSLSTUNE_LSB)
#define USBPCR_TXFSLSTUNE_DCR_25PPT (0x7 << USBPCR_TXFSLSTUNE_LSB)
-#define USBPCR_TXFSLSTUNE_DFT (0x3 << USBPCR_TXFSLSTUNE_LSB)
+#define USBPCR_TXFSLSTUNE_DFT (0x3 << USBPCR_TXFSLSTUNE_LSB)
#define USBPCR_TXFSLSTUNE_INC_25PPT (0x1 << USBPCR_TXFSLSTUNE_LSB)
#define USBPCR_TXFSLSTUNE_INC_50PPT (0x0 << USBPCR_TXFSLSTUNE_LSB)
-#define USBPCR_TXHSXVTUNE_LSB 4
-#define USBPCR_TXHSXVTUNE_MASK GENMASK(5, USBPCR_TXHSXVTUNE_LSB)
-#define USBPCR_TXHSXVTUNE_DFT (0x3 << USBPCR_TXHSXVTUNE_LSB)
+#define USBPCR_TXHSXVTUNE_LSB 4
+#define USBPCR_TXHSXVTUNE_MASK GENMASK(5, USBPCR_TXHSXVTUNE_LSB)
+#define USBPCR_TXHSXVTUNE_DFT (0x3 << USBPCR_TXHSXVTUNE_LSB)
#define USBPCR_TXHSXVTUNE_DCR_15MV (0x1 << USBPCR_TXHSXVTUNE_LSB)
-#define USBPCR_TXRISETUNE_LSB 4
-#define USBPCR_TXRISETUNE_MASK GENMASK(5, USBPCR_TXRISETUNE_LSB)
-#define USBPCR_TXRISETUNE_DFT (0x3 << USBPCR_TXRISETUNE_LSB)
+#define USBPCR_TXRISETUNE_LSB 4
+#define USBPCR_TXRISETUNE_MASK GENMASK(5, USBPCR_TXRISETUNE_LSB)
+#define USBPCR_TXRISETUNE_DFT (0x3 << USBPCR_TXRISETUNE_LSB)
-#define USBPCR_TXVREFTUNE_LSB 0
-#define USBPCR_TXVREFTUNE_MASK GENMASK(3, USBPCR_TXVREFTUNE_LSB)
+#define USBPCR_TXVREFTUNE_LSB 0
+#define USBPCR_TXVREFTUNE_MASK GENMASK(3, USBPCR_TXVREFTUNE_LSB)
#define USBPCR_TXVREFTUNE_INC_25PPT (0x7 << USBPCR_TXVREFTUNE_LSB)
-#define USBPCR_TXVREFTUNE_DFT (0x5 << USBPCR_TXVREFTUNE_LSB)
+#define USBPCR_TXVREFTUNE_DFT (0x5 << USBPCR_TXVREFTUNE_LSB)
/*USB Reset Detect Timer Register*/
-#define USBRDT_UTMI_RST BIT(27)
-#define USBRDT_HB_MASK BIT(26)
-#define USBRDT_VBFIL_LD_EN BIT(25)
-#define USBRDT_IDDIG_EN BIT(24)
-#define USBRDT_IDDIG_REG BIT(23)
-#define USBRDT_VBFIL_EN BIT(2)
+#define USBRDT_UTMI_RST BIT(27)
+#define USBRDT_HB_MASK BIT(26)
+#define USBRDT_VBFIL_LD_EN BIT(25)
+#define USBRDT_IDDIG_EN BIT(24)
+#define USBRDT_IDDIG_REG BIT(23)
+#define USBRDT_VBFIL_EN BIT(2)
/*USB Parameter Control Register 1*/
#define USBPCR1_BVLD_REG BIT(31)
--
2.11.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v2 2/3] USB: PHY: JZ4770: Add support for new Ingenic SoCs.
2020-07-13 14:32 ` [PATCH v2 2/3] USB: PHY: JZ4770: Add support " 周琰杰 (Zhou Yanjie)
@ 2020-07-13 18:46 ` kernel test robot
0 siblings, 0 replies; 6+ messages in thread
From: kernel test robot @ 2020-07-13 18:46 UTC (permalink / raw)
To: 周琰杰 (Zhou Yanjie), balbi, robh+dt
Cc: kbuild-all, clang-built-linux, linux-usb, devicetree,
linux-kernel, gregkh, dongsheng.qiu, aric.pzqi, rick.tyliu,
yanfei.li
[-- Attachment #1: Type: text/plain, Size: 3829 bytes --]
Hi "周琰杰,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on balbi-usb/testing/next]
[also build test WARNING on usb/usb-testing robh/for-next v5.8-rc5 next-20200713]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Zhou-Yanjie/Add-USB-PHY-support-for-new-Ingenic-SoCs/20200713-223543
base: https://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb.git testing/next
config: x86_64-allyesconfig (attached as .config)
compiler: clang version 11.0.0 (https://github.com/llvm/llvm-project 02946de3802d3bc65bc9f2eb9b8d4969b5a7add8)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install x86_64 cross compiling tool for clang build
# apt-get install binutils-x86-64-linux-gnu
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=x86_64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All warnings (new ones prefixed by >>):
>> drivers/usb/phy/phy-jz4770.c:275:19: warning: cast to smaller integer type 'enum ingenic_usb_phy_version' from 'const void *' [-Wvoid-pointer-to-enum-cast]
priv->version = (enum ingenic_usb_phy_version)match->data;
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1 warning generated.
vim +275 drivers/usb/phy/phy-jz4770.c
261
262 static int jz4770_phy_probe(struct platform_device *pdev)
263 {
264 struct device *dev = &pdev->dev;
265 struct jz4770_phy *priv;
266 const struct of_device_id *match;
267 int err;
268
269 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
270 if (!priv)
271 return -ENOMEM;
272
273 match = of_match_device(ingenic_usb_phy_of_matches, dev);
274 if (match)
> 275 priv->version = (enum ingenic_usb_phy_version)match->data;
276 else
277 return -ENODEV;
278
279 platform_set_drvdata(pdev, priv);
280 priv->dev = dev;
281 priv->phy.dev = dev;
282 priv->phy.otg = &priv->otg;
283 priv->phy.label = "ingenic-usb-phy";
284 priv->phy.init = jz4770_phy_init;
285 priv->phy.shutdown = jz4770_phy_shutdown;
286
287 priv->otg.state = OTG_STATE_UNDEFINED;
288 priv->otg.usb_phy = &priv->phy;
289 priv->otg.set_host = jz4770_phy_set_host;
290 priv->otg.set_peripheral = jz4770_phy_set_peripheral;
291
292 priv->base = devm_platform_ioremap_resource(pdev, 0);
293 if (IS_ERR(priv->base)) {
294 dev_err(dev, "Failed to map registers");
295 return PTR_ERR(priv->base);
296 }
297
298 priv->clk = devm_clk_get(dev, NULL);
299 if (IS_ERR(priv->clk)) {
300 err = PTR_ERR(priv->clk);
301 if (err != -EPROBE_DEFER)
302 dev_err(dev, "Failed to get clock");
303 return err;
304 }
305
306 priv->vcc_supply = devm_regulator_get(dev, "vcc");
307 if (IS_ERR(priv->vcc_supply)) {
308 err = PTR_ERR(priv->vcc_supply);
309 if (err != -EPROBE_DEFER)
310 dev_err(dev, "failed to get regulator");
311 return err;
312 }
313
314 err = usb_add_phy(&priv->phy, USB_PHY_TYPE_USB2);
315 if (err) {
316 if (err != -EPROBE_DEFER)
317 dev_err(dev, "Unable to register PHY");
318 return err;
319 }
320
321 return devm_add_action_or_reset(dev, jz4770_phy_remove, &priv->phy);
322 }
323
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 74004 bytes --]
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v2 2/3] USB: PHY: JZ4770: Add support for new Ingenic SoCs.
@ 2020-07-13 18:46 ` kernel test robot
0 siblings, 0 replies; 6+ messages in thread
From: kernel test robot @ 2020-07-13 18:46 UTC (permalink / raw)
To: kbuild-all
[-- Attachment #1: Type: text/plain, Size: 3932 bytes --]
Hi "周琰杰,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on balbi-usb/testing/next]
[also build test WARNING on usb/usb-testing robh/for-next v5.8-rc5 next-20200713]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Zhou-Yanjie/Add-USB-PHY-support-for-new-Ingenic-SoCs/20200713-223543
base: https://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb.git testing/next
config: x86_64-allyesconfig (attached as .config)
compiler: clang version 11.0.0 (https://github.com/llvm/llvm-project 02946de3802d3bc65bc9f2eb9b8d4969b5a7add8)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install x86_64 cross compiling tool for clang build
# apt-get install binutils-x86-64-linux-gnu
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=x86_64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All warnings (new ones prefixed by >>):
>> drivers/usb/phy/phy-jz4770.c:275:19: warning: cast to smaller integer type 'enum ingenic_usb_phy_version' from 'const void *' [-Wvoid-pointer-to-enum-cast]
priv->version = (enum ingenic_usb_phy_version)match->data;
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1 warning generated.
vim +275 drivers/usb/phy/phy-jz4770.c
261
262 static int jz4770_phy_probe(struct platform_device *pdev)
263 {
264 struct device *dev = &pdev->dev;
265 struct jz4770_phy *priv;
266 const struct of_device_id *match;
267 int err;
268
269 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
270 if (!priv)
271 return -ENOMEM;
272
273 match = of_match_device(ingenic_usb_phy_of_matches, dev);
274 if (match)
> 275 priv->version = (enum ingenic_usb_phy_version)match->data;
276 else
277 return -ENODEV;
278
279 platform_set_drvdata(pdev, priv);
280 priv->dev = dev;
281 priv->phy.dev = dev;
282 priv->phy.otg = &priv->otg;
283 priv->phy.label = "ingenic-usb-phy";
284 priv->phy.init = jz4770_phy_init;
285 priv->phy.shutdown = jz4770_phy_shutdown;
286
287 priv->otg.state = OTG_STATE_UNDEFINED;
288 priv->otg.usb_phy = &priv->phy;
289 priv->otg.set_host = jz4770_phy_set_host;
290 priv->otg.set_peripheral = jz4770_phy_set_peripheral;
291
292 priv->base = devm_platform_ioremap_resource(pdev, 0);
293 if (IS_ERR(priv->base)) {
294 dev_err(dev, "Failed to map registers");
295 return PTR_ERR(priv->base);
296 }
297
298 priv->clk = devm_clk_get(dev, NULL);
299 if (IS_ERR(priv->clk)) {
300 err = PTR_ERR(priv->clk);
301 if (err != -EPROBE_DEFER)
302 dev_err(dev, "Failed to get clock");
303 return err;
304 }
305
306 priv->vcc_supply = devm_regulator_get(dev, "vcc");
307 if (IS_ERR(priv->vcc_supply)) {
308 err = PTR_ERR(priv->vcc_supply);
309 if (err != -EPROBE_DEFER)
310 dev_err(dev, "failed to get regulator");
311 return err;
312 }
313
314 err = usb_add_phy(&priv->phy, USB_PHY_TYPE_USB2);
315 if (err) {
316 if (err != -EPROBE_DEFER)
317 dev_err(dev, "Unable to register PHY");
318 return err;
319 }
320
321 return devm_add_action_or_reset(dev, jz4770_phy_remove, &priv->phy);
322 }
323
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
[-- Attachment #2: config.gz --]
[-- Type: application/gzip, Size: 74004 bytes --]
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2020-07-13 18:50 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-07-13 14:32 [PATCH v2 0/3] Add USB PHY support for new Ingenic SoCs 周琰杰 (Zhou Yanjie)
2020-07-13 14:32 ` [PATCH v2 1/3] dt-bindings: USB: Add bindings " 周琰杰 (Zhou Yanjie)
2020-07-13 14:32 ` [PATCH v2 2/3] USB: PHY: JZ4770: Add support " 周琰杰 (Zhou Yanjie)
2020-07-13 18:46 ` kernel test robot
2020-07-13 18:46 ` kernel test robot
2020-07-13 14:32 ` [PATCH v2 3/3] USB: PHY: JZ4770: Reformat the code to align it 周琰杰 (Zhou Yanjie)
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