* [PULL 00/15] riscv-to-apply queue
@ 2020-07-14 0:32 Alistair Francis
2020-07-14 0:32 ` [PULL 01/15] MAINTAINERS: Add an entry for OpenSBI firmware Alistair Francis
` (16 more replies)
0 siblings, 17 replies; 32+ messages in thread
From: Alistair Francis @ 2020-07-14 0:32 UTC (permalink / raw)
To: qemu-devel; +Cc: Alistair Francis
The following changes since commit 20c1df5476e1e9b5d3f5b94f9f3ce01d21f14c46:
Merge remote-tracking branch 'remotes/kraxel/tags/fixes-20200713-pull-request' into staging (2020-07-13 16:58:44 +0100)
are available in the Git repository at:
git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20200713
for you to fetch changes up to cfad709bceb629a4ebeb5d8a3acd1871b9a6436b:
target/riscv: Fix pmp NA4 implementation (2020-07-13 17:25:37 -0700)
----------------------------------------------------------------
This is a colection of bug fixes and small imrprovements for RISC-V.
This includes some vector extensions fixes, a PMP bug fix, OpenTitan
UART bug fix and support for OpenSBI dynamic firmware.
----------------------------------------------------------------
Alexandre Mergnat (1):
target/riscv: Fix pmp NA4 implementation
Alistair Francis (2):
hw/char: Convert the Ibex UART to use the qdev Clock model
hw/char: Convert the Ibex UART to use the registerfields API
Atish Patra (4):
riscv: Unify Qemu's reset vector code path
RISC-V: Copy the fdt in dram instead of ROM
riscv: Add opensbi firmware dynamic support
RISC-V: Support 64 bit start address
Bin Meng (3):
MAINTAINERS: Add an entry for OpenSBI firmware
hw/riscv: virt: Sort the SoC memmap table entries
hw/riscv: Modify MROM size to end at 0x10000
Frank Chang (4):
target/riscv: fix rsub gvec tcg_assert_listed_vecop assertion
target/riscv: correct the gvec IR called in gen_vec_rsub16_i64()
target/riscv: fix return value of do_opivx_widen()
target/riscv: fix vill bit index in vtype register
Liao Pingfang (1):
tcg/riscv: Remove superfluous breaks
include/hw/char/ibex_uart.h | 79 ++++++++--------
include/hw/riscv/boot.h | 7 ++
include/hw/riscv/boot_opensbi.h | 58 ++++++++++++
target/riscv/cpu.h | 2 +-
hw/char/ibex_uart.c | 158 ++++++++++++++++++--------------
hw/riscv/boot.c | 107 +++++++++++++++++++++
hw/riscv/sifive_u.c | 53 ++++++-----
hw/riscv/spike.c | 59 ++++--------
hw/riscv/virt.c | 63 ++++---------
target/riscv/insn_trans/trans_rvv.inc.c | 9 +-
target/riscv/pmp.c | 2 +-
tcg/riscv/tcg-target.inc.c | 2 -
MAINTAINERS | 7 ++
13 files changed, 387 insertions(+), 219 deletions(-)
create mode 100644 include/hw/riscv/boot_opensbi.h
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PULL 01/15] MAINTAINERS: Add an entry for OpenSBI firmware
2020-07-14 0:32 [PULL 00/15] riscv-to-apply queue Alistair Francis
@ 2020-07-14 0:32 ` Alistair Francis
2020-07-14 0:32 ` [PULL 02/15] hw/riscv: virt: Sort the SoC memmap table entries Alistair Francis
` (15 subsequent siblings)
16 siblings, 0 replies; 32+ messages in thread
From: Alistair Francis @ 2020-07-14 0:32 UTC (permalink / raw)
To: qemu-devel; +Cc: Alistair Francis, Bin Meng, Philippe Mathieu-Daudé
From: Bin Meng <bmeng.cn@gmail.com>
List me as the maintainer for OpenSBI firmware related files.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <1593177220-28143-1-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
MAINTAINERS | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index fe8139f367..80fa8837e9 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2681,6 +2681,13 @@ F: hw/i386/intel_iommu.c
F: hw/i386/intel_iommu_internal.h
F: include/hw/i386/intel_iommu.h
+OpenSBI Firmware
+M: Bin Meng <bmeng.cn@gmail.com>
+S: Supported
+F: pc-bios/opensbi-*
+F: .gitlab-ci.d/opensbi.yml
+F: .gitlab-ci.d/opensbi/
+
Usermode Emulation
------------------
Overall usermode emulation
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PULL 02/15] hw/riscv: virt: Sort the SoC memmap table entries
2020-07-14 0:32 [PULL 00/15] riscv-to-apply queue Alistair Francis
2020-07-14 0:32 ` [PULL 01/15] MAINTAINERS: Add an entry for OpenSBI firmware Alistair Francis
@ 2020-07-14 0:32 ` Alistair Francis
2020-07-14 0:32 ` [PULL 03/15] riscv: Unify Qemu's reset vector code path Alistair Francis
` (14 subsequent siblings)
16 siblings, 0 replies; 32+ messages in thread
From: Alistair Francis @ 2020-07-14 0:32 UTC (permalink / raw)
To: qemu-devel; +Cc: Bin Meng, Alistair Francis
From: Bin Meng <bin.meng@windriver.com>
Adjust the PCIe memory maps to follow the order.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1593746511-19517-1-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/virt.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index f7630c8a89..18283e262e 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -60,14 +60,14 @@ static const struct MemmapEntry {
[VIRT_TEST] = { 0x100000, 0x1000 },
[VIRT_RTC] = { 0x101000, 0x1000 },
[VIRT_CLINT] = { 0x2000000, 0x10000 },
+ [VIRT_PCIE_PIO] = { 0x3000000, 0x10000 },
[VIRT_PLIC] = { 0xc000000, 0x4000000 },
[VIRT_UART0] = { 0x10000000, 0x100 },
[VIRT_VIRTIO] = { 0x10001000, 0x1000 },
[VIRT_FLASH] = { 0x20000000, 0x4000000 },
- [VIRT_DRAM] = { 0x80000000, 0x0 },
- [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 },
- [VIRT_PCIE_PIO] = { 0x03000000, 0x00010000 },
[VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 },
+ [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 },
+ [VIRT_DRAM] = { 0x80000000, 0x0 },
};
#define VIRT_FLASH_SECTOR_SIZE (256 * KiB)
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PULL 03/15] riscv: Unify Qemu's reset vector code path
2020-07-14 0:32 [PULL 00/15] riscv-to-apply queue Alistair Francis
2020-07-14 0:32 ` [PULL 01/15] MAINTAINERS: Add an entry for OpenSBI firmware Alistair Francis
2020-07-14 0:32 ` [PULL 02/15] hw/riscv: virt: Sort the SoC memmap table entries Alistair Francis
@ 2020-07-14 0:32 ` Alistair Francis
2020-07-14 0:32 ` [PULL 04/15] RISC-V: Copy the fdt in dram instead of ROM Alistair Francis
` (13 subsequent siblings)
16 siblings, 0 replies; 32+ messages in thread
From: Alistair Francis @ 2020-07-14 0:32 UTC (permalink / raw)
To: qemu-devel; +Cc: Atish Patra, Bin Meng, Alistair Francis
From: Atish Patra <atish.patra@wdc.com>
Currently, all riscv machines except sifive_u have identical reset vector
code implementations with memory addresses being different for all machines.
They can be easily combined into a single function in common code.
Move it to common function and let all the machines use the common function.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Message-Id: <20200701183949.398134-2-atish.patra@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/riscv/boot.h | 2 ++
hw/riscv/boot.c | 46 +++++++++++++++++++++++++++++++++++++++++
hw/riscv/sifive_u.c | 1 -
hw/riscv/spike.c | 41 +++---------------------------------
hw/riscv/virt.c | 40 +++--------------------------------
5 files changed, 54 insertions(+), 76 deletions(-)
diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
index 9daa98da08..3e9759c89a 100644
--- a/include/hw/riscv/boot.h
+++ b/include/hw/riscv/boot.h
@@ -35,5 +35,7 @@ target_ulong riscv_load_kernel(const char *kernel_filename,
symbol_fn_t sym_cb);
hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size,
uint64_t kernel_entry, hwaddr *start);
+void riscv_setup_rom_reset_vec(hwaddr saddr, hwaddr rom_base,
+ hwaddr rom_size, void *fdt);
#endif /* RISCV_BOOT_H */
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index adb421b91b..3df802380a 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -26,8 +26,11 @@
#include "hw/loader.h"
#include "hw/riscv/boot.h"
#include "elf.h"
+#include "sysemu/device_tree.h"
#include "sysemu/qtest.h"
+#include <libfdt.h>
+
#if defined(TARGET_RISCV32)
# define KERNEL_BOOT_ADDRESS 0x80400000
#else
@@ -155,3 +158,46 @@ hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size,
return *start + size;
}
+
+void riscv_setup_rom_reset_vec(hwaddr start_addr, hwaddr rom_base,
+ hwaddr rom_size, void *fdt)
+{
+ int i;
+
+ /* reset vector */
+ uint32_t reset_vec[8] = {
+ 0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */
+ 0x02028593, /* addi a1, t0, %pcrel_lo(1b) */
+ 0xf1402573, /* csrr a0, mhartid */
+#if defined(TARGET_RISCV32)
+ 0x0182a283, /* lw t0, 24(t0) */
+#elif defined(TARGET_RISCV64)
+ 0x0182b283, /* ld t0, 24(t0) */
+#endif
+ 0x00028067, /* jr t0 */
+ 0x00000000,
+ start_addr, /* start: .dword */
+ 0x00000000,
+ /* dtb: */
+ };
+
+ /* copy in the reset vector in little_endian byte order */
+ for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
+ reset_vec[i] = cpu_to_le32(reset_vec[i]);
+ }
+ rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
+ rom_base, &address_space_memory);
+
+ /* copy in the device tree */
+ if (fdt_pack(fdt) || fdt_totalsize(fdt) >
+ rom_size - sizeof(reset_vec)) {
+ error_report("not enough space to store device-tree");
+ exit(1);
+ }
+ qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
+ rom_add_blob_fixed_as("mrom.fdt", fdt, fdt_totalsize(fdt),
+ rom_base + sizeof(reset_vec),
+ &address_space_memory);
+
+ return;
+}
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 7851326988..0695c93d2c 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -56,7 +56,6 @@
#include "sysemu/device_tree.h"
#include "sysemu/runstate.h"
#include "sysemu/sysemu.h"
-#include "exec/address-spaces.h"
#include <libfdt.h>
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index c107bf3ba1..a8a0588824 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -41,9 +41,6 @@
#include "sysemu/device_tree.h"
#include "sysemu/qtest.h"
#include "sysemu/sysemu.h"
-#include "exec/address-spaces.h"
-
-#include <libfdt.h>
#if defined(TARGET_RISCV32)
# define BIOS_FILENAME "opensbi-riscv32-spike-fw_jump.elf"
@@ -165,7 +162,6 @@ static void spike_board_init(MachineState *machine)
MemoryRegion *system_memory = get_system_memory();
MemoryRegion *main_mem = g_new(MemoryRegion, 1);
MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
- int i;
unsigned int smp_cpus = machine->smp.cpus;
/* Initialize SOC */
@@ -212,40 +208,9 @@ static void spike_board_init(MachineState *machine)
}
}
- /* reset vector */
- uint32_t reset_vec[8] = {
- 0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */
- 0x02028593, /* addi a1, t0, %pcrel_lo(1b) */
- 0xf1402573, /* csrr a0, mhartid */
-#if defined(TARGET_RISCV32)
- 0x0182a283, /* lw t0, 24(t0) */
-#elif defined(TARGET_RISCV64)
- 0x0182b283, /* ld t0, 24(t0) */
-#endif
- 0x00028067, /* jr t0 */
- 0x00000000,
- memmap[SPIKE_DRAM].base, /* start: .dword DRAM_BASE */
- 0x00000000,
- /* dtb: */
- };
-
- /* copy in the reset vector in little_endian byte order */
- for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
- reset_vec[i] = cpu_to_le32(reset_vec[i]);
- }
- rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
- memmap[SPIKE_MROM].base, &address_space_memory);
-
- /* copy in the device tree */
- if (fdt_pack(s->fdt) || fdt_totalsize(s->fdt) >
- memmap[SPIKE_MROM].size - sizeof(reset_vec)) {
- error_report("not enough space to store device-tree");
- exit(1);
- }
- qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt));
- rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt),
- memmap[SPIKE_MROM].base + sizeof(reset_vec),
- &address_space_memory);
+ /* load the reset vector */
+ riscv_setup_rom_reset_vec(memmap[SPIKE_DRAM].base, memmap[SPIKE_MROM].base,
+ memmap[SPIKE_MROM].size, s->fdt);
/* initialize HTIF using symbols found in load_kernel */
htif_mm_init(system_memory, mask_rom, &s->soc.harts[0].env, serial_hd(0));
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 18283e262e..3463cf54aa 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -39,12 +39,9 @@
#include "sysemu/arch_init.h"
#include "sysemu/device_tree.h"
#include "sysemu/sysemu.h"
-#include "exec/address-spaces.h"
#include "hw/pci/pci.h"
#include "hw/pci-host/gpex.h"
-#include <libfdt.h>
-
#if defined(TARGET_RISCV32)
# define BIOS_FILENAME "opensbi-riscv32-virt-fw_jump.bin"
#else
@@ -535,40 +532,9 @@ static void virt_machine_init(MachineState *machine)
start_addr = virt_memmap[VIRT_FLASH].base;
}
- /* reset vector */
- uint32_t reset_vec[8] = {
- 0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */
- 0x02028593, /* addi a1, t0, %pcrel_lo(1b) */
- 0xf1402573, /* csrr a0, mhartid */
-#if defined(TARGET_RISCV32)
- 0x0182a283, /* lw t0, 24(t0) */
-#elif defined(TARGET_RISCV64)
- 0x0182b283, /* ld t0, 24(t0) */
-#endif
- 0x00028067, /* jr t0 */
- 0x00000000,
- start_addr, /* start: .dword */
- 0x00000000,
- /* dtb: */
- };
-
- /* copy in the reset vector in little_endian byte order */
- for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
- reset_vec[i] = cpu_to_le32(reset_vec[i]);
- }
- rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
- memmap[VIRT_MROM].base, &address_space_memory);
-
- /* copy in the device tree */
- if (fdt_pack(s->fdt) || fdt_totalsize(s->fdt) >
- memmap[VIRT_MROM].size - sizeof(reset_vec)) {
- error_report("not enough space to store device-tree");
- exit(1);
- }
- qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt));
- rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt),
- memmap[VIRT_MROM].base + sizeof(reset_vec),
- &address_space_memory);
+ /* load the reset vector */
+ riscv_setup_rom_reset_vec(start_addr, virt_memmap[VIRT_MROM].base,
+ virt_memmap[VIRT_MROM].size, s->fdt);
/* create PLIC hart topology configuration string */
plic_hart_config_len = (strlen(VIRT_PLIC_HART_CONFIG) + 1) * smp_cpus;
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PULL 04/15] RISC-V: Copy the fdt in dram instead of ROM
2020-07-14 0:32 [PULL 00/15] riscv-to-apply queue Alistair Francis
` (2 preceding siblings ...)
2020-07-14 0:32 ` [PULL 03/15] riscv: Unify Qemu's reset vector code path Alistair Francis
@ 2020-07-14 0:32 ` Alistair Francis
2021-07-13 10:43 ` Peter Maydell
2020-07-14 0:32 ` [PULL 05/15] riscv: Add opensbi firmware dynamic support Alistair Francis
` (12 subsequent siblings)
16 siblings, 1 reply; 32+ messages in thread
From: Alistair Francis @ 2020-07-14 0:32 UTC (permalink / raw)
To: qemu-devel; +Cc: Atish Patra, Bin Meng, Alistair Francis
From: Atish Patra <atish.patra@wdc.com>
Currently, the fdt is copied to the ROM after the reset vector. The firmware
has to copy it to DRAM. Instead of this, directly copy the device tree to a
pre-computed dram address. The device tree load address should be as far as
possible from kernel and initrd images. That's why it is kept at the end of
the DRAM or 4GB whichever is lesser.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Message-Id: <20200701183949.398134-3-atish.patra@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/riscv/boot.h | 4 +++-
hw/riscv/boot.c | 53 +++++++++++++++++++++++++++++------------
hw/riscv/sifive_u.c | 28 ++++++++++------------
hw/riscv/spike.c | 7 +++++-
hw/riscv/virt.c | 7 +++++-
5 files changed, 66 insertions(+), 33 deletions(-)
diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
index 3e9759c89a..35b6ddf710 100644
--- a/include/hw/riscv/boot.h
+++ b/include/hw/riscv/boot.h
@@ -35,7 +35,9 @@ target_ulong riscv_load_kernel(const char *kernel_filename,
symbol_fn_t sym_cb);
hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size,
uint64_t kernel_entry, hwaddr *start);
+uint32_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt);
void riscv_setup_rom_reset_vec(hwaddr saddr, hwaddr rom_base,
- hwaddr rom_size, void *fdt);
+ hwaddr rom_size,
+ uint32_t fdt_load_addr, void *fdt);
#endif /* RISCV_BOOT_H */
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index 3df802380a..c62f545f15 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -159,45 +159,68 @@ hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size,
return *start + size;
}
+uint32_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt)
+{
+ uint32_t temp, fdt_addr;
+ hwaddr dram_end = dram_base + mem_size;
+ int fdtsize = fdt_totalsize(fdt);
+
+ if (fdtsize <= 0) {
+ error_report("invalid device-tree");
+ exit(1);
+ }
+
+ /*
+ * We should put fdt as far as possible to avoid kernel/initrd overwriting
+ * its content. But it should be addressable by 32 bit system as well.
+ * Thus, put it at an aligned address that less than fdt size from end of
+ * dram or 4GB whichever is lesser.
+ */
+ temp = MIN(dram_end, 4096 * MiB);
+ fdt_addr = QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB);
+
+ fdt_pack(fdt);
+ /* copy in the device tree */
+ qemu_fdt_dumpdtb(fdt, fdtsize);
+
+ rom_add_blob_fixed_as("fdt", fdt, fdtsize, fdt_addr,
+ &address_space_memory);
+
+ return fdt_addr;
+}
+
void riscv_setup_rom_reset_vec(hwaddr start_addr, hwaddr rom_base,
- hwaddr rom_size, void *fdt)
+ hwaddr rom_size,
+ uint32_t fdt_load_addr, void *fdt)
{
int i;
/* reset vector */
- uint32_t reset_vec[8] = {
+ uint32_t reset_vec[10] = {
0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */
- 0x02028593, /* addi a1, t0, %pcrel_lo(1b) */
0xf1402573, /* csrr a0, mhartid */
#if defined(TARGET_RISCV32)
+ 0x0202a583, /* lw a1, 32(t0) */
0x0182a283, /* lw t0, 24(t0) */
#elif defined(TARGET_RISCV64)
+ 0x0202b583, /* ld a1, 32(t0) */
0x0182b283, /* ld t0, 24(t0) */
#endif
0x00028067, /* jr t0 */
0x00000000,
start_addr, /* start: .dword */
+ 0x00000000,
+ fdt_load_addr, /* fdt_laddr: .dword */
0x00000000,
/* dtb: */
};
/* copy in the reset vector in little_endian byte order */
- for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
+ for (i = 0; i < ARRAY_SIZE(reset_vec); i++) {
reset_vec[i] = cpu_to_le32(reset_vec[i]);
}
rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
rom_base, &address_space_memory);
- /* copy in the device tree */
- if (fdt_pack(fdt) || fdt_totalsize(fdt) >
- rom_size - sizeof(reset_vec)) {
- error_report("not enough space to store device-tree");
- exit(1);
- }
- qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
- rom_add_blob_fixed_as("mrom.fdt", fdt, fdt_totalsize(fdt),
- rom_base + sizeof(reset_vec),
- &address_space_memory);
-
return;
}
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 0695c93d2c..39923209f4 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -379,6 +379,7 @@ static void sifive_u_machine_init(MachineState *machine)
MemoryRegion *flash0 = g_new(MemoryRegion, 1);
target_ulong start_addr = memmap[SIFIVE_U_DRAM].base;
int i;
+ uint32_t fdt_load_addr;
/* Initialize SoC */
object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_U_SOC);
@@ -450,40 +451,37 @@ static void sifive_u_machine_init(MachineState *machine)
}
}
+ /* Compute the fdt load address in dram */
+ fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DRAM].base,
+ machine->ram_size, s->fdt);
+
/* reset vector */
- uint32_t reset_vec[8] = {
+ uint32_t reset_vec[11] = {
s->msel, /* MSEL pin state */
0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */
- 0x01c28593, /* addi a1, t0, %pcrel_lo(1b) */
0xf1402573, /* csrr a0, mhartid */
#if defined(TARGET_RISCV32)
+ 0x0202a583, /* lw a1, 32(t0) */
0x0182a283, /* lw t0, 24(t0) */
#elif defined(TARGET_RISCV64)
- 0x0182e283, /* lwu t0, 24(t0) */
+ 0x0202b583, /* ld a1, 32(t0) */
+ 0x0182b283, /* ld t0, 24(t0) */
#endif
0x00028067, /* jr t0 */
0x00000000,
start_addr, /* start: .dword */
+ 0x00000000,
+ fdt_load_addr, /* fdt_laddr: .dword */
+ 0x00000000,
/* dtb: */
};
/* copy in the reset vector in little_endian byte order */
- for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
+ for (i = 0; i < ARRAY_SIZE(reset_vec); i++) {
reset_vec[i] = cpu_to_le32(reset_vec[i]);
}
rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
memmap[SIFIVE_U_MROM].base, &address_space_memory);
-
- /* copy in the device tree */
- if (fdt_pack(s->fdt) || fdt_totalsize(s->fdt) >
- memmap[SIFIVE_U_MROM].size - sizeof(reset_vec)) {
- error_report("not enough space to store device-tree");
- exit(1);
- }
- qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt));
- rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt),
- memmap[SIFIVE_U_MROM].base + sizeof(reset_vec),
- &address_space_memory);
}
static bool sifive_u_machine_get_start_in_flash(Object *obj, Error **errp)
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index a8a0588824..13fa0455e3 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -163,6 +163,7 @@ static void spike_board_init(MachineState *machine)
MemoryRegion *main_mem = g_new(MemoryRegion, 1);
MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
unsigned int smp_cpus = machine->smp.cpus;
+ uint32_t fdt_load_addr;
/* Initialize SOC */
object_initialize_child(OBJECT(machine), "soc", &s->soc,
@@ -208,9 +209,13 @@ static void spike_board_init(MachineState *machine)
}
}
+ /* Compute the fdt load address in dram */
+ fdt_load_addr = riscv_load_fdt(memmap[SPIKE_DRAM].base,
+ machine->ram_size, s->fdt);
/* load the reset vector */
riscv_setup_rom_reset_vec(memmap[SPIKE_DRAM].base, memmap[SPIKE_MROM].base,
- memmap[SPIKE_MROM].size, s->fdt);
+ memmap[SPIKE_MROM].size,
+ fdt_load_addr, s->fdt);
/* initialize HTIF using symbols found in load_kernel */
htif_mm_init(system_memory, mask_rom, &s->soc.harts[0].env, serial_hd(0));
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 3463cf54aa..9d87319f70 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -478,6 +478,7 @@ static void virt_machine_init(MachineState *machine)
char *plic_hart_config;
size_t plic_hart_config_len;
target_ulong start_addr = memmap[VIRT_DRAM].base;
+ uint32_t fdt_load_addr;
int i;
unsigned int smp_cpus = machine->smp.cpus;
@@ -532,9 +533,13 @@ static void virt_machine_init(MachineState *machine)
start_addr = virt_memmap[VIRT_FLASH].base;
}
+ /* Compute the fdt load address in dram */
+ fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base,
+ machine->ram_size, s->fdt);
/* load the reset vector */
riscv_setup_rom_reset_vec(start_addr, virt_memmap[VIRT_MROM].base,
- virt_memmap[VIRT_MROM].size, s->fdt);
+ virt_memmap[VIRT_MROM].size,
+ fdt_load_addr, s->fdt);
/* create PLIC hart topology configuration string */
plic_hart_config_len = (strlen(VIRT_PLIC_HART_CONFIG) + 1) * smp_cpus;
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PULL 05/15] riscv: Add opensbi firmware dynamic support
2020-07-14 0:32 [PULL 00/15] riscv-to-apply queue Alistair Francis
` (3 preceding siblings ...)
2020-07-14 0:32 ` [PULL 04/15] RISC-V: Copy the fdt in dram instead of ROM Alistair Francis
@ 2020-07-14 0:32 ` Alistair Francis
2020-07-14 0:32 ` [PULL 06/15] RISC-V: Support 64 bit start address Alistair Francis
` (11 subsequent siblings)
16 siblings, 0 replies; 32+ messages in thread
From: Alistair Francis @ 2020-07-14 0:32 UTC (permalink / raw)
To: qemu-devel; +Cc: Atish Patra, Bin Meng, Alistair Francis
From: Atish Patra <atish.patra@wdc.com>
OpenSBI is the default firmware in Qemu and has various firmware loading
options. Currently, qemu loader uses fw_jump which has a compile time
pre-defined address where fdt & kernel image must reside. This puts a
constraint on image size of the Linux kernel depending on the fdt location
and available memory. However, fw_dynamic allows the loader to specify
the next stage location (i.e. Linux kernel/U-Boot) in memory and other
configurable boot options available in OpenSBI.
Add support for OpenSBI dynamic firmware loading support. This doesn't
break existing setup and fw_jump will continue to work as it is. Any
other firmware will continue to work without any issues as long as it
doesn't expect anything specific from loader in "a2" register.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Message-Id: <20200701183949.398134-4-atish.patra@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/riscv/boot.h | 5 ++-
include/hw/riscv/boot_opensbi.h | 58 +++++++++++++++++++++++++++++++++
hw/riscv/boot.c | 42 +++++++++++++++++++++---
hw/riscv/sifive_u.c | 20 +++++++++---
hw/riscv/spike.c | 13 ++++++--
hw/riscv/virt.c | 12 +++++--
6 files changed, 134 insertions(+), 16 deletions(-)
create mode 100644 include/hw/riscv/boot_opensbi.h
diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
index 35b6ddf710..451338780a 100644
--- a/include/hw/riscv/boot.h
+++ b/include/hw/riscv/boot.h
@@ -37,7 +37,10 @@ hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size,
uint64_t kernel_entry, hwaddr *start);
uint32_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt);
void riscv_setup_rom_reset_vec(hwaddr saddr, hwaddr rom_base,
- hwaddr rom_size,
+ hwaddr rom_size, uint64_t kernel_entry,
uint32_t fdt_load_addr, void *fdt);
+void riscv_rom_copy_firmware_info(hwaddr rom_base, hwaddr rom_size,
+ uint32_t reset_vec_size,
+ uint64_t kernel_entry);
#endif /* RISCV_BOOT_H */
diff --git a/include/hw/riscv/boot_opensbi.h b/include/hw/riscv/boot_opensbi.h
new file mode 100644
index 0000000000..0d5ddd6c3d
--- /dev/null
+++ b/include/hw/riscv/boot_opensbi.h
@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+/*
+ * Copyright (c) 2019 Western Digital Corporation or its affiliates.
+ *
+ * Based on include/sbi/{fw_dynamic.h,sbi_scratch.h} from the OpenSBI project.
+ */
+#ifndef OPENSBI_H
+#define OPENSBI_H
+
+/** Expected value of info magic ('OSBI' ascii string in hex) */
+#define FW_DYNAMIC_INFO_MAGIC_VALUE 0x4942534f
+
+/** Maximum supported info version */
+#define FW_DYNAMIC_INFO_VERSION 0x2
+
+/** Possible next mode values */
+#define FW_DYNAMIC_INFO_NEXT_MODE_U 0x0
+#define FW_DYNAMIC_INFO_NEXT_MODE_S 0x1
+#define FW_DYNAMIC_INFO_NEXT_MODE_M 0x3
+
+enum sbi_scratch_options {
+ /** Disable prints during boot */
+ SBI_SCRATCH_NO_BOOT_PRINTS = (1 << 0),
+ /** Enable runtime debug prints */
+ SBI_SCRATCH_DEBUG_PRINTS = (1 << 1),
+};
+
+/** Representation dynamic info passed by previous booting stage */
+struct fw_dynamic_info {
+ /** Info magic */
+ target_long magic;
+ /** Info version */
+ target_long version;
+ /** Next booting stage address */
+ target_long next_addr;
+ /** Next booting stage mode */
+ target_long next_mode;
+ /** Options for OpenSBI library */
+ target_long options;
+ /**
+ * Preferred boot HART id
+ *
+ * It is possible that the previous booting stage uses same link
+ * address as the FW_DYNAMIC firmware. In this case, the relocation
+ * lottery mechanism can potentially overwrite the previous booting
+ * stage while other HARTs are still running in the previous booting
+ * stage leading to boot-time crash. To avoid this boot-time crash,
+ * the previous booting stage can specify last HART that will jump
+ * to the FW_DYNAMIC firmware as the preferred boot HART.
+ *
+ * To avoid specifying a preferred boot HART, the previous booting
+ * stage can set it to -1UL which will force the FW_DYNAMIC firmware
+ * to use the relocation lottery mechanism.
+ */
+ target_long boot_hart;
+};
+
+#endif
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index c62f545f15..feff6e3f4e 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -25,6 +25,7 @@
#include "hw/boards.h"
#include "hw/loader.h"
#include "hw/riscv/boot.h"
+#include "hw/riscv/boot_opensbi.h"
#include "elf.h"
#include "sysemu/device_tree.h"
#include "sysemu/qtest.h"
@@ -33,8 +34,10 @@
#if defined(TARGET_RISCV32)
# define KERNEL_BOOT_ADDRESS 0x80400000
+#define fw_dynamic_info_data(__val) cpu_to_le32(__val)
#else
# define KERNEL_BOOT_ADDRESS 0x80200000
+#define fw_dynamic_info_data(__val) cpu_to_le64(__val)
#endif
void riscv_find_and_load_firmware(MachineState *machine,
@@ -189,15 +192,45 @@ uint32_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt)
return fdt_addr;
}
+void riscv_rom_copy_firmware_info(hwaddr rom_base, hwaddr rom_size,
+ uint32_t reset_vec_size, uint64_t kernel_entry)
+{
+ struct fw_dynamic_info dinfo;
+ size_t dinfo_len;
+
+ dinfo.magic = fw_dynamic_info_data(FW_DYNAMIC_INFO_MAGIC_VALUE);
+ dinfo.version = fw_dynamic_info_data(FW_DYNAMIC_INFO_VERSION);
+ dinfo.next_mode = fw_dynamic_info_data(FW_DYNAMIC_INFO_NEXT_MODE_S);
+ dinfo.next_addr = fw_dynamic_info_data(kernel_entry);
+ dinfo.options = 0;
+ dinfo.boot_hart = 0;
+ dinfo_len = sizeof(dinfo);
+
+ /**
+ * copy the dynamic firmware info. This information is specific to
+ * OpenSBI but doesn't break any other firmware as long as they don't
+ * expect any certain value in "a2" register.
+ */
+ if (dinfo_len > (rom_size - reset_vec_size)) {
+ error_report("not enough space to store dynamic firmware info");
+ exit(1);
+ }
+
+ rom_add_blob_fixed_as("mrom.finfo", &dinfo, dinfo_len,
+ rom_base + reset_vec_size,
+ &address_space_memory);
+}
+
void riscv_setup_rom_reset_vec(hwaddr start_addr, hwaddr rom_base,
- hwaddr rom_size,
+ hwaddr rom_size, uint64_t kernel_entry,
uint32_t fdt_load_addr, void *fdt)
{
int i;
/* reset vector */
uint32_t reset_vec[10] = {
- 0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */
+ 0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn) */
+ 0x02828613, /* addi a2, t0, %pcrel_lo(1b) */
0xf1402573, /* csrr a0, mhartid */
#if defined(TARGET_RISCV32)
0x0202a583, /* lw a1, 32(t0) */
@@ -207,12 +240,11 @@ void riscv_setup_rom_reset_vec(hwaddr start_addr, hwaddr rom_base,
0x0182b283, /* ld t0, 24(t0) */
#endif
0x00028067, /* jr t0 */
- 0x00000000,
start_addr, /* start: .dword */
0x00000000,
fdt_load_addr, /* fdt_laddr: .dword */
0x00000000,
- /* dtb: */
+ /* fw_dyn: */
};
/* copy in the reset vector in little_endian byte order */
@@ -221,6 +253,8 @@ void riscv_setup_rom_reset_vec(hwaddr start_addr, hwaddr rom_base,
}
rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
rom_base, &address_space_memory);
+ riscv_rom_copy_firmware_info(rom_base, rom_size, sizeof(reset_vec),
+ kernel_entry);
return;
}
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 39923209f4..46e6ed90ca 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -380,6 +380,7 @@ static void sifive_u_machine_init(MachineState *machine)
target_ulong start_addr = memmap[SIFIVE_U_DRAM].base;
int i;
uint32_t fdt_load_addr;
+ uint64_t kernel_entry;
/* Initialize SoC */
object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_U_SOC);
@@ -436,8 +437,7 @@ static void sifive_u_machine_init(MachineState *machine)
riscv_find_and_load_firmware(machine, BIOS_FILENAME, start_addr, NULL);
if (machine->kernel_filename) {
- uint64_t kernel_entry = riscv_load_kernel(machine->kernel_filename,
- NULL);
+ kernel_entry = riscv_load_kernel(machine->kernel_filename, NULL);
if (machine->initrd_filename) {
hwaddr start;
@@ -449,6 +449,12 @@ static void sifive_u_machine_init(MachineState *machine)
qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
end);
}
+ } else {
+ /*
+ * If dynamic firmware is used, it doesn't know where is the next mode
+ * if kernel argument is not set.
+ */
+ kernel_entry = 0;
}
/* Compute the fdt load address in dram */
@@ -458,7 +464,8 @@ static void sifive_u_machine_init(MachineState *machine)
/* reset vector */
uint32_t reset_vec[11] = {
s->msel, /* MSEL pin state */
- 0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */
+ 0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn) */
+ 0x02828613, /* addi a2, t0, %pcrel_lo(1b) */
0xf1402573, /* csrr a0, mhartid */
#if defined(TARGET_RISCV32)
0x0202a583, /* lw a1, 32(t0) */
@@ -468,12 +475,11 @@ static void sifive_u_machine_init(MachineState *machine)
0x0182b283, /* ld t0, 24(t0) */
#endif
0x00028067, /* jr t0 */
- 0x00000000,
start_addr, /* start: .dword */
0x00000000,
fdt_load_addr, /* fdt_laddr: .dword */
0x00000000,
- /* dtb: */
+ /* fw_dyn: */
};
/* copy in the reset vector in little_endian byte order */
@@ -482,6 +488,10 @@ static void sifive_u_machine_init(MachineState *machine)
}
rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
memmap[SIFIVE_U_MROM].base, &address_space_memory);
+
+ riscv_rom_copy_firmware_info(memmap[SIFIVE_U_MROM].base,
+ memmap[SIFIVE_U_MROM].size,
+ sizeof(reset_vec), kernel_entry);
}
static bool sifive_u_machine_get_start_in_flash(Object *obj, Error **errp)
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index 13fa0455e3..b17d96aec7 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -164,6 +164,7 @@ static void spike_board_init(MachineState *machine)
MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
unsigned int smp_cpus = machine->smp.cpus;
uint32_t fdt_load_addr;
+ uint64_t kernel_entry;
/* Initialize SOC */
object_initialize_child(OBJECT(machine), "soc", &s->soc,
@@ -194,8 +195,8 @@ static void spike_board_init(MachineState *machine)
htif_symbol_callback);
if (machine->kernel_filename) {
- uint64_t kernel_entry = riscv_load_kernel(machine->kernel_filename,
- htif_symbol_callback);
+ kernel_entry = riscv_load_kernel(machine->kernel_filename,
+ htif_symbol_callback);
if (machine->initrd_filename) {
hwaddr start;
@@ -207,6 +208,12 @@ static void spike_board_init(MachineState *machine)
qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
end);
}
+ } else {
+ /*
+ * If dynamic firmware is used, it doesn't know where is the next mode
+ * if kernel argument is not set.
+ */
+ kernel_entry = 0;
}
/* Compute the fdt load address in dram */
@@ -214,7 +221,7 @@ static void spike_board_init(MachineState *machine)
machine->ram_size, s->fdt);
/* load the reset vector */
riscv_setup_rom_reset_vec(memmap[SPIKE_DRAM].base, memmap[SPIKE_MROM].base,
- memmap[SPIKE_MROM].size,
+ memmap[SPIKE_MROM].size, kernel_entry,
fdt_load_addr, s->fdt);
/* initialize HTIF using symbols found in load_kernel */
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 9d87319f70..bc25ec69f7 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -479,6 +479,7 @@ static void virt_machine_init(MachineState *machine)
size_t plic_hart_config_len;
target_ulong start_addr = memmap[VIRT_DRAM].base;
uint32_t fdt_load_addr;
+ uint64_t kernel_entry;
int i;
unsigned int smp_cpus = machine->smp.cpus;
@@ -510,8 +511,7 @@ static void virt_machine_init(MachineState *machine)
memmap[VIRT_DRAM].base, NULL);
if (machine->kernel_filename) {
- uint64_t kernel_entry = riscv_load_kernel(machine->kernel_filename,
- NULL);
+ kernel_entry = riscv_load_kernel(machine->kernel_filename, NULL);
if (machine->initrd_filename) {
hwaddr start;
@@ -523,6 +523,12 @@ static void virt_machine_init(MachineState *machine)
qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
end);
}
+ } else {
+ /*
+ * If dynamic firmware is used, it doesn't know where is the next mode
+ * if kernel argument is not set.
+ */
+ kernel_entry = 0;
}
if (drive_get(IF_PFLASH, 0, 0)) {
@@ -538,7 +544,7 @@ static void virt_machine_init(MachineState *machine)
machine->ram_size, s->fdt);
/* load the reset vector */
riscv_setup_rom_reset_vec(start_addr, virt_memmap[VIRT_MROM].base,
- virt_memmap[VIRT_MROM].size,
+ virt_memmap[VIRT_MROM].size, kernel_entry,
fdt_load_addr, s->fdt);
/* create PLIC hart topology configuration string */
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PULL 06/15] RISC-V: Support 64 bit start address
2020-07-14 0:32 [PULL 00/15] riscv-to-apply queue Alistair Francis
` (4 preceding siblings ...)
2020-07-14 0:32 ` [PULL 05/15] riscv: Add opensbi firmware dynamic support Alistair Francis
@ 2020-07-14 0:32 ` Alistair Francis
2020-07-14 0:32 ` [PULL 07/15] hw/riscv: Modify MROM size to end at 0x10000 Alistair Francis
` (10 subsequent siblings)
16 siblings, 0 replies; 32+ messages in thread
From: Alistair Francis @ 2020-07-14 0:32 UTC (permalink / raw)
To: qemu-devel; +Cc: Atish Patra, Bin Meng, Alistair Francis
From: Atish Patra <atish.patra@wdc.com>
Even though the start address in ROM code is declared as a 64 bit address
for RV64, it can't be used as upper bits are set to zero in ROM code.
Update the ROM code correctly to reflect the 64bit value.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Message-Id: <20200701183949.398134-5-atish.patra@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/boot.c | 6 +++++-
hw/riscv/sifive_u.c | 6 +++++-
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index feff6e3f4e..4c6c101ff1 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -226,7 +226,11 @@ void riscv_setup_rom_reset_vec(hwaddr start_addr, hwaddr rom_base,
uint32_t fdt_load_addr, void *fdt)
{
int i;
+ uint32_t start_addr_hi32 = 0x00000000;
+ #if defined(TARGET_RISCV64)
+ start_addr_hi32 = start_addr >> 32;
+ #endif
/* reset vector */
uint32_t reset_vec[10] = {
0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn) */
@@ -241,7 +245,7 @@ void riscv_setup_rom_reset_vec(hwaddr start_addr, hwaddr rom_base,
#endif
0x00028067, /* jr t0 */
start_addr, /* start: .dword */
- 0x00000000,
+ start_addr_hi32,
fdt_load_addr, /* fdt_laddr: .dword */
0x00000000,
/* fw_dyn: */
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 46e6ed90ca..6595ab3f87 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -378,6 +378,7 @@ static void sifive_u_machine_init(MachineState *machine)
MemoryRegion *main_mem = g_new(MemoryRegion, 1);
MemoryRegion *flash0 = g_new(MemoryRegion, 1);
target_ulong start_addr = memmap[SIFIVE_U_DRAM].base;
+ uint32_t start_addr_hi32 = 0x00000000;
int i;
uint32_t fdt_load_addr;
uint64_t kernel_entry;
@@ -460,6 +461,9 @@ static void sifive_u_machine_init(MachineState *machine)
/* Compute the fdt load address in dram */
fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DRAM].base,
machine->ram_size, s->fdt);
+ #if defined(TARGET_RISCV64)
+ start_addr_hi32 = start_addr >> 32;
+ #endif
/* reset vector */
uint32_t reset_vec[11] = {
@@ -476,7 +480,7 @@ static void sifive_u_machine_init(MachineState *machine)
#endif
0x00028067, /* jr t0 */
start_addr, /* start: .dword */
- 0x00000000,
+ start_addr_hi32,
fdt_load_addr, /* fdt_laddr: .dword */
0x00000000,
/* fw_dyn: */
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PULL 07/15] hw/riscv: Modify MROM size to end at 0x10000
2020-07-14 0:32 [PULL 00/15] riscv-to-apply queue Alistair Francis
` (5 preceding siblings ...)
2020-07-14 0:32 ` [PULL 06/15] RISC-V: Support 64 bit start address Alistair Francis
@ 2020-07-14 0:32 ` Alistair Francis
2020-07-14 0:32 ` [PULL 08/15] target/riscv: fix rsub gvec tcg_assert_listed_vecop assertion Alistair Francis
` (9 subsequent siblings)
16 siblings, 0 replies; 32+ messages in thread
From: Alistair Francis @ 2020-07-14 0:32 UTC (permalink / raw)
To: qemu-devel; +Cc: Bin Meng, Alistair Francis, Philippe Mathieu-Daudé
From: Bin Meng <bin.meng@windriver.com>
At present the size of Mask ROM for sifive_u / spike / virt machines
is set to 0x11000, which ends at an unusual address. This changes the
size to 0xf000 so that it ends at 0x10000.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <1594289144-24723-1-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/sifive_u.c | 2 +-
hw/riscv/spike.c | 2 +-
hw/riscv/virt.c | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 6595ab3f87..19a976c9a6 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -70,7 +70,7 @@ static const struct MemmapEntry {
hwaddr size;
} sifive_u_memmap[] = {
[SIFIVE_U_DEBUG] = { 0x0, 0x100 },
- [SIFIVE_U_MROM] = { 0x1000, 0x11000 },
+ [SIFIVE_U_MROM] = { 0x1000, 0xf000 },
[SIFIVE_U_CLINT] = { 0x2000000, 0x10000 },
[SIFIVE_U_L2LIM] = { 0x8000000, 0x2000000 },
[SIFIVE_U_PLIC] = { 0xc000000, 0x4000000 },
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index b17d96aec7..7b23a297fc 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -52,7 +52,7 @@ static const struct MemmapEntry {
hwaddr base;
hwaddr size;
} spike_memmap[] = {
- [SPIKE_MROM] = { 0x1000, 0x11000 },
+ [SPIKE_MROM] = { 0x1000, 0xf000 },
[SPIKE_CLINT] = { 0x2000000, 0x10000 },
[SPIKE_DRAM] = { 0x80000000, 0x0 },
};
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index bc25ec69f7..55a907bb35 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -53,7 +53,7 @@ static const struct MemmapEntry {
hwaddr size;
} virt_memmap[] = {
[VIRT_DEBUG] = { 0x0, 0x100 },
- [VIRT_MROM] = { 0x1000, 0x11000 },
+ [VIRT_MROM] = { 0x1000, 0xf000 },
[VIRT_TEST] = { 0x100000, 0x1000 },
[VIRT_RTC] = { 0x101000, 0x1000 },
[VIRT_CLINT] = { 0x2000000, 0x10000 },
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PULL 08/15] target/riscv: fix rsub gvec tcg_assert_listed_vecop assertion
2020-07-14 0:32 [PULL 00/15] riscv-to-apply queue Alistair Francis
` (6 preceding siblings ...)
2020-07-14 0:32 ` [PULL 07/15] hw/riscv: Modify MROM size to end at 0x10000 Alistair Francis
@ 2020-07-14 0:32 ` Alistair Francis
2020-07-14 0:32 ` [PULL 09/15] target/riscv: correct the gvec IR called in gen_vec_rsub16_i64() Alistair Francis
` (8 subsequent siblings)
16 siblings, 0 replies; 32+ messages in thread
From: Alistair Francis @ 2020-07-14 0:32 UTC (permalink / raw)
To: qemu-devel; +Cc: Frank Chang, Alistair Francis, Richard Henderson
From: Frank Chang <frank.chang@sifive.com>
gvec should provide vecop_list to avoid:
"tcg_tcg_assert_listed_vecop: code should not be reached bug" assertion.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200710104920.13550-2-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn_trans/trans_rvv.inc.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index dc333e6a91..433cdacbe1 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -958,22 +958,27 @@ static void gen_rsub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
static void tcg_gen_gvec_rsubs(unsigned vece, uint32_t dofs, uint32_t aofs,
TCGv_i64 c, uint32_t oprsz, uint32_t maxsz)
{
+ static const TCGOpcode vecop_list[] = { INDEX_op_sub_vec, 0 };
static const GVecGen2s rsub_op[4] = {
{ .fni8 = gen_vec_rsub8_i64,
.fniv = gen_rsub_vec,
.fno = gen_helper_vec_rsubs8,
+ .opt_opc = vecop_list,
.vece = MO_8 },
{ .fni8 = gen_vec_rsub16_i64,
.fniv = gen_rsub_vec,
.fno = gen_helper_vec_rsubs16,
+ .opt_opc = vecop_list,
.vece = MO_16 },
{ .fni4 = gen_rsub_i32,
.fniv = gen_rsub_vec,
.fno = gen_helper_vec_rsubs32,
+ .opt_opc = vecop_list,
.vece = MO_32 },
{ .fni8 = gen_rsub_i64,
.fniv = gen_rsub_vec,
.fno = gen_helper_vec_rsubs64,
+ .opt_opc = vecop_list,
.prefer_i64 = TCG_TARGET_REG_BITS == 64,
.vece = MO_64 },
};
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PULL 09/15] target/riscv: correct the gvec IR called in gen_vec_rsub16_i64()
2020-07-14 0:32 [PULL 00/15] riscv-to-apply queue Alistair Francis
` (7 preceding siblings ...)
2020-07-14 0:32 ` [PULL 08/15] target/riscv: fix rsub gvec tcg_assert_listed_vecop assertion Alistair Francis
@ 2020-07-14 0:32 ` Alistair Francis
2020-07-14 0:32 ` [PULL 10/15] target/riscv: fix return value of do_opivx_widen() Alistair Francis
` (7 subsequent siblings)
16 siblings, 0 replies; 32+ messages in thread
From: Alistair Francis @ 2020-07-14 0:32 UTC (permalink / raw)
To: qemu-devel; +Cc: Frank Chang, Alistair Francis, Richard Henderson
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200710104920.13550-3-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn_trans/trans_rvv.inc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 433cdacbe1..7cd08f0868 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -937,7 +937,7 @@ static void gen_vec_rsub8_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
static void gen_vec_rsub16_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
{
- tcg_gen_vec_sub8_i64(d, b, a);
+ tcg_gen_vec_sub16_i64(d, b, a);
}
static void gen_rsub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PULL 10/15] target/riscv: fix return value of do_opivx_widen()
2020-07-14 0:32 [PULL 00/15] riscv-to-apply queue Alistair Francis
` (8 preceding siblings ...)
2020-07-14 0:32 ` [PULL 09/15] target/riscv: correct the gvec IR called in gen_vec_rsub16_i64() Alistair Francis
@ 2020-07-14 0:32 ` Alistair Francis
2020-07-14 0:32 ` [PULL 11/15] target/riscv: fix vill bit index in vtype register Alistair Francis
` (6 subsequent siblings)
16 siblings, 0 replies; 32+ messages in thread
From: Alistair Francis @ 2020-07-14 0:32 UTC (permalink / raw)
To: qemu-devel; +Cc: Frank Chang, Alistair Francis, Richard Henderson
From: Frank Chang <frank.chang@sifive.com>
do_opivx_widen() should return false if check function returns false.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200710104920.13550-4-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn_trans/trans_rvv.inc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 7cd08f0868..c0b7375927 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -1151,7 +1151,7 @@ static bool do_opivx_widen(DisasContext *s, arg_rmrr *a,
if (opivx_widen_check(s, a)) {
return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s);
}
- return true;
+ return false;
}
#define GEN_OPIVX_WIDEN_TRANS(NAME) \
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PULL 11/15] target/riscv: fix vill bit index in vtype register
2020-07-14 0:32 [PULL 00/15] riscv-to-apply queue Alistair Francis
` (9 preceding siblings ...)
2020-07-14 0:32 ` [PULL 10/15] target/riscv: fix return value of do_opivx_widen() Alistair Francis
@ 2020-07-14 0:32 ` Alistair Francis
2020-07-14 0:32 ` [PULL 12/15] hw/char: Convert the Ibex UART to use the qdev Clock model Alistair Francis
` (5 subsequent siblings)
16 siblings, 0 replies; 32+ messages in thread
From: Alistair Francis @ 2020-07-14 0:32 UTC (permalink / raw)
To: qemu-devel; +Cc: Frank Chang, Alistair Francis, Richard Henderson
From: Frank Chang <frank.chang@sifive.com>
vill bit is at vtype[XLEN-1].
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200710104920.13550-5-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index eef20ca6e5..a804a5d0ba 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -98,7 +98,7 @@ FIELD(VTYPE, VLMUL, 0, 2)
FIELD(VTYPE, VSEW, 2, 3)
FIELD(VTYPE, VEDIV, 5, 2)
FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 9)
-FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 2, 1)
+FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1)
struct CPURISCVState {
target_ulong gpr[32];
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PULL 12/15] hw/char: Convert the Ibex UART to use the qdev Clock model
2020-07-14 0:32 [PULL 00/15] riscv-to-apply queue Alistair Francis
` (10 preceding siblings ...)
2020-07-14 0:32 ` [PULL 11/15] target/riscv: fix vill bit index in vtype register Alistair Francis
@ 2020-07-14 0:32 ` Alistair Francis
2020-07-14 0:32 ` [PULL 13/15] hw/char: Convert the Ibex UART to use the registerfields API Alistair Francis
` (4 subsequent siblings)
16 siblings, 0 replies; 32+ messages in thread
From: Alistair Francis @ 2020-07-14 0:32 UTC (permalink / raw)
To: qemu-devel; +Cc: Alistair Francis, Philippe Mathieu-Daudé
Conver the Ibex UART to use the recently added qdev-clock functions.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: b0136fad870a29049959ec161c1217b967d7e19d.1594332223.git.alistair.francis@wdc.com
Message-Id: <b0136fad870a29049959ec161c1217b967d7e19d.1594332223.git.alistair.francis@wdc.com>
---
include/hw/char/ibex_uart.h | 3 +++
hw/char/ibex_uart.c | 30 +++++++++++++++++++++++++++---
2 files changed, 30 insertions(+), 3 deletions(-)
diff --git a/include/hw/char/ibex_uart.h b/include/hw/char/ibex_uart.h
index 2bec772615..6d81051161 100644
--- a/include/hw/char/ibex_uart.h
+++ b/include/hw/char/ibex_uart.h
@@ -72,6 +72,7 @@
#define IBEX_UART_TIMEOUT_CTRL 0x2c
#define IBEX_UART_TX_FIFO_SIZE 16
+#define IBEX_UART_CLOCK 50000000 /* 50MHz clock */
#define TYPE_IBEX_UART "ibex-uart"
#define IBEX_UART(obj) \
@@ -101,6 +102,8 @@ typedef struct {
uint32_t uart_val;
uint32_t uart_timeout_ctrl;
+ Clock *f_clk;
+
CharBackend chr;
qemu_irq tx_watermark;
qemu_irq rx_watermark;
diff --git a/hw/char/ibex_uart.c b/hw/char/ibex_uart.c
index 45cd724998..ab6247de89 100644
--- a/hw/char/ibex_uart.c
+++ b/hw/char/ibex_uart.c
@@ -28,6 +28,7 @@
#include "qemu/osdep.h"
#include "hw/char/ibex_uart.h"
#include "hw/irq.h"
+#include "hw/qdev-clock.h"
#include "hw/qdev-properties.h"
#include "migration/vmstate.h"
#include "qemu/log.h"
@@ -203,6 +204,17 @@ static void ibex_uart_reset(DeviceState *dev)
ibex_uart_update_irqs(s);
}
+static uint64_t ibex_uart_get_baud(IbexUartState *s)
+{
+ uint64_t baud;
+
+ baud = ((s->uart_ctrl & UART_CTRL_NCO) >> 16);
+ baud *= clock_get_hz(s->f_clk);
+ baud >>= 20;
+
+ return baud;
+}
+
static uint64_t ibex_uart_read(void *opaque, hwaddr addr,
unsigned int size)
{
@@ -329,9 +341,7 @@ static void ibex_uart_write(void *opaque, hwaddr addr,
"%s: UART_CTRL_RXBLVL is not supported\n", __func__);
}
if (value & UART_CTRL_NCO) {
- uint64_t baud = ((value & UART_CTRL_NCO) >> 16);
- baud *= 1000;
- baud >>= 20;
+ uint64_t baud = ibex_uart_get_baud(s);
s->char_tx_time = (NANOSECONDS_PER_SECOND / baud) * 10;
}
@@ -385,6 +395,16 @@ static void ibex_uart_write(void *opaque, hwaddr addr,
}
}
+static void ibex_uart_clk_update(void *opaque)
+{
+ IbexUartState *s = opaque;
+
+ /* recompute uart's speed on clock change */
+ uint64_t baud = ibex_uart_get_baud(s);
+
+ s->char_tx_time = (NANOSECONDS_PER_SECOND / baud) * 10;
+}
+
static void fifo_trigger_update(void *opaque)
{
IbexUartState *s = opaque;
@@ -444,6 +464,10 @@ static void ibex_uart_init(Object *obj)
{
IbexUartState *s = IBEX_UART(obj);
+ s->f_clk = qdev_init_clock_in(DEVICE(obj), "f_clock",
+ ibex_uart_clk_update, s);
+ clock_set_hz(s->f_clk, IBEX_UART_CLOCK);
+
sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->tx_watermark);
sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->rx_watermark);
sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->tx_empty);
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PULL 13/15] hw/char: Convert the Ibex UART to use the registerfields API
2020-07-14 0:32 [PULL 00/15] riscv-to-apply queue Alistair Francis
` (11 preceding siblings ...)
2020-07-14 0:32 ` [PULL 12/15] hw/char: Convert the Ibex UART to use the qdev Clock model Alistair Francis
@ 2020-07-14 0:32 ` Alistair Francis
2020-07-14 0:32 ` [PULL 14/15] tcg/riscv: Remove superfluous breaks Alistair Francis
` (3 subsequent siblings)
16 siblings, 0 replies; 32+ messages in thread
From: Alistair Francis @ 2020-07-14 0:32 UTC (permalink / raw)
To: qemu-devel; +Cc: Alistair Francis
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 06372c9cdeec715077899e71c858d9f0a2a3395b.1594332223.git.alistair.francis@wdc.com
Message-Id: <06372c9cdeec715077899e71c858d9f0a2a3395b.1594332223.git.alistair.francis@wdc.com>
---
include/hw/char/ibex_uart.h | 76 ++++++++++-----------
hw/char/ibex_uart.c | 130 ++++++++++++++++++------------------
2 files changed, 100 insertions(+), 106 deletions(-)
diff --git a/include/hw/char/ibex_uart.h b/include/hw/char/ibex_uart.h
index 6d81051161..b6bd5a6700 100644
--- a/include/hw/char/ibex_uart.h
+++ b/include/hw/char/ibex_uart.h
@@ -26,50 +26,44 @@
#define HW_IBEX_UART_H
#include "hw/sysbus.h"
+#include "hw/registerfields.h"
#include "chardev/char-fe.h"
#include "qemu/timer.h"
-#define IBEX_UART_INTR_STATE 0x00
- #define INTR_STATE_TX_WATERMARK (1 << 0)
- #define INTR_STATE_RX_WATERMARK (1 << 1)
- #define INTR_STATE_TX_EMPTY (1 << 2)
- #define INTR_STATE_RX_OVERFLOW (1 << 3)
-#define IBEX_UART_INTR_ENABLE 0x04
-#define IBEX_UART_INTR_TEST 0x08
-
-#define IBEX_UART_CTRL 0x0c
- #define UART_CTRL_TX_ENABLE (1 << 0)
- #define UART_CTRL_RX_ENABLE (1 << 1)
- #define UART_CTRL_NF (1 << 2)
- #define UART_CTRL_SLPBK (1 << 4)
- #define UART_CTRL_LLPBK (1 << 5)
- #define UART_CTRL_PARITY_EN (1 << 6)
- #define UART_CTRL_PARITY_ODD (1 << 7)
- #define UART_CTRL_RXBLVL (3 << 8)
- #define UART_CTRL_NCO (0xFFFF << 16)
-
-#define IBEX_UART_STATUS 0x10
- #define UART_STATUS_TXFULL (1 << 0)
- #define UART_STATUS_RXFULL (1 << 1)
- #define UART_STATUS_TXEMPTY (1 << 2)
- #define UART_STATUS_RXIDLE (1 << 4)
- #define UART_STATUS_RXEMPTY (1 << 5)
-
-#define IBEX_UART_RDATA 0x14
-#define IBEX_UART_WDATA 0x18
-
-#define IBEX_UART_FIFO_CTRL 0x1c
- #define FIFO_CTRL_RXRST (1 << 0)
- #define FIFO_CTRL_TXRST (1 << 1)
- #define FIFO_CTRL_RXILVL (7 << 2)
- #define FIFO_CTRL_RXILVL_SHIFT (2)
- #define FIFO_CTRL_TXILVL (3 << 5)
- #define FIFO_CTRL_TXILVL_SHIFT (5)
-
-#define IBEX_UART_FIFO_STATUS 0x20
-#define IBEX_UART_OVRD 0x24
-#define IBEX_UART_VAL 0x28
-#define IBEX_UART_TIMEOUT_CTRL 0x2c
+REG32(INTR_STATE, 0x00)
+ FIELD(INTR_STATE, TX_WATERMARK, 0, 1)
+ FIELD(INTR_STATE, RX_WATERMARK, 1, 1)
+ FIELD(INTR_STATE, TX_EMPTY, 2, 1)
+ FIELD(INTR_STATE, RX_OVERFLOW, 3, 1)
+REG32(INTR_ENABLE, 0x04)
+REG32(INTR_TEST, 0x08)
+REG32(CTRL, 0x0C)
+ FIELD(CTRL, TX_ENABLE, 0, 1)
+ FIELD(CTRL, RX_ENABLE, 1, 1)
+ FIELD(CTRL, NF, 2, 1)
+ FIELD(CTRL, SLPBK, 4, 1)
+ FIELD(CTRL, LLPBK, 5, 1)
+ FIELD(CTRL, PARITY_EN, 6, 1)
+ FIELD(CTRL, PARITY_ODD, 7, 1)
+ FIELD(CTRL, RXBLVL, 8, 2)
+ FIELD(CTRL, NCO, 16, 16)
+REG32(STATUS, 0x10)
+ FIELD(STATUS, TXFULL, 0, 1)
+ FIELD(STATUS, RXFULL, 1, 1)
+ FIELD(STATUS, TXEMPTY, 2, 1)
+ FIELD(STATUS, RXIDLE, 4, 1)
+ FIELD(STATUS, RXEMPTY, 5, 1)
+REG32(RDATA, 0x14)
+REG32(WDATA, 0x18)
+REG32(FIFO_CTRL, 0x1c)
+ FIELD(FIFO_CTRL, RXRST, 0, 1)
+ FIELD(FIFO_CTRL, TXRST, 1, 1)
+ FIELD(FIFO_CTRL, RXILVL, 2, 3)
+ FIELD(FIFO_CTRL, TXILVL, 5, 2)
+REG32(FIFO_STATUS, 0x20)
+REG32(OVRD, 0x24)
+REG32(VAL, 0x28)
+REG32(TIMEOUT_CTRL, 0x2c)
#define IBEX_UART_TX_FIFO_SIZE 16
#define IBEX_UART_CLOCK 50000000 /* 50MHz clock */
diff --git a/hw/char/ibex_uart.c b/hw/char/ibex_uart.c
index ab6247de89..cc49a35013 100644
--- a/hw/char/ibex_uart.c
+++ b/hw/char/ibex_uart.c
@@ -36,25 +36,25 @@
static void ibex_uart_update_irqs(IbexUartState *s)
{
- if (s->uart_intr_state & s->uart_intr_enable & INTR_STATE_TX_WATERMARK) {
+ if (s->uart_intr_state & s->uart_intr_enable & R_INTR_STATE_TX_WATERMARK_MASK) {
qemu_set_irq(s->tx_watermark, 1);
} else {
qemu_set_irq(s->tx_watermark, 0);
}
- if (s->uart_intr_state & s->uart_intr_enable & INTR_STATE_RX_WATERMARK) {
+ if (s->uart_intr_state & s->uart_intr_enable & R_INTR_STATE_RX_WATERMARK_MASK) {
qemu_set_irq(s->rx_watermark, 1);
} else {
qemu_set_irq(s->rx_watermark, 0);
}
- if (s->uart_intr_state & s->uart_intr_enable & INTR_STATE_TX_EMPTY) {
+ if (s->uart_intr_state & s->uart_intr_enable & R_INTR_STATE_TX_EMPTY_MASK) {
qemu_set_irq(s->tx_empty, 1);
} else {
qemu_set_irq(s->tx_empty, 0);
}
- if (s->uart_intr_state & s->uart_intr_enable & INTR_STATE_RX_OVERFLOW) {
+ if (s->uart_intr_state & s->uart_intr_enable & R_INTR_STATE_RX_OVERFLOW_MASK) {
qemu_set_irq(s->rx_overflow, 1);
} else {
qemu_set_irq(s->rx_overflow, 0);
@@ -65,7 +65,7 @@ static int ibex_uart_can_receive(void *opaque)
{
IbexUartState *s = opaque;
- if (s->uart_ctrl & UART_CTRL_RX_ENABLE) {
+ if (s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) {
return 1;
}
@@ -75,16 +75,16 @@ static int ibex_uart_can_receive(void *opaque)
static void ibex_uart_receive(void *opaque, const uint8_t *buf, int size)
{
IbexUartState *s = opaque;
- uint8_t rx_fifo_level = (s->uart_fifo_ctrl & FIFO_CTRL_RXILVL)
- >> FIFO_CTRL_RXILVL_SHIFT;
+ uint8_t rx_fifo_level = (s->uart_fifo_ctrl & R_FIFO_CTRL_RXILVL_MASK)
+ >> R_FIFO_CTRL_RXILVL_SHIFT;
s->uart_rdata = *buf;
- s->uart_status &= ~UART_STATUS_RXIDLE;
- s->uart_status &= ~UART_STATUS_RXEMPTY;
+ s->uart_status &= ~R_STATUS_RXIDLE_MASK;
+ s->uart_status &= ~R_STATUS_RXEMPTY_MASK;
if (size > rx_fifo_level) {
- s->uart_intr_state |= INTR_STATE_RX_WATERMARK;
+ s->uart_intr_state |= R_INTR_STATE_RX_WATERMARK_MASK;
}
ibex_uart_update_irqs(s);
@@ -94,8 +94,8 @@ static gboolean ibex_uart_xmit(GIOChannel *chan, GIOCondition cond,
void *opaque)
{
IbexUartState *s = opaque;
- uint8_t tx_fifo_level = (s->uart_fifo_ctrl & FIFO_CTRL_TXILVL)
- >> FIFO_CTRL_TXILVL_SHIFT;
+ uint8_t tx_fifo_level = (s->uart_fifo_ctrl & R_FIFO_CTRL_TXILVL_MASK)
+ >> R_FIFO_CTRL_TXILVL_SHIFT;
int ret;
/* instant drain the fifo when there's no back-end */
@@ -105,10 +105,10 @@ static gboolean ibex_uart_xmit(GIOChannel *chan, GIOCondition cond,
}
if (!s->tx_level) {
- s->uart_status &= ~UART_STATUS_TXFULL;
- s->uart_status |= UART_STATUS_TXEMPTY;
- s->uart_intr_state |= INTR_STATE_TX_EMPTY;
- s->uart_intr_state &= ~INTR_STATE_TX_WATERMARK;
+ s->uart_status &= ~R_STATUS_TXFULL_MASK;
+ s->uart_status |= R_STATUS_TXEMPTY_MASK;
+ s->uart_intr_state |= R_INTR_STATE_TX_EMPTY_MASK;
+ s->uart_intr_state &= ~R_INTR_STATE_TX_WATERMARK_MASK;
ibex_uart_update_irqs(s);
return FALSE;
}
@@ -131,18 +131,18 @@ static gboolean ibex_uart_xmit(GIOChannel *chan, GIOCondition cond,
/* Clear the TX Full bit */
if (s->tx_level != IBEX_UART_TX_FIFO_SIZE) {
- s->uart_status &= ~UART_STATUS_TXFULL;
+ s->uart_status &= ~R_STATUS_TXFULL_MASK;
}
/* Disable the TX_WATERMARK IRQ */
if (s->tx_level < tx_fifo_level) {
- s->uart_intr_state &= ~INTR_STATE_TX_WATERMARK;
+ s->uart_intr_state &= ~R_INTR_STATE_TX_WATERMARK_MASK;
}
/* Set TX empty */
if (s->tx_level == 0) {
- s->uart_status |= UART_STATUS_TXEMPTY;
- s->uart_intr_state |= INTR_STATE_TX_EMPTY;
+ s->uart_status |= R_STATUS_TXEMPTY_MASK;
+ s->uart_intr_state |= R_INTR_STATE_TX_EMPTY_MASK;
}
ibex_uart_update_irqs(s);
@@ -153,8 +153,8 @@ static void uart_write_tx_fifo(IbexUartState *s, const uint8_t *buf,
int size)
{
uint64_t current_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
- uint8_t tx_fifo_level = (s->uart_fifo_ctrl & FIFO_CTRL_TXILVL)
- >> FIFO_CTRL_TXILVL_SHIFT;
+ uint8_t tx_fifo_level = (s->uart_fifo_ctrl & R_FIFO_CTRL_TXILVL_MASK)
+ >> R_FIFO_CTRL_TXILVL_SHIFT;
if (size > IBEX_UART_TX_FIFO_SIZE - s->tx_level) {
size = IBEX_UART_TX_FIFO_SIZE - s->tx_level;
@@ -165,16 +165,16 @@ static void uart_write_tx_fifo(IbexUartState *s, const uint8_t *buf,
s->tx_level += size;
if (s->tx_level > 0) {
- s->uart_status &= ~UART_STATUS_TXEMPTY;
+ s->uart_status &= ~R_STATUS_TXEMPTY_MASK;
}
if (s->tx_level >= tx_fifo_level) {
- s->uart_intr_state |= INTR_STATE_TX_WATERMARK;
+ s->uart_intr_state |= R_INTR_STATE_TX_WATERMARK_MASK;
ibex_uart_update_irqs(s);
}
if (s->tx_level == IBEX_UART_TX_FIFO_SIZE) {
- s->uart_status |= UART_STATUS_TXFULL;
+ s->uart_status |= R_STATUS_TXFULL_MASK;
}
timer_mod(s->fifo_trigger_handle, current_time +
@@ -208,7 +208,7 @@ static uint64_t ibex_uart_get_baud(IbexUartState *s)
{
uint64_t baud;
- baud = ((s->uart_ctrl & UART_CTRL_NCO) >> 16);
+ baud = ((s->uart_ctrl & R_CTRL_NCO_MASK) >> 16);
baud *= clock_get_hz(s->f_clk);
baud >>= 20;
@@ -221,43 +221,43 @@ static uint64_t ibex_uart_read(void *opaque, hwaddr addr,
IbexUartState *s = opaque;
uint64_t retvalue = 0;
- switch (addr) {
- case IBEX_UART_INTR_STATE:
+ switch (addr >> 2) {
+ case R_INTR_STATE:
retvalue = s->uart_intr_state;
break;
- case IBEX_UART_INTR_ENABLE:
+ case R_INTR_ENABLE:
retvalue = s->uart_intr_enable;
break;
- case IBEX_UART_INTR_TEST:
+ case R_INTR_TEST:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: wdata is write only\n", __func__);
break;
- case IBEX_UART_CTRL:
+ case R_CTRL:
retvalue = s->uart_ctrl;
break;
- case IBEX_UART_STATUS:
+ case R_STATUS:
retvalue = s->uart_status;
break;
- case IBEX_UART_RDATA:
+ case R_RDATA:
retvalue = s->uart_rdata;
- if (s->uart_ctrl & UART_CTRL_RX_ENABLE) {
+ if (s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) {
qemu_chr_fe_accept_input(&s->chr);
- s->uart_status |= UART_STATUS_RXIDLE;
- s->uart_status |= UART_STATUS_RXEMPTY;
+ s->uart_status |= R_STATUS_RXIDLE_MASK;
+ s->uart_status |= R_STATUS_RXEMPTY_MASK;
}
break;
- case IBEX_UART_WDATA:
+ case R_WDATA:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: wdata is write only\n", __func__);
break;
- case IBEX_UART_FIFO_CTRL:
+ case R_FIFO_CTRL:
retvalue = s->uart_fifo_ctrl;
break;
- case IBEX_UART_FIFO_STATUS:
+ case R_FIFO_STATUS:
retvalue = s->uart_fifo_status;
retvalue |= s->tx_level & 0x1F;
@@ -266,17 +266,17 @@ static uint64_t ibex_uart_read(void *opaque, hwaddr addr,
"%s: RX fifos are not supported\n", __func__);
break;
- case IBEX_UART_OVRD:
+ case R_OVRD:
retvalue = s->uart_ovrd;
qemu_log_mask(LOG_UNIMP,
"%s: ovrd is not supported\n", __func__);
break;
- case IBEX_UART_VAL:
+ case R_VAL:
retvalue = s->uart_val;
qemu_log_mask(LOG_UNIMP,
"%s: val is not supported\n", __func__);
break;
- case IBEX_UART_TIMEOUT_CTRL:
+ case R_TIMEOUT_CTRL:
retvalue = s->uart_timeout_ctrl;
qemu_log_mask(LOG_UNIMP,
"%s: timeout_ctrl is not supported\n", __func__);
@@ -296,95 +296,95 @@ static void ibex_uart_write(void *opaque, hwaddr addr,
IbexUartState *s = opaque;
uint32_t value = val64;
- switch (addr) {
- case IBEX_UART_INTR_STATE:
+ switch (addr >> 2) {
+ case R_INTR_STATE:
/* Write 1 clear */
s->uart_intr_state &= ~value;
ibex_uart_update_irqs(s);
break;
- case IBEX_UART_INTR_ENABLE:
+ case R_INTR_ENABLE:
s->uart_intr_enable = value;
ibex_uart_update_irqs(s);
break;
- case IBEX_UART_INTR_TEST:
+ case R_INTR_TEST:
s->uart_intr_state |= value;
ibex_uart_update_irqs(s);
break;
- case IBEX_UART_CTRL:
+ case R_CTRL:
s->uart_ctrl = value;
- if (value & UART_CTRL_NF) {
+ if (value & R_CTRL_NF_MASK) {
qemu_log_mask(LOG_UNIMP,
"%s: UART_CTRL_NF is not supported\n", __func__);
}
- if (value & UART_CTRL_SLPBK) {
+ if (value & R_CTRL_SLPBK_MASK) {
qemu_log_mask(LOG_UNIMP,
"%s: UART_CTRL_SLPBK is not supported\n", __func__);
}
- if (value & UART_CTRL_LLPBK) {
+ if (value & R_CTRL_LLPBK_MASK) {
qemu_log_mask(LOG_UNIMP,
"%s: UART_CTRL_LLPBK is not supported\n", __func__);
}
- if (value & UART_CTRL_PARITY_EN) {
+ if (value & R_CTRL_PARITY_EN_MASK) {
qemu_log_mask(LOG_UNIMP,
"%s: UART_CTRL_PARITY_EN is not supported\n",
__func__);
}
- if (value & UART_CTRL_PARITY_ODD) {
+ if (value & R_CTRL_PARITY_ODD_MASK) {
qemu_log_mask(LOG_UNIMP,
"%s: UART_CTRL_PARITY_ODD is not supported\n",
__func__);
}
- if (value & UART_CTRL_RXBLVL) {
+ if (value & R_CTRL_RXBLVL_MASK) {
qemu_log_mask(LOG_UNIMP,
"%s: UART_CTRL_RXBLVL is not supported\n", __func__);
}
- if (value & UART_CTRL_NCO) {
+ if (value & R_CTRL_NCO_MASK) {
uint64_t baud = ibex_uart_get_baud(s);
s->char_tx_time = (NANOSECONDS_PER_SECOND / baud) * 10;
}
break;
- case IBEX_UART_STATUS:
+ case R_STATUS:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: status is read only\n", __func__);
break;
- case IBEX_UART_RDATA:
+ case R_RDATA:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: rdata is read only\n", __func__);
break;
- case IBEX_UART_WDATA:
+ case R_WDATA:
uart_write_tx_fifo(s, (uint8_t *) &value, 1);
break;
- case IBEX_UART_FIFO_CTRL:
+ case R_FIFO_CTRL:
s->uart_fifo_ctrl = value;
- if (value & FIFO_CTRL_RXRST) {
+ if (value & R_FIFO_CTRL_RXRST_MASK) {
qemu_log_mask(LOG_UNIMP,
"%s: RX fifos are not supported\n", __func__);
}
- if (value & FIFO_CTRL_TXRST) {
+ if (value & R_FIFO_CTRL_TXRST_MASK) {
s->tx_level = 0;
}
break;
- case IBEX_UART_FIFO_STATUS:
+ case R_FIFO_STATUS:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: fifo_status is read only\n", __func__);
break;
- case IBEX_UART_OVRD:
+ case R_OVRD:
s->uart_ovrd = value;
qemu_log_mask(LOG_UNIMP,
"%s: ovrd is not supported\n", __func__);
break;
- case IBEX_UART_VAL:
+ case R_VAL:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: val is read only\n", __func__);
break;
- case IBEX_UART_TIMEOUT_CTRL:
+ case R_TIMEOUT_CTRL:
s->uart_timeout_ctrl = value;
qemu_log_mask(LOG_UNIMP,
"%s: timeout_ctrl is not supported\n", __func__);
@@ -409,7 +409,7 @@ static void fifo_trigger_update(void *opaque)
{
IbexUartState *s = opaque;
- if (s->uart_ctrl & UART_CTRL_TX_ENABLE) {
+ if (s->uart_ctrl & R_CTRL_TX_ENABLE_MASK) {
ibex_uart_xmit(NULL, G_IO_OUT, s);
}
}
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PULL 14/15] tcg/riscv: Remove superfluous breaks
2020-07-14 0:32 [PULL 00/15] riscv-to-apply queue Alistair Francis
` (12 preceding siblings ...)
2020-07-14 0:32 ` [PULL 13/15] hw/char: Convert the Ibex UART to use the registerfields API Alistair Francis
@ 2020-07-14 0:32 ` Alistair Francis
2020-07-14 0:32 ` [PULL 15/15] target/riscv: Fix pmp NA4 implementation Alistair Francis
` (2 subsequent siblings)
16 siblings, 0 replies; 32+ messages in thread
From: Alistair Francis @ 2020-07-14 0:32 UTC (permalink / raw)
To: qemu-devel
Cc: Yi Wang, Thomas Huth, Alistair Francis,
Philippe Mathieu-Daudé,
Liao Pingfang
From: Liao Pingfang <liao.pingfang@zte.com.cn>
Remove superfluous breaks, as there is a "return" before them.
Signed-off-by: Liao Pingfang <liao.pingfang@zte.com.cn>
Signed-off-by: Yi Wang <wang.yi59@zte.com.cn>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1594600421-22942-1-git-send-email-wang.yi59@zte.com.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
tcg/riscv/tcg-target.inc.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c
index 2bc0ba71f2..3c11ab8b7a 100644
--- a/tcg/riscv/tcg-target.inc.c
+++ b/tcg/riscv/tcg-target.inc.c
@@ -502,10 +502,8 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
break;
case R_RISCV_JAL:
return reloc_jimm20(code_ptr, (tcg_insn_unit *)value);
- break;
case R_RISCV_CALL:
return reloc_call(code_ptr, (tcg_insn_unit *)value);
- break;
default:
tcg_abort();
}
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PULL 15/15] target/riscv: Fix pmp NA4 implementation
2020-07-14 0:32 [PULL 00/15] riscv-to-apply queue Alistair Francis
` (13 preceding siblings ...)
2020-07-14 0:32 ` [PULL 14/15] tcg/riscv: Remove superfluous breaks Alistair Francis
@ 2020-07-14 0:32 ` Alistair Francis
2020-07-14 0:37 ` [PULL 00/15] riscv-to-apply queue Alistair Francis
2020-07-14 18:39 ` Peter Maydell
16 siblings, 0 replies; 32+ messages in thread
From: Alistair Francis @ 2020-07-14 0:32 UTC (permalink / raw)
To: qemu-devel; +Cc: Alistair Francis, Alexandre Mergnat
From: Alexandre Mergnat <amergnat@baylibre.com>
The end address calculation for NA4 mode is wrong because the address
used isn't shifted.
It doesn't watch 4 bytes but a huge range because the end address
calculation is wrong.
The solution is to use the shifted address calculated for start address
variable.
Modifications are tested on Zephyr OS userspace test suite which works
for other RISC-V boards (E31 and E34 core).
Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20200706084550.24117-1-amergnat@baylibre.com
Message-Id: <20200706084550.24117-1-amergnat@baylibre.com>
[ Changes by AF:
- Improve the commit title and message
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/pmp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 9418660f1b..2a2b9f5363 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -171,7 +171,7 @@ static void pmp_update_rule(CPURISCVState *env, uint32_t pmp_index)
case PMP_AMATCH_NA4:
sa = this_addr << 2; /* shift up from [xx:0] to [xx+2:2] */
- ea = (this_addr + 4u) - 1u;
+ ea = (sa + 4u) - 1u;
break;
case PMP_AMATCH_NAPOT:
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread
* Re: [PULL 00/15] riscv-to-apply queue
2020-07-14 0:32 [PULL 00/15] riscv-to-apply queue Alistair Francis
` (14 preceding siblings ...)
2020-07-14 0:32 ` [PULL 15/15] target/riscv: Fix pmp NA4 implementation Alistair Francis
@ 2020-07-14 0:37 ` Alistair Francis
2020-07-14 18:39 ` Peter Maydell
16 siblings, 0 replies; 32+ messages in thread
From: Alistair Francis @ 2020-07-14 0:37 UTC (permalink / raw)
To: Alistair Francis; +Cc: qemu-devel@nongnu.org Developers
On Mon, Jul 13, 2020 at 5:43 PM Alistair Francis
<alistair.francis@wdc.com> wrote:
>
> The following changes since commit 20c1df5476e1e9b5d3f5b94f9f3ce01d21f14c46:
>
> Merge remote-tracking branch 'remotes/kraxel/tags/fixes-20200713-pull-request' into staging (2020-07-13 16:58:44 +0100)
>
> are available in the Git repository at:
>
> git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20200713
>
> for you to fetch changes up to cfad709bceb629a4ebeb5d8a3acd1871b9a6436b:
>
> target/riscv: Fix pmp NA4 implementation (2020-07-13 17:25:37 -0700)
Sorry these are a little late, I was hoping to send them out last week
but I was chasing down some bugs and waiting on a few patches.
Alistair
>
> ----------------------------------------------------------------
> This is a colection of bug fixes and small imrprovements for RISC-V.
>
> This includes some vector extensions fixes, a PMP bug fix, OpenTitan
> UART bug fix and support for OpenSBI dynamic firmware.
>
> ----------------------------------------------------------------
> Alexandre Mergnat (1):
> target/riscv: Fix pmp NA4 implementation
>
> Alistair Francis (2):
> hw/char: Convert the Ibex UART to use the qdev Clock model
> hw/char: Convert the Ibex UART to use the registerfields API
>
> Atish Patra (4):
> riscv: Unify Qemu's reset vector code path
> RISC-V: Copy the fdt in dram instead of ROM
> riscv: Add opensbi firmware dynamic support
> RISC-V: Support 64 bit start address
>
> Bin Meng (3):
> MAINTAINERS: Add an entry for OpenSBI firmware
> hw/riscv: virt: Sort the SoC memmap table entries
> hw/riscv: Modify MROM size to end at 0x10000
>
> Frank Chang (4):
> target/riscv: fix rsub gvec tcg_assert_listed_vecop assertion
> target/riscv: correct the gvec IR called in gen_vec_rsub16_i64()
> target/riscv: fix return value of do_opivx_widen()
> target/riscv: fix vill bit index in vtype register
>
> Liao Pingfang (1):
> tcg/riscv: Remove superfluous breaks
>
> include/hw/char/ibex_uart.h | 79 ++++++++--------
> include/hw/riscv/boot.h | 7 ++
> include/hw/riscv/boot_opensbi.h | 58 ++++++++++++
> target/riscv/cpu.h | 2 +-
> hw/char/ibex_uart.c | 158 ++++++++++++++++++--------------
> hw/riscv/boot.c | 107 +++++++++++++++++++++
> hw/riscv/sifive_u.c | 53 ++++++-----
> hw/riscv/spike.c | 59 ++++--------
> hw/riscv/virt.c | 63 ++++---------
> target/riscv/insn_trans/trans_rvv.inc.c | 9 +-
> target/riscv/pmp.c | 2 +-
> tcg/riscv/tcg-target.inc.c | 2 -
> MAINTAINERS | 7 ++
> 13 files changed, 387 insertions(+), 219 deletions(-)
> create mode 100644 include/hw/riscv/boot_opensbi.h
>
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PULL 00/15] riscv-to-apply queue
2020-07-14 0:32 [PULL 00/15] riscv-to-apply queue Alistair Francis
` (15 preceding siblings ...)
2020-07-14 0:37 ` [PULL 00/15] riscv-to-apply queue Alistair Francis
@ 2020-07-14 18:39 ` Peter Maydell
16 siblings, 0 replies; 32+ messages in thread
From: Peter Maydell @ 2020-07-14 18:39 UTC (permalink / raw)
To: Alistair Francis; +Cc: QEMU Developers
On Tue, 14 Jul 2020 at 01:44, Alistair Francis <alistair.francis@wdc.com> wrote:
>
> The following changes since commit 20c1df5476e1e9b5d3f5b94f9f3ce01d21f14c46:
>
> Merge remote-tracking branch 'remotes/kraxel/tags/fixes-20200713-pull-request' into staging (2020-07-13 16:58:44 +0100)
>
> are available in the Git repository at:
>
> git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20200713
>
> for you to fetch changes up to cfad709bceb629a4ebeb5d8a3acd1871b9a6436b:
>
> target/riscv: Fix pmp NA4 implementation (2020-07-13 17:25:37 -0700)
>
> ----------------------------------------------------------------
> This is a colection of bug fixes and small imrprovements for RISC-V.
>
> This includes some vector extensions fixes, a PMP bug fix, OpenTitan
> UART bug fix and support for OpenSBI dynamic firmware.
>
> ----------------------------------------------------------------
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/5.1
for any user-visible changes.
-- PMM
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PULL 04/15] RISC-V: Copy the fdt in dram instead of ROM
2020-07-14 0:32 ` [PULL 04/15] RISC-V: Copy the fdt in dram instead of ROM Alistair Francis
@ 2021-07-13 10:43 ` Peter Maydell
2021-07-14 6:35 ` Alistair Francis
0 siblings, 1 reply; 32+ messages in thread
From: Peter Maydell @ 2021-07-13 10:43 UTC (permalink / raw)
To: Alistair Francis; +Cc: Atish Patra, Bin Meng, QEMU Developers
On Tue, 14 Jul 2020 at 01:44, Alistair Francis <alistair.francis@wdc.com> wrote:
>
> From: Atish Patra <atish.patra@wdc.com>
>
> Currently, the fdt is copied to the ROM after the reset vector. The firmware
> has to copy it to DRAM. Instead of this, directly copy the device tree to a
> pre-computed dram address. The device tree load address should be as far as
> possible from kernel and initrd images. That's why it is kept at the end of
> the DRAM or 4GB whichever is lesser.
Hi; Coverity reports an issue in this code (CID 1458136):
> +uint32_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt)
> +{
> + uint32_t temp, fdt_addr;
> + hwaddr dram_end = dram_base + mem_size;
> + int fdtsize = fdt_totalsize(fdt);
> +
> + if (fdtsize <= 0) {
> + error_report("invalid device-tree");
> + exit(1);
> + }
> +
> + /*
> + * We should put fdt as far as possible to avoid kernel/initrd overwriting
> + * its content. But it should be addressable by 32 bit system as well.
> + * Thus, put it at an aligned address that less than fdt size from end of
> + * dram or 4GB whichever is lesser.
> + */
> + temp = MIN(dram_end, 4096 * MiB);
> + fdt_addr = QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB);
> +
> + fdt_pack(fdt);
fdt_pack() can return an error code, but we are not checking its
return value here.
(This is one of Coverity's heuristics where it only reports failure
to check errors if it sees enough other callsites in the codebase
which do check errors to make it decide this is an "always need a
check" API, which is why the error has only popped up now a year on...)
> + /* copy in the device tree */
> + qemu_fdt_dumpdtb(fdt, fdtsize);
> +
> + rom_add_blob_fixed_as("fdt", fdt, fdtsize, fdt_addr,
> + &address_space_memory);
> +
> + return fdt_addr;
> +}
thanks
-- PMM
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PULL 04/15] RISC-V: Copy the fdt in dram instead of ROM
2021-07-13 10:43 ` Peter Maydell
@ 2021-07-14 6:35 ` Alistair Francis
0 siblings, 0 replies; 32+ messages in thread
From: Alistair Francis @ 2021-07-14 6:35 UTC (permalink / raw)
To: Peter Maydell; +Cc: Atish Patra, Bin Meng, Alistair Francis, QEMU Developers
On Tue, Jul 13, 2021 at 8:44 PM Peter Maydell <peter.maydell@linaro.org> wrote:
>
> On Tue, 14 Jul 2020 at 01:44, Alistair Francis <alistair.francis@wdc.com> wrote:
> >
> > From: Atish Patra <atish.patra@wdc.com>
> >
> > Currently, the fdt is copied to the ROM after the reset vector. The firmware
> > has to copy it to DRAM. Instead of this, directly copy the device tree to a
> > pre-computed dram address. The device tree load address should be as far as
> > possible from kernel and initrd images. That's why it is kept at the end of
> > the DRAM or 4GB whichever is lesser.
>
> Hi; Coverity reports an issue in this code (CID 1458136):
>
> > +uint32_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt)
> > +{
> > + uint32_t temp, fdt_addr;
> > + hwaddr dram_end = dram_base + mem_size;
> > + int fdtsize = fdt_totalsize(fdt);
> > +
> > + if (fdtsize <= 0) {
> > + error_report("invalid device-tree");
> > + exit(1);
> > + }
> > +
> > + /*
> > + * We should put fdt as far as possible to avoid kernel/initrd overwriting
> > + * its content. But it should be addressable by 32 bit system as well.
> > + * Thus, put it at an aligned address that less than fdt size from end of
> > + * dram or 4GB whichever is lesser.
> > + */
> > + temp = MIN(dram_end, 4096 * MiB);
> > + fdt_addr = QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB);
> > +
> > + fdt_pack(fdt);
>
> fdt_pack() can return an error code, but we are not checking its
> return value here.
>
> (This is one of Coverity's heuristics where it only reports failure
> to check errors if it sees enough other callsites in the codebase
> which do check errors to make it decide this is an "always need a
> check" API, which is why the error has only popped up now a year on...)
Thanks Peter, sending a patch now.
Alistair
>
> > + /* copy in the device tree */
> > + qemu_fdt_dumpdtb(fdt, fdtsize);
> > +
> > + rom_add_blob_fixed_as("fdt", fdt, fdtsize, fdt_addr,
> > + &address_space_memory);
> > +
> > + return fdt_addr;
> > +}
>
> thanks
> -- PMM
>
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PULL 00/15] riscv-to-apply queue
2024-03-26 9:56 ` Alistair Francis
2024-03-26 12:09 ` Daniel Henrique Barboza
@ 2024-03-27 10:13 ` Michael Tokarev
1 sibling, 0 replies; 32+ messages in thread
From: Michael Tokarev @ 2024-03-27 10:13 UTC (permalink / raw)
To: Alistair Francis
Cc: Daniel Henrique Barboza, qemu-devel, Alistair Francis, qemu-stable
26.03.2024 12:56, Alistair Francis пишет:
> On Tue, Mar 26, 2024 at 7:53 PM Michael Tokarev <mjt@tls.msk.ru> wrote:
>>
>> On 24.03.2024 21:12, Daniel Henrique Barboza wrote:
>>> On 3/24/24 12:07, Michael Tokarev wrote:
>>
>>>> Unfortunately this doesn't quite work, the following changes
>>>> fail to apply to 8.2:
>>>>
>>>> 929e521a47 target/riscv: always clear vstart for ldst_whole insns
>>>> b46631f122 target/riscv: remove 'over' brconds from vector trans
>>>> d57dfe4b37 trans_rvv.c.inc: remove redundant mark_vs_dirty() calls
>>>> bac802ada8 target/riscv: enable 'vstart_eq_zero' in the end of insns
>>>> 385e575cd5 target/riscv/kvm: fix timebase-frequency when using KVM acceleration
>>
>>> The amount of work can be non-trivial for this backport, so I'd say we should
>>> leave it aside for now. If someone has a good argument for this work then we
>>> can re-evaluate.
>>
>> So, out of 15 patches in this series (minus the first one already
>> mentioned) - should I pick 9 remaining patches for stable (the ones
>> which applies) or none at all? :)
>
> Sorry for the confusion.
>
> The 9 patches that applied and
>
> 385e575cd5 target/riscv/kvm: fix timebase-frequency when using KVM acceleration
>
> should all be picked for stable.
Got it, picked all plus 385e575cd5 which needed just trivial context fixup.
Thank you for the clarification!
> PS: What is the best way in future to help ease some of the stable
> burden? Should I try and cherry pick them beforehand and then mention
> that as a follow up to the PR?
The only problem for me so far is the patch selection, - this is why I'm
asking to Cc changes which should go to stable, to qemu-stable@. So far
I was a bit pro-active and asked about some changes which I *feel* are
suitable, like in this case. It is much better if someone who actually
has knowledge about the area being changed, decides if it's stable material
or not. At the same time, I don't mind at all if more changes than needed
are Cc'ed like this, - at least as long as it's obvious they're not really
needed (like fixing a bug introduced in commit which isn't in any release
yet).
I usually don't have any issues with applying patches which don't apply
directly to stable - this is not a burden. In some cases when this happens,
I can edit the commit (like I just did for 385e575cd5), or pick some previous
changes too if they're okay, or in even more rare cases, ask for clarification
or even for help with back-porting, - but this last category is really rare.
Some changes gets rejected for stable in the end due to too much back-porting
effort or requiring too much prior context.
So the only real issue for me is to know which changes are to pick, - that's all.
And this is the only thing I'm asking, - in this thread and elsewhere.
Thank you!
/mjt
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PULL 00/15] riscv-to-apply queue
2024-03-26 9:56 ` Alistair Francis
@ 2024-03-26 12:09 ` Daniel Henrique Barboza
2024-03-27 10:13 ` Michael Tokarev
1 sibling, 0 replies; 32+ messages in thread
From: Daniel Henrique Barboza @ 2024-03-26 12:09 UTC (permalink / raw)
To: Alistair Francis, Michael Tokarev
Cc: qemu-devel, Alistair Francis, qemu-stable
On 3/26/24 06:56, Alistair Francis wrote:
> On Tue, Mar 26, 2024 at 7:53 PM Michael Tokarev <mjt@tls.msk.ru> wrote:
>>
>> On 24.03.2024 21:12, Daniel Henrique Barboza wrote:
>>> On 3/24/24 12:07, Michael Tokarev wrote:
>>
>>>> Unfortunately this doesn't quite work, the following changes
>>>> fail to apply to 8.2:
>>>>
>>>> 929e521a47 target/riscv: always clear vstart for ldst_whole insns
>>>> b46631f122 target/riscv: remove 'over' brconds from vector trans
>>>> d57dfe4b37 trans_rvv.c.inc: remove redundant mark_vs_dirty() calls
>>>> bac802ada8 target/riscv: enable 'vstart_eq_zero' in the end of insns
>>>> 385e575cd5 target/riscv/kvm: fix timebase-frequency when using KVM acceleration
>>
>>> The amount of work can be non-trivial for this backport, so I'd say we should
>>> leave it aside for now. If someone has a good argument for this work then we
>>> can re-evaluate.
>>
>> So, out of 15 patches in this series (minus the first one already
>> mentioned) - should I pick 9 remaining patches for stable (the ones
>> which applies) or none at all? :)
>
> Sorry for the confusion.
>
> The 9 patches that applied and
>
> 385e575cd5 target/riscv/kvm: fix timebase-frequency when using KVM acceleration
>
> should all be picked for stable.
>
> PS: What is the best way in future to help ease some of the stable
> burden? Should I try and cherry pick them beforehand and then mention
> that as a follow up to the PR?
We believe your judgement about what should or shouldn't be in stable, so IMO you can
be pro-active into cherry picking fixes into stable and mention it in the PR.
Thanks,
Daniel
>
> Alistair
>
>>
>> Thanks,
>>
>> /mjt
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PULL 00/15] riscv-to-apply queue
2024-03-26 9:53 ` Michael Tokarev
@ 2024-03-26 9:56 ` Alistair Francis
2024-03-26 12:09 ` Daniel Henrique Barboza
2024-03-27 10:13 ` Michael Tokarev
0 siblings, 2 replies; 32+ messages in thread
From: Alistair Francis @ 2024-03-26 9:56 UTC (permalink / raw)
To: Michael Tokarev
Cc: Daniel Henrique Barboza, qemu-devel, Alistair Francis, qemu-stable
On Tue, Mar 26, 2024 at 7:53 PM Michael Tokarev <mjt@tls.msk.ru> wrote:
>
> On 24.03.2024 21:12, Daniel Henrique Barboza wrote:
> > On 3/24/24 12:07, Michael Tokarev wrote:
>
> >> Unfortunately this doesn't quite work, the following changes
> >> fail to apply to 8.2:
> >>
> >> 929e521a47 target/riscv: always clear vstart for ldst_whole insns
> >> b46631f122 target/riscv: remove 'over' brconds from vector trans
> >> d57dfe4b37 trans_rvv.c.inc: remove redundant mark_vs_dirty() calls
> >> bac802ada8 target/riscv: enable 'vstart_eq_zero' in the end of insns
> >> 385e575cd5 target/riscv/kvm: fix timebase-frequency when using KVM acceleration
>
> > The amount of work can be non-trivial for this backport, so I'd say we should
> > leave it aside for now. If someone has a good argument for this work then we
> > can re-evaluate.
>
> So, out of 15 patches in this series (minus the first one already
> mentioned) - should I pick 9 remaining patches for stable (the ones
> which applies) or none at all? :)
Sorry for the confusion.
The 9 patches that applied and
385e575cd5 target/riscv/kvm: fix timebase-frequency when using KVM acceleration
should all be picked for stable.
PS: What is the best way in future to help ease some of the stable
burden? Should I try and cherry pick them beforehand and then mention
that as a follow up to the PR?
Alistair
>
> Thanks,
>
> /mjt
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PULL 00/15] riscv-to-apply queue
2024-03-24 18:12 ` Daniel Henrique Barboza
@ 2024-03-26 9:53 ` Michael Tokarev
2024-03-26 9:56 ` Alistair Francis
0 siblings, 1 reply; 32+ messages in thread
From: Michael Tokarev @ 2024-03-26 9:53 UTC (permalink / raw)
To: Daniel Henrique Barboza, Alistair Francis, qemu-devel
Cc: Alistair Francis, qemu-stable
On 24.03.2024 21:12, Daniel Henrique Barboza wrote:
> On 3/24/24 12:07, Michael Tokarev wrote:
>> Unfortunately this doesn't quite work, the following changes
>> fail to apply to 8.2:
>>
>> 929e521a47 target/riscv: always clear vstart for ldst_whole insns
>> b46631f122 target/riscv: remove 'over' brconds from vector trans
>> d57dfe4b37 trans_rvv.c.inc: remove redundant mark_vs_dirty() calls
>> bac802ada8 target/riscv: enable 'vstart_eq_zero' in the end of insns
>> 385e575cd5 target/riscv/kvm: fix timebase-frequency when using KVM acceleration
> The amount of work can be non-trivial for this backport, so I'd say we should
> leave it aside for now. If someone has a good argument for this work then we
> can re-evaluate.
So, out of 15 patches in this series (minus the first one already
mentioned) - should I pick 9 remaining patches for stable (the ones
which applies) or none at all? :)
Thanks,
/mjt
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PULL 00/15] riscv-to-apply queue
2024-03-24 15:07 ` Michael Tokarev
@ 2024-03-24 18:12 ` Daniel Henrique Barboza
2024-03-26 9:53 ` Michael Tokarev
0 siblings, 1 reply; 32+ messages in thread
From: Daniel Henrique Barboza @ 2024-03-24 18:12 UTC (permalink / raw)
To: Michael Tokarev, Alistair Francis, qemu-devel
Cc: Alistair Francis, qemu-stable
On 3/24/24 12:07, Michael Tokarev wrote:
> 22.03.2024 22:46, Daniel Henrique Barboza :
>>
>>
>> On 3/22/24 14:16, Michael Tokarev wrote:
>>> 22.03.2024 11:53, Alistair Francis :
>>>
>>>> RISC-V PR for 9.0
>>>>
>>>> * Do not enable all named features by default
>>>> * A range of Vector fixes
>>>> * Update APLIC IDC after claiming iforce register
>>>> * Remove the dependency of Zvfbfmin to Zfbfmin
>>>> * Fix mode in riscv_tlb_fill
>>>> * Fix timebase-frequency when using KVM acceleration
>>>
>>> Should something from there be picked up for stable (8.2 and probably 7.2)?
>>
>> Ignore the "Do not enable all named features by default" since it's fixing something
>> that were added in 9.0.
>>
>> The rest you can pick it up to 8.2 at least. Thanks,
>
> Unfortunately this doesn't quite work, the following changes
> fail to apply to 8.2:
>
> 929e521a47 target/riscv: always clear vstart for ldst_whole insns
> b46631f122 target/riscv: remove 'over' brconds from vector trans
> d57dfe4b37 trans_rvv.c.inc: remove redundant mark_vs_dirty() calls
> bac802ada8 target/riscv: enable 'vstart_eq_zero' in the end of insns
> 385e575cd5 target/riscv/kvm: fix timebase-frequency when using KVM acceleration
>
> I tried to back-port at least the first one but it turned out to be
> another failure. Didn't try looking at the rest.
This particular code (vector emulation) has been going through a lot of
changes in the last couple of releases, so I'm not surprised with the
difficulty with backporting these.
>
> If these really should be in 8.2 (it's your guys to decide, not me),
> I need help with back-porting these to 8.2 (and/or cherry-picking
> additional patches from master).
The amount of work can be non-trivial for this backport, so I'd say we should
leave it aside for now. If someone has a good argument for this work then we
can re-evaluate.
Thanks,
Daniel
>
> Thanks,
>
> /mjt
>
>>>> ----------------------------------------------------------------
>>>> Daniel Henrique Barboza (10):
>>>> target/riscv: do not enable all named features by default
>>>> target/riscv/vector_helper.c: set vstart = 0 in GEN_VEXT_VSLIDEUP_VX()
>>>> trans_rvv.c.inc: set vstart = 0 in int scalar move insns
>>>> target/riscv/vector_helper.c: fix 'vmvr_v' memcpy endianess
>>>> target/riscv: always clear vstart in whole vec move insns
>>>> target/riscv: always clear vstart for ldst_whole insns
>>>> target/riscv/vector_helpers: do early exit when vstart >= vl
>>>> target/riscv: remove 'over' brconds from vector trans
>>>> trans_rvv.c.inc: remove redundant mark_vs_dirty() calls
>>>> target/riscv/vector_helper.c: optimize loops in ldst helpers
>>>>
>>>> Frank Chang (1):
>>>> hw/intc: Update APLIC IDC after claiming iforce register
>>>>
>>>> Irina Ryapolova (1):
>>>> target/riscv: Fix mode in riscv_tlb_fill
>>>>
>>>> Ivan Klokov (1):
>>>> target/riscv: enable 'vstart_eq_zero' in the end of insns
>>>>
>>>> Max Chou (1):
>>>> target/riscv: rvv: Remove the dependency of Zvfbfmin to Zfbfmin
>>>>
>>>> Yong-Xuan Wang (1):
>>>> target/riscv/kvm: fix timebase-frequency when using KVM acceleration
>>>
>>
>
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PULL 00/15] riscv-to-apply queue
2024-03-22 19:46 ` Daniel Henrique Barboza
@ 2024-03-24 15:07 ` Michael Tokarev
2024-03-24 18:12 ` Daniel Henrique Barboza
0 siblings, 1 reply; 32+ messages in thread
From: Michael Tokarev @ 2024-03-24 15:07 UTC (permalink / raw)
To: Daniel Henrique Barboza, Alistair Francis, qemu-devel
Cc: Alistair Francis, qemu-stable
22.03.2024 22:46, Daniel Henrique Barboza :
>
>
> On 3/22/24 14:16, Michael Tokarev wrote:
>> 22.03.2024 11:53, Alistair Francis :
>>
>>> RISC-V PR for 9.0
>>>
>>> * Do not enable all named features by default
>>> * A range of Vector fixes
>>> * Update APLIC IDC after claiming iforce register
>>> * Remove the dependency of Zvfbfmin to Zfbfmin
>>> * Fix mode in riscv_tlb_fill
>>> * Fix timebase-frequency when using KVM acceleration
>>
>> Should something from there be picked up for stable (8.2 and probably 7.2)?
>
> Ignore the "Do not enable all named features by default" since it's fixing something
> that were added in 9.0.
>
> The rest you can pick it up to 8.2 at least. Thanks,
Unfortunately this doesn't quite work, the following changes
fail to apply to 8.2:
929e521a47 target/riscv: always clear vstart for ldst_whole insns
b46631f122 target/riscv: remove 'over' brconds from vector trans
d57dfe4b37 trans_rvv.c.inc: remove redundant mark_vs_dirty() calls
bac802ada8 target/riscv: enable 'vstart_eq_zero' in the end of insns
385e575cd5 target/riscv/kvm: fix timebase-frequency when using KVM acceleration
I tried to back-port at least the first one but it turned out to be
another failure. Didn't try looking at the rest.
If these really should be in 8.2 (it's your guys to decide, not me),
I need help with back-porting these to 8.2 (and/or cherry-picking
additional patches from master).
Thanks,
/mjt
>>> ----------------------------------------------------------------
>>> Daniel Henrique Barboza (10):
>>> target/riscv: do not enable all named features by default
>>> target/riscv/vector_helper.c: set vstart = 0 in GEN_VEXT_VSLIDEUP_VX()
>>> trans_rvv.c.inc: set vstart = 0 in int scalar move insns
>>> target/riscv/vector_helper.c: fix 'vmvr_v' memcpy endianess
>>> target/riscv: always clear vstart in whole vec move insns
>>> target/riscv: always clear vstart for ldst_whole insns
>>> target/riscv/vector_helpers: do early exit when vstart >= vl
>>> target/riscv: remove 'over' brconds from vector trans
>>> trans_rvv.c.inc: remove redundant mark_vs_dirty() calls
>>> target/riscv/vector_helper.c: optimize loops in ldst helpers
>>>
>>> Frank Chang (1):
>>> hw/intc: Update APLIC IDC after claiming iforce register
>>>
>>> Irina Ryapolova (1):
>>> target/riscv: Fix mode in riscv_tlb_fill
>>>
>>> Ivan Klokov (1):
>>> target/riscv: enable 'vstart_eq_zero' in the end of insns
>>>
>>> Max Chou (1):
>>> target/riscv: rvv: Remove the dependency of Zvfbfmin to Zfbfmin
>>>
>>> Yong-Xuan Wang (1):
>>> target/riscv/kvm: fix timebase-frequency when using KVM acceleration
>>
>
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PULL 00/15] riscv-to-apply queue
2024-03-22 17:16 ` Michael Tokarev
@ 2024-03-22 19:46 ` Daniel Henrique Barboza
2024-03-24 15:07 ` Michael Tokarev
0 siblings, 1 reply; 32+ messages in thread
From: Daniel Henrique Barboza @ 2024-03-22 19:46 UTC (permalink / raw)
To: Michael Tokarev, Alistair Francis, qemu-devel
Cc: Alistair Francis, qemu-stable
On 3/22/24 14:16, Michael Tokarev wrote:
> 22.03.2024 11:53, Alistair Francis :
>
>> RISC-V PR for 9.0
>>
>> * Do not enable all named features by default
>> * A range of Vector fixes
>> * Update APLIC IDC after claiming iforce register
>> * Remove the dependency of Zvfbfmin to Zfbfmin
>> * Fix mode in riscv_tlb_fill
>> * Fix timebase-frequency when using KVM acceleration
>
> Should something from there be picked up for stable (8.2 and probably 7.2)?
Ignore the "Do not enable all named features by default" since it's fixing something
that were added in 9.0.
The rest you can pick it up to 8.2 at least. Thanks,
Daniel
>
> Thanks,
>
> /mjt
>
>> ----------------------------------------------------------------
>> Daniel Henrique Barboza (10):
>> target/riscv: do not enable all named features by default
>> target/riscv/vector_helper.c: set vstart = 0 in GEN_VEXT_VSLIDEUP_VX()
>> trans_rvv.c.inc: set vstart = 0 in int scalar move insns
>> target/riscv/vector_helper.c: fix 'vmvr_v' memcpy endianess
>> target/riscv: always clear vstart in whole vec move insns
>> target/riscv: always clear vstart for ldst_whole insns
>> target/riscv/vector_helpers: do early exit when vstart >= vl
>> target/riscv: remove 'over' brconds from vector trans
>> trans_rvv.c.inc: remove redundant mark_vs_dirty() calls
>> target/riscv/vector_helper.c: optimize loops in ldst helpers
>>
>> Frank Chang (1):
>> hw/intc: Update APLIC IDC after claiming iforce register
>>
>> Irina Ryapolova (1):
>> target/riscv: Fix mode in riscv_tlb_fill
>>
>> Ivan Klokov (1):
>> target/riscv: enable 'vstart_eq_zero' in the end of insns
>>
>> Max Chou (1):
>> target/riscv: rvv: Remove the dependency of Zvfbfmin to Zfbfmin
>>
>> Yong-Xuan Wang (1):
>> target/riscv/kvm: fix timebase-frequency when using KVM acceleration
>
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PULL 00/15] riscv-to-apply queue
2024-03-22 8:53 Alistair Francis
2024-03-22 12:58 ` Peter Maydell
@ 2024-03-22 17:16 ` Michael Tokarev
2024-03-22 19:46 ` Daniel Henrique Barboza
1 sibling, 1 reply; 32+ messages in thread
From: Michael Tokarev @ 2024-03-22 17:16 UTC (permalink / raw)
To: Alistair Francis, qemu-devel
Cc: Alistair Francis, qemu-stable, Daniel Henrique Barboza
22.03.2024 11:53, Alistair Francis :
> RISC-V PR for 9.0
>
> * Do not enable all named features by default
> * A range of Vector fixes
> * Update APLIC IDC after claiming iforce register
> * Remove the dependency of Zvfbfmin to Zfbfmin
> * Fix mode in riscv_tlb_fill
> * Fix timebase-frequency when using KVM acceleration
Should something from there be picked up for stable (8.2 and probably 7.2)?
Thanks,
/mjt
> ----------------------------------------------------------------
> Daniel Henrique Barboza (10):
> target/riscv: do not enable all named features by default
> target/riscv/vector_helper.c: set vstart = 0 in GEN_VEXT_VSLIDEUP_VX()
> trans_rvv.c.inc: set vstart = 0 in int scalar move insns
> target/riscv/vector_helper.c: fix 'vmvr_v' memcpy endianess
> target/riscv: always clear vstart in whole vec move insns
> target/riscv: always clear vstart for ldst_whole insns
> target/riscv/vector_helpers: do early exit when vstart >= vl
> target/riscv: remove 'over' brconds from vector trans
> trans_rvv.c.inc: remove redundant mark_vs_dirty() calls
> target/riscv/vector_helper.c: optimize loops in ldst helpers
>
> Frank Chang (1):
> hw/intc: Update APLIC IDC after claiming iforce register
>
> Irina Ryapolova (1):
> target/riscv: Fix mode in riscv_tlb_fill
>
> Ivan Klokov (1):
> target/riscv: enable 'vstart_eq_zero' in the end of insns
>
> Max Chou (1):
> target/riscv: rvv: Remove the dependency of Zvfbfmin to Zfbfmin
>
> Yong-Xuan Wang (1):
> target/riscv/kvm: fix timebase-frequency when using KVM acceleration
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PULL 00/15] riscv-to-apply queue
2024-03-22 8:53 Alistair Francis
@ 2024-03-22 12:58 ` Peter Maydell
2024-03-22 17:16 ` Michael Tokarev
1 sibling, 0 replies; 32+ messages in thread
From: Peter Maydell @ 2024-03-22 12:58 UTC (permalink / raw)
To: Alistair Francis; +Cc: qemu-devel, Alistair Francis
On Fri, 22 Mar 2024 at 09:01, Alistair Francis <alistair23@gmail.com> wrote:
>
> The following changes since commit fea445e8fe9acea4f775a832815ee22bdf2b0222:
>
> Merge tag 'pull-maintainer-final-for-real-this-time-200324-1' of https://gitlab.com/stsquad/qemu into staging (2024-03-21 10:31:56 +0000)
>
> are available in the Git repository at:
>
> https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20240322
>
> for you to fetch changes up to 385e575cd5ab2436c123e4b7f8c9b383a64c0dbe:
>
> target/riscv/kvm: fix timebase-frequency when using KVM acceleration (2024-03-22 15:41:01 +1000)
>
> ----------------------------------------------------------------
> RISC-V PR for 9.0
>
> * Do not enable all named features by default
> * A range of Vector fixes
> * Update APLIC IDC after claiming iforce register
> * Remove the dependency of Zvfbfmin to Zfbfmin
> * Fix mode in riscv_tlb_fill
> * Fix timebase-frequency when using KVM acceleration
>
> ----------------------------------------------------------------
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/9.0
for any user-visible changes.
-- PMM
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PULL 00/15] riscv-to-apply queue
@ 2024-03-22 8:53 Alistair Francis
2024-03-22 12:58 ` Peter Maydell
2024-03-22 17:16 ` Michael Tokarev
0 siblings, 2 replies; 32+ messages in thread
From: Alistair Francis @ 2024-03-22 8:53 UTC (permalink / raw)
To: qemu-devel; +Cc: alistair23, Alistair Francis
The following changes since commit fea445e8fe9acea4f775a832815ee22bdf2b0222:
Merge tag 'pull-maintainer-final-for-real-this-time-200324-1' of https://gitlab.com/stsquad/qemu into staging (2024-03-21 10:31:56 +0000)
are available in the Git repository at:
https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20240322
for you to fetch changes up to 385e575cd5ab2436c123e4b7f8c9b383a64c0dbe:
target/riscv/kvm: fix timebase-frequency when using KVM acceleration (2024-03-22 15:41:01 +1000)
----------------------------------------------------------------
RISC-V PR for 9.0
* Do not enable all named features by default
* A range of Vector fixes
* Update APLIC IDC after claiming iforce register
* Remove the dependency of Zvfbfmin to Zfbfmin
* Fix mode in riscv_tlb_fill
* Fix timebase-frequency when using KVM acceleration
----------------------------------------------------------------
Daniel Henrique Barboza (10):
target/riscv: do not enable all named features by default
target/riscv/vector_helper.c: set vstart = 0 in GEN_VEXT_VSLIDEUP_VX()
trans_rvv.c.inc: set vstart = 0 in int scalar move insns
target/riscv/vector_helper.c: fix 'vmvr_v' memcpy endianess
target/riscv: always clear vstart in whole vec move insns
target/riscv: always clear vstart for ldst_whole insns
target/riscv/vector_helpers: do early exit when vstart >= vl
target/riscv: remove 'over' brconds from vector trans
trans_rvv.c.inc: remove redundant mark_vs_dirty() calls
target/riscv/vector_helper.c: optimize loops in ldst helpers
Frank Chang (1):
hw/intc: Update APLIC IDC after claiming iforce register
Irina Ryapolova (1):
target/riscv: Fix mode in riscv_tlb_fill
Ivan Klokov (1):
target/riscv: enable 'vstart_eq_zero' in the end of insns
Max Chou (1):
target/riscv: rvv: Remove the dependency of Zvfbfmin to Zfbfmin
Yong-Xuan Wang (1):
target/riscv/kvm: fix timebase-frequency when using KVM acceleration
target/riscv/cpu_cfg.h | 8 +-
target/riscv/kvm/kvm_riscv.h | 1 +
target/riscv/vector_internals.h | 9 ++
hw/intc/riscv_aplic.c | 1 +
hw/riscv/virt.c | 2 +
target/riscv/cpu.c | 40 ++---
target/riscv/cpu_helper.c | 2 +-
target/riscv/kvm/kvm-cpu.c | 9 ++
target/riscv/tcg/tcg-cpu.c | 19 ++-
target/riscv/translate.c | 6 +
target/riscv/vcrypto_helper.c | 32 ++++
target/riscv/vector_helper.c | 93 ++++++++++-
target/riscv/vector_internals.c | 4 +
target/riscv/insn_trans/trans_rvbf16.c.inc | 18 +--
target/riscv/insn_trans/trans_rvv.c.inc | 244 +++++++++--------------------
target/riscv/insn_trans/trans_rvvk.c.inc | 30 +---
16 files changed, 259 insertions(+), 259 deletions(-)
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PULL 00/15] riscv-to-apply queue
2020-06-03 16:13 Alistair Francis
@ 2020-06-04 11:40 ` Peter Maydell
0 siblings, 0 replies; 32+ messages in thread
From: Peter Maydell @ 2020-06-04 11:40 UTC (permalink / raw)
To: Alistair Francis; +Cc: Alistair Francis, QEMU Developers
On Wed, 3 Jun 2020 at 17:22, Alistair Francis <alistair.francis@wdc.com> wrote:
>
> The following changes since commit 5cc7a54c2e91d82cb6a52e4921325c511fd90712:
>
> Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20200602' into staging (2020-06-02 18:16:38 +0100)
>
> are available in the Git repository at:
>
> git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20200603
>
> for you to fetch changes up to fe0fe4735e798578097758781166cc221319b93d:
>
> riscv: Initial commit of OpenTitan machine (2020-06-03 09:11:51 -0700)
>
> ----------------------------------------------------------------
> This is a collection of RISC-V patches for 5.1.
>
> This incldues removing deprecated features and part of the OpenTitan
> support series.
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/5.1
for any user-visible changes.
-- PMM
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PULL 00/15] riscv-to-apply queue
@ 2020-06-03 16:13 Alistair Francis
2020-06-04 11:40 ` Peter Maydell
0 siblings, 1 reply; 32+ messages in thread
From: Alistair Francis @ 2020-06-03 16:13 UTC (permalink / raw)
To: qemu-devel, peter.maydell; +Cc: alistair23, Alistair Francis
The following changes since commit 5cc7a54c2e91d82cb6a52e4921325c511fd90712:
Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20200602' into staging (2020-06-02 18:16:38 +0100)
are available in the Git repository at:
git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20200603
for you to fetch changes up to fe0fe4735e798578097758781166cc221319b93d:
riscv: Initial commit of OpenTitan machine (2020-06-03 09:11:51 -0700)
----------------------------------------------------------------
This is a collection of RISC-V patches for 5.1.
This incldues removing deprecated features and part of the OpenTitan
support series.
----------------------------------------------------------------
Alistair Francis (11):
hw/riscv: spike: Remove deprecated ISA specific machines
target/riscv: Remove the deprecated CPUs
target/riscv: Drop support for ISA spec version 1.09.1
docs: deprecated: Update the -bios documentation
riscv: sifive_e: Manually define the machine
riscv/boot: Add a missing header include
target/riscv: Don't overwrite the reset vector
target/riscv: Disable the MMU correctly
target/riscv: Don't set PMP feature in the cpu init
target/riscv: Add the lowRISC Ibex CPU
riscv: Initial commit of OpenTitan machine
Bin Meng (4):
riscv: Suppress the error report for QEMU testing with riscv_find_firmware()
riscv: Change the default behavior if no -bios option is specified
hw/riscv: sifive_u: Remove the riscv_ prefix of the soc* functions
hw/riscv: virt: Remove the riscv_ prefix of the machine* functions
docs/system/deprecated.rst | 98 +++++------
default-configs/riscv32-softmmu.mak | 1 +
default-configs/riscv64-softmmu.mak | 11 +-
include/hw/riscv/boot.h | 1 +
include/hw/riscv/opentitan.h | 68 ++++++++
include/hw/riscv/sifive_e.h | 4 +
include/hw/riscv/spike.h | 6 +-
target/riscv/cpu.h | 9 +-
hw/riscv/boot.c | 45 ++---
hw/riscv/opentitan.c | 184 +++++++++++++++++++++
hw/riscv/sifive_e.c | 41 +++--
hw/riscv/sifive_u.c | 24 +--
hw/riscv/spike.c | 217 -------------------------
hw/riscv/virt.c | 20 +--
target/riscv/cpu.c | 45 ++---
target/riscv/cpu_helper.c | 82 ++++------
target/riscv/csr.c | 138 +++-------------
target/riscv/insn_trans/trans_privileged.inc.c | 18 +-
target/riscv/monitor.c | 5 -
target/riscv/op_helper.c | 17 +-
tests/qtest/machine-none-test.c | 4 +-
MAINTAINERS | 9 +
hw/riscv/Kconfig | 5 +
hw/riscv/Makefile.objs | 1 +
24 files changed, 480 insertions(+), 573 deletions(-)
create mode 100644 include/hw/riscv/opentitan.h
create mode 100644 hw/riscv/opentitan.c
^ permalink raw reply [flat|nested] 32+ messages in thread
end of thread, other threads:[~2024-03-27 10:14 UTC | newest]
Thread overview: 32+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-07-14 0:32 [PULL 00/15] riscv-to-apply queue Alistair Francis
2020-07-14 0:32 ` [PULL 01/15] MAINTAINERS: Add an entry for OpenSBI firmware Alistair Francis
2020-07-14 0:32 ` [PULL 02/15] hw/riscv: virt: Sort the SoC memmap table entries Alistair Francis
2020-07-14 0:32 ` [PULL 03/15] riscv: Unify Qemu's reset vector code path Alistair Francis
2020-07-14 0:32 ` [PULL 04/15] RISC-V: Copy the fdt in dram instead of ROM Alistair Francis
2021-07-13 10:43 ` Peter Maydell
2021-07-14 6:35 ` Alistair Francis
2020-07-14 0:32 ` [PULL 05/15] riscv: Add opensbi firmware dynamic support Alistair Francis
2020-07-14 0:32 ` [PULL 06/15] RISC-V: Support 64 bit start address Alistair Francis
2020-07-14 0:32 ` [PULL 07/15] hw/riscv: Modify MROM size to end at 0x10000 Alistair Francis
2020-07-14 0:32 ` [PULL 08/15] target/riscv: fix rsub gvec tcg_assert_listed_vecop assertion Alistair Francis
2020-07-14 0:32 ` [PULL 09/15] target/riscv: correct the gvec IR called in gen_vec_rsub16_i64() Alistair Francis
2020-07-14 0:32 ` [PULL 10/15] target/riscv: fix return value of do_opivx_widen() Alistair Francis
2020-07-14 0:32 ` [PULL 11/15] target/riscv: fix vill bit index in vtype register Alistair Francis
2020-07-14 0:32 ` [PULL 12/15] hw/char: Convert the Ibex UART to use the qdev Clock model Alistair Francis
2020-07-14 0:32 ` [PULL 13/15] hw/char: Convert the Ibex UART to use the registerfields API Alistair Francis
2020-07-14 0:32 ` [PULL 14/15] tcg/riscv: Remove superfluous breaks Alistair Francis
2020-07-14 0:32 ` [PULL 15/15] target/riscv: Fix pmp NA4 implementation Alistair Francis
2020-07-14 0:37 ` [PULL 00/15] riscv-to-apply queue Alistair Francis
2020-07-14 18:39 ` Peter Maydell
-- strict thread matches above, loose matches on Subject: below --
2024-03-22 8:53 Alistair Francis
2024-03-22 12:58 ` Peter Maydell
2024-03-22 17:16 ` Michael Tokarev
2024-03-22 19:46 ` Daniel Henrique Barboza
2024-03-24 15:07 ` Michael Tokarev
2024-03-24 18:12 ` Daniel Henrique Barboza
2024-03-26 9:53 ` Michael Tokarev
2024-03-26 9:56 ` Alistair Francis
2024-03-26 12:09 ` Daniel Henrique Barboza
2024-03-27 10:13 ` Michael Tokarev
2020-06-03 16:13 Alistair Francis
2020-06-04 11:40 ` Peter Maydell
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